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[86.58.126.118]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483a3deb73bsm59542655e9.3.2026.02.22.02.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Feb 2026 02:41:28 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Samuel Holland , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard , Junhui Liu Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, Junhui Liu Subject: Re: [PATCH 0/7] rtc: sun6i: Add support for Allwinner A733 SoC Date: Sun, 22 Feb 2026 11:41:26 +0100 Message-ID: <5061953.GXAFRqVoOG@jernej-laptop> In-Reply-To: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> References: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hi! Dne sreda, 21. januar 2026 ob 11:59:06 Srednjeevropski standardni =C4=8Das = je Junhui Liu napisal(a): > Add support for the Allwinner A733 RTC and its internal Clock Control > Unit (CCU). Reuse the rtc-sun6i rtc driver while introducing a new > SoC-specific RTC CCU driver to handle the hardware's evolved clock > structure. >=20 > To facilitate this addition and improve driver modularity, transition > the binding between the RTC and its internal CCU from direct > cross-subsystem function calls to the auxiliary bus. Also extract shared > IOSC and 32kHz clock logic into a standalone ccu_rtc module for reuse > across newer SoC generations. >=20 > The A733 implementation supports hardware detection of three external > crystal frequencies (19.2MHz, 24MHz and 26MHz), which is represented in > the driver via read-only mux operations. Implement logic to derive a > normalized 32kHz reference from these DCXO sources using fixed > pre-dividers. Additionally, provide several new DCXO gate clocks for > peripherals, including SerDes, HDMI, and UFS. This work looks nice, but I have some questions/comments: =2D you're missing RTC SPI clock, which is needed for RTC, at least accordi= ng to vendor 5.15 DT. Could it be that this bit set by vendor U-Boot so you missed it during testing? Manual says that it's disabled by default. =2D Vendor DT has strange RTC CCU phandles for UFS and HDMI. In first case uses RTC wakeup and in second DCXO, which doesn't make any sense. Did you do any experimentation with these clocks? It wouldn't be the first time that either code or manual contained some kind of error. Btw, switch last two patches. With current order during bisection you would get a complaint that A733 RTC CCU driver is not present. Best regards, Jernej