From: Pratyush Anand <pratyush.anand@st.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Shiraz HASHIM <shiraz.hashim@st.com>,
"viresh.linux@gmail.com" <viresh.linux@gmail.com>,
spear-devel <spear-devel@list.st.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree-discuss@lists.ozlabs.org"
<devicetree-discuss@lists.ozlabs.org>,
"olof@lixom.net" <olof@lixom.net>
Subject: Re: [PATCH 09/15] SPEAr13xx: dts: Fix PCIe core address ranges
Date: Wed, 31 Oct 2012 16:54:38 +0530 [thread overview]
Message-ID: <50910A76.9030308@st.com> (raw)
In-Reply-To: <201210302155.05206.arnd@arndb.de>
On 10/31/2012 3:25 AM, Arnd Bergmann wrote:
> On Monday 29 October 2012, Pratyush Anand wrote:
>> sible by
>> AHB and used to communicate with PCIe devices connected with the host
>> controller.
>>
>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>> ---
>> arch/arm/boot/dts/spear13xx.dtsi | 9 +++++----
>> 1 files changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
>> index 9ff4f5f..b7990754 100644
>> --- a/arch/arm/boot/dts/spear13xx.dtsi
>> +++ b/arch/arm/boot/dts/spear13xx.dtsi
>> @@ -76,7 +76,8 @@
>> #size-cells = <1>;
>> compatible = "simple-bus";
>> ranges = <0x50000000 0x50000000 0x10000000
>> - 0xb0000000 0xb0000000 0x10000000
>> + 0x80000000 0x80000000 0x20000000
>> + 0xb0000000 0xb0000000 0x20000000
>> 0xd0000000 0xd0000000 0x02000000
>> 0xd8000000 0xd8000000 0x01000000
>> 0xe0000000 0xe0000000 0x10000000>;
>> @@ -194,7 +195,7 @@
>> pcie0@b1000000 {
>> compatible = "st,pcie-gadget", "st,pcie-host" ;
>> reg = < 0xb1000000 0x4000
>> - 0x80000000 0x2000
>> + 0x80000000 0x10000000
>> 0xeb800000 0x1000 >;
>> interrupts = <0 68 0x4>;
>> status = "disabled";
>
> The code that I'm looking at in the upstream kernel looks very different, so I don't
> see how this patch would apply. Also, the version that you are patching as well
> as the changes you do don't actually follow the generic PCI bindings at all
> and should be done quite differently.
>
Yes, this was my mistake. I rebased with ST repo. Will send V2 with
correct rebase.
> Please have a look at how to configure the PCI ranges in the IEEE1275 PCI
> bindings and in examples you find in arch/powerpc/.
>
Will look into.
> Most importantly, the compatible string used here can't really refer to both
> the host and the endpoint mode, you really need separate bindings for those
> and have only one of the two used in a particular system. What you can do is
> to put both into the dtsi file and mark them as "disabled" and then enable
> just one of the two on a given board file.
Yes, we had though of this limitation and had decided to do exactly the
same way you have suggested.
thanks for your review comments.
Regards
Pratyush
>
> Arnd
> .
>
next prev parent reply other threads:[~2012-10-31 11:24 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-29 7:01 [PATCH 00/15] SPEAr13xx PCIe patches Pratyush Anand
2012-10-29 7:01 ` [PATCH 01/15] arm: source drivers/pci/pcie/kconfig Pratyush Anand
2012-10-29 7:01 ` [PATCH 02/15] arm: Call pcie_bus_configure_settings for pcie devices Pratyush Anand
2012-10-29 7:01 ` [PATCH 03/15] SPEAr13xx: Add mach/io.h Pratyush Anand
2012-10-29 7:29 ` viresh kumar
2012-10-29 8:11 ` Pratyush Anand
[not found] ` <508E3A2E.3000204-qxv4g6HH51o@public.gmane.org>
2012-10-30 21:45 ` Arnd Bergmann
2012-10-31 11:24 ` Pratyush Anand
2012-10-31 22:05 ` Arnd Bergmann
2012-10-29 7:01 ` [PATCH 04/15] SPEAr13xx: Add PCIe Root Complex driver support Pratyush Anand
2012-10-30 22:20 ` Arnd Bergmann
2012-10-31 11:24 ` Pratyush Anand
2012-10-31 22:00 ` Arnd Bergmann
2012-11-01 7:25 ` Pratyush Anand
2012-10-29 7:01 ` [PATCH 05/15] clk: SPEAr1340: Fix pcie0 clock name Pratyush Anand
2012-10-29 7:01 ` [PATCH 06/15] clk: SPEAr1310: Fix pcie " Pratyush Anand
2012-10-29 13:11 ` viresh kumar
2012-10-29 7:01 ` [PATCH 07/15] SPEAr1340: Add PCIe auxdata for miphy clock initialization Pratyush Anand
2012-10-29 7:01 ` [PATCH 08/15] SPEAr1310: " Pratyush Anand
2012-10-30 21:57 ` Arnd Bergmann
2012-10-29 7:01 ` [PATCH 09/15] SPEAr13xx: dts: Fix PCIe core address ranges Pratyush Anand
2012-10-29 13:23 ` viresh kumar
2012-10-30 3:23 ` Pratyush Anand
2012-10-30 21:55 ` Arnd Bergmann
2012-10-31 11:24 ` Pratyush Anand [this message]
2012-10-29 7:01 ` [PATCH 10/15] SPEAr13xx: DTS: Add auxiliary data for PCIe host Pratyush Anand
2012-10-29 13:24 ` viresh kumar
2012-10-30 3:24 ` Pratyush Anand
2012-10-30 5:47 ` Viresh Kumar
2012-10-29 7:01 ` [PATCH 11/15] SPEAr1340-evb: dts: Enable PCIe0 Pratyush Anand
2012-10-29 7:01 ` [PATCH 12/15] SPEAr1310-EVB: DTS: Fix PCIe1 enable Pratyush Anand
2012-10-29 7:01 ` [PATCH 13/15] SPEAr13xx: update kconfig for PCIe selection Pratyush Anand
2012-10-29 13:33 ` viresh kumar
2012-10-30 3:25 ` Pratyush Anand
2012-10-29 7:01 ` [PATCH 14/15] SPEAR13xx: Update makefile for PCIe inclusion Pratyush Anand
2012-10-29 13:34 ` viresh kumar
2012-10-29 7:01 ` [PATCH 15/15] SPEAR13xx: update defconfig for PCIe compilation Pratyush Anand
2012-10-29 7:16 ` [PATCH 00/15] SPEAr13xx PCIe patches viresh kumar
2012-10-29 7:22 ` Pratyush Anand
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=50910A76.9030308@st.com \
--to=pratyush.anand@st.com \
--cc=arnd@arndb.de \
--cc=devicetree-discuss@lists.ozlabs.org \
--cc=linux-pci@vger.kernel.org \
--cc=olof@lixom.net \
--cc=shiraz.hashim@st.com \
--cc=spear-devel@list.st.com \
--cc=viresh.linux@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).