[PATCH V3 0/5] SMP support for Armada XP

[PATCH V3 0/5] SMP support for Armada XP

[Gregory CLEMENT]

Hello,

The purpose of this patch set is to add the SMP support for the Armada
XP SoCs. Beside the SMP support itself brought by the last 3 patches,
this patch set also adds the support for the coherency fabric unit and
the power management service unit.

The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.

The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.

The original code is from Yehuda Yitschak, it was reworked by myself
and reviewed by Yehuda.

This patch set is based on 3.7-rc5 and depends one the framework clock
support which should be being included in the marvell branch
maintained by Jason Cooper. The git branch called
ArmadaXP-SMP-for-3.8-V3 is also available at
https://github.com/MISL-EBU-System-SW/mainline-public.git.

Changelog:
V2 -> V3:
- Rebased on to v3.7-rc5
- removed the unnecessary used of __iomem flag for a pointer to a
  function. the second parameter of armada_xp_boot_cpu is now just a
  void *.
- removed the dsb() call in armada_xp_boot_cpu(), as the following
  writel calls dsb if needed.
- Change the PJ4B mask for proc_info in arch/arm/mm/proc-v7.S to be
  less restrictive, the last 4 bits contain revision information
- Merge the multiple 'or' instruction in a single instruction in
  __v7_pj4b_setup

V1 -> V2:
- Rebased on to v3.7-rc3
- Fixed typos found by Alexandre Belloni
- Added clk_prepare_enable() before getting rate clk in
  set_secondary_cpus_clock()
- Add explanation in the binding documentation about the per-CPU
  interrupt registers: the address of the virtual register must be
  used.
- Removed the armada_xp prefix in the coherency.c file to be more
  compliant with the name convention of the other files.
- Coherency_init is now called from armada_370_xp_dt_init() and is no
  more an early_init() call. As the device tree is not available from
  an early_init(), it was useless to call coherency_init() so
  early. The need to be able to call some function very early during
  the boot were already resolved by using the hard code address of the
  register.

Yehuda Yitschak (5):
  arm: mvebu: Added support for coherency fabric in mach-mvebu
  arm: mvebu: Added initial support for power managmement service unit
  arm: mvebu: Added IPI support via doorbells
  arm: mm: Added support for PJ4B cpu and init routines
  arm: mvebu: Added SMP support for Armada XP

 .../devicetree/bindings/arm/armada-370-xp-mpic.txt |   12 +-
 .../devicetree/bindings/arm/armada-370-xp-pmsu.txt |   20 ++++
 .../devicetree/bindings/arm/coherency-fabric.txt   |   16 +++
 arch/arm/boot/dts/armada-370-xp.dtsi               |    5 +
 arch/arm/boot/dts/armada-xp.dtsi                   |   12 +-
 arch/arm/configs/mvebu_defconfig                   |    3 +
 arch/arm/mach-mvebu/Kconfig                        |    3 +-
 arch/arm/mach-mvebu/Makefile                       |    4 +-
 arch/arm/mach-mvebu/armada-370-xp.c                |    3 +
 arch/arm/mach-mvebu/armada-370-xp.h                |   10 ++
 arch/arm/mach-mvebu/coherency.c                    |   89 ++++++++++++++
 arch/arm/mach-mvebu/coherency.h                    |   24 ++++
 arch/arm/mach-mvebu/common.h                       |    6 +
 arch/arm/mach-mvebu/headsmp.S                      |   66 +++++++++++
 arch/arm/mach-mvebu/hotplug.c                      |   30 +++++
 arch/arm/mach-mvebu/irq-armada-370-xp.c            |   92 ++++++++++++++-
 arch/arm/mach-mvebu/platsmp.c                      |  124 ++++++++++++++++++++
 arch/arm/mach-mvebu/pmsu.c                         |   75 ++++++++++++
 arch/arm/mach-mvebu/pmsu.h                         |   16 +++
 arch/arm/mm/Kconfig                                |    4 +
 arch/arm/mm/proc-v7.S                              |   51 ++++++++
 21 files changed, 653 insertions(+), 12 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/coherency-fabric.txt
 create mode 100644 arch/arm/mach-mvebu/coherency.c
 create mode 100644 arch/arm/mach-mvebu/coherency.h
 create mode 100644 arch/arm/mach-mvebu/headsmp.S
 create mode 100644 arch/arm/mach-mvebu/hotplug.c
 create mode 100644 arch/arm/mach-mvebu/platsmp.c
 create mode 100644 arch/arm/mach-mvebu/pmsu.c
 create mode 100644 arch/arm/mach-mvebu/pmsu.h

-- 
1.7.9.5

[PATCH V3 1/5] arm: mvebu: Added support for coherency fabric in mach-mvebu

[Gregory CLEMENT]

From: Yehuda Yitschak <yehuday@marvell.com>

Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 .../devicetree/bindings/arm/coherency-fabric.txt   |   16 ++++
 arch/arm/boot/dts/armada-370-xp.dtsi               |    5 ++
 arch/arm/mach-mvebu/Makefile                       |    2 +-
 arch/arm/mach-mvebu/coherency.c                    |   89 ++++++++++++++++++++
 arch/arm/mach-mvebu/coherency.h                    |   24 ++++++
 arch/arm/mach-mvebu/common.h                       |    2 +
 6 files changed, 137 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/coherency-fabric.txt
 create mode 100644 arch/arm/mach-mvebu/coherency.c
 create mode 100644 arch/arm/mach-mvebu/coherency.h

diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
new file mode 100644
index 0000000..2bfbf67
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
@@ -0,0 +1,16 @@
+Coherency fabric
+----------------
+Available on Marvell SOCs: Armada 370 and Armada XP
+
+Required properties:
+
+- compatible: "marvell,coherency-fabric"
+- reg: Should contain,coherency fabric registers location and length.
+
+Example:
+
+coherency-fabric@d0020200 {
+	compatible = "marvell,coherency-fabric";
+	reg = <0xd0020200 0xb0>;
+};
+
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 94b4b9e..b0d075b 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -36,6 +36,11 @@
 	      interrupt-controller;
 	};
 
+	coherency-fabric@d0020200 {
+		compatible = "marvell,coherency-fabric";
+		reg = <0xd0020200 0xb0>;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 57f996b..abd6d3b 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -2,4 +2,4 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 	-I$(srctree)/arch/arm/plat-orion/include
 
 obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
new file mode 100644
index 0000000..20a0ccc
--- /dev/null
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -0,0 +1,89 @@
+/*
+ * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory Clement <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada 370 and Armada XP SOCs have a coherency fabric which is
+ * responsible for ensuring hardware coherency between all CPUs and between
+ * CPUs and I/O masters. This file initializes the coherency fabric and
+ * supplies basic routines for configuring and controlling hardware coherency
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <asm/smp_plat.h>
+#include "armada-370-xp.h"
+
+/* Some functions in this file are called very early during SMP
+ * initialization. At that time the device tree framework is not yet
+ * ready, and it is not possible to get the register address to
+ * ioremap it. That's why the pointer below is given with an initial
+ * value matching its virtual mapping
+ */
+static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
+
+/* Coherency fabric registers */
+#define COHERENCY_FABRIC_CTL_OFFSET		   0x0
+#define COHERENCY_FABRIC_CFG_OFFSET		   0x4
+
+static struct of_device_id of_coherency_table[] = {
+	{.compatible = "marvell,coherency-fabric"},
+	{ /* end of list */ },
+};
+#ifdef CONFIG_SMP
+int coherency_get_cpu_count(void)
+{
+	int reg, cnt;
+
+	reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
+	cnt = (reg & 0xF) + 1;
+
+	return cnt;
+}
+#endif
+int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id)
+{
+	int reg;
+
+	if (!coherency_base) {
+		pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id);
+		pr_warn("Coherency fabric is not initialized\n");
+		return 1;
+	}
+
+	/* Enable the CPU in coherency fabric */
+	reg = readl(coherency_base + COHERENCY_FABRIC_CTL_OFFSET);
+	reg |= 1 << (24 + hw_cpu_id);
+	writel(reg, coherency_base + COHERENCY_FABRIC_CTL_OFFSET);
+
+	/* Add CPU to SMP group */
+	reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
+	reg |= 1 << (16 + hw_cpu_id + (smp_group_id == 0 ? 8 : 0));
+	writel(reg, coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
+
+	return 0;
+}
+
+int __init coherency_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, of_coherency_table);
+	if (np) {
+		pr_info("Initializing Coherency fabric\n");
+		coherency_base = of_iomap(np, 0);
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
new file mode 100644
index 0000000..2f42813
--- /dev/null
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-mvebu/include/mach/coherency.h
+ *
+ *
+ * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_370_XP_COHERENCY_H
+#define __MACH_370_XP_COHERENCY_H
+
+#ifdef CONFIG_SMP
+int coherency_get_cpu_count(void);
+#endif
+
+int set_cpu_coherent(int cpu_id, int smp_group_id);
+int coherency_init(void);
+
+#endif	/* __MACH_370_XP_COHERENCY_H */
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index 281fab3..ea08919 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -21,4 +21,6 @@ void mvebu_clocks_init(void);
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
 
+
+int armada_370_xp_coherency_init(void);
 #endif
-- 
1.7.9.5

[PATCH V3 2/5] arm: mvebu: Added initial support for power managmement service unit

[Gregory CLEMENT]

From: Yehuda Yitschak <yehuday@marvell.com>

Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 .../devicetree/bindings/arm/armada-370-xp-pmsu.txt |   20 ++++++
 arch/arm/boot/dts/armada-xp.dtsi                   |    6 ++
 arch/arm/mach-mvebu/Makefile                       |    2 +-
 arch/arm/mach-mvebu/common.h                       |    1 +
 arch/arm/mach-mvebu/pmsu.c                         |   75 ++++++++++++++++++++
 arch/arm/mach-mvebu/pmsu.h                         |   16 +++++
 6 files changed, 119 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
 create mode 100644 arch/arm/mach-mvebu/pmsu.c
 create mode 100644 arch/arm/mach-mvebu/pmsu.h

diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
new file mode 100644
index 0000000..926b4d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
@@ -0,0 +1,20 @@
+Power Management Service Unit(PMSU)
+-----------------------------------
+Available on Marvell SOCs: Armada 370 and Armada XP
+
+Required properties:
+
+- compatible: "marvell,armada-370-xp-pmsu"
+
+- reg: Should contain PMSU registers location and length. First pair
+  for the per-CPU SW Reset Control registers, second pair for the
+  Power Management Service Unit.
+
+Example:
+
+armada-370-xp-pmsu@d0022000 {
+	compatible = "marvell,armada-370-xp-pmsu";
+	reg = <0xd0022100 0x430>,
+	      <0xd0020800 0x20>;
+};
+
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index a564b52..f521ed8 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -27,6 +27,12 @@
 		    <0xd0021870 0x58>;
 	};
 
+	armada-370-xp-pmsu@d0022000 {
+		compatible = "marvell,armada-370-xp-pmsu";
+		reg = <0xd0022100 0x430>,
+		      <0xd0020800 0x20>;
+	};
+
 	cpus {
 	    #address-cells = <1>;
 	    #size-cells = <0>;
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index abd6d3b..8e6e50b 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -2,4 +2,4 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 	-I$(srctree)/arch/arm/plat-orion/include
 
 obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o pmsu.o
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index ea08919..74ee0b2 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -23,4 +23,5 @@ void armada_370_xp_handle_irq(struct pt_regs *regs);
 
 
 int armada_370_xp_coherency_init(void);
+int armada_370_xp_pmsu_init(void);
 #endif
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
new file mode 100644
index 0000000..3cc4bef
--- /dev/null
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -0,0 +1,75 @@
+/*
+ * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory Clement <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada 370 and Armada XP SOCs have a power management service
+ * unit which is responsible for powering down and waking up CPUs and
+ * other SOC units
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <asm/smp_plat.h>
+
+static void __iomem *pmsu_mp_base;
+static void __iomem *pmsu_reset_base;
+
+#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu)	((cpu * 0x100) + 0x24)
+#define PMSU_RESET_CTL_OFFSET(cpu)		(cpu * 0x8)
+
+static struct of_device_id of_pmsu_table[] = {
+	{.compatible = "marvell,armada-370-xp-pmsu"},
+	{ /* end of list */ },
+};
+
+#ifdef CONFIG_SMP
+int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr)
+{
+	int reg, hw_cpu;
+
+	if (!pmsu_mp_base || !pmsu_reset_base) {
+		pr_warn("Can't boot CPU. PMSU is uninitialized\n");
+		return 1;
+	}
+
+	hw_cpu = cpu_logical_map(cpu_id);
+
+	writel(virt_to_phys(boot_addr), pmsu_mp_base +
+			PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
+
+	/* Release CPU from reset by clearing reset bit*/
+	reg = readl(pmsu_reset_base + PMSU_RESET_CTL_OFFSET(hw_cpu));
+	reg &= (~0x1);
+	writel(reg, pmsu_reset_base + PMSU_RESET_CTL_OFFSET(hw_cpu));
+
+	return 0;
+}
+#endif
+
+int __init armada_370_xp_pmsu_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, of_pmsu_table);
+	if (np) {
+		pr_info("Initializing Power Management Service Unit\n");
+		pmsu_mp_base = of_iomap(np, 0);
+		pmsu_reset_base = of_iomap(np, 1);
+	}
+
+	return 0;
+}
+
+early_initcall(armada_370_xp_pmsu_init);
diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h
new file mode 100644
index 0000000..07a737c
--- /dev/null
+++ b/arch/arm/mach-mvebu/pmsu.h
@@ -0,0 +1,16 @@
+/*
+ * Power Management Service Unit (PMSU) support for Armada 370/XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MVEBU_PMSU_H
+#define __MACH_MVEBU_PMSU_H
+
+int armada_xp_boot_cpu(unsigned int cpu_id, void *phys_addr);
+
+#endif	/* __MACH_370_XP_PMSU_H */
-- 
1.7.9.5

[PATCH V3 3/5] arm: mvebu: Added IPI support via doorbells

[Gregory CLEMENT]

From: Yehuda Yitschak <yehuday@marvell.com>

Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 .../devicetree/bindings/arm/armada-370-xp-mpic.txt |   12 ++-
 arch/arm/boot/dts/armada-xp.dtsi                   |    2 +-
 arch/arm/mach-mvebu/armada-370-xp.h                |   10 +++
 arch/arm/mach-mvebu/irq-armada-370-xp.c            |   92 ++++++++++++++++++--
 4 files changed, 106 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
index 70c0dc5..61df564 100644
--- a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
@@ -6,9 +6,15 @@ Required properties:
 - interrupt-controller: Identifies the node as an interrupt controller.
 - #interrupt-cells: The number of cells to define the interrupts. Should be 1.
   The cell is the IRQ number
+
 - reg: Should contain PMIC registers location and length. First pair
   for the main interrupt registers, second pair for the per-CPU
-  interrupt registers
+  interrupt registers. For this last pair, to be compliant with SMP
+  support, the "virtual" must be use (For the record, these registers
+  automatically map to the interrupt controller registers of the
+  current CPU)
+
+
 
 Example:
 
@@ -18,6 +24,6 @@ Example:
               #address-cells = <1>;
               #size-cells = <1>;
               interrupt-controller;
-              reg = <0xd0020000 0x1000>,
-                    <0xd0021000 0x1000>;
+              reg = <0xd0020a00 0x1d0>,
+                    <0xd0021070 0x58>;
         };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index f521ed8..531619f 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -24,7 +24,7 @@
 
 	mpic: interrupt-controller@d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
-		    <0xd0021870 0x58>;
+		    <0xd0021070 0x58>;
 	};
 
 	armada-370-xp-pmsu@d0022000 {
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index aac9beb..dce590d 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -19,4 +19,14 @@
 #define ARMADA_370_XP_REGS_VIRT_BASE	IOMEM(0xfeb00000)
 #define ARMADA_370_XP_REGS_SIZE		SZ_1M
 
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_SMP
+#include <linux/cpumask.h>
+
+void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq);
+void armada_xp_mpic_smp_cpu_init(void);
+#endif
+#endif
+
 #endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 5f5f939..549b684 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -24,6 +24,7 @@
 #include <linux/irqdomain.h>
 #include <asm/mach/arch.h>
 #include <asm/exception.h>
+#include <asm/smp_plat.h>
 
 /* Interrupt Controller Registers Map */
 #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
@@ -35,6 +36,12 @@
 
 #define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
 
+#define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
+#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
+#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)
+
+#define ACTIVE_DOORBELLS			(8)
+
 static void __iomem *per_cpu_int_base;
 static void __iomem *main_int_base;
 static struct irq_domain *armada_370_xp_mpic_domain;
@@ -51,11 +58,22 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
 	       per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 }
 
+#ifdef CONFIG_SMP
+static int armada_xp_set_affinity(struct irq_data *d,
+				  const struct cpumask *mask_val, bool force)
+{
+	return 0;
+}
+#endif
+
 static struct irq_chip armada_370_xp_irq_chip = {
 	.name		= "armada_370_xp_irq",
 	.irq_mask       = armada_370_xp_irq_mask,
 	.irq_mask_ack   = armada_370_xp_irq_mask,
 	.irq_unmask     = armada_370_xp_irq_unmask,
+#ifdef CONFIG_SMP
+	.irq_set_affinity = armada_xp_set_affinity,
+#endif
 };
 
 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
@@ -72,6 +90,41 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 	return 0;
 }
 
+#ifdef CONFIG_SMP
+void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
+{
+	int cpu;
+	unsigned long map = 0;
+
+	/* Convert our logical CPU mask into a physical one. */
+	for_each_cpu(cpu, mask)
+		map |= 1 << cpu_logical_map(cpu);
+
+	/*
+	 * Ensure that stores to Normal memory are visible to the
+	 * other CPUs before issuing the IPI.
+	 */
+	dsb();
+
+	/* submit softirq */
+	writel((map << 8) | irq, main_int_base +
+		ARMADA_370_XP_SW_TRIG_INT_OFFS);
+}
+
+void armada_xp_mpic_smp_cpu_init(void)
+{
+	/* Clear pending IPIs */
+	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+
+	/* Enable first 8 IPIs */
+	writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
+		ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+
+	/* Unmask IPI interrupt */
+	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+}
+#endif /* CONFIG_SMP */
+
 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
 	.map = armada_370_xp_mpic_irq_map,
 	.xlate = irq_domain_xlate_onecell,
@@ -91,13 +144,18 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
 
 	armada_370_xp_mpic_domain =
-	    irq_domain_add_linear(node, (control >> 2) & 0x3ff,
-				  &armada_370_xp_mpic_irq_ops, NULL);
+		irq_domain_add_linear(node, (control >> 2) & 0x3ff,
+				&armada_370_xp_mpic_irq_ops, NULL);
 
 	if (!armada_370_xp_mpic_domain)
 		panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
 
 	irq_set_default_host(armada_370_xp_mpic_domain);
+
+#ifdef CONFIG_SMP
+	armada_xp_mpic_smp_cpu_init();
+#endif
+
 	return 0;
 }
 
@@ -111,14 +169,36 @@ asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
 					ARMADA_370_XP_CPU_INTACK_OFFS);
 		irqnr = irqstat & 0x3FF;
 
-		if (irqnr < 1023) {
-			irqnr =
-			    irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
+		if (irqnr > 1022)
+			break;
+
+		if (irqnr >= 8) {
+			irqnr =	irq_find_mapping(armada_370_xp_mpic_domain,
+					irqnr);
 			handle_IRQ(irqnr, regs);
 			continue;
 		}
+#ifdef CONFIG_SMP
+		/* IPI Handling */
+		if (irqnr == 0) {
+			u32 ipimask, ipinr;
+
+			ipimask = readl_relaxed(per_cpu_int_base +
+						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
+				& 0xFF;
+
+			writel(0x0, per_cpu_int_base +
+				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+
+			/* Handle all pending doorbells */
+			for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
+				if (ipimask & (0x1 << ipinr))
+					handle_IPI(ipinr, regs);
+			}
+			continue;
+		}
+#endif
 
-		break;
 	} while (1);
 }
 
-- 
1.7.9.5

[PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Gregory CLEMENT]

From: Yehuda Yitschak <yehuday@marvell.com>

Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/mach-mvebu/Kconfig |    2 +-
 arch/arm/mm/Kconfig         |    4 ++++
 arch/arm/mm/proc-v7.S       |   51 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 17d246b..9bfaa0c 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -22,7 +22,7 @@ config MVEBU_CLK_CPU
 config MACH_ARMADA_370_XP
 	bool
 	select ARMADA_370_XP_TIMER
-	select CPU_V7
+	select CPU_PJ4B
 
 config MACH_ARMADA_370
 	bool "Marvell Armada 370 boards"
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 94186b6..3fd629d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -352,6 +352,10 @@ config CPU_PJ4
 	select ARM_THUMBEE
 	select CPU_V7
 
+config CPU_PJ4B
+	bool
+	select CPU_V7
+
 # ARMv6
 config CPU_V6
 	bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 846d279..a4c0ccf 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -169,6 +169,47 @@ __v7_ca15mp_setup:
 	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
 	mcreq	p15, 0, r0, c1, c0, 1
 #endif
+
+__v7_pj4b_setup:
+#ifdef CONFIG_CPU_PJ4B
+
+#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
+#define CWF           (1 << 27) /* Disable Critical Word First feature */
+#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
+#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
+
+#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
+
+	/* Auxiliary Debug Modes Control 1 Register */
+	mrc	p15, 1,	r0, c15, c1, 1
+	orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
+	orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
+	orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
+	bic	r0, r0, #(1 << 2)      @ Disable Static BP
+	mcr	p15, 1,	r0, c15, c1, 1
+
+	/* Auxiliary Debug Modes Control 2 Register */
+	mrc	p15, 1,	r0, c15, c1, 2
+	bic	r0, r0, #(1 << 23)   @ Enable fast LDR.
+	orr	r0, r0, #AUX_DBG_CTRL2
+	mcr	p15, 1,	r0, c15, c1, 2
+
+	/* Auxiliary Functional Modes Control Register 0 */
+	mrc	p15, 1,	r0, c15, c2, 0
+#ifdef CONFIG_SMP
+	orr	r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
+#endif
+	orr	r0, r0, #(1 << 2)     @ Support L1 parity checking
+	orr	r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
+	mcr	p15, 1,	r0, c15, c2, 0
+
+	/* Auxiliary Debug Modes Control 0 Register */
+	mrc	p15, 1,	r0, c15, c1, 0
+	orr	r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
+	mcr	p15, 1,	r0, c15, c1, 0
+
+#endif /* CONFIG_CPU_PJ4B */
+
 __v7_setup:
 	adr	r12, __v7_setup_stack		@ the local stack
 	stmia	r12, {r0-r5, r7, r9, r11, lr}
@@ -342,6 +383,16 @@ __v7_ca9mp_proc_info:
 	.long	0xff0ffff0
 	__v7_proc __v7_ca9mp_setup
 	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+
+	/*
+	 * Marvell PJ4B processor.
+	 */
+	.type   __v7_pj4b_proc_info, #object
+__v7_pj4b_proc_info:
+	.long	0x562f5840
+	.long	0xfffffff0
+	__v7_proc __v7_pj4b_setup
+	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 #endif	/* CONFIG_ARM_LPAE */
 
 	/*
-- 
1.7.9.5

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Gregory CLEMENT]

Hello Russell,

With the 2 changes I have done on according your comments
do you think you can give your acked-by for this patch?

Thanks

On 11/14/2012 11:20 PM, Gregory CLEMENT wrote:
> From: Yehuda Yitschak <yehuday@marvell.com>
> 
> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  arch/arm/mach-mvebu/Kconfig |    2 +-
>  arch/arm/mm/Kconfig         |    4 ++++
>  arch/arm/mm/proc-v7.S       |   51 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 56 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 17d246b..9bfaa0c 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -22,7 +22,7 @@ config MVEBU_CLK_CPU
>  config MACH_ARMADA_370_XP
>  	bool
>  	select ARMADA_370_XP_TIMER
> -	select CPU_V7
> +	select CPU_PJ4B
>  
>  config MACH_ARMADA_370
>  	bool "Marvell Armada 370 boards"
> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> index 94186b6..3fd629d 100644
> --- a/arch/arm/mm/Kconfig
> +++ b/arch/arm/mm/Kconfig
> @@ -352,6 +352,10 @@ config CPU_PJ4
>  	select ARM_THUMBEE
>  	select CPU_V7
>  
> +config CPU_PJ4B
> +	bool
> +	select CPU_V7
> +
>  # ARMv6
>  config CPU_V6
>  	bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 846d279..a4c0ccf 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -169,6 +169,47 @@ __v7_ca15mp_setup:
>  	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
>  	mcreq	p15, 0, r0, c1, c0, 1
>  #endif
> +
> +__v7_pj4b_setup:
> +#ifdef CONFIG_CPU_PJ4B
> +
> +#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
> +#define CWF           (1 << 27) /* Disable Critical Word First feature */
> +#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
> +#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
> +
> +#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
> +
> +	/* Auxiliary Debug Modes Control 1 Register */
> +	mrc	p15, 1,	r0, c15, c1, 1
> +	orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
> +	orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
> +	orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
> +	bic	r0, r0, #(1 << 2)      @ Disable Static BP
> +	mcr	p15, 1,	r0, c15, c1, 1
> +
> +	/* Auxiliary Debug Modes Control 2 Register */
> +	mrc	p15, 1,	r0, c15, c1, 2
> +	bic	r0, r0, #(1 << 23)   @ Enable fast LDR.
> +	orr	r0, r0, #AUX_DBG_CTRL2
> +	mcr	p15, 1,	r0, c15, c1, 2
> +
> +	/* Auxiliary Functional Modes Control Register 0 */
> +	mrc	p15, 1,	r0, c15, c2, 0
> +#ifdef CONFIG_SMP
> +	orr	r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
> +#endif
> +	orr	r0, r0, #(1 << 2)     @ Support L1 parity checking
> +	orr	r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
> +	mcr	p15, 1,	r0, c15, c2, 0
> +
> +	/* Auxiliary Debug Modes Control 0 Register */
> +	mrc	p15, 1,	r0, c15, c1, 0
> +	orr	r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
> +	mcr	p15, 1,	r0, c15, c1, 0
> +
> +#endif /* CONFIG_CPU_PJ4B */
> +
>  __v7_setup:
>  	adr	r12, __v7_setup_stack		@ the local stack
>  	stmia	r12, {r0-r5, r7, r9, r11, lr}
> @@ -342,6 +383,16 @@ __v7_ca9mp_proc_info:
>  	.long	0xff0ffff0
>  	__v7_proc __v7_ca9mp_setup
>  	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
> +
> +	/*
> +	 * Marvell PJ4B processor.
> +	 */
> +	.type   __v7_pj4b_proc_info, #object
> +__v7_pj4b_proc_info:
> +	.long	0x562f5840
> +	.long	0xfffffff0
> +	__v7_proc __v7_pj4b_setup
> +	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
>  #endif	/* CONFIG_ARM_LPAE */
>  
>  	/*
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Gregory CLEMENT]

On 11/14/2012 11:31 PM, Gregory CLEMENT wrote:
> Hello Russell,
> 
> With the 2 changes I have done on according your comments
> do you think you can give your acked-by for this patch?
> 

Hello Russell,

I didn't have any feedback from you for this version.
If you are fine with this, could you give your Acked-by?


Thanks again,

Gregory


> On 11/14/2012 11:20 PM, Gregory CLEMENT wrote:
>> From: Yehuda Yitschak <yehuday-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
>>
>> Signed-off-by: Yehuda Yitschak <yehuday-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
>> Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> ---
>>  arch/arm/mach-mvebu/Kconfig |    2 +-
>>  arch/arm/mm/Kconfig         |    4 ++++
>>  arch/arm/mm/proc-v7.S       |   51 +++++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 56 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
>> index 17d246b..9bfaa0c 100644
>> --- a/arch/arm/mach-mvebu/Kconfig
>> +++ b/arch/arm/mach-mvebu/Kconfig
>> @@ -22,7 +22,7 @@ config MVEBU_CLK_CPU
>>  config MACH_ARMADA_370_XP
>>  	bool
>>  	select ARMADA_370_XP_TIMER
>> -	select CPU_V7
>> +	select CPU_PJ4B
>>  
>>  config MACH_ARMADA_370
>>  	bool "Marvell Armada 370 boards"
>> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
>> index 94186b6..3fd629d 100644
>> --- a/arch/arm/mm/Kconfig
>> +++ b/arch/arm/mm/Kconfig
>> @@ -352,6 +352,10 @@ config CPU_PJ4
>>  	select ARM_THUMBEE
>>  	select CPU_V7
>>  
>> +config CPU_PJ4B
>> +	bool
>> +	select CPU_V7
>> +
>>  # ARMv6
>>  config CPU_V6
>>  	bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
>> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
>> index 846d279..a4c0ccf 100644
>> --- a/arch/arm/mm/proc-v7.S
>> +++ b/arch/arm/mm/proc-v7.S
>> @@ -169,6 +169,47 @@ __v7_ca15mp_setup:
>>  	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
>>  	mcreq	p15, 0, r0, c1, c0, 1
>>  #endif
>> +
>> +__v7_pj4b_setup:
>> +#ifdef CONFIG_CPU_PJ4B
>> +
>> +#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
>> +#define CWF           (1 << 27) /* Disable Critical Word First feature */
>> +#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
>> +#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
>> +
>> +#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
>> +
>> +	/* Auxiliary Debug Modes Control 1 Register */
>> +	mrc	p15, 1,	r0, c15, c1, 1
>> +	orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
>> +	orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
>> +	orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
>> +	bic	r0, r0, #(1 << 2)      @ Disable Static BP
>> +	mcr	p15, 1,	r0, c15, c1, 1
>> +
>> +	/* Auxiliary Debug Modes Control 2 Register */
>> +	mrc	p15, 1,	r0, c15, c1, 2
>> +	bic	r0, r0, #(1 << 23)   @ Enable fast LDR.
>> +	orr	r0, r0, #AUX_DBG_CTRL2
>> +	mcr	p15, 1,	r0, c15, c1, 2
>> +
>> +	/* Auxiliary Functional Modes Control Register 0 */
>> +	mrc	p15, 1,	r0, c15, c2, 0
>> +#ifdef CONFIG_SMP
>> +	orr	r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
>> +#endif
>> +	orr	r0, r0, #(1 << 2)     @ Support L1 parity checking
>> +	orr	r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
>> +	mcr	p15, 1,	r0, c15, c2, 0
>> +
>> +	/* Auxiliary Debug Modes Control 0 Register */
>> +	mrc	p15, 1,	r0, c15, c1, 0
>> +	orr	r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
>> +	mcr	p15, 1,	r0, c15, c1, 0
>> +
>> +#endif /* CONFIG_CPU_PJ4B */
>> +
>>  __v7_setup:
>>  	adr	r12, __v7_setup_stack		@ the local stack
>>  	stmia	r12, {r0-r5, r7, r9, r11, lr}
>> @@ -342,6 +383,16 @@ __v7_ca9mp_proc_info:
>>  	.long	0xff0ffff0
>>  	__v7_proc __v7_ca9mp_setup
>>  	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
>> +
>> +	/*
>> +	 * Marvell PJ4B processor.
>> +	 */
>> +	.type   __v7_pj4b_proc_info, #object
>> +__v7_pj4b_proc_info:
>> +	.long	0x562f5840
>> +	.long	0xfffffff0
>> +	__v7_proc __v7_pj4b_setup
>> +	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
>>  #endif	/* CONFIG_ARM_LPAE */
>>  
>>  	/*
>>
> 
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Jason Cooper]

On Fri, Nov 16, 2012 at 10:46:15PM +0100, Gregory CLEMENT wrote:
> On 11/14/2012 11:31 PM, Gregory CLEMENT wrote:
> > Hello Russell,
> > 
> > With the 2 changes I have done on according your comments
> > do you think you can give your acked-by for this patch?
> > 
> 
> Hello Russell,
> 
> I didn't have any feedback from you for this version.
> If you are fine with this, could you give your Acked-by?
> 
> 

Gregory,

>From the looks of things, Russell has his head wrapped around buggy
sound driver code for the CuBox.  Perhaps Will Deacon or Catalin Marinas
would care to weigh in?  I'm reluctant to take the series without an
Acked-By from at least one of them.

thx,

Jason.

> 
> > On 11/14/2012 11:20 PM, Gregory CLEMENT wrote:
> >> From: Yehuda Yitschak <yehuday-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
> >>
> >> Signed-off-by: Yehuda Yitschak <yehuday-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
> >> Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> >> ---
> >>  arch/arm/mach-mvebu/Kconfig |    2 +-
> >>  arch/arm/mm/Kconfig         |    4 ++++
> >>  arch/arm/mm/proc-v7.S       |   51 +++++++++++++++++++++++++++++++++++++++++++
> >>  3 files changed, 56 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> >> index 17d246b..9bfaa0c 100644
> >> --- a/arch/arm/mach-mvebu/Kconfig
> >> +++ b/arch/arm/mach-mvebu/Kconfig
> >> @@ -22,7 +22,7 @@ config MVEBU_CLK_CPU
> >>  config MACH_ARMADA_370_XP
> >>  	bool
> >>  	select ARMADA_370_XP_TIMER
> >> -	select CPU_V7
> >> +	select CPU_PJ4B
> >>  
> >>  config MACH_ARMADA_370
> >>  	bool "Marvell Armada 370 boards"
> >> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> >> index 94186b6..3fd629d 100644
> >> --- a/arch/arm/mm/Kconfig
> >> +++ b/arch/arm/mm/Kconfig
> >> @@ -352,6 +352,10 @@ config CPU_PJ4
> >>  	select ARM_THUMBEE
> >>  	select CPU_V7
> >>  
> >> +config CPU_PJ4B
> >> +	bool
> >> +	select CPU_V7
> >> +
> >>  # ARMv6
> >>  config CPU_V6
> >>  	bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
> >> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> >> index 846d279..a4c0ccf 100644
> >> --- a/arch/arm/mm/proc-v7.S
> >> +++ b/arch/arm/mm/proc-v7.S
> >> @@ -169,6 +169,47 @@ __v7_ca15mp_setup:
> >>  	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
> >>  	mcreq	p15, 0, r0, c1, c0, 1
> >>  #endif
> >> +
> >> +__v7_pj4b_setup:
> >> +#ifdef CONFIG_CPU_PJ4B
> >> +
> >> +#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
> >> +#define CWF           (1 << 27) /* Disable Critical Word First feature */
> >> +#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
> >> +#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
> >> +
> >> +#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
> >> +
> >> +	/* Auxiliary Debug Modes Control 1 Register */
> >> +	mrc	p15, 1,	r0, c15, c1, 1
> >> +	orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
> >> +	orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
> >> +	orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
> >> +	bic	r0, r0, #(1 << 2)      @ Disable Static BP
> >> +	mcr	p15, 1,	r0, c15, c1, 1
> >> +
> >> +	/* Auxiliary Debug Modes Control 2 Register */
> >> +	mrc	p15, 1,	r0, c15, c1, 2
> >> +	bic	r0, r0, #(1 << 23)   @ Enable fast LDR.
> >> +	orr	r0, r0, #AUX_DBG_CTRL2
> >> +	mcr	p15, 1,	r0, c15, c1, 2
> >> +
> >> +	/* Auxiliary Functional Modes Control Register 0 */
> >> +	mrc	p15, 1,	r0, c15, c2, 0
> >> +#ifdef CONFIG_SMP
> >> +	orr	r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
> >> +#endif
> >> +	orr	r0, r0, #(1 << 2)     @ Support L1 parity checking
> >> +	orr	r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
> >> +	mcr	p15, 1,	r0, c15, c2, 0
> >> +
> >> +	/* Auxiliary Debug Modes Control 0 Register */
> >> +	mrc	p15, 1,	r0, c15, c1, 0
> >> +	orr	r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
> >> +	mcr	p15, 1,	r0, c15, c1, 0
> >> +
> >> +#endif /* CONFIG_CPU_PJ4B */
> >> +
> >>  __v7_setup:
> >>  	adr	r12, __v7_setup_stack		@ the local stack
> >>  	stmia	r12, {r0-r5, r7, r9, r11, lr}
> >> @@ -342,6 +383,16 @@ __v7_ca9mp_proc_info:
> >>  	.long	0xff0ffff0
> >>  	__v7_proc __v7_ca9mp_setup
> >>  	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
> >> +
> >> +	/*
> >> +	 * Marvell PJ4B processor.
> >> +	 */
> >> +	.type   __v7_pj4b_proc_info, #object
> >> +__v7_pj4b_proc_info:
> >> +	.long	0x562f5840
> >> +	.long	0xfffffff0
> >> +	__v7_proc __v7_pj4b_setup
> >> +	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
> >>  #endif	/* CONFIG_ARM_LPAE */
> >>  
> >>  	/*
> >>
> > 
> > 
> 
> 
> -- 
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Gregory CLEMENT]

On 11/19/2012 04:12 AM, Jason Cooper wrote:
> On Fri, Nov 16, 2012 at 10:46:15PM +0100, Gregory CLEMENT wrote:
>> On 11/14/2012 11:31 PM, Gregory CLEMENT wrote:
>>> Hello Russell,
>>>
>>> With the 2 changes I have done on according your comments
>>> do you think you can give your acked-by for this patch?
>>>
>>
>> Hello Russell,
>>
>> I didn't have any feedback from you for this version.
>> If you are fine with this, could you give your Acked-by?
>>
>>
> 
> Gregory,
> 
> From the looks of things, Russell has his head wrapped around buggy
> sound driver code for the CuBox.  Perhaps Will Deacon or Catalin Marinas
> would care to weigh in?  I'm reluctant to take the series without an
> Acked-By from at least one of them.


I am fine with this as Will already have done the review.

Arnd, Olof,
Do you agree to get the pull from Jason with an acked-by from
Will and/or Catalin instead of Russell?


Catalin, Will,
If Arnd and Olof agree, would you mind give your acked-by on this
pacth?

Russell,
if you had a couple of minutes, the best would be to have your acked-by
of course.

Thanks all,

Gregory

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Will Deacon]

On Mon, Nov 19, 2012 at 08:13:05AM +0000, Gregory CLEMENT wrote:
> On 11/19/2012 04:12 AM, Jason Cooper wrote:
> > On Fri, Nov 16, 2012 at 10:46:15PM +0100, Gregory CLEMENT wrote:
> >> On 11/14/2012 11:31 PM, Gregory CLEMENT wrote:
> >>> Hello Russell,
> >>>
> >>> With the 2 changes I have done on according your comments
> >>> do you think you can give your acked-by for this patch?
> >>>
> >>
> >> Hello Russell,
> >>
> >> I didn't have any feedback from you for this version.
> >> If you are fine with this, could you give your Acked-by?
> >>
> >>
> > 
> > Gregory,
> > 
> > From the looks of things, Russell has his head wrapped around buggy
> > sound driver code for the CuBox.  Perhaps Will Deacon or Catalin Marinas
> > would care to weigh in?  I'm reluctant to take the series without an
> > Acked-By from at least one of them.
> 
> 
> I am fine with this as Will already have done the review.

I reviewed the thing, so you can add:

  Reviewed-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>

However, if Russell wants to take this via his tree then perhaps it's best
for arm-soc to pull a branch from him containing this, like we've done in the
past.

The alternative is to order the pull requests to Linus, but that sounds like
a bad idea (although I suspect the rest of your series still at least compiles
without this patch?).

Will

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Russell King - ARM Linux]

On Sun, Nov 18, 2012 at 10:12:10PM -0500, Jason Cooper wrote:
> On Fri, Nov 16, 2012 at 10:46:15PM +0100, Gregory CLEMENT wrote:
> > On 11/14/2012 11:31 PM, Gregory CLEMENT wrote:
> > > Hello Russell,
> > > 
> > > With the 2 changes I have done on according your comments
> > > do you think you can give your acked-by for this patch?
> > > 
> > 
> > Hello Russell,
> > 
> > I didn't have any feedback from you for this version.
> > If you are fine with this, could you give your Acked-by?
> > 
> > 
> 
> Gregory,
> 
> >From the looks of things, Russell has his head wrapped around buggy
> sound driver code for the CuBox.  Perhaps Will Deacon or Catalin Marinas
> would care to weigh in?  I'm reluctant to take the series without an
> Acked-By from at least one of them.

Well, I would like to say - it should go through my tree, as it's generic
ARM changes, and as very little (even generic stuff) seems to come through
my tree anymore.  But that's going to make the remainder of your patches
difficult to merge.

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Jason Cooper]

On Mon, Nov 19, 2012 at 09:19:12AM +0000, Russell King - ARM Linux wrote:
> On Sun, Nov 18, 2012 at 10:12:10PM -0500, Jason Cooper wrote:
> > On Fri, Nov 16, 2012 at 10:46:15PM +0100, Gregory CLEMENT wrote:
> > > On 11/14/2012 11:31 PM, Gregory CLEMENT wrote:
> > > > Hello Russell,
> > > > 
> > > > With the 2 changes I have done on according your comments
> > > > do you think you can give your acked-by for this patch?
> > > > 
> > > 
> > > Hello Russell,
> > > 
> > > I didn't have any feedback from you for this version.
> > > If you are fine with this, could you give your Acked-by?
> > > 
> > > 
> > 
> > Gregory,
> > 
> > >From the looks of things, Russell has his head wrapped around buggy
> > sound driver code for the CuBox.  Perhaps Will Deacon or Catalin Marinas
> > would care to weigh in?  I'm reluctant to take the series without an
> > Acked-By from at least one of them.
> 
> Well, I would like to say - it should go through my tree, as it's generic
> ARM changes, and as very little (even generic stuff) seems to come through
> my tree anymore.  But that's going to make the remainder of your patches
> difficult to merge.

We'd really appreciate it if we could take it with your Ack.  This
series and one more that depends on it are my only hold overs for v3.8.

thx,

Jason.

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Gregory CLEMENT]

On 11/19/2012 10:19 AM, Russell King - ARM Linux wrote:
> On Sun, Nov 18, 2012 at 10:12:10PM -0500, Jason Cooper wrote:
>> On Fri, Nov 16, 2012 at 10:46:15PM +0100, Gregory CLEMENT wrote:
>>> On 11/14/2012 11:31 PM, Gregory CLEMENT wrote:
>>>> Hello Russell,
>>>>
>>>> With the 2 changes I have done on according your comments
>>>> do you think you can give your acked-by for this patch?
>>>>
>>>
>>> Hello Russell,
>>>
>>> I didn't have any feedback from you for this version.
>>> If you are fine with this, could you give your Acked-by?
>>>
>>>
>>
>> Gregory,
>>
>> >From the looks of things, Russell has his head wrapped around buggy
>> sound driver code for the CuBox.  Perhaps Will Deacon or Catalin Marinas
>> would care to weigh in?  I'm reluctant to take the series without an
>> Acked-By from at least one of them.
> 
> Well, I would like to say - it should go through my tree, as it's generic
> ARM changes, and as very little (even generic stuff) seems to come through
> my tree anymore.  But that's going to make the remainder of your patches
> difficult to merge.
> 

When I asked if it was possible to Arnd and Olof to take this patch in their tree
with your Acked-by, you didn't raise any objection. At this moment it would have
been possible to rework the patch set. But now I am afraid that we are out of
time to do it in a proper way.

Now if you really want to get this patch through your patch system instead of giving
a acked-by, well then I will do my best, of course, to fulfil your requirements. But
in this case I would have appreciate to be notified earlier.

Thanks,

Gregory

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Catalin Marinas]

Hi Gregory,

On 14 November 2012 22:20, Gregory CLEMENT
<gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> index 94186b6..3fd629d 100644
> --- a/arch/arm/mm/Kconfig
> +++ b/arch/arm/mm/Kconfig
> @@ -352,6 +352,10 @@ config CPU_PJ4
>         select ARM_THUMBEE
>         select CPU_V7
>
> +config CPU_PJ4B
> +       bool
> +       select CPU_V7

With ARMv6 we started just using the generic architecture name for
different processors (i.e. CPU_V6, CPU_V7). Is PJ4B another ARMv7
implementation (like Cortex-A9)?

> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 846d279..a4c0ccf 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -169,6 +169,47 @@ __v7_ca15mp_setup:
>         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
>         mcreq   p15, 0, r0, c1, c0, 1
>  #endif
> +
> +__v7_pj4b_setup:
> +#ifdef CONFIG_CPU_PJ4B
> +
> +#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
> +#define CWF           (1 << 27) /* Disable Critical Word First feature */
> +#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
> +#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
> +
> +#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
> +
> +       /* Auxiliary Debug Modes Control 1 Register */
> +       mrc     p15, 1, r0, c15, c1, 1
> +       orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
> +       orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
> +       orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
> +       bic     r0, r0, #(1 << 2)      @ Disable Static BP
> +       mcr     p15, 1, r0, c15, c1, 1
> +
> +       /* Auxiliary Debug Modes Control 2 Register */
> +       mrc     p15, 1, r0, c15, c1, 2
> +       bic     r0, r0, #(1 << 23)   @ Enable fast LDR.
> +       orr     r0, r0, #AUX_DBG_CTRL2
> +       mcr     p15, 1, r0, c15, c1, 2
> +
> +       /* Auxiliary Functional Modes Control Register 0 */
> +       mrc     p15, 1, r0, c15, c2, 0
> +#ifdef CONFIG_SMP
> +       orr     r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
> +#endif
> +       orr     r0, r0, #(1 << 2)     @ Support L1 parity checking
> +       orr     r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
> +       mcr     p15, 1, r0, c15, c2, 0
> +
> +       /* Auxiliary Debug Modes Control 0 Register */
> +       mrc     p15, 1, r0, c15, c1, 0
> +       orr     r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
> +       mcr     p15, 1, r0, c15, c1, 0

Any chance that these could be set by the firmware prior to starting
the kernel? We don't have any guidance for Linux here but longer term
it seems to cause problems (i.e. you add some secure layer in a new
CPU version).

-- 
Catalin

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Gregory CLEMENT]

On 11/19/2012 11:51 AM, Catalin Marinas wrote:
> Hi Gregory,
> 
> On 14 November 2012 22:20, Gregory CLEMENT
> <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
>> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
>> index 94186b6..3fd629d 100644
>> --- a/arch/arm/mm/Kconfig
>> +++ b/arch/arm/mm/Kconfig
>> @@ -352,6 +352,10 @@ config CPU_PJ4
>>         select ARM_THUMBEE
>>         select CPU_V7
>>
>> +config CPU_PJ4B
>> +       bool
>> +       select CPU_V7
> 
> With ARMv6 we started just using the generic architecture name for
> different processors (i.e. CPU_V6, CPU_V7). Is PJ4B another ARMv7
> implementation (like Cortex-A9)?

Yes it is.

> 
>> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
>> index 846d279..a4c0ccf 100644
>> --- a/arch/arm/mm/proc-v7.S
>> +++ b/arch/arm/mm/proc-v7.S
>> @@ -169,6 +169,47 @@ __v7_ca15mp_setup:
>>         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
>>         mcreq   p15, 0, r0, c1, c0, 1
>>  #endif
>> +
>> +__v7_pj4b_setup:
>> +#ifdef CONFIG_CPU_PJ4B
>> +
>> +#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
>> +#define CWF           (1 << 27) /* Disable Critical Word First feature */
>> +#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
>> +#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
>> +
>> +#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
>> +
>> +       /* Auxiliary Debug Modes Control 1 Register */
>> +       mrc     p15, 1, r0, c15, c1, 1
>> +       orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
>> +       orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
>> +       orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
>> +       bic     r0, r0, #(1 << 2)      @ Disable Static BP
>> +       mcr     p15, 1, r0, c15, c1, 1
>> +
>> +       /* Auxiliary Debug Modes Control 2 Register */
>> +       mrc     p15, 1, r0, c15, c1, 2
>> +       bic     r0, r0, #(1 << 23)   @ Enable fast LDR.
>> +       orr     r0, r0, #AUX_DBG_CTRL2
>> +       mcr     p15, 1, r0, c15, c1, 2
>> +
>> +       /* Auxiliary Functional Modes Control Register 0 */
>> +       mrc     p15, 1, r0, c15, c2, 0
>> +#ifdef CONFIG_SMP
>> +       orr     r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
>> +#endif
>> +       orr     r0, r0, #(1 << 2)     @ Support L1 parity checking
>> +       orr     r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
>> +       mcr     p15, 1, r0, c15, c2, 0
>> +
>> +       /* Auxiliary Debug Modes Control 0 Register */
>> +       mrc     p15, 1, r0, c15, c1, 0
>> +       orr     r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
>> +       mcr     p15, 1, r0, c15, c1, 0
> 
> Any chance that these could be set by the firmware prior to starting
> the kernel? We don't have any guidance for Linux here but longer term
> it seems to cause problems (i.e. you add some secure layer in a new
> CPU version).
> 

I will ask to Marvell engineers.

However I hope it won't be show stopper for merging this code in 3.8.
This patch set was released 7 weeks ago, so would have though there was
a lot of time to raise the issue related to this code.

That's said, if the change to be done are small enough it could be done
as a fix for the 3.8 release candidate.

Thanks,
Gregory

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Catalin Marinas]

On Mon, Nov 19, 2012 at 12:18:14PM +0000, Gregory CLEMENT wrote:
> On 11/19/2012 11:51 AM, Catalin Marinas wrote:
> > On 14 November 2012 22:20, Gregory CLEMENT
> > <gregory.clement@free-electrons.com> wrote:
> >> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> >> index 846d279..a4c0ccf 100644
> >> --- a/arch/arm/mm/proc-v7.S
> >> +++ b/arch/arm/mm/proc-v7.S
> >> @@ -169,6 +169,47 @@ __v7_ca15mp_setup:
> >>         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
> >>         mcreq   p15, 0, r0, c1, c0, 1
> >>  #endif
> >> +
> >> +__v7_pj4b_setup:
> >> +#ifdef CONFIG_CPU_PJ4B
> >> +
> >> +#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
> >> +#define CWF           (1 << 27) /* Disable Critical Word First feature */
> >> +#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
> >> +#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
> >> +
> >> +#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
> >> +
> >> +       /* Auxiliary Debug Modes Control 1 Register */
> >> +       mrc     p15, 1, r0, c15, c1, 1
> >> +       orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
> >> +       orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
> >> +       orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
> >> +       bic     r0, r0, #(1 << 2)      @ Disable Static BP
> >> +       mcr     p15, 1, r0, c15, c1, 1
> >> +
> >> +       /* Auxiliary Debug Modes Control 2 Register */
> >> +       mrc     p15, 1, r0, c15, c1, 2
> >> +       bic     r0, r0, #(1 << 23)   @ Enable fast LDR.
> >> +       orr     r0, r0, #AUX_DBG_CTRL2
> >> +       mcr     p15, 1, r0, c15, c1, 2

BTW, for some bits you defined macros while others are just immediate
values. Just a cosmetic inconsistency (I would have preferred to use
either macros or just immediate values).

> >> +
> >> +       /* Auxiliary Functional Modes Control Register 0 */
> >> +       mrc     p15, 1, r0, c15, c2, 0
> >> +#ifdef CONFIG_SMP
> >> +       orr     r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
> >> +#endif
> >> +       orr     r0, r0, #(1 << 2)     @ Support L1 parity checking
> >> +       orr     r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
> >> +       mcr     p15, 1, r0, c15, c2, 0
> >> +
> >> +       /* Auxiliary Debug Modes Control 0 Register */
> >> +       mrc     p15, 1, r0, c15, c1, 0
> >> +       orr     r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
> >> +       mcr     p15, 1, r0, c15, c1, 0
> > 
> > Any chance that these could be set by the firmware prior to starting
> > the kernel? We don't have any guidance for Linux here but longer term
> > it seems to cause problems (i.e. you add some secure layer in a new
> > CPU version).
> 
> I will ask to Marvell engineers.
> 
> However I hope it won't be show stopper for merging this code in 3.8.
> This patch set was released 7 weeks ago, so would have though there was
> a lot of time to raise the issue related to this code.

It shouldn't prevent the code being merged as we don't have clear
requirement in Linux for this. But it would be good practice to push
some sane defaults to the firmware. For example you set some option like
L1 replacement which is optimal for your platform. Later you put the
same CPU on a different SoC which may have different optimal value.
There is no way in proc-v7.S to detect the SoC.

Otherwise the patch looks fine to me.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

Re: [PATCH V3 4/5] arm: mm: Added support for PJ4B cpu and init routines

[Gregory CLEMENT]

On 11/19/2012 03:50 PM, Catalin Marinas wrote:
> On Mon, Nov 19, 2012 at 12:18:14PM +0000, Gregory CLEMENT wrote:
>> On 11/19/2012 11:51 AM, Catalin Marinas wrote:
>>> On 14 November 2012 22:20, Gregory CLEMENT
>>> <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
>>>> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
>>>> index 846d279..a4c0ccf 100644
>>>> --- a/arch/arm/mm/proc-v7.S
>>>> +++ b/arch/arm/mm/proc-v7.S
>>>> @@ -169,6 +169,47 @@ __v7_ca15mp_setup:
>>>>         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
>>>>         mcreq   p15, 0, r0, c1, c0, 1
>>>>  #endif
>>>> +
>>>> +__v7_pj4b_setup:
>>>> +#ifdef CONFIG_CPU_PJ4B
>>>> +
>>>> +#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
>>>> +#define CWF           (1 << 27) /* Disable Critical Word First feature */
>>>> +#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
>>>> +#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
>>>> +
>>>> +#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
>>>> +
>>>> +       /* Auxiliary Debug Modes Control 1 Register */
>>>> +       mrc     p15, 1, r0, c15, c1, 1
>>>> +       orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
>>>> +       orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
>>>> +       orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
>>>> +       bic     r0, r0, #(1 << 2)      @ Disable Static BP
>>>> +       mcr     p15, 1, r0, c15, c1, 1
>>>> +
>>>> +       /* Auxiliary Debug Modes Control 2 Register */
>>>> +       mrc     p15, 1, r0, c15, c1, 2
>>>> +       bic     r0, r0, #(1 << 23)   @ Enable fast LDR.
>>>> +       orr     r0, r0, #AUX_DBG_CTRL2
>>>> +       mcr     p15, 1, r0, c15, c1, 2
> 
> BTW, for some bits you defined macros while others are just immediate
> values. Just a cosmetic inconsistency (I would have preferred to use
> either macros or just immediate values).

Oh yes indeed: I made some change after Russell comments. But I should
have review the whole code to notice it. If I didn't have time to change
the code before the merge, I will fix it for the v3.8-rc1

> 
>>>> +
>>>> +       /* Auxiliary Functional Modes Control Register 0 */
>>>> +       mrc     p15, 1, r0, c15, c2, 0
>>>> +#ifdef CONFIG_SMP
>>>> +       orr     r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
>>>> +#endif
>>>> +       orr     r0, r0, #(1 << 2)     @ Support L1 parity checking
>>>> +       orr     r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
>>>> +       mcr     p15, 1, r0, c15, c2, 0
>>>> +
>>>> +       /* Auxiliary Debug Modes Control 0 Register */
>>>> +       mrc     p15, 1, r0, c15, c1, 0
>>>> +       orr     r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
>>>> +       mcr     p15, 1, r0, c15, c1, 0
>>>
>>> Any chance that these could be set by the firmware prior to starting
>>> the kernel? We don't have any guidance for Linux here but longer term
>>> it seems to cause problems (i.e. you add some secure layer in a new
>>> CPU version).
>>
>> I will ask to Marvell engineers.
>>
>> However I hope it won't be show stopper for merging this code in 3.8.
>> This patch set was released 7 weeks ago, so would have though there was
>> a lot of time to raise the issue related to this code.
> 
> It shouldn't prevent the code being merged as we don't have clear
> requirement in Linux for this. But it would be good practice to push
> some sane defaults to the firmware. For example you set some option like
> L1 replacement which is optimal for your platform. Later you put the
> same CPU on a different SoC which may have different optimal value.
> There is no way in proc-v7.S to detect the SoC.
> 

OK I see your point. At this stage that would imply to change the bootloader
already deployed. I don't know how it will be easy to do it quickly. So
I am not sure that we can change it immediately, but maybe for future release.
However I still wait for more feedback on this subject for Marvell.

> Otherwise the patch looks fine to me.
> 
> Acked-by: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>

Thanks a lot!


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH V3 5/5] arm: mvebu: Added SMP support for Armada XP

[Gregory CLEMENT]

From: Yehuda Yitschak <yehuday@marvell.com>

1. added smp init functions in platsmp.c
2. added secondary cpu entry point in headsmp.S
3. added hotplog initial support in hotplug.c
4. added SMP support for PJ4B cpu

Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/boot/dts/armada-xp.dtsi    |    4 ++
 arch/arm/configs/mvebu_defconfig    |    3 +
 arch/arm/mach-mvebu/Kconfig         |    1 +
 arch/arm/mach-mvebu/Makefile        |    2 +
 arch/arm/mach-mvebu/armada-370-xp.c |    3 +
 arch/arm/mach-mvebu/common.h        |    3 +
 arch/arm/mach-mvebu/headsmp.S       |   66 +++++++++++++++++++
 arch/arm/mach-mvebu/hotplug.c       |   30 +++++++++
 arch/arm/mach-mvebu/platsmp.c       |  124 +++++++++++++++++++++++++++++++++++
 9 files changed, 236 insertions(+)
 create mode 100644 arch/arm/mach-mvebu/headsmp.S
 create mode 100644 arch/arm/mach-mvebu/hotplug.c
 create mode 100644 arch/arm/mach-mvebu/platsmp.c

diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 531619f..7f968dc 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -38,24 +38,28 @@
 	    #size-cells = <0>;
 
 	    cpu@0 {
+		device_type = "cpu";
 	       	compatible = "marvell,sheeva-v7";
 		reg = <0>;
 		clocks = <&cpuclk 0>;
 	    };
 
 	    cpu@1 {
+		device_type = "cpu";
 		compatible = "marvell,sheeva-v7";
 		reg = <1>;
 		clocks = <&cpuclk 1>;
 	    };
 
 	    cpu@2 {
+		device_type = "cpu";
 		compatible = "marvell,sheeva-v7";
 		reg = <2>;
 		clocks = <&cpuclk 2>;
 	    };
 
 	    cpu@3 {
+		device_type = "cpu";
 		compatible = "marvell,sheeva-v7";
 		reg = <3>;
 		clocks = <&cpuclk 3>;
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 3458752..da598d3 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -12,6 +12,9 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 # CONFIG_CACHE_L2X0 is not set
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SMP=y
+# CONFIG_LOCAL_TIMERS is not set
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 # CONFIG_COMPACTION is not set
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 9bfaa0c..d70afe3 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -22,6 +22,7 @@ config MVEBU_CLK_CPU
 config MACH_ARMADA_370_XP
 	bool
 	select ARMADA_370_XP_TIMER
+	select HAVE_SMP
 	select CPU_PJ4B
 
 config MACH_ARMADA_370
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 8e6e50b..eb3cbd1 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -3,3 +3,5 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 
 obj-y += system-controller.o
 obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o pmsu.o
+obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 2af6ce5..66befa1 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -22,6 +22,7 @@
 #include <asm/mach/time.h>
 #include "armada-370-xp.h"
 #include "common.h"
+#include "coherency.h"
 
 static struct map_desc armada_370_xp_io_desc[] __initdata = {
 	{
@@ -50,6 +51,7 @@ struct sys_timer armada_370_xp_timer = {
 static void __init armada_370_xp_dt_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	coherency_init();
 }
 
 static const char * const armada_370_xp_dt_board_dt_compat[] = {
@@ -59,6 +61,7 @@ static const char * const armada_370_xp_dt_board_dt_compat[] = {
 };
 
 DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
+	.smp		= smp_ops(armada_xp_smp_ops),
 	.init_machine	= armada_370_xp_dt_init,
 	.map_io		= armada_370_xp_map_io,
 	.init_irq	= armada_370_xp_init_irq,
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index 74ee0b2..86484bb 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -21,7 +21,10 @@ void mvebu_clocks_init(void);
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
 
+void armada_xp_cpu_die(unsigned int cpu);
 
 int armada_370_xp_coherency_init(void);
 int armada_370_xp_pmsu_init(void);
+void armada_xp_secondary_startup(void);
+extern struct smp_operations armada_xp_smp_ops;
 #endif
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
new file mode 100644
index 0000000..33db1d5
--- /dev/null
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -0,0 +1,66 @@
+/*
+ * SMP support: Entry point for secondary CPUs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file implements the assembly entry point for secondary CPUs
+ * in an SMP kernel. The only thing we need to do is to add the CPU
+ * to the coherency fabric by writing to 2 registers. Currently these
+ * register addresses are hard coded due to the early initialisation problems.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+/*
+ * At this stage the secondary CPUs don't have acces yet to the MMU, so
+ * we have to provide physical addresses
+ */
+#define ARMADA_XP_COHERENCY_FABRIC_CTL_REG 0xD0020200
+#define ARMADA_XP_COHERENCY_FABRIC_CFG_REG 0xD0020204
+
+	__INIT
+
+/*
+ * Armada XP specific entry point for secondary CPUs.
+ * We add the CPU to the coherency fabric and then jump to secondary
+ * startup
+ */
+
+ENTRY(armada_xp_secondary_startup)
+
+	/* Read CPU id */
+ 	mrc     p15, 0, r1, c0, c0, 5
+	and     r1, r1, #0xF
+
+	/* Add CPU to coherency fabric */
+
+	/* Create bit by cpu index */
+	mov     r2,r1
+	add     r2,r2,#24
+	mov     r3, #1
+	lsl     r3, r3, r2
+
+	/* Add CPU to SMP group - Atomic */
+	ldr     r0, = ARMADA_XP_COHERENCY_FABRIC_CTL_REG
+	ldr     r10, [r0]
+	orr     r10 , r10, r3
+	str	r10,[r0]
+
+	/* Enable coherency on CPU - Atomic*/
+	ldr     r0, = ARMADA_XP_COHERENCY_FABRIC_CFG_REG
+	ldr     r10, [r0]
+	orr     r10 , r10, r3
+	str     r10,[r0]
+
+	b	secondary_startup
+
+ENDPROC(armada_xp_secondary_startup)
diff --git a/arch/arm/mach-mvebu/hotplug.c b/arch/arm/mach-mvebu/hotplug.c
new file mode 100644
index 0000000..b228b6a
--- /dev/null
+++ b/arch/arm/mach-mvebu/hotplug.c
@@ -0,0 +1,30 @@
+/*
+ * Symmetric Multi Processing (SMP) support for Armada XP
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/proc-fns.h>
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __ref armada_xp_cpu_die(unsigned int cpu)
+{
+	cpu_do_idle();
+
+	/* We should never return from idle */
+	panic("mvebu: cpu %d unexpectedly exit from shutdown\n", cpu);
+}
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
new file mode 100644
index 0000000..1cd6c08
--- /dev/null
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -0,0 +1,124 @@
+/*
+ * Symmetric Multi Processing (SMP) support for Armada XP
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
+ * This file implements the routines for preparing the SMP infrastructure
+ * and waking up the secondary CPUs
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include "common.h"
+#include "armada-370-xp.h"
+#include "pmsu.h"
+#include "coherency.h"
+
+void __init set_secondary_cpus_clock(void)
+{
+	int cpu;
+	unsigned long rate;
+	struct clk *cpu_clk = NULL;
+	struct device_node *np = NULL;
+
+	cpu = smp_processor_id();
+	np = of_find_node_by_type(np, "cpu");
+	np = NULL;
+	while ((np = of_find_node_by_type(np, "cpu"))) {
+		const u32 *reg;
+		int len;
+		reg = of_get_property(np, "reg", &len);
+		if (!reg || len != 4) {
+			pr_err("%s missing reg property\n", np->full_name);
+			continue;
+		}
+		if (be32_to_cpup(reg) == cpu) {
+			cpu_clk = of_clk_get(np, 0);
+			break;
+		}
+	}
+	WARN_ON(IS_ERR(cpu_clk));
+	clk_prepare_enable(cpu_clk);
+	rate = clk_get_rate(cpu_clk);
+
+	/* set all the other CPU clk to the same rate than the boot CPU */
+	np = NULL;
+	while ((np = of_find_node_by_type(np, "cpu"))) {
+		const u32 *reg;
+		int len;
+		reg = of_get_property(np, "reg", &len);
+		if (!reg || len != 4) {
+			pr_err("%s missing reg property\n", np->full_name);
+			continue;
+		}
+		if (be32_to_cpup(reg) != cpu) {
+			cpu_clk = of_clk_get(np, 0);
+			clk_set_rate(cpu_clk, rate);
+		}
+	}
+}
+
+static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
+{
+	armada_xp_mpic_smp_cpu_init();
+}
+
+static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
+					      struct task_struct *idle)
+{
+	pr_info("Booting CPU %d\n", cpu);
+
+	armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
+
+	return 0;
+}
+
+static void __init armada_xp_smp_init_cpus(void)
+{
+	unsigned int i, ncores;
+	ncores = coherency_get_cpu_count();
+
+	/* Limit possbile CPUs to defconfig */
+	if (ncores > nr_cpu_ids) {
+		pr_warn("SMP: %d CPUs physically present. Only %d configured.",
+			ncores, nr_cpu_ids);
+		pr_warn("Clipping CPU count to %d\n", nr_cpu_ids);
+		ncores = nr_cpu_ids;
+	}
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+
+	set_smp_cross_call(armada_mpic_send_doorbell);
+}
+
+void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
+{
+	set_secondary_cpus_clock();
+	flush_cache_all();
+	set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
+}
+
+struct smp_operations armada_xp_smp_ops __initdata = {
+	.smp_init_cpus		= armada_xp_smp_init_cpus,
+	.smp_prepare_cpus	= armada_xp_smp_prepare_cpus,
+	.smp_secondary_init	= armada_xp_secondary_init,
+	.smp_boot_secondary	= armada_xp_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_die		= armada_xp_cpu_die,
+#endif
+};
-- 
1.7.9.5

Re: [PATCH V3 5/5] arm: mvebu: Added SMP support for Armada XP

[Hui Wang]

Gregory CLEMENT wrote:
> From: Yehuda Yitschak <yehuday@marvell.com>
>
> 1. added smp init functions in platsmp.c
> 2. added secondary cpu entry point in headsmp.S
> 3. added hotplog initial support in hotplug.c
> 4. added SMP support for PJ4B cpu
>
> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-xp.dtsi    |    4 ++
>  arch/arm/configs/mvebu_defconfig    |    3 +
>  arch/arm/mach-mvebu/Kconfig         |    1 +
>  arch/arm/mach-mvebu/Makefile        |    2 +
>  arch/arm/mach-mvebu/armada-370-xp.c |    3 +
>  arch/arm/mach-mvebu/common.h        |    3 +
>  arch/arm/mach-mvebu/headsmp.S       |   66 +++++++++++++++++++
>  arch/arm/mach-mvebu/hotplug.c       |   30 +++++++++
>  arch/arm/mach-mvebu/platsmp.c       |  124 +++++++++++++++++++++++++++++++++++
>  9 files changed, 236 insertions(+)
>  create mode 100644 arch/arm/mach-mvebu/headsmp.S
>  create mode 100644 arch/arm/mach-mvebu/hotplug.c
>  create mode 100644 arch/arm/mach-mvebu/platsmp.c
>
> diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
> index 531619f..7f968dc 100644
> --- a/arch/arm/boot/dts/armada-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-xp.dtsi
> @@ -38,24 +38,28 @@
>  	    #size-cells = <0>;
>  
>  	    cpu@0 {
> +		device_type = "cpu";
>  	       	compatible = "marvell,sheeva-v7";
>  		reg = <0>;
>  		clocks = <&cpuclk 0>;
>  	    };
>  
>  	    cpu@1 {
> +		device_type = "cpu";
>  		compatible = "marvell,sheeva-v7";
>  		reg = <1>;
>  		clocks = <&cpuclk 1>;
>  	    };
>  
>  	    cpu@2 {
> +		device_type = "cpu";
>  		compatible = "marvell,sheeva-v7";
>  		reg = <2>;
>  		clocks = <&cpuclk 2>;
>  	    };
>  
>  	    cpu@3 {
> +		device_type = "cpu";
>  		compatible = "marvell,sheeva-v7";
>  		reg = <3>;
>  		clocks = <&cpuclk 3>;
> diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
> index 3458752..da598d3 100644
> --- a/arch/arm/configs/mvebu_defconfig
> +++ b/arch/arm/configs/mvebu_defconfig
> @@ -12,6 +12,9 @@ CONFIG_ARCH_MVEBU=y
>  CONFIG_MACH_ARMADA_370=y
>  CONFIG_MACH_ARMADA_XP=y
>  # CONFIG_CACHE_L2X0 is not set
> +# CONFIG_SWP_EMULATE is not set
> +CONFIG_SMP=y
> +# CONFIG_LOCAL_TIMERS is not set
>  CONFIG_AEABI=y
>  CONFIG_HIGHMEM=y
>  # CONFIG_COMPACTION is not set
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 9bfaa0c..d70afe3 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -22,6 +22,7 @@ config MVEBU_CLK_CPU
>  config MACH_ARMADA_370_XP
>  	bool
>  	select ARMADA_370_XP_TIMER
> +	select HAVE_SMP
>  	select CPU_PJ4B
>  
>  config MACH_ARMADA_370
> diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
> index 8e6e50b..eb3cbd1 100644
> --- a/arch/arm/mach-mvebu/Makefile
> +++ b/arch/arm/mach-mvebu/Makefile
> @@ -3,3 +3,5 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
>  
>  obj-y += system-controller.o
>  obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o pmsu.o
> +obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
> +obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
> diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
> index 2af6ce5..66befa1 100644
> --- a/arch/arm/mach-mvebu/armada-370-xp.c
> +++ b/arch/arm/mach-mvebu/armada-370-xp.c
> @@ -22,6 +22,7 @@
>  #include <asm/mach/time.h>
>  #include "armada-370-xp.h"
>  #include "common.h"
> +#include "coherency.h"
>  
>  static struct map_desc armada_370_xp_io_desc[] __initdata = {
>  	{
> @@ -50,6 +51,7 @@ struct sys_timer armada_370_xp_timer = {
>  static void __init armada_370_xp_dt_init(void)
>  {
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +	coherency_init();
>  }
>  
>  static const char * const armada_370_xp_dt_board_dt_compat[] = {
> @@ -59,6 +61,7 @@ static const char * const armada_370_xp_dt_board_dt_compat[] = {
>  };
>  
>  DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
> +	.smp		= smp_ops(armada_xp_smp_ops),
>  	.init_machine	= armada_370_xp_dt_init,
>  	.map_io		= armada_370_xp_map_io,
>  	.init_irq	= armada_370_xp_init_irq,
> diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
> index 74ee0b2..86484bb 100644
> --- a/arch/arm/mach-mvebu/common.h
> +++ b/arch/arm/mach-mvebu/common.h
> @@ -21,7 +21,10 @@ void mvebu_clocks_init(void);
>  void armada_370_xp_init_irq(void);
>  void armada_370_xp_handle_irq(struct pt_regs *regs);
>  
> +void armada_xp_cpu_die(unsigned int cpu);
>  
>  int armada_370_xp_coherency_init(void);
>  int armada_370_xp_pmsu_init(void);
> +void armada_xp_secondary_startup(void);
> +extern struct smp_operations armada_xp_smp_ops;
>  #endif
> diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
> new file mode 100644
> index 0000000..33db1d5
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/headsmp.S
> @@ -0,0 +1,66 @@
> +/*
> + * SMP support: Entry point for secondary CPUs
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Yehuda Yitschak <yehuday@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + *
> + * This file implements the assembly entry point for secondary CPUs
> + * in an SMP kernel. The only thing we need to do is to add the CPU
> + * to the coherency fabric by writing to 2 registers. Currently these
> + * register addresses are hard coded due to the early initialisation problems.
> + */
> +
> +#include <linux/linkage.h>
> +#include <linux/init.h>
> +
> +/*
> + * At this stage the secondary CPUs don't have acces yet to the MMU, so
> + * we have to provide physical addresses
> + */
> +#define ARMADA_XP_COHERENCY_FABRIC_CTL_REG 0xD0020200
> +#define ARMADA_XP_COHERENCY_FABRIC_CFG_REG 0xD0020204
> +
> +	__INIT
> +
> +/*
> + * Armada XP specific entry point for secondary CPUs.
> + * We add the CPU to the coherency fabric and then jump to secondary
> + * startup
> + */
> +
> +ENTRY(armada_xp_secondary_startup)
> +
> +	/* Read CPU id */
> + 	mrc     p15, 0, r1, c0, c0, 5
> +	and     r1, r1, #0xF
> +
> +	/* Add CPU to coherency fabric */
> +
> +	/* Create bit by cpu index */
> +	mov     r2,r1
> +	add     r2,r2,#24
> +	mov     r3, #1
> +	lsl     r3, r3, r2
> +
> +	/* Add CPU to SMP group - Atomic */
> +	ldr     r0, = ARMADA_XP_COHERENCY_FABRIC_CTL_REG
> +	ldr     r10, [r0]
> +	orr     r10 , r10, r3
> +	str	r10,[r0]
> +
> +	/* Enable coherency on CPU - Atomic*/
> +	ldr     r0, = ARMADA_XP_COHERENCY_FABRIC_CFG_REG
> +	ldr     r10, [r0]
> +	orr     r10 , r10, r3
> +	str     r10,[r0]
> +
> +	b	secondary_startup
> +
> +ENDPROC(armada_xp_secondary_startup)
> diff --git a/arch/arm/mach-mvebu/hotplug.c b/arch/arm/mach-mvebu/hotplug.c
> new file mode 100644
> index 0000000..b228b6a
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/hotplug.c
> @@ -0,0 +1,30 @@
> +/*
> + * Symmetric Multi Processing (SMP) support for Armada XP
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/kernel.h>
> +#include <linux/errno.h>
> +#include <linux/smp.h>
> +#include <asm/proc-fns.h>
> +
> +/*
> + * platform-specific code to shutdown a CPU
> + *
> + * Called with IRQs disabled
> + */
> +void __ref armada_xp_cpu_die(unsigned int cpu)
> +{
> +	cpu_do_idle();
> +
> +	/* We should never return from idle */
> +	panic("mvebu: cpu %d unexpectedly exit from shutdown\n", cpu);
> +}
> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
> new file mode 100644
> index 0000000..1cd6c08
> --- /dev/null
> +++ b/arch/arm/mach-mvebu/platsmp.c
> @@ -0,0 +1,124 @@
> +/*
> + * Symmetric Multi Processing (SMP) support for Armada XP
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Yehuda Yitschak <yehuday@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + *
> + * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
> + * This file implements the routines for preparing the SMP infrastructure
> + * and waking up the secondary CPUs
> + */
> +
> +#include <linux/init.h>
> +#include <linux/smp.h>
> +#include <linux/clk.h>
> +#include <linux/of.h>
> +#include <asm/cacheflush.h>
> +#include <asm/smp_plat.h>
> +#include "common.h"
> +#include "armada-370-xp.h"
> +#include "pmsu.h"
> +#include "coherency.h"
> +
> +void __init set_secondary_cpus_clock(void)
> +{
> +	int cpu;
> +	unsigned long rate;
> +	struct clk *cpu_clk = NULL;
> +	struct device_node *np = NULL;
> +
> +	cpu = smp_processor_id();
> +	np = of_find_node_by_type(np, "cpu");
> +	np = NULL;
> +	while ((np = of_find_node_by_type(np, "cpu"))) {
> +		const u32 *reg;
> +		int len;
> +		reg = of_get_property(np, "reg", &len);
> +		if (!reg || len != 4) {
> +			pr_err("%s missing reg property\n", np->full_name);
> +			continue;
> +		}
> +		if (be32_to_cpup(reg) == cpu) {
> +			cpu_clk = of_clk_get(np, 0);
> +			break;
> +		}
> +	}
> +	WARN_ON(IS_ERR(cpu_clk));
> +	clk_prepare_enable(cpu_clk);
> +	rate = clk_get_rate(cpu_clk);
> +
> +	/* set all the other CPU clk to the same rate than the boot CPU */
> +	np = NULL;
> +	while ((np = of_find_node_by_type(np, "cpu"))) {
> +		const u32 *reg;
> +		int len;
> +		reg = of_get_property(np, "reg", &len);
> +		if (!reg || len != 4) {
> +			pr_err("%s missing reg property\n", np->full_name);
> +			continue;
> +		}
> +		if (be32_to_cpup(reg) != cpu) {
> +			cpu_clk = of_clk_get(np, 0);
> +			clk_set_rate(cpu_clk, rate);
> +		}
> +	}
> +}
> +
> +static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
> +{
> +	armada_xp_mpic_smp_cpu_init();
> +}
> +
> +static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
> +					      struct task_struct *idle)
> +{
> +	pr_info("Booting CPU %d\n", cpu);
> +
> +	armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
>   
Where is this function implemented?

Re: [PATCH V3 5/5] arm: mvebu: Added SMP support for Armada XP

[Hui Wang]

Hui Wang wrote:
> Gregory CLEMENT wrote:
>> From: Yehuda Yitschak <yehuday@marvell.com>
>>
>> 1. added smp init functions in platsmp.c
>> 2. added secondary cpu entry point in headsmp.S
>> 3. added hotplog initial support in hotplug.c
>> 4. added SMP support for PJ4B cpu
>>
>> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>> ---
>> arch/arm/boot/dts/armada-xp.dtsi | 4 ++
>> arch/arm/configs/mvebu_defconfig | 3 +
>> arch/arm/mach-mvebu/Kconfig | 1 +
>> arch/arm/mach-mvebu/Makefile | 2 +
>> arch/arm/mach-mvebu/armada-370-xp.c | 3 +
>> arch/arm/mach-mvebu/common.h | 3 +
>> arch/arm/mach-mvebu/headsmp.S | 66 +++++++++++++++++++
>> arch/arm/mach-mvebu/hotplug.c | 30 +++++++++
>> arch/arm/mach-mvebu/platsmp.c | 124 +++++++++++++++++++++++++++++++++++
>> 9 files changed, 236 insertions(+)
>> create mode 100644 arch/arm/mach-mvebu/headsmp.S
>> create mode 100644 arch/arm/mach-mvebu/hotplug.c
>> create mode 100644 arch/arm/mach-mvebu/platsmp.c
>>
>> diff --git a/arch/arm/boot/dts/armada-xp.dtsi 
>> b/arch/arm/boot/dts/armada-xp.dtsi
>> index 531619f..7f968dc 100644
>> --- a/arch/arm/boot/dts/armada-xp.dtsi
>> +++ b/arch/arm/boot/dts/armada-xp.dtsi
>> @@ -38,24 +38,28 @@
>> #size-cells = <0>;
>>
>> cpu@0 {
>> + device_type = "cpu";
>> compatible = "marvell,sheeva-v7";
>> reg = <0>;
>> clocks = <&cpuclk 0>;
>> };
>>
>> cpu@1 {
>> + device_type = "cpu";
>> compatible = "marvell,sheeva-v7";
>> reg = <1>;
>> clocks = <&cpuclk 1>;
>> };
>>
>> cpu@2 {
>> + device_type = "cpu";
>> compatible = "marvell,sheeva-v7";
>> reg = <2>;
>> clocks = <&cpuclk 2>;
>> };
>>
>> cpu@3 {
>> + device_type = "cpu";
>> compatible = "marvell,sheeva-v7";
>> reg = <3>;
>> clocks = <&cpuclk 3>;
>> diff --git a/arch/arm/configs/mvebu_defconfig 
>> b/arch/arm/configs/mvebu_defconfig
>> index 3458752..da598d3 100644
>> --- a/arch/arm/configs/mvebu_defconfig
>> +++ b/arch/arm/configs/mvebu_defconfig
>> @@ -12,6 +12,9 @@ CONFIG_ARCH_MVEBU=y
>> CONFIG_MACH_ARMADA_370=y
>> CONFIG_MACH_ARMADA_XP=y
>> # CONFIG_CACHE_L2X0 is not set
>> +# CONFIG_SWP_EMULATE is not set
>> +CONFIG_SMP=y
>> +# CONFIG_LOCAL_TIMERS is not set
>> CONFIG_AEABI=y
>> CONFIG_HIGHMEM=y
>> # CONFIG_COMPACTION is not set
>> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
>> index 9bfaa0c..d70afe3 100644
>> --- a/arch/arm/mach-mvebu/Kconfig
>> +++ b/arch/arm/mach-mvebu/Kconfig
>> @@ -22,6 +22,7 @@ config MVEBU_CLK_CPU
>> config MACH_ARMADA_370_XP
>> bool
>> select ARMADA_370_XP_TIMER
>> + select HAVE_SMP
>> select CPU_PJ4B
>>
>> config MACH_ARMADA_370
>> diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
>> index 8e6e50b..eb3cbd1 100644
>> --- a/arch/arm/mach-mvebu/Makefile
>> +++ b/arch/arm/mach-mvebu/Makefile
>> @@ -3,3 +3,5 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := 
>> -I$(srctree)/$(src)/include \
>>
>> obj-y += system-controller.o
>> obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o 
>> irq-armada-370-xp.o addr-map.o coherency.o pmsu.o
>> +obj-$(CONFIG_SMP) += platsmp.o headsmp.o
>> +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
>> diff --git a/arch/arm/mach-mvebu/armada-370-xp.c 
>> b/arch/arm/mach-mvebu/armada-370-xp.c
>> index 2af6ce5..66befa1 100644
>> --- a/arch/arm/mach-mvebu/armada-370-xp.c
>> +++ b/arch/arm/mach-mvebu/armada-370-xp.c
>> @@ -22,6 +22,7 @@
>> #include <asm/mach/time.h>
>> #include "armada-370-xp.h"
>> #include "common.h"
>> +#include "coherency.h"
>>
>> static struct map_desc armada_370_xp_io_desc[] __initdata = {
>> {
>> @@ -50,6 +51,7 @@ struct sys_timer armada_370_xp_timer = {
>> static void __init armada_370_xp_dt_init(void)
>> {
>> of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>> + coherency_init();
>> }
>>
>> static const char * const armada_370_xp_dt_board_dt_compat[] = {
>> @@ -59,6 +61,7 @@ static const char * const 
>> armada_370_xp_dt_board_dt_compat[] = {
>> };
>>
>> DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
>> + .smp = smp_ops(armada_xp_smp_ops),
>> .init_machine = armada_370_xp_dt_init,
>> .map_io = armada_370_xp_map_io,
>> .init_irq = armada_370_xp_init_irq,
>> diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
>> index 74ee0b2..86484bb 100644
>> --- a/arch/arm/mach-mvebu/common.h
>> +++ b/arch/arm/mach-mvebu/common.h
>> @@ -21,7 +21,10 @@ void mvebu_clocks_init(void);
>> void armada_370_xp_init_irq(void);
>> void armada_370_xp_handle_irq(struct pt_regs *regs);
>>
>> +void armada_xp_cpu_die(unsigned int cpu);
>>
>> int armada_370_xp_coherency_init(void);
>> int armada_370_xp_pmsu_init(void);
>> +void armada_xp_secondary_startup(void);
>> +extern struct smp_operations armada_xp_smp_ops;
>> #endif
>> diff --git a/arch/arm/mach-mvebu/headsmp.S 
>> b/arch/arm/mach-mvebu/headsmp.S
>> new file mode 100644
>> index 0000000..33db1d5
>> --- /dev/null
>> +++ b/arch/arm/mach-mvebu/headsmp.S
>> @@ -0,0 +1,66 @@
>> +/*
>> + * SMP support: Entry point for secondary CPUs
>> + *
>> + * Copyright (C) 2012 Marvell
>> + *
>> + * Yehuda Yitschak <yehuday@marvell.com>
>> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
>> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + *
>> + * This file implements the assembly entry point for secondary CPUs
>> + * in an SMP kernel. The only thing we need to do is to add the CPU
>> + * to the coherency fabric by writing to 2 registers. Currently these
>> + * register addresses are hard coded due to the early initialisation 
>> problems.
>> + */
>> +
>> +#include <linux/linkage.h>
>> +#include <linux/init.h>
>> +
>> +/*
>> + * At this stage the secondary CPUs don't have acces yet to the MMU, so
>> + * we have to provide physical addresses
>> + */
>> +#define ARMADA_XP_COHERENCY_FABRIC_CTL_REG 0xD0020200
>> +#define ARMADA_XP_COHERENCY_FABRIC_CFG_REG 0xD0020204
>> +
>> + __INIT
>> +
>> +/*
>> + * Armada XP specific entry point for secondary CPUs.
>> + * We add the CPU to the coherency fabric and then jump to secondary
>> + * startup
>> + */
>> +
>> +ENTRY(armada_xp_secondary_startup)
>> +
>> + /* Read CPU id */
>> + mrc p15, 0, r1, c0, c0, 5
>> + and r1, r1, #0xF
>> +
>> + /* Add CPU to coherency fabric */
>> +
>> + /* Create bit by cpu index */
>> + mov r2,r1
>> + add r2,r2,#24
>> + mov r3, #1
>> + lsl r3, r3, r2
>> +
>> + /* Add CPU to SMP group - Atomic */
>> + ldr r0, = ARMADA_XP_COHERENCY_FABRIC_CTL_REG
>> + ldr r10, [r0]
>> + orr r10 , r10, r3
>> + str r10,[r0]
>> +
>> + /* Enable coherency on CPU - Atomic*/
>> + ldr r0, = ARMADA_XP_COHERENCY_FABRIC_CFG_REG
>> + ldr r10, [r0]
>> + orr r10 , r10, r3
>> + str r10,[r0]
>> +
>> + b secondary_startup
>> +
>> +ENDPROC(armada_xp_secondary_startup)
>> diff --git a/arch/arm/mach-mvebu/hotplug.c 
>> b/arch/arm/mach-mvebu/hotplug.c
>> new file mode 100644
>> index 0000000..b228b6a
>> --- /dev/null
>> +++ b/arch/arm/mach-mvebu/hotplug.c
>> @@ -0,0 +1,30 @@
>> +/*
>> + * Symmetric Multi Processing (SMP) support for Armada XP
>> + *
>> + * Copyright (C) 2012 Marvell
>> + *
>> + * Lior Amsalem <alior@marvell.com>
>> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
>> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +#include <linux/kernel.h>
>> +#include <linux/errno.h>
>> +#include <linux/smp.h>
>> +#include <asm/proc-fns.h>
>> +
>> +/*
>> + * platform-specific code to shutdown a CPU
>> + *
>> + * Called with IRQs disabled
>> + */
>> +void __ref armada_xp_cpu_die(unsigned int cpu)
>> +{
>> + cpu_do_idle();
>> +
>> + /* We should never return from idle */
>> + panic("mvebu: cpu %d unexpectedly exit from shutdown\n", cpu);
>> +}
>> diff --git a/arch/arm/mach-mvebu/platsmp.c 
>> b/arch/arm/mach-mvebu/platsmp.c
>> new file mode 100644
>> index 0000000..1cd6c08
>> --- /dev/null
>> +++ b/arch/arm/mach-mvebu/platsmp.c
>> @@ -0,0 +1,124 @@
>> +/*
>> + * Symmetric Multi Processing (SMP) support for Armada XP
>> + *
>> + * Copyright (C) 2012 Marvell
>> + *
>> + * Lior Amsalem <alior@marvell.com>
>> + * Yehuda Yitschak <yehuday@marvell.com>
>> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
>> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + *
>> + * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
>> + * This file implements the routines for preparing the SMP 
>> infrastructure
>> + * and waking up the secondary CPUs
>> + */
>> +
>> +#include <linux/init.h>
>> +#include <linux/smp.h>
>> +#include <linux/clk.h>
>> +#include <linux/of.h>
>> +#include <asm/cacheflush.h>
>> +#include <asm/smp_plat.h>
>> +#include "common.h"
>> +#include "armada-370-xp.h"
>> +#include "pmsu.h"
>> +#include "coherency.h"
>> +
>> +void __init set_secondary_cpus_clock(void)
>> +{
>> + int cpu;
>> + unsigned long rate;
>> + struct clk *cpu_clk = NULL;
>> + struct device_node *np = NULL;
>> +
>> + cpu = smp_processor_id();
>> + np = of_find_node_by_type(np, "cpu");
>> + np = NULL;
>> + while ((np = of_find_node_by_type(np, "cpu"))) {
>> + const u32 *reg;
>> + int len;
>> + reg = of_get_property(np, "reg", &len);
>> + if (!reg || len != 4) {
>> + pr_err("%s missing reg property\n", np->full_name);
>> + continue;
>> + }
>> + if (be32_to_cpup(reg) == cpu) {
>> + cpu_clk = of_clk_get(np, 0);
>> + break;
>> + }
>> + }
>> + WARN_ON(IS_ERR(cpu_clk));
>> + clk_prepare_enable(cpu_clk);
>> + rate = clk_get_rate(cpu_clk);
>> +
>> + /* set all the other CPU clk to the same rate than the boot CPU */
>> + np = NULL;
>> + while ((np = of_find_node_by_type(np, "cpu"))) {
>> + const u32 *reg;
>> + int len;
>> + reg = of_get_property(np, "reg", &len);
>> + if (!reg || len != 4) {
>> + pr_err("%s missing reg property\n", np->full_name);
>> + continue;
>> + }
>> + if (be32_to_cpup(reg) != cpu) {
>> + cpu_clk = of_clk_get(np, 0);
>> + clk_set_rate(cpu_clk, rate);
>> + }
>> + }
>> +}
>> +
>> +static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
>> +{
>> + armada_xp_mpic_smp_cpu_init();
>> +}
>> +
>> +static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
>> + struct task_struct *idle)
>> +{
>> + pr_info("Booting CPU %d\n", cpu);
>> +
>> + armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
> Where is this function implemented?
>
Sorry, i got it, it is in [patch 2/5]. :-).

>
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> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

Re: [PATCH V3 0/5] SMP support for Armada XP

[Hui Wang]

Sorry for asking a question. Does it support CPU HOTPLUG? I am just 
testing the marvell 2012_Q4.1, and found the CPU HOTPLUG (echo 0|1 > 
/sys/devices/system/cpu/cpu1/online) doesn't work on the XP_GP board, 
does your BSP have the same problem?

Regards,
Hui.

Gregory CLEMENT wrote:
> Hello,
>
> The purpose of this patch set is to add the SMP support for the Armada
> XP SoCs. Beside the SMP support itself brought by the last 3 patches,
> this patch set also adds the support for the coherency fabric unit and
>   

Re: [PATCH V3 0/5] SMP support for Armada XP

[Gregory CLEMENT]

Hello Hui,

On 11/15/2012 09:46 AM, Hui Wang wrote:
> Sorry for asking a question. Does it support CPU HOTPLUG? I am just 
> testing the marvell 2012_Q4.1, and found the CPU HOTPLUG (echo 0|1 > 
> /sys/devices/system/cpu/cpu1/online) doesn't work on the XP_GP board, 
> does your BSP have the same problem?
> 

Indeed, we don't support it yet, but we plan to add this feature once
this "basic" support will be included in the 3.8.

> Regards,
> Hui.
> 
> Gregory CLEMENT wrote:
>> Hello,
>>
>> The purpose of this patch set is to add the SMP support for the Armada
>> XP SoCs. Beside the SMP support itself brought by the last 3 patches,
>> this patch set also adds the support for the coherency fabric unit and
>>   
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH V3 0/5] SMP support for Armada XP

[Hui Wang]

Gregory CLEMENT wrote:
> Hello Hui,
>
> On 11/15/2012 09:46 AM, Hui Wang wrote:
>   
>> Sorry for asking a question. Does it support CPU HOTPLUG? I am just 
>> testing the marvell 2012_Q4.1, and found the CPU HOTPLUG (echo 0|1 > 
>> /sys/devices/system/cpu/cpu1/online) doesn't work on the XP_GP board, 
>> does your BSP have the same problem?
>>
>>     
>
> Indeed, we don't support it yet, but we plan to add this feature once
> this "basic" support will be included in the 3.8.
>
>   
Got it, thanks.

>> Regards,
>> Hui.
>>
>> Gregory CLEMENT wrote:
>>     
>>> Hello,
>>>
>>> The purpose of this patch set is to add the SMP support for the Armada
>>> XP SoCs. Beside the SMP support itself brought by the last 3 patches,
>>> this patch set also adds the support for the coherency fabric unit and
>>>   
>>>       
>
>
>