[PATCH 0/9] ARM: Initial support for Tegra 114 SoC.

[PATCH 0/9] ARM: Initial support for Tegra 114 SoC.

[Hiroshi Doyu]

Hi,

This patchset adds initial support for the NVIDIA's new Tegra 114
SoC (T114) based on the ARM Cortex-A15 MP. It has the minimal support
to allow the kernel to boot up into shell console. This can be used as
a basis for adding other device drivers for this SoC. Currently there
are 2 evaluation boards available, "Dalmore" and "Pluto".

This patchset is against Stephen Warren's linux-next_common branch:

  git://nv-tegra.nvidia.com/user/swarren/linux-2.6 linux-next_common

For those who want to try:

  $ make ARCH=arm tegra_defconfig
  $ scripts/config -e ARCH_TEGRA_114_SOC -d DRM -d SUSPEND \
    	-d PM_RUNTIME -d CPU_FREQ -d CPU_IDLE
  $ make ARCH=arm menuconfig # if needed to configure more
  $ make ARCH=arm all -j9

Verified that this single image booted up with "Dalmore(T114)",
"Pluto(T114)" and "Cardhu(T30)". For "Cardhu(T30)" with this single
image, SPI driver doesn't seem to afford the above configuration , it
hangs at boot-up. With SPI disabled, it's ok.


Hiroshi Doyu (9):
  ARM: tegra: fuse: Add chipid TEGRA114 0x35
  HACK: ARM: tegra: Use CLK_IGNORE_UNUSED for Tegra 114 SoC
  ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU
  clocksource: tegra: Reorganize funcs by clock functionarities
  clocksource: tegra: Enable ARM arch_timer with TSC
  ARM: dt: tegra114: Add new SoC base, Tegra 114 SoC
  ARM: dt: tegra114: Add new board, Dalmore
  ARM: dt: tegra114: Add new board, Pluto
  ARM: tegra: Add initial support for Tegra 114 SoC.

 .../bindings/arm/tegra/nvidia,tegra114-tsc.txt     |   11 +
 arch/arm/boot/dts/Makefile                         |    4 +-
 arch/arm/boot/dts/tegra114-dalmore.dts             |   21 ++
 arch/arm/boot/dts/tegra114-pluto.dts               |   21 ++
 arch/arm/boot/dts/tegra114.dtsi                    |   89 ++++++++
 arch/arm/mach-tegra/Kconfig                        |   10 +
 arch/arm/mach-tegra/Makefile                       |    1 +
 arch/arm/mach-tegra/board-dt-tegra114.c            |   48 +++++
 arch/arm/mach-tegra/common.c                       |    1 +
 arch/arm/mach-tegra/fuse.h                         |    1 +
 arch/arm/mach-tegra/platsmp.c                      |   31 ++-
 arch/arm/mach-tegra/tegra30_clocks_data.c          |    2 +
 drivers/clocksource/tegra20_timer.c                |  222 +++++++++++++-------
 13 files changed, 384 insertions(+), 78 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
 create mode 100644 arch/arm/boot/dts/tegra114-dalmore.dts
 create mode 100644 arch/arm/boot/dts/tegra114-pluto.dts
 create mode 100644 arch/arm/boot/dts/tegra114.dtsi
 create mode 100644 arch/arm/mach-tegra/board-dt-tegra114.c

-- 
1.7.9.5

[PATCH 1/9] ARM: tegra: fuse: Add chipid TEGRA114 0x35

[Hiroshi Doyu]

Add tegra_chip_id TEGRA114 0x35

Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/mach-tegra/fuse.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index ff1383d..da78434 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -37,6 +37,7 @@ enum tegra_revision {
 
 #define TEGRA20		0x20
 #define TEGRA30		0x30
+#define TEGRA114	0x35
 
 extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
-- 
1.7.9.5

[PATCH 2/9] HACK: ARM: tegra: Use CLK_IGNORE_UNUSED for Tegra 114 SoC

[Hiroshi Doyu]

Use CLK_IGNORE_UNUSED for the Tegra 114 SoC to ensure
clk_disable_unused() is not called. Otherwise the system will die,
because the usecount of the clocks is incorrect. This patch will be
reverted once the Tegra 114 clocks are implemented.

Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/mach-tegra/tegra30_clocks_data.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 6942c7a..4865ba5 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1384,6 +1384,8 @@ static void tegra30_init_one_clock(struct clk *c)
 	if (!clk->lookup.dev_id && !clk->lookup.con_id)
 		clk->lookup.con_id = c->name;
 	clk->lookup.clk = c;
+	if (tegra_chip_id == TEGRA114) /* FIXME: Implement T114 clocks */
+		c->flags |= CLK_IGNORE_UNUSED;
 	clkdev_add(&clk->lookup);
 	tegra_clk_add(c);
 }
-- 
1.7.9.5

[PATCH 7/9] ARM: dt: tegra114: Add new board, Dalmore

[Hiroshi Doyu]

Add a new evaluation board, Dalmore for Tegra 114 family.

Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/Makefile             |    3 ++-
 arch/arm/boot/dts/tegra114-dalmore.dts |   21 +++++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/tegra114-dalmore.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ca6fb8e..b37f7c2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -143,7 +143,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra20-ventana.dtb \
 	tegra20-whistler.dtb \
 	tegra30-cardhu-a02.dtb \
-	tegra30-cardhu-a04.dtb
+	tegra30-cardhu-a04.dtb \
+	tegra114-dalmore.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
 	vexpress-v2p-ca9.dtb \
 	vexpress-v2p-ca15-tc1.dtb \
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
new file mode 100644
index 0000000..a30aca6
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+/include/ "tegra114.dtsi"
+
+/ {
+	model = "NVIDIA Tegra114 Dalmore evaluation board";
+	compatible = "nvidia,dalmore", "nvidia,tegra114";
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	serial@70006300 {
+		status = "okay";
+		clock-frequency = <408000000>;
+	};
+
+	pmc {
+		nvidia,invert-interrupt;
+	};
+};
-- 
1.7.9.5

[PATCH 8/9] ARM: dt: tegra114: Add new board, Pluto

[Hiroshi Doyu]

Add a new evaluation board, Pluto for Tegra 114 family.

Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/Makefile           |    3 ++-
 arch/arm/boot/dts/tegra114-pluto.dts |   21 +++++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/tegra114-pluto.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b37f7c2..7e7fde0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -144,7 +144,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra20-whistler.dtb \
 	tegra30-cardhu-a02.dtb \
 	tegra30-cardhu-a04.dtb \
-	tegra114-dalmore.dtb
+	tegra114-dalmore.dtb \
+	tegra114-pluto.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
 	vexpress-v2p-ca9.dtb \
 	vexpress-v2p-ca15-tc1.dtb \
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
new file mode 100644
index 0000000..9bea8f5
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+/include/ "tegra114.dtsi"
+
+/ {
+	model = "NVIDIA Tegra114 Pluto evaluation board";
+	compatible = "nvidia,pluto", "nvidia,tegra114";
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	serial@70006300 {
+		status = "okay";
+		clock-frequency = <408000000>;
+	};
+
+	pmc {
+		nvidia,invert-interrupt;
+	};
+};
-- 
1.7.9.5

[PATCH 9/9] ARM: tegra: Add initial support for Tegra 114 SoC.

[Hiroshi Doyu]

Add new Tegra 114 SoC support.

Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/mach-tegra/Kconfig             |   10 +++++++
 arch/arm/mach-tegra/Makefile            |    1 +
 arch/arm/mach-tegra/board-dt-tegra114.c |   48 +++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/common.c            |    1 +
 4 files changed, 60 insertions(+)
 create mode 100644 arch/arm/mach-tegra/board-dt-tegra114.c

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 56e5dd8..3be5639 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -61,6 +61,16 @@ config ARCH_TEGRA_3x_SOC
 	  Support for NVIDIA Tegra T30 processor family, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
+config ARCH_TEGRA_114_SOC
+	bool "Enable support for Tegra114 family"
+	select ARM_GIC
+	select CPU_V7
+	select ARM_L1_CACHE_SHIFT_6
+	select ARM_ARCH_TIMER
+	help
+	  Support for NVIDIA Tegra T114 processor family, based on the
+	  ARM CortexA15MP CPU
+
 config TEGRA_PCI
 	bool "PCI Express support"
 	depends on ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 8a108ef..3d6f645 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= board-dt-tegra114.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-harmony-pcie.o
 
diff --git a/arch/arm/mach-tegra/board-dt-tegra114.c b/arch/arm/mach-tegra/board-dt-tegra114.c
new file mode 100644
index 0000000..4c36dd0
--- /dev/null
+++ b/arch/arm/mach-tegra/board-dt-tegra114.c
@@ -0,0 +1,48 @@
+/*
+ * NVIDIA Tegra114 device tree board support
+ *
+ * Copyright (C) 2012 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include "board.h"
+#include "common.h"
+
+static void __init tegra114_dt_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const tegra114_dt_board_compat[] = {
+	"nvidia,tegra114",
+	NULL,
+};
+
+DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)")
+	.smp		= smp_ops(tegra_smp_ops),
+	.map_io		= tegra_map_common_io,
+	.init_early	= tegra30_init_early,
+	.init_irq	= tegra_dt_init_irq,
+	.handle_irq	= gic_handle_irq,
+	.init_time	= clocksource_of_init,
+	.init_machine	= tegra114_dt_init,
+	.init_late	= tegra_init_late,
+	.restart	= tegra_assert_system_reset,
+	.dt_compat	= tegra114_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index d54cfc5..debcaf4 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -59,6 +59,7 @@ u32 tegra_uart_config[4] = {
 #ifdef CONFIG_OF
 static const struct of_device_id tegra_dt_irq_match[] __initconst = {
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
+	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init },
 	{ }
 };
 
-- 
1.7.9.5

Re: [PATCH 9/9] ARM: tegra: Add initial support for Tegra 114 SoC.

[Arnd Bergmann]

On Thursday 20 December 2012, Hiroshi Doyu wrote:
> +
> +DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)")
> +       .smp            = smp_ops(tegra_smp_ops),
> +       .map_io         = tegra_map_common_io,
> +       .init_early     = tegra30_init_early,
> +       .init_irq       = tegra_dt_init_irq,
> +       .handle_irq     = gic_handle_irq,
> +       .init_time      = clocksource_of_init,
> +       .init_machine   = tegra114_dt_init,
> +       .init_late      = tegra_init_late,
> +       .restart        = tegra_assert_system_reset,
> +       .dt_compat      = tegra114_dt_board_compat,
> +MACHINE_END

This one is so similar to Tegra30 that I wonder if it's actually worth keeping
them separate still. The only difference I see is the clock initialization.
Maybe that can be factored out to keep this the same as Tegra30.

Or are you planning to add more SoC specific here that would make this harder?

	Arnd

Re: [PATCH 9/9] ARM: tegra: Add initial support for Tegra 114 SoC.

[Hiroshi Doyu]

Arnd Bergmann <arnd@arndb.de> wrote @ Thu, 3 Jan 2013 17:28:19 +0100:

> On Thursday 20 December 2012, Hiroshi Doyu wrote:
> > +
> > +DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)")
> > +       .smp            = smp_ops(tegra_smp_ops),
> > +       .map_io         = tegra_map_common_io,
> > +       .init_early     = tegra30_init_early,
> > +       .init_irq       = tegra_dt_init_irq,
> > +       .handle_irq     = gic_handle_irq,
> > +       .init_time      = clocksource_of_init,
> > +       .init_machine   = tegra114_dt_init,
> > +       .init_late      = tegra_init_late,
> > +       .restart        = tegra_assert_system_reset,
> > +       .dt_compat      = tegra114_dt_board_compat,
> > +MACHINE_END
> 
> This one is so similar to Tegra30 that I wonder if it's actually worth keeping
> them separate still. The only difference I see is the clock initialization.
> Maybe that can be factored out to keep this the same as Tegra30.
> 
> Or are you planning to add more SoC specific here that would make this harder?

That was the original plan, but I'll consider if your proposal works
or not once again. Thanks.

Re: [PATCH 0/9] ARM: Initial support for Tegra 114 SoC.

[Hiroshi Doyu]

Hi Stephen,

Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote @ Thu, 20 Dec 2012 10:43:58 +0100:

> Hi,
> 
> This patchset adds initial support for the NVIDIA's new Tegra 114
> SoC (T114) based on the ARM Cortex-A15 MP. It has the minimal support
> to allow the kernel to boot up into shell console. This can be used as
> a basis for adding other device drivers for this SoC. Currently there
> are 2 evaluation boards available, "Dalmore" and "Pluto".

I'll resend v2 of this series just with /cpus node in DT added. The
rest would be same since TSC initialization and dynamic core
detections are still necessary/valid for Tegra as backup of /cpus DT
failure. Or if you take this series as is first, I'll make a /cpus DT
patchset agaist this series.

> This patchset is against Stephen Warren's linux-next_common branch:
> 
>   git://nv-tegra.nvidia.com/user/swarren/linux-2.6 linux-next_common
> 
> For those who want to try:
> 
>   $ make ARCH=arm tegra_defconfig
>   $ scripts/config -e ARCH_TEGRA_114_SOC -d DRM -d SUSPEND \
>     	-d PM_RUNTIME -d CPU_FREQ -d CPU_IDLE
>   $ make ARCH=arm menuconfig # if needed to configure more
>   $ make ARCH=arm all -j9
> 
> Verified that this single image booted up with "Dalmore(T114)",
> "Pluto(T114)" and "Cardhu(T30)". For "Cardhu(T30)" with this single
> image, SPI driver doesn't seem to afford the above configuration , it
> hangs at boot-up. With SPI disabled, it's ok.
> 
> 
> Hiroshi Doyu (9):
>   ARM: tegra: fuse: Add chipid TEGRA114 0x35
>   HACK: ARM: tegra: Use CLK_IGNORE_UNUSED for Tegra 114 SoC
>   ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU
>   clocksource: tegra: Reorganize funcs by clock functionarities
>   clocksource: tegra: Enable ARM arch_timer with TSC
>   ARM: dt: tegra114: Add new SoC base, Tegra 114 SoC
>   ARM: dt: tegra114: Add new board, Dalmore
>   ARM: dt: tegra114: Add new board, Pluto
>   ARM: tegra: Add initial support for Tegra 114 SoC.
> 
>  .../bindings/arm/tegra/nvidia,tegra114-tsc.txt     |   11 +
>  arch/arm/boot/dts/Makefile                         |    4 +-
>  arch/arm/boot/dts/tegra114-dalmore.dts             |   21 ++
>  arch/arm/boot/dts/tegra114-pluto.dts               |   21 ++
>  arch/arm/boot/dts/tegra114.dtsi                    |   89 ++++++++
>  arch/arm/mach-tegra/Kconfig                        |   10 +
>  arch/arm/mach-tegra/Makefile                       |    1 +
>  arch/arm/mach-tegra/board-dt-tegra114.c            |   48 +++++
>  arch/arm/mach-tegra/common.c                       |    1 +
>  arch/arm/mach-tegra/fuse.h                         |    1 +
>  arch/arm/mach-tegra/platsmp.c                      |   31 ++-
>  arch/arm/mach-tegra/tegra30_clocks_data.c          |    2 +
>  drivers/clocksource/tegra20_timer.c                |  222 +++++++++++++-------
>  13 files changed, 384 insertions(+), 78 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
>  create mode 100644 arch/arm/boot/dts/tegra114-dalmore.dts
>  create mode 100644 arch/arm/boot/dts/tegra114-pluto.dts
>  create mode 100644 arch/arm/boot/dts/tegra114.dtsi
>  create mode 100644 arch/arm/mach-tegra/board-dt-tegra114.c
> 
> -- 
> 1.7.9.5
> 

Re: [PATCH 0/9] ARM: Initial support for Tegra 114 SoC.

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 893 bytes --]

On Thu, Dec 20, 2012 at 11:43:58AM +0200, Hiroshi Doyu wrote:
> Hi,
> 
> This patchset adds initial support for the NVIDIA's new Tegra 114
> SoC (T114) based on the ARM Cortex-A15 MP. It has the minimal support
> to allow the kernel to boot up into shell console. This can be used as
> a basis for adding other device drivers for this SoC. Currently there
> are 2 evaluation boards available, "Dalmore" and "Pluto".
> 
> This patchset is against Stephen Warren's linux-next_common branch:
> 
>   git://nv-tegra.nvidia.com/user/swarren/linux-2.6 linux-next_common
> 
> For those who want to try:
> 
>   $ make ARCH=arm tegra_defconfig
>   $ scripts/config -e ARCH_TEGRA_114_SOC -d DRM -d SUSPEND \
>     	-d PM_RUNTIME -d CPU_FREQ -d CPU_IDLE

I wonder, what's the reason for disabling DRM? And while on the topic,
are there any plans to release a Tegra114 TRM?

Thierry

[-- Attachment #1.2: Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 192 bytes --]

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Re: [PATCH 0/9] ARM: Initial support for Tegra 114 SoC.

[Stephen Warren]

On 01/03/2013 02:00 PM, Thierry Reding wrote:
> On Thu, Dec 20, 2012 at 11:43:58AM +0200, Hiroshi Doyu wrote:
>> Hi,
>> 
>> This patchset adds initial support for the NVIDIA's new Tegra
>> 114 SoC (T114) based on the ARM Cortex-A15 MP. It has the minimal
>> support to allow the kernel to boot up into shell console. This
>> can be used as a basis for adding other device drivers for this
>> SoC. Currently there are 2 evaluation boards available, "Dalmore"
>> and "Pluto".
>> 
>> This patchset is against Stephen Warren's linux-next_common
>> branch:
>> 
>> git://nv-tegra.nvidia.com/user/swarren/linux-2.6
>> linux-next_common
>> 
>> For those who want to try:
>> 
>> $ make ARCH=arm tegra_defconfig $ scripts/config -e
>> ARCH_TEGRA_114_SOC -d DRM -d SUSPEND \ -d PM_RUNTIME -d CPU_FREQ
>> -d CPU_IDLE
> 
> I wonder, what's the reason for disabling DRM? And while on the
> topic, are there any plans to release a Tegra114 TRM?

AFAIK, the HW is basically compatible with previous chips, so I expect
to see a DRM driver for it show up once all the various more basic
devices are supported.

[PATCH 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU

[Hiroshi Doyu]

The method to detect the number of CPU cores on Cortex-A9 MPCore and
Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this
information from the Snoop Control Unit(SCU). On Cortex-A15 MPCore we
have to read it from the system coprocessor(CP15), because the SCU on
Cortex-A15 MPCore does not have software readable registers. This
patch selects the correct method at runtime based on the CPU ID.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 arch/arm/mach-tegra/platsmp.c |   31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1b926df..68e76ef 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -23,6 +23,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/smp_scu.h>
+#include <asm/cputype.h>
 
 #include <mach/powergate.h>
 
@@ -34,9 +35,13 @@
 #include "common.h"
 #include "iomap.h"
 
+#define CPU_MASK		0xff0ffff0
+#define CPU_CORTEX_A9		0x410fc090
+#define CPU_CORTEX_A15		0x410fc0f0
+
 extern void tegra_secondary_startup(void);
 
-static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
+static void __iomem *scu_base;
 
 #define EVP_CPU_RESET_VECTOR \
 	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
@@ -149,7 +154,26 @@ done:
  */
 static void __init tegra_smp_init_cpus(void)
 {
-	unsigned int i, ncores = scu_get_core_count(scu_base);
+	unsigned int i, cpu_id, ncores;
+	u32 l2ctlr;
+	phys_addr_t pa;
+
+	cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
+	switch (cpu_id) {
+	case CPU_CORTEX_A15:
+		asm("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
+		ncores = ((l2ctlr >> 24) & 3) + 1;
+		break;
+	case CPU_CORTEX_A9:
+		/* Get SCU physical base */
+		asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
+		scu_base = IO_ADDRESS(pa);
+		ncores = scu_get_core_count(scu_base);
+		break;
+	default:
+		BUG();
+		break;
+	}
 
 	if (ncores > nr_cpu_ids) {
 		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
@@ -166,7 +190,8 @@ static void __init tegra_smp_init_cpus(void)
 static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
 {
 	tegra_cpu_reset_handler_init();
-	scu_enable(scu_base);
+	if (scu_base)
+		scu_enable(scu_base);
 }
 
 struct smp_operations tegra_smp_ops __initdata = {
-- 
1.7.9.5

Re: [PATCH 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU

[Felipe Balbi]

[-- Attachment #1.1: Type: text/plain, Size: 2286 bytes --]

Hi,

On Thu, Dec 20, 2012 at 11:44:01AM +0200, Hiroshi Doyu wrote:
> The method to detect the number of CPU cores on Cortex-A9 MPCore and
> Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this
> information from the Snoop Control Unit(SCU). On Cortex-A15 MPCore we
> have to read it from the system coprocessor(CP15), because the SCU on
> Cortex-A15 MPCore does not have software readable registers. This
> patch selects the correct method at runtime based on the CPU ID.
> 
> Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm/mach-tegra/platsmp.c |   31 ++++++++++++++++++++++++++++---
>  1 file changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> index 1b926df..68e76ef 100644
> --- a/arch/arm/mach-tegra/platsmp.c
> +++ b/arch/arm/mach-tegra/platsmp.c
> @@ -23,6 +23,7 @@
>  #include <asm/hardware/gic.h>
>  #include <asm/mach-types.h>
>  #include <asm/smp_scu.h>
> +#include <asm/cputype.h>
>  
>  #include <mach/powergate.h>
>  
> @@ -34,9 +35,13 @@
>  #include "common.h"
>  #include "iomap.h"
>  
> +#define CPU_MASK		0xff0ffff0
> +#define CPU_CORTEX_A9		0x410fc090
> +#define CPU_CORTEX_A15		0x410fc0f0
> +
>  extern void tegra_secondary_startup(void);
>  
> -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
> +static void __iomem *scu_base;
>  
>  #define EVP_CPU_RESET_VECTOR \
>  	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
> @@ -149,7 +154,26 @@ done:
>   */
>  static void __init tegra_smp_init_cpus(void)
>  {
> -	unsigned int i, ncores = scu_get_core_count(scu_base);
> +	unsigned int i, cpu_id, ncores;
> +	u32 l2ctlr;
> +	phys_addr_t pa;
> +
> +	cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
> +	switch (cpu_id) {
> +	case CPU_CORTEX_A15:
> +		asm("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
> +		ncores = ((l2ctlr >> 24) & 3) + 1;
> +		break;
> +	case CPU_CORTEX_A9:
> +		/* Get SCU physical base */
> +		asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
> +		scu_base = IO_ADDRESS(pa);
> +		ncores = scu_get_core_count(scu_base);
> +		break;
> +	default:
> +		BUG();

instead of bugging out, how about setting ncores to 1 instead ?

-- 
balbi

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Re: [PATCH 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU

[Hiroshi Doyu]

Felipe Balbi <balbi@ti.com> wrote @ Thu, 20 Dec 2012 11:06:25 +0100:
...
> > @@ -149,7 +154,26 @@ done:
> >   */
> >  static void __init tegra_smp_init_cpus(void)
> >  {
> > -	unsigned int i, ncores = scu_get_core_count(scu_base);
> > +	unsigned int i, cpu_id, ncores;
> > +	u32 l2ctlr;
> > +	phys_addr_t pa;
> > +
> > +	cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
> > +	switch (cpu_id) {
> > +	case CPU_CORTEX_A15:
> > +		asm("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
> > +		ncores = ((l2ctlr >> 24) & 3) + 1;
> > +		break;
> > +	case CPU_CORTEX_A9:
> > +		/* Get SCU physical base */
> > +		asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
> > +		scu_base = IO_ADDRESS(pa);
> > +		ncores = scu_get_core_count(scu_base);
> > +		break;
> > +	default:
> > +		BUG();
> 
> instead of bugging out, how about setting ncores to 1 instead ?

Maybe that would be useful in the case of adding new ARM core in the
future.

Re: [PATCH 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU

[Felipe Balbi]

[-- Attachment #1.1: Type: text/plain, Size: 1161 bytes --]

Hi,

On Thu, Dec 20, 2012 at 12:21:36PM +0100, Hiroshi Doyu wrote:
> Felipe Balbi <balbi-l0cyMroinI0@public.gmane.org> wrote @ Thu, 20 Dec 2012 11:06:25 +0100:
> ...
> > > @@ -149,7 +154,26 @@ done:
> > >   */
> > >  static void __init tegra_smp_init_cpus(void)
> > >  {
> > > -	unsigned int i, ncores = scu_get_core_count(scu_base);
> > > +	unsigned int i, cpu_id, ncores;
> > > +	u32 l2ctlr;
> > > +	phys_addr_t pa;
> > > +
> > > +	cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
> > > +	switch (cpu_id) {
> > > +	case CPU_CORTEX_A15:
> > > +		asm("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
> > > +		ncores = ((l2ctlr >> 24) & 3) + 1;
> > > +		break;
> > > +	case CPU_CORTEX_A9:
> > > +		/* Get SCU physical base */
> > > +		asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
> > > +		scu_base = IO_ADDRESS(pa);
> > > +		ncores = scu_get_core_count(scu_base);
> > > +		break;
> > > +	default:
> > > +		BUG();
> > 
> > instead of bugging out, how about setting ncores to 1 instead ?
> 
> Maybe that would be useful in the case of adding new ARM core in the
> future.

right, kernel would at least boot in that case.

-- 
balbi

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Re: [PATCH 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU

[Marc Zyngier]

On 20/12/12 09:44, Hiroshi Doyu wrote:
> The method to detect the number of CPU cores on Cortex-A9 MPCore and
> Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this
> information from the Snoop Control Unit(SCU). On Cortex-A15 MPCore we
> have to read it from the system coprocessor(CP15), because the SCU on
> Cortex-A15 MPCore does not have software readable registers. This
> patch selects the correct method at runtime based on the CPU ID.
> 
> Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
> ---
>  arch/arm/mach-tegra/platsmp.c |   31 ++++++++++++++++++++++++++++---
>  1 file changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> index 1b926df..68e76ef 100644
> --- a/arch/arm/mach-tegra/platsmp.c
> +++ b/arch/arm/mach-tegra/platsmp.c
> @@ -23,6 +23,7 @@
>  #include <asm/hardware/gic.h>
>  #include <asm/mach-types.h>
>  #include <asm/smp_scu.h>
> +#include <asm/cputype.h>
>  
>  #include <mach/powergate.h>
>  
> @@ -34,9 +35,13 @@
>  #include "common.h"
>  #include "iomap.h"
>  
> +#define CPU_MASK		0xff0ffff0
> +#define CPU_CORTEX_A9		0x410fc090
> +#define CPU_CORTEX_A15		0x410fc0f0
> +
>  extern void tegra_secondary_startup(void);
>  
> -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
> +static void __iomem *scu_base;
>  
>  #define EVP_CPU_RESET_VECTOR \
>  	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
> @@ -149,7 +154,26 @@ done:
>   */
>  static void __init tegra_smp_init_cpus(void)
>  {
> -	unsigned int i, ncores = scu_get_core_count(scu_base);
> +	unsigned int i, cpu_id, ncores;
> +	u32 l2ctlr;
> +	phys_addr_t pa;
> +
> +	cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
> +	switch (cpu_id) {
> +	case CPU_CORTEX_A15:
> +		asm("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
> +		ncores = ((l2ctlr >> 24) & 3) + 1;

Please, do not do that. It doesn't scale to multiple clusters. Instead,
you can now rely on arm_dt_init_cpu_maps() to do the right thing as long
as your device tree exposes all the cpu nodes.

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU

[Hiroshi Doyu]

Marc Zyngier <marc.zyngier@arm.com> wrote @ Thu, 20 Dec 2012 12:17:08 +0100:

> On 20/12/12 09:44, Hiroshi Doyu wrote:
> > The method to detect the number of CPU cores on Cortex-A9 MPCore and
> > Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this
> > information from the Snoop Control Unit(SCU). On Cortex-A15 MPCore we
> > have to read it from the system coprocessor(CP15), because the SCU on
> > Cortex-A15 MPCore does not have software readable registers. This
> > patch selects the correct method at runtime based on the CPU ID.
> > 
> > Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
> > ---
> >  arch/arm/mach-tegra/platsmp.c |   31 ++++++++++++++++++++++++++++---
> >  1 file changed, 28 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> > index 1b926df..68e76ef 100644
> > --- a/arch/arm/mach-tegra/platsmp.c
> > +++ b/arch/arm/mach-tegra/platsmp.c
> > @@ -23,6 +23,7 @@
> >  #include <asm/hardware/gic.h>
> >  #include <asm/mach-types.h>
> >  #include <asm/smp_scu.h>
> > +#include <asm/cputype.h>
> >  
> >  #include <mach/powergate.h>
> >  
> > @@ -34,9 +35,13 @@
> >  #include "common.h"
> >  #include "iomap.h"
> >  
> > +#define CPU_MASK		0xff0ffff0
> > +#define CPU_CORTEX_A9		0x410fc090
> > +#define CPU_CORTEX_A15		0x410fc0f0
> > +
> >  extern void tegra_secondary_startup(void);
> >  
> > -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
> > +static void __iomem *scu_base;
> >  
> >  #define EVP_CPU_RESET_VECTOR \
> >  	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
> > @@ -149,7 +154,26 @@ done:
> >   */
> >  static void __init tegra_smp_init_cpus(void)
> >  {
> > -	unsigned int i, ncores = scu_get_core_count(scu_base);
> > +	unsigned int i, cpu_id, ncores;
> > +	u32 l2ctlr;
> > +	phys_addr_t pa;
> > +
> > +	cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
> > +	switch (cpu_id) {
> > +	case CPU_CORTEX_A15:
> > +		asm("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
> > +		ncores = ((l2ctlr >> 24) & 3) + 1;
> 
> Please, do not do that. It doesn't scale to multiple clusters. Instead,
> you can now rely on arm_dt_init_cpu_maps() to do the right thing as long
> as your device tree exposes all the cpu nodes.

Ok, this could be the answer why DT for cpu is necessary even when
it's got from CP15?

http://lists.infradead.org/pipermail/linux-arm-kernel/2012-December/137989.html

Re: [PATCH 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU

[Marc Zyngier]

On 20/12/12 11:26, Hiroshi Doyu wrote:
> Marc Zyngier <marc.zyngier@arm.com> wrote @ Thu, 20 Dec 2012 12:17:08 +0100:
> 
>> On 20/12/12 09:44, Hiroshi Doyu wrote:
>>> The method to detect the number of CPU cores on Cortex-A9 MPCore and
>>> Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this
>>> information from the Snoop Control Unit(SCU). On Cortex-A15 MPCore we
>>> have to read it from the system coprocessor(CP15), because the SCU on
>>> Cortex-A15 MPCore does not have software readable registers. This
>>> patch selects the correct method at runtime based on the CPU ID.
>>>
>>> Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
>>> ---
>>>  arch/arm/mach-tegra/platsmp.c |   31 ++++++++++++++++++++++++++++---
>>>  1 file changed, 28 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
>>> index 1b926df..68e76ef 100644
>>> --- a/arch/arm/mach-tegra/platsmp.c
>>> +++ b/arch/arm/mach-tegra/platsmp.c
>>> @@ -23,6 +23,7 @@
>>>  #include <asm/hardware/gic.h>
>>>  #include <asm/mach-types.h>
>>>  #include <asm/smp_scu.h>
>>> +#include <asm/cputype.h>
>>>  
>>>  #include <mach/powergate.h>
>>>  
>>> @@ -34,9 +35,13 @@
>>>  #include "common.h"
>>>  #include "iomap.h"
>>>  
>>> +#define CPU_MASK		0xff0ffff0
>>> +#define CPU_CORTEX_A9		0x410fc090
>>> +#define CPU_CORTEX_A15		0x410fc0f0
>>> +
>>>  extern void tegra_secondary_startup(void);
>>>  
>>> -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
>>> +static void __iomem *scu_base;
>>>  
>>>  #define EVP_CPU_RESET_VECTOR \
>>>  	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
>>> @@ -149,7 +154,26 @@ done:
>>>   */
>>>  static void __init tegra_smp_init_cpus(void)
>>>  {
>>> -	unsigned int i, ncores = scu_get_core_count(scu_base);
>>> +	unsigned int i, cpu_id, ncores;
>>> +	u32 l2ctlr;
>>> +	phys_addr_t pa;
>>> +
>>> +	cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
>>> +	switch (cpu_id) {
>>> +	case CPU_CORTEX_A15:
>>> +		asm("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
>>> +		ncores = ((l2ctlr >> 24) & 3) + 1;
>>
>> Please, do not do that. It doesn't scale to multiple clusters. Instead,
>> you can now rely on arm_dt_init_cpu_maps() to do the right thing as long
>> as your device tree exposes all the cpu nodes.
> 
> Ok, this could be the answer why DT for cpu is necessary even when
> it's got from CP15?
> 
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-December/137989.html
> 

Indeed, there is no unified way to find out how many CPUs are present in
a system. The A15 trick is neat (we used it in the past), but doesn't
scale to multiple clusters, not to mention heterogeneous clusters.

Hence the DT bindings for cpus, which neatly solves this problem and is
future proof.

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH 4/9] clocksource: tegra: Reorganize funcs by clock functionarities

[Hiroshi Doyu]

Relocate functions by clock functionarities{RTC, TMR}. Also created
some new functions as helper.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 drivers/clocksource/tegra20_timer.c |  160 +++++++++++++++++++----------------
 1 file changed, 86 insertions(+), 74 deletions(-)

diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index 5bc1429..1d25de8 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -35,6 +35,83 @@
 #define RTC_SHADOW_SECONDS     0x0c
 #define RTC_MILLISECONDS       0x10
 
+static void __iomem *rtc_base;
+static struct timespec persistent_ts;
+static u64 persistent_ms, last_persistent_ms;
+
+/*
+ * tegra_rtc_read - Reads the Tegra RTC registers
+ * Care must be taken that this funciton is not called while the
+ * tegra_rtc driver could be executing to avoid race conditions
+ * on the RTC shadow register
+ */
+static u64 tegra_rtc_read_ms(void)
+{
+	u32 ms = readl(rtc_base + RTC_MILLISECONDS);
+	u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
+	return (u64)s * MSEC_PER_SEC + ms;
+}
+
+/*
+ * tegra_read_persistent_clock -  Return time from a persistent clock.
+ *
+ * Reads the time from a source which isn't disabled during PM, the
+ * 32k sync timer.  Convert the cycles elapsed since last read into
+ * nsecs and adds to a monotonically increasing timespec.
+ * Care must be taken that this funciton is not called while the
+ * tegra_rtc driver could be executing to avoid race conditions
+ * on the RTC shadow register
+ */
+static void tegra_read_persistent_clock(struct timespec *ts)
+{
+	u64 delta;
+	struct timespec *tsp = &persistent_ts;
+
+	last_persistent_ms = persistent_ms;
+	persistent_ms = tegra_rtc_read_ms();
+	delta = persistent_ms - last_persistent_ms;
+
+	timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
+	*ts = *tsp;
+}
+
+static const struct of_device_id rtc_match[] __initconst = {
+	{ .compatible = "nvidia,tegra20-rtc" },
+	{}
+};
+
+static void __init tegra20_init_rtc(void)
+{
+	struct device_node *np;
+	struct clk *clk;
+
+	np = of_find_matching_node(NULL, rtc_match);
+	if (!np) {
+		pr_err("Failed to find RTC DT node\n");
+		BUG();
+	}
+
+	rtc_base = of_iomap(np, 0);
+	if (!rtc_base) {
+		pr_err("Can't map RTC registers");
+		BUG();
+	}
+
+	/*
+	 * rtc registers are used by read_persistent_clock, keep the rtc clock
+	 * enabled
+	 */
+	clk = clk_get_sys("rtc-tegra", NULL);
+	if (IS_ERR(clk))
+		pr_warn("Unable to get rtc-tegra clock\n");
+	else
+		clk_prepare_enable(clk);
+
+	of_node_put(np);
+
+	register_persistent_clock(NULL, tegra_read_persistent_clock);
+}
+
 #define TIMERUS_CNTR_1US 0x10
 #define TIMERUS_USEC_CFG 0x14
 #define TIMERUS_CNTR_FREEZE 0x4c
@@ -48,10 +125,6 @@
 #define TIMER_PCR 0x4
 
 static void __iomem *timer_reg_base;
-static void __iomem *rtc_base;
-
-static struct timespec persistent_ts;
-static u64 persistent_ms, last_persistent_ms;
 
 #define timer_writel(value, reg) \
 	__raw_writel(value, timer_reg_base + (reg))
@@ -103,46 +176,10 @@ static u32 notrace tegra_read_sched_clock(void)
 	return timer_readl(TIMERUS_CNTR_1US);
 }
 
-/*
- * tegra_rtc_read - Reads the Tegra RTC registers
- * Care must be taken that this funciton is not called while the
- * tegra_rtc driver could be executing to avoid race conditions
- * on the RTC shadow register
- */
-static u64 tegra_rtc_read_ms(void)
-{
-	u32 ms = readl(rtc_base + RTC_MILLISECONDS);
-	u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
-	return (u64)s * MSEC_PER_SEC + ms;
-}
-
-/*
- * tegra_read_persistent_clock -  Return time from a persistent clock.
- *
- * Reads the time from a source which isn't disabled during PM, the
- * 32k sync timer.  Convert the cycles elapsed since last read into
- * nsecs and adds to a monotonically increasing timespec.
- * Care must be taken that this funciton is not called while the
- * tegra_rtc driver could be executing to avoid race conditions
- * on the RTC shadow register
- */
-static void tegra_read_persistent_clock(struct timespec *ts)
-{
-	u64 delta;
-	struct timespec *tsp = &persistent_ts;
-
-	last_persistent_ms = persistent_ms;
-	persistent_ms = tegra_rtc_read_ms();
-	delta = persistent_ms - last_persistent_ms;
-
-	timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
-	*ts = *tsp;
-}
-
 static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
 {
 	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
-	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
+	timer_writel(1 << 30, TIMER3_BASE + TIMER_PCR);
 	evt->event_handler(evt);
 	return IRQ_HANDLED;
 }
@@ -159,12 +196,7 @@ static const struct of_device_id timer_match[] __initconst = {
 	{}
 };
 
-static const struct of_device_id rtc_match[] __initconst = {
-	{ .compatible = "nvidia,tegra20-rtc" },
-	{}
-};
-
-static void __init tegra20_init_timer(void)
+static void __init tegra20_init_tmr(void)
 {
 	struct device_node *np;
 	struct clk *clk;
@@ -200,30 +232,6 @@ static void __init tegra20_init_timer(void)
 
 	of_node_put(np);
 
-	np = of_find_matching_node(NULL, rtc_match);
-	if (!np) {
-		pr_err("Failed to find RTC DT node\n");
-		BUG();
-	}
-
-	rtc_base = of_iomap(np, 0);
-	if (!rtc_base) {
-		pr_err("Can't map RTC registers");
-		BUG();
-	}
-
-	/*
-	 * rtc registers are used by read_persistent_clock, keep the rtc clock
-	 * enabled
-	 */
-	clk = clk_get_sys("rtc-tegra", NULL);
-	if (IS_ERR(clk))
-		pr_warn("Unable to get rtc-tegra clock\n");
-	else
-		clk_prepare_enable(clk);
-
-	of_node_put(np);
-
 	switch (rate) {
 	case 12000000:
 		timer_writel(0x000b, TIMERUS_USEC_CFG);
@@ -241,8 +249,6 @@ static void __init tegra20_init_timer(void)
 		WARN(1, "Unknown clock rate");
 	}
 
-	setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
-
 	if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
 		"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
 		pr_err("Failed to register clocksource\n");
@@ -263,10 +269,16 @@ static void __init tegra20_init_timer(void)
 	tegra_clockevent.cpumask = cpu_all_mask;
 	tegra_clockevent.irq = tegra_timer_irq.irq;
 	clockevents_register_device(&tegra_clockevent);
+}
+
+static void __init tegra20_init_timer(void)
+{
+	tegra20_init_tmr();
+	setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
+	tegra20_init_rtc();
 #ifdef CONFIG_HAVE_ARM_TWD
 	twd_local_timer_of_register();
 #endif
-	register_persistent_clock(NULL, tegra_read_persistent_clock);
 }
 CLOCKSOURCE_OF_DECLARE(tegra20, "nvidia,tegra20-timer", tegra20_init_timer);
 
-- 
1.7.9.5

[PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Hiroshi Doyu]

Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
timer than TMR0. If it's available, it will be used for clock source
and sched_clock. Otherwise, TMR0 is used. In any case TMR0 is
necessary for clock event.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 .../bindings/arm/tegra/nvidia,tegra114-tsc.txt     |   11 ++++
 drivers/clocksource/tegra20_timer.c                |   64 +++++++++++++++++++-
 2 files changed, 74 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
new file mode 100644
index 0000000..9de936a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
@@ -0,0 +1,11 @@
+NVIDIA Tegra Timer Stamp Counter(TSC)
+
+Required properties:
+- compatible : "nvidia,tegra114-tsc
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+	tsc {
+		compatible = "nvidia,tegra114-tsc";
+		reg = <0x700f0000 0x20000>;
+	};
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index 1d25de8..285a6f1 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -30,6 +30,7 @@
 #include <asm/mach/time.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
+#include <asm/arch_timer.h>
 
 #define RTC_SECONDS            0x08
 #define RTC_SHADOW_SECONDS     0x0c
@@ -271,10 +272,71 @@ static void __init tegra20_init_tmr(void)
 	clockevents_register_device(&tegra_clockevent);
 }
 
+#define TSC_CNTCR		0		/* TSC control registers */
+#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
+#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
+
+#define TSC_CNTCV0		0x8		/* TSC counter (LSW) */
+#define TSC_CNTCV1		0xc		/* TSC counter (MSW) */
+#define TSC_CNTFID0		0x20		/* TSC freq id 0 */
+
+static const struct of_device_id tegra_tsc_match[] __initconst = {
+	{ .compatible = "nvidia,tegra114-tsc" },
+	{}
+};
+
+static int tegra_arch_timer_init(void)
+{
+	int err;
+	struct device_node *np;
+	struct clk *clk;
+	void __iomem *tsc_base;
+	u32 freq, val;
+
+	np = of_find_matching_node(NULL, tegra_tsc_match);
+	if (!np)
+		return -ENODEV;
+
+	tsc_base = of_iomap(np, 0);
+	if (!tsc_base)
+		return -ENODEV;
+
+	clk = clk_get_sys("clk_m", NULL);
+	if (IS_ERR(clk)) {
+		freq = 12000000;
+		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
+	} else {
+		freq = clk_get_rate(clk);
+		clk_put(clk);
+	}
+	writel_relaxed(freq, tsc_base + TSC_CNTFID0);
+
+	/* CNTFRQ */
+	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
+	BUG_ON(val != freq);
+
+	val = readl_relaxed(tsc_base + TSC_CNTCR);
+	val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+	writel_relaxed(val, tsc_base + TSC_CNTCR);
+
+	err = arch_timer_of_register();
+	if (!err)
+		err = arch_timer_sched_clock_init();
+	if (err)
+		pr_err("Failed to register ARM arch_timer(TSC)\n");
+	return err;
+}
+
 static void __init tegra20_init_timer(void)
 {
+	int err = -ENODEV;
+
 	tegra20_init_tmr();
-	setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
+	if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
+		err = tegra_arch_timer_init();
+	if (err)
+		setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
 	tegra20_init_rtc();
 #ifdef CONFIG_HAVE_ARM_TWD
 	twd_local_timer_of_register();
-- 
1.7.9.5

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Marc Zyngier]

On 20/12/12 09:44, Hiroshi Doyu wrote:
> Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
> timer than TMR0. If it's available, it will be used for clock source
> and sched_clock. Otherwise, TMR0 is used. In any case TMR0 is
> necessary for clock event.
> 
> Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  .../bindings/arm/tegra/nvidia,tegra114-tsc.txt     |   11 ++++
>  drivers/clocksource/tegra20_timer.c                |   64 +++++++++++++++++++-
>  2 files changed, 74 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
> new file mode 100644
> index 0000000..9de936a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
> @@ -0,0 +1,11 @@
> +NVIDIA Tegra Timer Stamp Counter(TSC)
> +
> +Required properties:
> +- compatible : "nvidia,tegra114-tsc
> +- reg : Should contain 1 register ranges(address and length)
> +
> +Example:
> +	tsc {
> +		compatible = "nvidia,tegra114-tsc";
> +		reg = <0x700f0000 0x20000>;
> +	};
> diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
> index 1d25de8..285a6f1 100644
> --- a/drivers/clocksource/tegra20_timer.c
> +++ b/drivers/clocksource/tegra20_timer.c
> @@ -30,6 +30,7 @@
>  #include <asm/mach/time.h>
>  #include <asm/smp_twd.h>
>  #include <asm/sched_clock.h>
> +#include <asm/arch_timer.h>
>  
>  #define RTC_SECONDS            0x08
>  #define RTC_SHADOW_SECONDS     0x0c
> @@ -271,10 +272,71 @@ static void __init tegra20_init_tmr(void)
>  	clockevents_register_device(&tegra_clockevent);
>  }
>  
> +#define TSC_CNTCR		0		/* TSC control registers */
> +#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
> +#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
> +
> +#define TSC_CNTCV0		0x8		/* TSC counter (LSW) */
> +#define TSC_CNTCV1		0xc		/* TSC counter (MSW) */
> +#define TSC_CNTFID0		0x20		/* TSC freq id 0 */
> +
> +static const struct of_device_id tegra_tsc_match[] __initconst = {
> +	{ .compatible = "nvidia,tegra114-tsc" },
> +	{}
> +};
> +
> +static int tegra_arch_timer_init(void)
> +{
> +	int err;
> +	struct device_node *np;
> +	struct clk *clk;
> +	void __iomem *tsc_base;
> +	u32 freq, val;
> +
> +	np = of_find_matching_node(NULL, tegra_tsc_match);
> +	if (!np)
> +		return -ENODEV;
> +
> +	tsc_base = of_iomap(np, 0);
> +	if (!tsc_base)
> +		return -ENODEV;
> +
> +	clk = clk_get_sys("clk_m", NULL);
> +	if (IS_ERR(clk)) {
> +		freq = 12000000;
> +		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
> +	} else {
> +		freq = clk_get_rate(clk);
> +		clk_put(clk);
> +	}
> +	writel_relaxed(freq, tsc_base + TSC_CNTFID0);
> +
> +	/* CNTFRQ */
> +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
> +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
> +	BUG_ON(val != freq);

This is scary. CNTFRQ is only writable from secure mode, and will
explode in any other situation.

Also, writing to CNTFRQ doesn't change the timer frequency! This is just
a way for secure mode to tell the rest of the world the frequency the
timer is ticking at. Unless you've wired the input clock to be able to
change the frequency?

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Hiroshi Doyu]

Marc Zyngier <marc.zyngier@arm.com> wrote @ Thu, 20 Dec 2012 12:01:15 +0100:

> On 20/12/12 09:44, Hiroshi Doyu wrote:
> > Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
> > timer than TMR0. If it's available, it will be used for clock source
> > and sched_clock. Otherwise, TMR0 is used. In any case TMR0 is
> > necessary for clock event.
> > 
> > Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
> > ---
> >  .../bindings/arm/tegra/nvidia,tegra114-tsc.txt     |   11 ++++
> >  drivers/clocksource/tegra20_timer.c                |   64 +++++++++++++++++++-
> >  2 files changed, 74 insertions(+), 1 deletion(-)
> >  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
> > new file mode 100644
> > index 0000000..9de936a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
> > @@ -0,0 +1,11 @@
> > +NVIDIA Tegra Timer Stamp Counter(TSC)
> > +
> > +Required properties:
> > +- compatible : "nvidia,tegra114-tsc
> > +- reg : Should contain 1 register ranges(address and length)
> > +
> > +Example:
> > +	tsc {
> > +		compatible = "nvidia,tegra114-tsc";
> > +		reg = <0x700f0000 0x20000>;
> > +	};
> > diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
> > index 1d25de8..285a6f1 100644
> > --- a/drivers/clocksource/tegra20_timer.c
> > +++ b/drivers/clocksource/tegra20_timer.c
> > @@ -30,6 +30,7 @@
> >  #include <asm/mach/time.h>
> >  #include <asm/smp_twd.h>
> >  #include <asm/sched_clock.h>
> > +#include <asm/arch_timer.h>
> >  
> >  #define RTC_SECONDS            0x08
> >  #define RTC_SHADOW_SECONDS     0x0c
> > @@ -271,10 +272,71 @@ static void __init tegra20_init_tmr(void)
> >  	clockevents_register_device(&tegra_clockevent);
> >  }
> >  
> > +#define TSC_CNTCR		0		/* TSC control registers */
> > +#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
> > +#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
> > +
> > +#define TSC_CNTCV0		0x8		/* TSC counter (LSW) */
> > +#define TSC_CNTCV1		0xc		/* TSC counter (MSW) */
> > +#define TSC_CNTFID0		0x20		/* TSC freq id 0 */
> > +
> > +static const struct of_device_id tegra_tsc_match[] __initconst = {
> > +	{ .compatible = "nvidia,tegra114-tsc" },
> > +	{}
> > +};
> > +
> > +static int tegra_arch_timer_init(void)
> > +{
> > +	int err;
> > +	struct device_node *np;
> > +	struct clk *clk;
> > +	void __iomem *tsc_base;
> > +	u32 freq, val;
> > +
> > +	np = of_find_matching_node(NULL, tegra_tsc_match);
> > +	if (!np)
> > +		return -ENODEV;
> > +
> > +	tsc_base = of_iomap(np, 0);
> > +	if (!tsc_base)
> > +		return -ENODEV;
> > +
> > +	clk = clk_get_sys("clk_m", NULL);
> > +	if (IS_ERR(clk)) {
> > +		freq = 12000000;
> > +		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
> > +	} else {
> > +		freq = clk_get_rate(clk);
> > +		clk_put(clk);
> > +	}
> > +	writel_relaxed(freq, tsc_base + TSC_CNTFID0);
> > +
> > +	/* CNTFRQ */
> > +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
> > +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
> > +	BUG_ON(val != freq);
> 
> This is scary. CNTFRQ is only writable from secure mode, and will
> explode in any other situation.
> 
> Also, writing to CNTFRQ doesn't change the timer frequency! This is just
> a way for secure mode to tell the rest of the world the frequency the
> timer is ticking at. Unless you've wired the input clock to be able to
> change the frequency?

ATM, our upstream kernel is expected in secure mode. This situation
may be changed later, though....

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Marc Zyngier]

On 20/12/12 11:57, Hiroshi Doyu wrote:
> Marc Zyngier <marc.zyngier@arm.com> wrote @ Thu, 20 Dec 2012 12:01:15 +0100:
> 
>> On 20/12/12 09:44, Hiroshi Doyu wrote:
>>> Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
>>> timer than TMR0. If it's available, it will be used for clock source
>>> and sched_clock. Otherwise, TMR0 is used. In any case TMR0 is
>>> necessary for clock event.
>>>
>>> Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
>>> ---
>>>  .../bindings/arm/tegra/nvidia,tegra114-tsc.txt     |   11 ++++
>>>  drivers/clocksource/tegra20_timer.c                |   64 +++++++++++++++++++-
>>>  2 files changed, 74 insertions(+), 1 deletion(-)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
>>> new file mode 100644
>>> index 0000000..9de936a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
>>> @@ -0,0 +1,11 @@
>>> +NVIDIA Tegra Timer Stamp Counter(TSC)
>>> +
>>> +Required properties:
>>> +- compatible : "nvidia,tegra114-tsc
>>> +- reg : Should contain 1 register ranges(address and length)
>>> +
>>> +Example:
>>> +	tsc {
>>> +		compatible = "nvidia,tegra114-tsc";
>>> +		reg = <0x700f0000 0x20000>;
>>> +	};
>>> diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
>>> index 1d25de8..285a6f1 100644
>>> --- a/drivers/clocksource/tegra20_timer.c
>>> +++ b/drivers/clocksource/tegra20_timer.c
>>> @@ -30,6 +30,7 @@
>>>  #include <asm/mach/time.h>
>>>  #include <asm/smp_twd.h>
>>>  #include <asm/sched_clock.h>
>>> +#include <asm/arch_timer.h>
>>>  
>>>  #define RTC_SECONDS            0x08
>>>  #define RTC_SHADOW_SECONDS     0x0c
>>> @@ -271,10 +272,71 @@ static void __init tegra20_init_tmr(void)
>>>  	clockevents_register_device(&tegra_clockevent);
>>>  }
>>>  
>>> +#define TSC_CNTCR		0		/* TSC control registers */
>>> +#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
>>> +#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
>>> +
>>> +#define TSC_CNTCV0		0x8		/* TSC counter (LSW) */
>>> +#define TSC_CNTCV1		0xc		/* TSC counter (MSW) */
>>> +#define TSC_CNTFID0		0x20		/* TSC freq id 0 */
>>> +
>>> +static const struct of_device_id tegra_tsc_match[] __initconst = {
>>> +	{ .compatible = "nvidia,tegra114-tsc" },
>>> +	{}
>>> +};
>>> +
>>> +static int tegra_arch_timer_init(void)
>>> +{
>>> +	int err;
>>> +	struct device_node *np;
>>> +	struct clk *clk;
>>> +	void __iomem *tsc_base;
>>> +	u32 freq, val;
>>> +
>>> +	np = of_find_matching_node(NULL, tegra_tsc_match);
>>> +	if (!np)
>>> +		return -ENODEV;
>>> +
>>> +	tsc_base = of_iomap(np, 0);
>>> +	if (!tsc_base)
>>> +		return -ENODEV;
>>> +
>>> +	clk = clk_get_sys("clk_m", NULL);
>>> +	if (IS_ERR(clk)) {
>>> +		freq = 12000000;
>>> +		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
>>> +	} else {
>>> +		freq = clk_get_rate(clk);
>>> +		clk_put(clk);
>>> +	}
>>> +	writel_relaxed(freq, tsc_base + TSC_CNTFID0);
>>> +
>>> +	/* CNTFRQ */
>>> +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
>>> +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
>>> +	BUG_ON(val != freq);
>>
>> This is scary. CNTFRQ is only writable from secure mode, and will
>> explode in any other situation.
>>
>> Also, writing to CNTFRQ doesn't change the timer frequency! This is just
>> a way for secure mode to tell the rest of the world the frequency the
>> timer is ticking at. Unless you've wired the input clock to be able to
>> change the frequency?
> 
> ATM, our upstream kernel is expected in secure mode. This situation
> may be changed later, though....

I appreciate this. But I expect this kernel to be also used on the
non-secure side if someone tried to run KVM with it. And this would go
bang right away.

	M.

-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Peter De Schrijver]

> >>> +
> >>> +	/* CNTFRQ */
> >>> +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
> >>> +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
> >>> +	BUG_ON(val != freq);
> >>
> >> This is scary. CNTFRQ is only writable from secure mode, and will
> >> explode in any other situation.
> >>
> >> Also, writing to CNTFRQ doesn't change the timer frequency! This is just
> >> a way for secure mode to tell the rest of the world the frequency the
> >> timer is ticking at. Unless you've wired the input clock to be able to
> >> change the frequency?
> > 
> > ATM, our upstream kernel is expected in secure mode. This situation
> > may be changed later, though....
> 
> I appreciate this. But I expect this kernel to be also used on the
> non-secure side if someone tried to run KVM with it. And this would go
> bang right away.
> 

But the guest wouldn't necessarily have this peripheral, or any other Tegra114
peripheral for that matter?

Cheers,

Peter.

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Marc Zyngier]

On 20/12/12 12:22, Peter De Schrijver wrote:
>>>>> +
>>>>> +	/* CNTFRQ */
>>>>> +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
>>>>> +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
>>>>> +	BUG_ON(val != freq);
>>>>
>>>> This is scary. CNTFRQ is only writable from secure mode, and will
>>>> explode in any other situation.
>>>>
>>>> Also, writing to CNTFRQ doesn't change the timer frequency! This is just
>>>> a way for secure mode to tell the rest of the world the frequency the
>>>> timer is ticking at. Unless you've wired the input clock to be able to
>>>> change the frequency?
>>>
>>> ATM, our upstream kernel is expected in secure mode. This situation
>>> may be changed later, though....
>>
>> I appreciate this. But I expect this kernel to be also used on the
>> non-secure side if someone tried to run KVM with it. And this would go
>> bang right away.
>>
> 
> But the guest wouldn't necessarily have this peripheral, or any other Tegra114
> peripheral for that matter?

The problem is not so much the guest but the host. The host has to be
booted in non-secure, so just saying "we do not support non-secure" is
not a very convincing argument.

Unless of course you've already decided that you don't want to support
KVM on this SoC...

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Peter De Schrijver]

On Thu, Dec 20, 2012 at 01:33:42PM +0100, Marc Zyngier wrote:
> On 20/12/12 12:22, Peter De Schrijver wrote:
> >>>>> +
> >>>>> +	/* CNTFRQ */
> >>>>> +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
> >>>>> +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
> >>>>> +	BUG_ON(val != freq);
> >>>>
> >>>> This is scary. CNTFRQ is only writable from secure mode, and will
> >>>> explode in any other situation.
> >>>>
> >>>> Also, writing to CNTFRQ doesn't change the timer frequency! This is just
> >>>> a way for secure mode to tell the rest of the world the frequency the
> >>>> timer is ticking at. Unless you've wired the input clock to be able to
> >>>> change the frequency?
> >>>
> >>> ATM, our upstream kernel is expected in secure mode. This situation
> >>> may be changed later, though....
> >>
> >> I appreciate this. But I expect this kernel to be also used on the
> >> non-secure side if someone tried to run KVM with it. And this would go
> >> bang right away.
> >>
> > 
> > But the guest wouldn't necessarily have this peripheral, or any other Tegra114
> > peripheral for that matter?
> 
> The problem is not so much the guest but the host. The host has to be
> booted in non-secure, so just saying "we do not support non-secure" is
> not a very convincing argument.
> 
> Unless of course you've already decided that you don't want to support
> KVM on this SoC...
> 

I guess that means we can't support KVM yet. Tegra does not have a secure
monitor by default. It all depends on what that system integrator does.

Cheers,

Peter.

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Marc Zyngier]

On 20/12/12 12:55, Peter De Schrijver wrote:
> On Thu, Dec 20, 2012 at 01:33:42PM +0100, Marc Zyngier wrote:
>> On 20/12/12 12:22, Peter De Schrijver wrote:
>>>>>>> +
>>>>>>> +	/* CNTFRQ */
>>>>>>> +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
>>>>>>> +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
>>>>>>> +	BUG_ON(val != freq);
>>>>>>
>>>>>> This is scary. CNTFRQ is only writable from secure mode, and will
>>>>>> explode in any other situation.
>>>>>>
>>>>>> Also, writing to CNTFRQ doesn't change the timer frequency! This is just
>>>>>> a way for secure mode to tell the rest of the world the frequency the
>>>>>> timer is ticking at. Unless you've wired the input clock to be able to
>>>>>> change the frequency?
>>>>>
>>>>> ATM, our upstream kernel is expected in secure mode. This situation
>>>>> may be changed later, though....
>>>>
>>>> I appreciate this. But I expect this kernel to be also used on the
>>>> non-secure side if someone tried to run KVM with it. And this would go
>>>> bang right away.
>>>>
>>>
>>> But the guest wouldn't necessarily have this peripheral, or any other Tegra114
>>> peripheral for that matter?
>>
>> The problem is not so much the guest but the host. The host has to be
>> booted in non-secure, so just saying "we do not support non-secure" is
>> not a very convincing argument.
>>
>> Unless of course you've already decided that you don't want to support
>> KVM on this SoC...
>>
> 
> I guess that means we can't support KVM yet. Tegra does not have a secure
> monitor by default. It all depends on what that system integrator does.

VExpress doesn't have a secure monitor either, and yet we run KVM on it
(by switching to non-secure before loading the kernel). Same for Exynos5.

What I'm trying to say is that this code is rather pointless (this
should be done by the firmware/bootloader, not the kernel, or the
information should be provided in DT if CNTFRQ is not set).

This way, no breakage, no dependency on the security level.

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Hiroshi Doyu]

Marc Zyngier <marc.zyngier@arm.com> wrote @ Thu, 20 Dec 2012 14:32:21 +0100:

> On 20/12/12 12:55, Peter De Schrijver wrote:
> > On Thu, Dec 20, 2012 at 01:33:42PM +0100, Marc Zyngier wrote:
> >> On 20/12/12 12:22, Peter De Schrijver wrote:
> >>>>>>> +
> >>>>>>> +	/* CNTFRQ */
> >>>>>>> +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
> >>>>>>> +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
> >>>>>>> +	BUG_ON(val != freq);
> >>>>>>
> >>>>>> This is scary. CNTFRQ is only writable from secure mode, and will
> >>>>>> explode in any other situation.
> >>>>>>
> >>>>>> Also, writing to CNTFRQ doesn't change the timer frequency! This is just
> >>>>>> a way for secure mode to tell the rest of the world the frequency the
> >>>>>> timer is ticking at. Unless you've wired the input clock to be able to
> >>>>>> change the frequency?
> >>>>>
> >>>>> ATM, our upstream kernel is expected in secure mode. This situation
> >>>>> may be changed later, though....
> >>>>
> >>>> I appreciate this. But I expect this kernel to be also used on the
> >>>> non-secure side if someone tried to run KVM with it. And this would go
> >>>> bang right away.
> >>>>
> >>>
> >>> But the guest wouldn't necessarily have this peripheral, or any other Tegra114
> >>> peripheral for that matter?
> >>
> >> The problem is not so much the guest but the host. The host has to be
> >> booted in non-secure, so just saying "we do not support non-secure" is
> >> not a very convincing argument.
> >>
> >> Unless of course you've already decided that you don't want to support
> >> KVM on this SoC...
> >>
> > 
> > I guess that means we can't support KVM yet. Tegra does not have a secure
> > monitor by default. It all depends on what that system integrator does.
> 
> VExpress doesn't have a secure monitor either, and yet we run KVM on it
> (by switching to non-secure before loading the kernel). Same for Exynos5.
> 
> What I'm trying to say is that this code is rather pointless (this
> should be done by the firmware/bootloader, not the kernel, or the
> information should be provided in DT if CNTFRQ is not set).

"tegra114.dtsi" has the folloiwng "tsc" entry. So can we consider that
if dts has this entry, CNTFRQ is not set, which implies it's in secure
mode. kernel should set it up by itself? Otherwise, skip this setup
and use it. For example:

 	tsc {
 		compatible = "nvidia,tegra114-tsc";
 		reg = <0x700f0000 0x20000>;
+		setup-cntfrq;
 	};

Is this what you explained in the above?
At least, kernel can survive without bootloader/firmware support, ATM.

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Marc Zyngier]

On 20/12/12 14:42, Hiroshi Doyu wrote:
> Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> wrote @ Thu, 20 Dec 2012 14:32:21 +0100:
> 
>> On 20/12/12 12:55, Peter De Schrijver wrote:
>>> On Thu, Dec 20, 2012 at 01:33:42PM +0100, Marc Zyngier wrote:
>>>> On 20/12/12 12:22, Peter De Schrijver wrote:
>>>>>>>>> +
>>>>>>>>> +	/* CNTFRQ */
>>>>>>>>> +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
>>>>>>>>> +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
>>>>>>>>> +	BUG_ON(val != freq);
>>>>>>>>
>>>>>>>> This is scary. CNTFRQ is only writable from secure mode, and will
>>>>>>>> explode in any other situation.
>>>>>>>>
>>>>>>>> Also, writing to CNTFRQ doesn't change the timer frequency! This is just
>>>>>>>> a way for secure mode to tell the rest of the world the frequency the
>>>>>>>> timer is ticking at. Unless you've wired the input clock to be able to
>>>>>>>> change the frequency?
>>>>>>>
>>>>>>> ATM, our upstream kernel is expected in secure mode. This situation
>>>>>>> may be changed later, though....
>>>>>>
>>>>>> I appreciate this. But I expect this kernel to be also used on the
>>>>>> non-secure side if someone tried to run KVM with it. And this would go
>>>>>> bang right away.
>>>>>>
>>>>>
>>>>> But the guest wouldn't necessarily have this peripheral, or any other Tegra114
>>>>> peripheral for that matter?
>>>>
>>>> The problem is not so much the guest but the host. The host has to be
>>>> booted in non-secure, so just saying "we do not support non-secure" is
>>>> not a very convincing argument.
>>>>
>>>> Unless of course you've already decided that you don't want to support
>>>> KVM on this SoC...
>>>>
>>>
>>> I guess that means we can't support KVM yet. Tegra does not have a secure
>>> monitor by default. It all depends on what that system integrator does.
>>
>> VExpress doesn't have a secure monitor either, and yet we run KVM on it
>> (by switching to non-secure before loading the kernel). Same for Exynos5.
>>
>> What I'm trying to say is that this code is rather pointless (this
>> should be done by the firmware/bootloader, not the kernel, or the
>> information should be provided in DT if CNTFRQ is not set).
> 
> "tegra114.dtsi" has the folloiwng "tsc" entry. So can we consider that
> if dts has this entry, CNTFRQ is not set, which implies it's in secure
> mode. kernel should set it up by itself? Otherwise, skip this setup
> and use it. For example:
> 
>  	tsc {
>  		compatible = "nvidia,tegra114-tsc";
>  		reg = <0x700f0000 0x20000>;
> +		setup-cntfrq;
>  	};
> 
> Is this what you explained in the above?
> At least, kernel can survive without bootloader/firmware support, ATM.

No. The DT should only describe the hardware, and not something that is
Linux specific.

Just use the "clock-frequency" attribute in the timer arch-timer node,
and get rid of this CNTFRQ setting. The driver already knows how to deal
with this situation if this attribute is set.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Peter De Schrijver]

> > 
> > "tegra114.dtsi" has the folloiwng "tsc" entry. So can we consider that
> > if dts has this entry, CNTFRQ is not set, which implies it's in secure
> > mode. kernel should set it up by itself? Otherwise, skip this setup
> > and use it. For example:
> > 
> >  	tsc {
> >  		compatible = "nvidia,tegra114-tsc";
> >  		reg = <0x700f0000 0x20000>;
> > +		setup-cntfrq;
> >  	};
> > 
> > Is this what you explained in the above?
> > At least, kernel can survive without bootloader/firmware support, ATM.
> 
> No. The DT should only describe the hardware, and not something that is
> Linux specific.
> 
> Just use the "clock-frequency" attribute in the timer arch-timer node,
> and get rid of this CNTFRQ setting. The driver already knows how to deal
> with this situation if this attribute is set.

The frequency is probed at boottime by the kernel though. It will not
necessarily be the same for every board.

Cheers,

Peter.

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Hiroshi Doyu]

Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> wrote @ Thu, 20 Dec 2012 13:05:45 +0100:

> On 20/12/12 11:57, Hiroshi Doyu wrote:
> > Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> wrote @ Thu, 20 Dec 2012 12:01:15 +0100:
> > 
> >> On 20/12/12 09:44, Hiroshi Doyu wrote:
> >>> Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
> >>> timer than TMR0. If it's available, it will be used for clock source
> >>> and sched_clock. Otherwise, TMR0 is used. In any case TMR0 is
> >>> necessary for clock event.
> >>>
> >>> Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> >>> ---
> >>>  .../bindings/arm/tegra/nvidia,tegra114-tsc.txt     |   11 ++++
> >>>  drivers/clocksource/tegra20_timer.c                |   64 +++++++++++++++++++-
> >>>  2 files changed, 74 insertions(+), 1 deletion(-)
> >>>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
> >>> new file mode 100644
> >>> index 0000000..9de936a
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
> >>> @@ -0,0 +1,11 @@
> >>> +NVIDIA Tegra Timer Stamp Counter(TSC)
> >>> +
> >>> +Required properties:
> >>> +- compatible : "nvidia,tegra114-tsc
> >>> +- reg : Should contain 1 register ranges(address and length)
> >>> +
> >>> +Example:
> >>> +	tsc {
> >>> +		compatible = "nvidia,tegra114-tsc";
> >>> +		reg = <0x700f0000 0x20000>;
> >>> +	};
> >>> diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
> >>> index 1d25de8..285a6f1 100644
> >>> --- a/drivers/clocksource/tegra20_timer.c
> >>> +++ b/drivers/clocksource/tegra20_timer.c
> >>> @@ -30,6 +30,7 @@
> >>>  #include <asm/mach/time.h>
> >>>  #include <asm/smp_twd.h>
> >>>  #include <asm/sched_clock.h>
> >>> +#include <asm/arch_timer.h>
> >>>  
> >>>  #define RTC_SECONDS            0x08
> >>>  #define RTC_SHADOW_SECONDS     0x0c
> >>> @@ -271,10 +272,71 @@ static void __init tegra20_init_tmr(void)
> >>>  	clockevents_register_device(&tegra_clockevent);
> >>>  }
> >>>  
> >>> +#define TSC_CNTCR		0		/* TSC control registers */
> >>> +#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
> >>> +#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
> >>> +
> >>> +#define TSC_CNTCV0		0x8		/* TSC counter (LSW) */
> >>> +#define TSC_CNTCV1		0xc		/* TSC counter (MSW) */
> >>> +#define TSC_CNTFID0		0x20		/* TSC freq id 0 */
> >>> +
> >>> +static const struct of_device_id tegra_tsc_match[] __initconst = {
> >>> +	{ .compatible = "nvidia,tegra114-tsc" },
> >>> +	{}
> >>> +};
> >>> +
> >>> +static int tegra_arch_timer_init(void)
> >>> +{
> >>> +	int err;
> >>> +	struct device_node *np;
> >>> +	struct clk *clk;
> >>> +	void __iomem *tsc_base;
> >>> +	u32 freq, val;
> >>> +
> >>> +	np = of_find_matching_node(NULL, tegra_tsc_match);
> >>> +	if (!np)
> >>> +		return -ENODEV;
> >>> +
> >>> +	tsc_base = of_iomap(np, 0);
> >>> +	if (!tsc_base)
> >>> +		return -ENODEV;
> >>> +
> >>> +	clk = clk_get_sys("clk_m", NULL);
> >>> +	if (IS_ERR(clk)) {
> >>> +		freq = 12000000;
> >>> +		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
> >>> +	} else {
> >>> +		freq = clk_get_rate(clk);
> >>> +		clk_put(clk);
> >>> +	}
> >>> +	writel_relaxed(freq, tsc_base + TSC_CNTFID0);
> >>> +
> >>> +	/* CNTFRQ */
> >>> +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
> >>> +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
> >>> +	BUG_ON(val != freq);
> >>
> >> This is scary. CNTFRQ is only writable from secure mode, and will
> >> explode in any other situation.
> >>
> >> Also, writing to CNTFRQ doesn't change the timer frequency! This is just
> >> a way for secure mode to tell the rest of the world the frequency the
> >> timer is ticking at. Unless you've wired the input clock to be able to
> >> change the frequency?
> > 
> > ATM, our upstream kernel is expected in secure mode. This situation
> > may be changed later, though....
> 
> I appreciate this. But I expect this kernel to be also used on the
> non-secure side if someone tried to run KVM with it. And this would go
> bang right away.

What is the common way to make the above code selective at run
time(secure or non-secure path)?

Re: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC

[Marc Zyngier]

On 20/12/12 13:25, Hiroshi Doyu wrote:
> Marc Zyngier <marc.zyngier@arm.com> wrote @ Thu, 20 Dec 2012 13:05:45 +0100:
> 
>> On 20/12/12 11:57, Hiroshi Doyu wrote:
>>> Marc Zyngier <marc.zyngier@arm.com> wrote @ Thu, 20 Dec 2012 12:01:15 +0100:
>>>
>>>> On 20/12/12 09:44, Hiroshi Doyu wrote:
>>>>> Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
>>>>> timer than TMR0. If it's available, it will be used for clock source
>>>>> and sched_clock. Otherwise, TMR0 is used. In any case TMR0 is
>>>>> necessary for clock event.
>>>>>
>>>>> Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
>>>>> ---
>>>>>  .../bindings/arm/tegra/nvidia,tegra114-tsc.txt     |   11 ++++
>>>>>  drivers/clocksource/tegra20_timer.c                |   64 +++++++++++++++++++-
>>>>>  2 files changed, 74 insertions(+), 1 deletion(-)
>>>>>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
>>>>> new file mode 100644
>>>>> index 0000000..9de936a
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
>>>>> @@ -0,0 +1,11 @@
>>>>> +NVIDIA Tegra Timer Stamp Counter(TSC)
>>>>> +
>>>>> +Required properties:
>>>>> +- compatible : "nvidia,tegra114-tsc
>>>>> +- reg : Should contain 1 register ranges(address and length)
>>>>> +
>>>>> +Example:
>>>>> +	tsc {
>>>>> +		compatible = "nvidia,tegra114-tsc";
>>>>> +		reg = <0x700f0000 0x20000>;
>>>>> +	};
>>>>> diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
>>>>> index 1d25de8..285a6f1 100644
>>>>> --- a/drivers/clocksource/tegra20_timer.c
>>>>> +++ b/drivers/clocksource/tegra20_timer.c
>>>>> @@ -30,6 +30,7 @@
>>>>>  #include <asm/mach/time.h>
>>>>>  #include <asm/smp_twd.h>
>>>>>  #include <asm/sched_clock.h>
>>>>> +#include <asm/arch_timer.h>
>>>>>  
>>>>>  #define RTC_SECONDS            0x08
>>>>>  #define RTC_SHADOW_SECONDS     0x0c
>>>>> @@ -271,10 +272,71 @@ static void __init tegra20_init_tmr(void)
>>>>>  	clockevents_register_device(&tegra_clockevent);
>>>>>  }
>>>>>  
>>>>> +#define TSC_CNTCR		0		/* TSC control registers */
>>>>> +#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
>>>>> +#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
>>>>> +
>>>>> +#define TSC_CNTCV0		0x8		/* TSC counter (LSW) */
>>>>> +#define TSC_CNTCV1		0xc		/* TSC counter (MSW) */
>>>>> +#define TSC_CNTFID0		0x20		/* TSC freq id 0 */
>>>>> +
>>>>> +static const struct of_device_id tegra_tsc_match[] __initconst = {
>>>>> +	{ .compatible = "nvidia,tegra114-tsc" },
>>>>> +	{}
>>>>> +};
>>>>> +
>>>>> +static int tegra_arch_timer_init(void)
>>>>> +{
>>>>> +	int err;
>>>>> +	struct device_node *np;
>>>>> +	struct clk *clk;
>>>>> +	void __iomem *tsc_base;
>>>>> +	u32 freq, val;
>>>>> +
>>>>> +	np = of_find_matching_node(NULL, tegra_tsc_match);
>>>>> +	if (!np)
>>>>> +		return -ENODEV;
>>>>> +
>>>>> +	tsc_base = of_iomap(np, 0);
>>>>> +	if (!tsc_base)
>>>>> +		return -ENODEV;
>>>>> +
>>>>> +	clk = clk_get_sys("clk_m", NULL);
>>>>> +	if (IS_ERR(clk)) {
>>>>> +		freq = 12000000;
>>>>> +		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
>>>>> +	} else {
>>>>> +		freq = clk_get_rate(clk);
>>>>> +		clk_put(clk);
>>>>> +	}
>>>>> +	writel_relaxed(freq, tsc_base + TSC_CNTFID0);
>>>>> +
>>>>> +	/* CNTFRQ */
>>>>> +	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
>>>>> +	asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val));
>>>>> +	BUG_ON(val != freq);
>>>>
>>>> This is scary. CNTFRQ is only writable from secure mode, and will
>>>> explode in any other situation.
>>>>
>>>> Also, writing to CNTFRQ doesn't change the timer frequency! This is just
>>>> a way for secure mode to tell the rest of the world the frequency the
>>>> timer is ticking at. Unless you've wired the input clock to be able to
>>>> change the frequency?
>>>
>>> ATM, our upstream kernel is expected in secure mode. This situation
>>> may be changed later, though....
>>
>> I appreciate this. But I expect this kernel to be also used on the
>> non-secure side if someone tried to run KVM with it. And this would go
>> bang right away.
> 
> What is the common way to make the above code selective at run
> time(secure or non-secure path)?

All platforms are currently doing it in their firmware/bootloader, which
runs on the secure side. The kernel itself should be able to run on both
sides.

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH 6/9] ARM: dt: tegra114: Add new SoC base, Tegra 114 SoC

[Hiroshi Doyu]

Initial support for Tegra 114 SoC. This is expected to be included in
the board DTS files, Tegra 114 SoC based evaluation board family.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi |   89 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra114.dtsi

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
new file mode 100644
index 0000000..a5b7330
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -0,0 +1,89 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra114";
+	interrupt-parent = <&gic>;
+
+	gic: interrupt-controller {
+		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+		reg = <0x50041000 0x1000
+		       0x50042000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
+	timer@60005000 {
+		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
+		reg = <0x60005000 0x400>;
+		interrupts = <0 0 0x04
+			      0 1 0x04
+			      0 41 0x04
+			      0 42 0x04
+			      0 121 0x04
+			      0 122 0x04>;
+	};
+
+	serial@70006000 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006000 0x40>;
+		reg-shift = <2>;
+		interrupts = <0 36 0x04>;
+		status = "disabled";
+	};
+
+	serial@70006040 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006040 0x40>;
+		reg-shift = <2>;
+		interrupts = <0 37 0x04>;
+		status = "disabled";
+	};
+
+	serial@70006200 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006200 0x100>;
+		reg-shift = <2>;
+		interrupts = <0 46 0x04>;
+		status = "disabled";
+	};
+
+	serial@70006300 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006300 0x100>;
+		reg-shift = <2>;
+		interrupts = <0 90 0x04>;
+		status = "disabled";
+	};
+
+	serial@70006400 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006400 0x100>;
+		reg-shift = <2>;
+		interrupts = <0 91 0x04>;
+		status = "disabled";
+	};
+
+	rtc {
+		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
+		reg = <0x7000e000 0x100>;
+		interrupts = <0 2 0x04>;
+	};
+
+	pmc {
+		compatible = "nvidia,tegra114-pmc", "nvidia,tegra20-pmc";
+		reg = <0x7000e400 0x400>;
+	};
+
+	tsc {
+		compatible = "nvidia,tegra114-tsc";
+		reg = <0x700f0000 0x20000>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>,
+			     <1 11 0xf08>,
+			     <1 10 0xf08>;
+	};
+};
-- 
1.7.9.5

Re: [PATCH 6/9] ARM: dt: tegra114: Add new SoC base, Tegra 114 SoC

[Marc Zyngier]

On 20/12/12 09:44, Hiroshi Doyu wrote:
> Initial support for Tegra 114 SoC. This is expected to be included in
> the board DTS files, Tegra 114 SoC based evaluation board family.
> 
> Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

You definitely need to add some cpu nodes here, or get someone to merge
the NR_CPUS=0 patch: https://lkml.org/lkml/2012/3/31/131

;-)

> ---
>  arch/arm/boot/dts/tegra114.dtsi |   89 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 89 insertions(+)
>  create mode 100644 arch/arm/boot/dts/tegra114.dtsi
> 
> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
> new file mode 100644
> index 0000000..a5b7330
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra114.dtsi
> @@ -0,0 +1,89 @@
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	compatible = "nvidia,tegra114";
> +	interrupt-parent = <&gic>;
> +
> +	gic: interrupt-controller {
> +		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
> +		reg = <0x50041000 0x1000
> +		       0x50042000 0x1000>;

If this is indeed an A15 GIC, how about adding the GICH and GICV
regions, as well as the VGIC maintenance interrupt?

> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +	};
> +
> +	timer@60005000 {
> +		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
> +		reg = <0x60005000 0x400>;
> +		interrupts = <0 0 0x04
> +			      0 1 0x04
> +			      0 41 0x04
> +			      0 42 0x04
> +			      0 121 0x04
> +			      0 122 0x04>;
> +	};
> +
> +	serial@70006000 {
> +		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> +		reg = <0x70006000 0x40>;
> +		reg-shift = <2>;
> +		interrupts = <0 36 0x04>;
> +		status = "disabled";
> +	};
> +
> +	serial@70006040 {
> +		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> +		reg = <0x70006040 0x40>;
> +		reg-shift = <2>;
> +		interrupts = <0 37 0x04>;
> +		status = "disabled";
> +	};
> +
> +	serial@70006200 {
> +		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> +		reg = <0x70006200 0x100>;
> +		reg-shift = <2>;
> +		interrupts = <0 46 0x04>;
> +		status = "disabled";
> +	};
> +
> +	serial@70006300 {
> +		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> +		reg = <0x70006300 0x100>;
> +		reg-shift = <2>;
> +		interrupts = <0 90 0x04>;
> +		status = "disabled";
> +	};
> +
> +	serial@70006400 {
> +		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
> +		reg = <0x70006400 0x100>;
> +		reg-shift = <2>;
> +		interrupts = <0 91 0x04>;
> +		status = "disabled";
> +	};
> +
> +	rtc {
> +		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
> +		reg = <0x7000e000 0x100>;
> +		interrupts = <0 2 0x04>;
> +	};
> +
> +	pmc {
> +		compatible = "nvidia,tegra114-pmc", "nvidia,tegra20-pmc";
> +		reg = <0x7000e400 0x400>;
> +	};
> +
> +	tsc {
> +		compatible = "nvidia,tegra114-tsc";
> +		reg = <0x700f0000 0x20000>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <1 13 0xf08>,
> +			     <1 14 0xf08>,
> +			     <1 11 0xf08>,
> +			     <1 10 0xf08>;
> +	};
> +};
> 


-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 6/9] ARM: dt: tegra114: Add new SoC base, Tegra 114 SoC

[Olof Johansson]

On Thu, Dec 20, 2012 at 11:44:04AM +0200, Hiroshi Doyu wrote:
> Initial support for Tegra 114 SoC. This is expected to be included in
> the board DTS files, Tegra 114 SoC based evaluation board family.
> 
> Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Hi,

I think it could be a good idea to start documenting the cpu configuration in
the device tree on some of these larger platforms as well, i.e. include a cpus/
hierarchy. Would you mind adding those, please?

It would give you the flexibility of switching over to using device
tree to probe the number of cpus in case the platform grows yet another
way to figure out the number of cores in the future, without having to
update the device-trees at that time. :)


-Olof

Re: [PATCH 6/9] ARM: dt: tegra114: Add new SoC base, Tegra 114 SoC

[Hiroshi Doyu]

Hi Olof,

Olof Johansson <olof@lixom.net> wrote @ Sat, 29 Dec 2012 07:39:13 +0100:

> On Thu, Dec 20, 2012 at 11:44:04AM +0200, Hiroshi Doyu wrote:
> > Initial support for Tegra 114 SoC. This is expected to be included in
> > the board DTS files, Tegra 114 SoC based evaluation board family.
> > 
> > Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
> 
> Hi,
> 
> I think it could be a good idea to start documenting the cpu configuration in
> the device tree on some of these larger platforms as well, i.e. include a cpus/
> hierarchy. Would you mind adding those, please?

Ok, I'll.

> It would give you the flexibility of switching over to using device
> tree to probe the number of cpus in case the platform grows yet another
> way to figure out the number of cores in the future, without having to
> update the device-trees at that time. :)
> 
> 
> -Olof

Re: [PATCH 0/9] ARM: Initial support for Tegra 114 SoC.

[Mark Zhang]

On 12/20/2012 05:43 PM, Hiroshi Doyu wrote:
> Hi,
> 
> This patchset adds initial support for the NVIDIA's new Tegra 114
> SoC (T114) based on the ARM Cortex-A15 MP. It has the minimal support
> to allow the kernel to boot up into shell console. This can be used as
> a basis for adding other device drivers for this SoC. Currently there
> are 2 evaluation boards available, "Dalmore" and "Pluto".
> 
> This patchset is against Stephen Warren's linux-next_common branch:
> 
>   git://nv-tegra.nvidia.com/user/swarren/linux-2.6 linux-next_common
> 
> For those who want to try:
> 
>   $ make ARCH=arm tegra_defconfig
>   $ scripts/config -e ARCH_TEGRA_114_SOC -d DRM -d SUSPEND \
>     	-d PM_RUNTIME -d CPU_FREQ -d CPU_IDLE
>   $ make ARCH=arm menuconfig # if needed to configure more

I think we also need to enable:

CONFIG_ARM_APPENDED_DTB
CONFIG_ARM_ATAG_DTB_COMPAT

because currently we append the dtb to the kernel image(will not do this
after u-boot supports dalmore and we can load the dtb in u-boot cmd), so
we need to make kernel being aware of this.

My experience is after I enabled these 2 configs, kernel starts up normally.

Mark
>   $ make ARCH=arm all -j9
> 
> Verified that this single image booted up with "Dalmore(T114)",
> "Pluto(T114)" and "Cardhu(T30)". For "Cardhu(T30)" with this single
> image, SPI driver doesn't seem to afford the above configuration , it
> hangs at boot-up. With SPI disabled, it's ok.
> 
> 
> Hiroshi Doyu (9):
>   ARM: tegra: fuse: Add chipid TEGRA114 0x35
>   HACK: ARM: tegra: Use CLK_IGNORE_UNUSED for Tegra 114 SoC
>   ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU
>   clocksource: tegra: Reorganize funcs by clock functionarities
>   clocksource: tegra: Enable ARM arch_timer with TSC
>   ARM: dt: tegra114: Add new SoC base, Tegra 114 SoC
>   ARM: dt: tegra114: Add new board, Dalmore
>   ARM: dt: tegra114: Add new board, Pluto
>   ARM: tegra: Add initial support for Tegra 114 SoC.
> 
>  .../bindings/arm/tegra/nvidia,tegra114-tsc.txt     |   11 +
>  arch/arm/boot/dts/Makefile                         |    4 +-
>  arch/arm/boot/dts/tegra114-dalmore.dts             |   21 ++
>  arch/arm/boot/dts/tegra114-pluto.dts               |   21 ++
>  arch/arm/boot/dts/tegra114.dtsi                    |   89 ++++++++
>  arch/arm/mach-tegra/Kconfig                        |   10 +
>  arch/arm/mach-tegra/Makefile                       |    1 +
>  arch/arm/mach-tegra/board-dt-tegra114.c            |   48 +++++
>  arch/arm/mach-tegra/common.c                       |    1 +
>  arch/arm/mach-tegra/fuse.h                         |    1 +
>  arch/arm/mach-tegra/platsmp.c                      |   31 ++-
>  arch/arm/mach-tegra/tegra30_clocks_data.c          |    2 +
>  drivers/clocksource/tegra20_timer.c                |  222 +++++++++++++-------
>  13 files changed, 384 insertions(+), 78 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt
>  create mode 100644 arch/arm/boot/dts/tegra114-dalmore.dts
>  create mode 100644 arch/arm/boot/dts/tegra114-pluto.dts
>  create mode 100644 arch/arm/boot/dts/tegra114.dtsi
>  create mode 100644 arch/arm/mach-tegra/board-dt-tegra114.c
>