From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH 05/14] lib: Add I/O map cache implementation Date: Wed, 09 Jan 2013 16:12:31 -0700 Message-ID: <50EDF95F.4070209@wwwdotorg.org> References: <1357764194-12677-1-git-send-email-thierry.reding@avionic-design.de> <201301092119.57067.arnd@arndb.de> <20130109215428.GA13648@avionic-0098.adnet.avionic-design.de> <201301092210.49452.arnd@arndb.de> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <201301092210.49452.arnd-r2nGTMty4D4@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Arnd Bergmann Cc: Thierry Reding , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Grant Likely , Rob Herring , Russell King , Bjorn Helgaas , Andrew Murray , Jason Gunthorpe , Thomas Petazzoni , devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 01/09/2013 03:10 PM, Arnd Bergmann wrote: > On Wednesday 09 January 2013, Thierry Reding wrote: >> What happens on Tegra is that we need to map 256 MiB of physical memory >> to access all the PCIe extended configuration space. However, ioremap() >> on such a large region fails if not enough vmalloc() space is available. >> >> This was observed when somebody tested this on CardHu which has a 1 GiB >> of RAM and therefore remapping the full 256 MiB fails. ... > Have you checked if the hardware supports an alternative config > space access mechanism that does not depend on a huge address range? > A lot of them provide an index/data register pair somewhere, as the > original PC implementation did. That would be nice, but I've talked to the HW engineers, and there's no indication that any alternative mechanism exists.