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Tue, 16 Dec 2025 05:16:36 -0800 (PST) Message-ID: <50bea4bef338490cae92f61a8cc9a555db4529c2.camel@gmail.com> Subject: Re: [PATCH v4 2/3] hwmon: ltc4283: Add support for the LTC4283 Swap Controller From: Nuno =?ISO-8859-1?Q?S=E1?= To: Guenter Roeck , nuno.sa@analog.com, linux-hwmon@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Krzysztof Kozlowski , Conor Dooley , Jean Delvare , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski Date: Tue, 16 Dec 2025 13:17:17 +0000 In-Reply-To: References: <20251204-ltc4283-support-v4-0-db0197fd7984@analog.com> <20251204-ltc4283-support-v4-2-db0197fd7984@analog.com> <56a6c6a1b800090522a61eea5141aa8c986faea1.camel@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2025-12-12 at 09:07 -0800, Guenter Roeck wrote: > On 12/12/25 08:50, Nuno S=C3=A1 wrote: > > On Thu, 2025-12-11 at 09:56 -0800, Guenter Roeck wrote: > > > On 12/4/25 08:15, Nuno S=C3=A1 via B4 Relay wrote: > > > > From: Nuno S=C3=A1 > > > >=20 > > > > Support the LTC4283 How Swap Controller. The device features progra= mmable > > > > current limit with foldback and independently adjustable inrush cur= rent to > > > > optimize the MOSFET safe operating area (SOA). The SOA timer limits= MOSFET > > > > temperature rise for reliable protection against overstresses. > > > >=20 > > > > An I2C interface and onboard ADC allow monitoring of board current, > > > > voltage, power, energy, and fault status. > > > >=20 > > > > Signed-off-by: Nuno S=C3=A1 > > > > --- > > > ... > > > > diff --git a/drivers/hwmon/ltc4283.c b/drivers/hwmon/ltc4283.c > > > > new file mode 100644 > > > > index 000000000000..d79432678b84 > > > > --- /dev/null > > > > +++ b/drivers/hwmon/ltc4283.c > > > ... > > > > + > > > > +static int ltc4283_read_voltage_word(const struct ltc4283_hwmon *s= t, > > > > + =C2=A0=C2=A0=C2=A0=C2=A0 u32 reg, u32 fs, long *val) > > > > +{ > > > > + __be16 in; > > > > + int ret; > > > > + > > > > + ret =3D regmap_bulk_read(st->map, reg, &in, sizeof(in)); > > >=20 > > > I had a look into the regmap code. In its current implementation, > > > that will work as long as > > > 1) regmap is configured to not cache anything > > > 2) the I2C controller supports I2C_FUNC_SMBUS_I2C_BLOCK > > >=20 > >=20 > > Possibly dumb question... what would be the issue about doing multiple > > regmap reads if we can't do the bulk?=C2=A0That would be my naive appro= ach in > > the driver if I'm not going to use the bulk API. > >=20 >=20 > You mean on the same address ? I don't have the chip to check, but I am q= uite > sure that it would return the 1st byte again. >=20 > FWIW, in the lm92 driver I used a regmap_bus to solve pretty much the sam= e > problem. >=20 >=20 Ok, I know understand the issue. We do have real word registers (though the= energy spans 6 registers IIRC) in which case the regmap bulk fallback would fail. = So I do agree with you that relying on regmap implementation details is questionabl= e so I'll add my own bus. But the above made me start thinking about how we should handle i2c_check_functionality()? For this device, I2C_FUNC_SMBUS_WORD_DATA and I2C_FUNC_SMBUS_BYTE_DATA (can we have word without byte??) are the minimum = the controller needs to support. So I could add the below: if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA)) return -ENODEV; But can't we have I2C_FUNC_I2C (or even I2C_FUNC_SMBUS_I2C_BLOCK) without supporting SMBUS? I mean, I can so something similar to what's being done in regmap-i2c but m= aybe that's too much? I'm leaning in that direction though... This made me wonder, again, about ltc4282 but in there word registers are i= n fact reg and reg + 1. - Nuno S=C3=A1