[PATCH 1/3] Document: devicetree: add OF documents for MIPS interrupt controller

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* [PATCH 1/3] Document: devicetree: add OF documents for MIPS interrupt controller
@ 2013-01-31 13:20 John Crispin
  2013-01-31 13:20 ` [PATCH 2/3] MIPS: add irqdomain support for the CPU IRQ controller John Crispin
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: John Crispin @ 2013-01-31 13:20 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, devicetree-discuss, John Crispin

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 Documentation/devicetree/bindings/mips/cpu_irq.txt |   47 ++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/cpu_irq.txt

diff --git a/Documentation/devicetree/bindings/mips/cpu_irq.txt b/Documentation/devicetree/bindings/mips/cpu_irq.txt
new file mode 100644
index 0000000..13aa4b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cpu_irq.txt
@@ -0,0 +1,47 @@
+MIPS CPU interrupt controller
+
+On MIPS the mips_cpu_intc_init() helper can be used to initialize the 8 CPU
+IRQs from a devicetree file and create a irq_domain for IRQ controller.
+
+With the irq_domain in place we can describe how the 8 IRQs are wired to the
+platforms internal interrupt controller cascade.
+
+Below is an example of a platform describing the cascade inside the devicetree
+and the code used to load it inside arch_init_irq().
+
+Required properties:
+- compatible : Should be "mti,cpu-interrupt-controller"
+
+Example devicetree:
+	cpu-irq: cpu-irq@0 {
+		#address-cells = <0>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		compatible = "mti,cpu-interrupt-controller";
+	};
+
+	intc: intc@200 {
+		compatible = "ralink,rt2880-intc";
+		reg = <0x200 0x100>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		interrupt-parent = <&cpu-irq>;
+		interrupts = <2>;
+	};
+
+
+Example platform irq.c:
+static struct of_device_id __initdata of_irq_ids[] = {
+	{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
+	{ .compatible = "ralink,rt2880-intc", .data = intc_of_init },
+	{},
+};
+
+void __init arch_init_irq(void)
+{
+	of_irq_init(of_irq_ids);
+}
-- 
1.7.10.4

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH 2/3] MIPS: add irqdomain support for the CPU IRQ controller
  2013-01-31 13:20 [PATCH 1/3] Document: devicetree: add OF documents for MIPS interrupt controller John Crispin
@ 2013-01-31 13:20 ` John Crispin
  2013-01-31 13:20 ` [PATCH 3/3] MIPS: ralink: add CPU interrupt controller to of_irq_ids John Crispin
       [not found] ` <1359638444-8891-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
  2 siblings, 0 replies; 4+ messages in thread
From: John Crispin @ 2013-01-31 13:20 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, devicetree-discuss, Gabor Juhos, John Crispin

From: Gabor Juhos <juhosg@openwrt.org>

Add code to load a irq_domain for the MIPS IRQ controller from a devicetree
file.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/irq_cpu.h |    6 ++++++
 arch/mips/kernel/irq_cpu.c      |   42 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
index ef6a07c..3f11fdb 100644
--- a/arch/mips/include/asm/irq_cpu.h
+++ b/arch/mips/include/asm/irq_cpu.h
@@ -17,4 +17,10 @@ extern void mips_cpu_irq_init(void);
 extern void rm7k_cpu_irq_init(void);
 extern void rm9k_cpu_irq_init(void);
 
+#ifdef CONFIG_IRQ_DOMAIN
+struct device_node;
+extern int mips_cpu_intc_init(struct device_node *of_node,
+			      struct device_node *parent);
+#endif
+
 #endif /* _ASM_IRQ_CPU_H */
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 972263b..49bc9ca 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -31,6 +31,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 
 #include <asm/irq_cpu.h>
 #include <asm/mipsregs.h>
@@ -113,3 +114,44 @@ void __init mips_cpu_irq_init(void)
 		irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
 					 handle_percpu_irq);
 }
+
+#ifdef CONFIG_IRQ_DOMAIN
+static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
+			     irq_hw_number_t hw)
+{
+	static struct irq_chip *chip;
+
+	if (hw < 2 && cpu_has_mipsmt) {
+		/* Software interrupts are used for MT/CMT IPI */
+		chip = &mips_mt_cpu_irq_controller;
+	} else {
+		chip = &mips_cpu_irq_controller;
+	}
+
+	irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
+	.map = mips_cpu_intc_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+int __init mips_cpu_intc_init(struct device_node *of_node,
+			      struct device_node *parent)
+{
+	struct irq_domain *domain;
+
+	/* Mask interrupts. */
+	clear_c0_status(ST0_IM);
+	clear_c0_cause(CAUSEF_IP);
+
+	domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+				       &mips_cpu_intc_irq_domain_ops, NULL);
+	if (!domain)
+		panic("Failed to add irqdomain for MIPS CPU\n");
+
+	return 0;
+}
+#endif /* CONFIG_IRQ_DOMAIN */
-- 
1.7.10.4

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH 3/3] MIPS: ralink: add CPU interrupt controller to of_irq_ids
  2013-01-31 13:20 [PATCH 1/3] Document: devicetree: add OF documents for MIPS interrupt controller John Crispin
  2013-01-31 13:20 ` [PATCH 2/3] MIPS: add irqdomain support for the CPU IRQ controller John Crispin
@ 2013-01-31 13:20 ` John Crispin
       [not found] ` <1359638444-8891-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
  2 siblings, 0 replies; 4+ messages in thread
From: John Crispin @ 2013-01-31 13:20 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, devicetree-discuss, Gabor Juhos, John Crispin

From: Gabor Juhos <juhosg@openwrt.org>

Convert the ralink IRQ code to make use of the new MIPS IRQ controller OF
mappings.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/dts/rt305x.dts |   10 ++++++++++
 arch/mips/ralink/irq.c          |   10 +++++++---
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/mips/ralink/dts/rt305x.dts b/arch/mips/ralink/dts/rt305x.dts
index c7298f3..a9acdb2 100644
--- a/arch/mips/ralink/dts/rt305x.dts
+++ b/arch/mips/ralink/dts/rt305x.dts
@@ -11,6 +11,13 @@
 		};
 	};
 
+	cpuintc: cpuintc@0 {
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "mti,cpu-interrupt-controller";
+	};
+
 	memory@0 {
 		reg = <0x0 0x2000000>;
 	};
@@ -47,6 +54,9 @@
 
 			interrupt-controller;
 			#interrupt-cells = <1>;
+
+			interrupt-parent = <&cpuintc>;
+			interrupts = <2>;
 		};
 
 		memc@300 {
diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
index e62c975..6d054c5 100644
--- a/arch/mips/ralink/irq.c
+++ b/arch/mips/ralink/irq.c
@@ -128,8 +128,11 @@ static int __init intc_of_init(struct device_node *node,
 {
 	struct resource res;
 	struct irq_domain *domain;
+	int irq;
 
-	mips_cpu_irq_init();
+	irq = irq_of_parse_and_map(node, 0);
+	if (!irq)
+		panic("Failed to get INTC IRQ");
 
 	if (of_address_to_resource(node, 0, &res))
 		panic("Failed to get intc memory range");
@@ -156,8 +159,8 @@ static int __init intc_of_init(struct device_node *node,
 
 	rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
 
-	irq_set_chained_handler(RALINK_CPU_IRQ_INTC, ralink_intc_irq_handler);
-	irq_set_handler_data(RALINK_CPU_IRQ_INTC, domain);
+	irq_set_chained_handler(irq, ralink_intc_irq_handler);
+	irq_set_handler_data(irq, domain);
 
 	cp0_perfcount_irq = irq_create_mapping(domain, 9);
 
@@ -165,6 +168,7 @@ static int __init intc_of_init(struct device_node *node,
 }
 
 static struct of_device_id __initdata of_irq_ids[] = {
+	{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
 	{ .compatible = "ralink,rt2880-intc", .data = intc_of_init },
 	{},
 };
-- 
1.7.10.4

^ permalink raw reply related	[flat|nested] 4+ messages in thread

[parent not found: <1359638444-8891-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>]

* Re: [PATCH 1/3] Document: devicetree: add OF documents for MIPS interrupt controller
       [not found] ` <1359638444-8891-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
@ 2013-01-31 17:07   ` David Daney
  0 siblings, 0 replies; 4+ messages in thread
From: David Daney @ 2013-01-31 17:07 UTC (permalink / raw)
  To: John Crispin
  Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
	devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Ralf Baechle

On 01/31/2013 05:20 AM, John Crispin wrote:
> Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Acked-by: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>

> ---
>   Documentation/devicetree/bindings/mips/cpu_irq.txt |   47 ++++++++++++++++++++
>   1 file changed, 47 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/mips/cpu_irq.txt
>
> diff --git a/Documentation/devicetree/bindings/mips/cpu_irq.txt b/Documentation/devicetree/bindings/mips/cpu_irq.txt
> new file mode 100644
> index 0000000..13aa4b6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/cpu_irq.txt
> @@ -0,0 +1,47 @@
> +MIPS CPU interrupt controller
> +
> +On MIPS the mips_cpu_intc_init() helper can be used to initialize the 8 CPU
> +IRQs from a devicetree file and create a irq_domain for IRQ controller.
> +
> +With the irq_domain in place we can describe how the 8 IRQs are wired to the
> +platforms internal interrupt controller cascade.
> +
> +Below is an example of a platform describing the cascade inside the devicetree
> +and the code used to load it inside arch_init_irq().
> +
> +Required properties:
> +- compatible : Should be "mti,cpu-interrupt-controller"
> +
> +Example devicetree:
> +	cpu-irq: cpu-irq@0 {
> +		#address-cells = <0>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +
> +		compatible = "mti,cpu-interrupt-controller";
> +	};
> +
> +	intc: intc@200 {
> +		compatible = "ralink,rt2880-intc";
> +		reg = <0x200 0x100>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +
> +		interrupt-parent = <&cpu-irq>;
> +		interrupts = <2>;
> +	};
> +
> +
> +Example platform irq.c:
> +static struct of_device_id __initdata of_irq_ids[] = {
> +	{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
> +	{ .compatible = "ralink,rt2880-intc", .data = intc_of_init },
> +	{},
> +};
> +
> +void __init arch_init_irq(void)
> +{
> +	of_irq_init(of_irq_ids);
> +}
>

^ permalink raw reply	[flat|nested] 4+ messages in thread

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2013-01-31 13:20 [PATCH 1/3] Document: devicetree: add OF documents for MIPS interrupt controller John Crispin
2013-01-31 13:20 ` [PATCH 2/3] MIPS: add irqdomain support for the CPU IRQ controller John Crispin
2013-01-31 13:20 ` [PATCH 3/3] MIPS: ralink: add CPU interrupt controller to of_irq_ids John Crispin
     [not found] ` <1359638444-8891-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2013-01-31 17:07   ` [PATCH 1/3] Document: devicetree: add OF documents for MIPS interrupt controller David Daney

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