Re: [RFC PATCH 4/6] riscv: select RISCV_ISA_XPBMTUC in STARFIVE and ESWIN SoC

[Bo Gan <ganboing@gmail.com>]

Hi Conor,

On 3/13/26 06:28, Conor Dooley wrote:
> On Fri, Mar 13, 2026 at 01:44:05AM -0700, Bo Gan wrote:
>> Enable the XPbmtUC feature for Starfive and ESWIN SoC
>>
>> Signed-off-by: Bo Gan <ganboing@gmail.com>
>> ---
>>   arch/riscv/Kconfig.socs | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>> index d621b85dd63bd..0584511707c7c 100644
>> --- a/arch/riscv/Kconfig.socs
>> +++ b/arch/riscv/Kconfig.socs
>> @@ -14,6 +14,7 @@ config ARCH_ANLOGIC
>>   
>>   config ARCH_ESWIN
>>   	bool "ESWIN SoCs"
>> +	select RISCV_ISA_XPBMTUC
> 
> Nah, you can't do this. Either RISCV_ISA_XPBMTUC is user selectable or
> it is mandatory for these platforms and selected. Don't mix and match
> please.
> 

Sure.

>>   	help
>>   	  This enables support for ESWIN SoC platform hardware,
>>   	  including the ESWIN EIC7700 SoC.
>> @@ -56,6 +57,7 @@ config SOC_STARFIVE
>>   	select PINCTRL
>>   	select RESET_CONTROLLER
>>   	select ARM_AMBA
>> +	select RISCV_ISA_XPBMTUC
>>   	help
>>   	  This enables support for StarFive SoC platform hardware.
>>   
>> -- 
>> 2.34.1
>>

Bo