From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matthias Brugger Subject: Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 Date: Sun, 3 Jul 2016 21:12:11 +0200 Message-ID: <51441f39-e5b5-2cce-63ab-47bd3cf298b3@gmail.com> References: <1465379461-14757-1-git-send-email-honghui.zhang@mediatek.com> <1465379461-14757-6-git-send-email-honghui.zhang@mediatek.com> <09eaf7a5-2b18-1ea6-5699-2e968c6b79a4@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <09eaf7a5-2b18-1ea6-5699-2e968c6b79a4-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org Cc: youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, pebolle-IWqWACnzNjzz+pZb47iToQ@public.gmane.org, kendrick.hsu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, arnd-r2nGTMty4D4@public.gmane.org, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, catalin.marinas-5wv7dgnIgG8@public.gmane.org, erin.lo-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, tfiga-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, djkurtz-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org, yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org List-Id: devicetree@vger.kernel.org On 07/03/2016 08:24 AM, Matthias Brugger wrote: > > > On 06/08/2016 11:51 AM, honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote: >> From: Honghui Zhang >> >> Add the dtsi node of iommu and smi for mt2701. >> >> Signed-off-by: Honghui Zhang >> --- >> arch/arm/boot/dts/mt2701.dtsi | 51 >> +++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 51 insertions(+) >> > > Applied, Please resend the patch including the infracfg and mmsys node. Regards, Matthias > > Thanks. > >> diff --git a/arch/arm/boot/dts/mt2701.dtsi >> b/arch/arm/boot/dts/mt2701.dtsi >> index 42d5a37..363de0d 100644 >> --- a/arch/arm/boot/dts/mt2701.dtsi >> +++ b/arch/arm/boot/dts/mt2701.dtsi >> @@ -16,6 +16,7 @@ >> #include >> #include >> #include >> +#include >> #include "skeleton64.dtsi" >> #include "mt2701-pinfunc.h" >> >> @@ -160,6 +161,16 @@ >> clock-names = "system-clk", "rtc-clk"; >> }; >> >> + smi_common: smi@1000c000 { >> + compatible = "mediatek,mt2701-smi-common"; >> + reg = <0 0x1000c000 0 0x1000>; >> + clocks = <&infracfg CLK_INFRA_SMI>, >> + <&mmsys CLK_MM_SMI_COMMON>, >> + <&infracfg CLK_INFRA_SMI>; >> + clock-names = "apb", "smi", "async"; >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; >> + }; >> + >> sysirq: interrupt-controller@10200100 { >> compatible = "mediatek,mt2701-sysirq", >> "mediatek,mt6577-sysirq"; >> @@ -169,6 +180,16 @@ >> reg = <0 0x10200100 0 0x1c>; >> }; >> >> + iommu: mmsys_iommu@10205000 { >> + compatible = "mediatek,mt2701-m4u"; >> + reg = <0 0x10205000 0 0x1000>; >> + interrupts = ; >> + clocks = <&infracfg CLK_INFRA_M4U>; >> + clock-names = "bclk"; >> + mediatek,larbs = <&larb0 &larb1 &larb2>; >> + #iommu-cells = <1>; >> + }; >> + >> apmixedsys: syscon@10209000 { >> compatible = "mediatek,mt2701-apmixedsys", "syscon"; >> reg = <0 0x10209000 0 0x1000>; >> @@ -234,6 +255,16 @@ >> status = "disabled"; >> }; >> >> + larb0: larb@14010000 { >> + compatible = "mediatek,mt2701-smi-larb"; >> + reg = <0 0x14010000 0 0x1000>; >> + mediatek,smi = <&smi_common>; >> + clocks = <&mmsys CLK_MM_SMI_LARB0>, >> + <&mmsys CLK_MM_SMI_LARB0>; >> + clock-names = "apb", "smi"; >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; >> + }; >> + >> imgsys: syscon@15000000 { >> compatible = "mediatek,mt2701-imgsys", "syscon"; >> reg = <0 0x15000000 0 0x1000>; >> @@ -241,6 +272,16 @@ >> status = "disabled"; >> }; >> >> + larb2: larb@15001000 { >> + compatible = "mediatek,mt2701-smi-larb"; >> + reg = <0 0x15001000 0 0x1000>; >> + mediatek,smi = <&smi_common>; >> + clocks = <&imgsys CLK_IMG_SMI_COMM>, >> + <&imgsys CLK_IMG_SMI_COMM>; >> + clock-names = "apb", "smi"; >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; >> + }; >> + >> vdecsys: syscon@16000000 { >> compatible = "mediatek,mt2701-vdecsys", "syscon"; >> reg = <0 0x16000000 0 0x1000>; >> @@ -248,6 +289,16 @@ >> status = "disabled"; >> }; >> >> + larb1: larb@16010000 { >> + compatible = "mediatek,mt2701-smi-larb"; >> + reg = <0 0x16010000 0 0x1000>; >> + mediatek,smi = <&smi_common>; >> + clocks = <&vdecsys CLK_VDEC_CKGEN>, >> + <&vdecsys CLK_VDEC_LARB>; >> + clock-names = "apb", "smi"; >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; >> + }; >> + >> hifsys: syscon@1a000000 { >> compatible = "mediatek,mt2701-hifsys", "syscon"; >> reg = <0 0x1a000000 0 0x1000>; >>