devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Vinod Koul <vkoul@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH 3/6] dt-bindings: pci/qcom-pcie: specify reg-names explicitly
Date: Fri, 22 Apr 2022 22:09:32 +0300	[thread overview]
Message-ID: <5149ef96-0cdd-64cc-091f-bc97c04e7835@linaro.org> (raw)
In-Reply-To: <338344c8-1812-de27-80f2-df4c2dc3c17b@linaro.org>

On 22/04/2022 18:51, Krzysztof Kozlowski wrote:
> On 22/04/2022 17:47, Dmitry Baryshkov wrote:
>> On Fri, 22 Apr 2022 at 15:55, Krzysztof Kozlowski
>> <krzysztof.kozlowski@linaro.org> wrote:
>>>
>>> On 22/04/2022 13:48, Dmitry Baryshkov wrote:
>>>> Instead of specifying the enum of possible reg-names, specify them
>>>> explicitly. This allows us to specify which chipsets need the "atu"
>>>> regions, which do not. Also it clearly describes which platforms
>>>> enumerate PCIe cores using the dbi region and which use parf region for
>>>> that.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>>>   .../devicetree/bindings/pci/qcom,pcie.yaml    | 96 ++++++++++++++++---
>>>>   1 file changed, 81 insertions(+), 15 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>> index 7210057d1511..e78e63ea4b25 100644
>>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>> @@ -35,21 +35,6 @@ properties:
>>>>             - qcom,pcie-ipq6018
>>>>         - const: snps,dw-pcie
>>>>
>>>> -  reg:
>>>> -    minItems: 4
>>>> -    maxItems: 5
>>>
>>> This should stay.
>>>
>>>> -
>>>> -  reg-names:
>>>> -    minItems: 4
>>>> -    maxItems: 5
>>>> -    items:
>>>> -      enum:
>>>> -        - parf # Qualcomm specific registers
>>>> -        - dbi # DesignWare PCIe registers
>>>> -        - elbi # External local bus interface registers
>>>> -        - config # PCIe configuration space
>>>> -        - atu # ATU address space (optional)
>>>
>>> Move one of your lists for specific compatibles here and name last
>>> element optional (minItems: 4).
>>>
>>> You will need to fix the order of regs in DTS to match the one defined here.
>>
>> I see your idea. I wanted to be explicit, which platforms need atu and
>> which do not. You'd prefer not to.
> 
> Opposite, I wish platforms to be specific, which need atu which not.
> However I wish the strictly defined, same order for everyone because it
> looks possible.

Well, the same order is not possible, since for some devices the first, 
address-defining reg is "parf", for others it is "dbi". So, there will 
be two "families" of the devices. Unless we want to change the DT 
address of the unit.

>> Let's probably drop this for now. The bindings proposed in patch 1
>> work for now. I will work on updating reg-names later.
> 
> 
> Best regards,
> Krzysztof


-- 
With best wishes
Dmitry

  reply	other threads:[~2022-04-22 19:29 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22 11:48 [PATCH 0/6] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
2022-04-22 11:48 ` [PATCH 1/6] dt-bindings: pci/qcom,pcie: convert to YAML Dmitry Baryshkov
2022-04-22 13:10   ` Krzysztof Kozlowski
2022-04-22 16:49     ` Dmitry Baryshkov
2022-04-22 11:48 ` [PATCH 2/6] dt-bindings: pci/qcom,pcie: add schema for sc7280 chipset Dmitry Baryshkov
2022-04-22 13:11   ` Krzysztof Kozlowski
2022-04-22 11:48 ` [PATCH 3/6] dt-bindings: pci/qcom-pcie: specify reg-names explicitly Dmitry Baryshkov
2022-04-22 12:55   ` Krzysztof Kozlowski
2022-04-22 15:47     ` Dmitry Baryshkov
2022-04-22 15:51       ` Krzysztof Kozlowski
2022-04-22 19:09         ` Dmitry Baryshkov [this message]
2022-04-23  9:48           ` Krzysztof Kozlowski
2022-04-22 11:48 ` [PATCH 4/6] dt-bindings: pci/qcom,pcie: stop using snps,dw-pcie fallback Dmitry Baryshkov
2022-04-22 13:13   ` Krzysztof Kozlowski
2022-04-22 11:48 ` [PATCH 5/6] arm64: dts: qcom: stop using snps,dw-pcie falback Dmitry Baryshkov
2022-04-22 13:20   ` Krzysztof Kozlowski
2022-04-22 11:48 ` [PATCH 6/6] arm: " Dmitry Baryshkov
2022-04-22 13:19   ` Krzysztof Kozlowski
2022-04-22 13:19 ` [PATCH 0/6] dt-bindings: YAMLify pci/qcom,pcie schema Krzysztof Kozlowski

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5149ef96-0cdd-64cc-091f-bc97c04e7835@linaro.org \
    --to=dmitry.baryshkov@linaro.org \
    --cc=agross@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=bjorn.andersson@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=krzysztof.kozlowski@linaro.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=robh+dt@kernel.org \
    --cc=svarbanov@mm-sol.com \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).