* [RFC 01/12] exynos-fimc-is: Adding device tree nodes
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-23 13:14 ` Sylwester Nawrocki
2013-03-08 14:59 ` [RFC 02/12] exynos-fimc-is: Adding ARCH support for fimc-is Arun Kumar K
` (10 subsequent siblings)
11 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
Add the fimc-is node and the required pinctrl nodes for
fimc-is driver for Exynos5. Also adds the DT binding documentation
for the new fimc-is node.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
.../devicetree/bindings/media/soc/exynos5-is.txt | 81 ++++++++++++++++++++
arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 60 +++++++++++++++
arch/arm/boot/dts/exynos5250-smdk5250.dts | 54 ++++++++++++-
arch/arm/boot/dts/exynos5250.dtsi | 8 ++
4 files changed, 201 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/soc/exynos5-is.txt
mode change 100644 => 100755 arch/arm/boot/dts/exynos5250-smdk5250.dts
mode change 100644 => 100755 arch/arm/boot/dts/exynos5250.dtsi
diff --git a/Documentation/devicetree/bindings/media/soc/exynos5-is.txt b/Documentation/devicetree/bindings/media/soc/exynos5-is.txt
new file mode 100644
index 0000000..e0fdf02
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/soc/exynos5-is.txt
@@ -0,0 +1,81 @@
+Samsung EXYNOS SoC Camera Subsystem
+-----------------------------------
+
+The camera subsystem on Samsung Exynos5 SoC has some changes relative
+to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
+FIMC-LITE IPs but removed the FIMC-CAPTURE. Instead it has an improved
+FIMC-IS which can provide imate data DMA output.
+
+The device tree binding remain similar to the Exynos4 bindings which can
+be seen at samsung-fimc.txt with the addition of fimc-is sub-node which will
+be explained here.
+
+fimc-is subnode of camera node
+------------------------------
+
+Required properties:
+
+- compatible : must be "samsung,exynos5250-fimc-is"
+- reg : physical base address and size of the memory mapped
+ registers
+- interrupt-parent : Parent interrupt controller
+- interrupts : fimc-is interrupt to the parent combiner
+
+Board specific properties:
+
+- pinctrl-names : pinctrl names for camera port pinmux control, at least
+ "default" needs to be specified.
+- pinctrl-0...N : pinctrl properties corresponding to pinctrl-names
+
+Sensor sub-nodes:
+
+FIMC-IS IP supports custom built sensors to be controlled exclusively by
+the FIMC-IS firmware. These sensor properties are to be defined here.
+Sensor nodes are described in the same way as in generic sensors used in
+Exynos4 and described in samsung-fimc.txt.
+
+Example:
+
+SoC common node:
+
+ fimc_is: fimc-is@13000000 {
+ compatible = "samsung,exynos5250-fimc-is";
+ reg = <0x13000000 0x200000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <19 1>;
+ status = "disabled";
+ };
+
+Board specific node:
+
+ fimc-is@13000000 {
+ status = "okay";
+ pinctrl-0 =
+ <&cam_port_a_clk_active
+ &cam_bayer_clk_active
+ &isp_uart
+ &cam_i2c0
+ &cam_i2c1>;
+ pinctrl-names = "default";
+ s5k4e5 {
+ compatible = "samsung,s5k4e5";
+ gpios = <&gpx1 2 1>;
+ clock-frequency = <24000000>;
+ port {
+ is_s5k4e5_ep: endpoint {
+ remote-endpoint = <&csis0_ep>;
+ };
+ };
+ };
+ s5k6a3 {
+ compatible = "samsung,s5k6a3";
+ gpios = <&gpx1 0 1>;
+ clock-frequency = <24000000>;
+ port {
+ is_s5k6a3_ep: endpoint {
+ remote-endpoint = <&csis1_ep>;
+ };
+ };
+ };
+ };
+
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index 3caaa21..320c22b 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -556,6 +556,38 @@
};
pinctrl@13400000 {
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
gph0: gph0 {
gpio-controller;
#gpio-cells = <2>;
@@ -594,6 +626,34 @@
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
+
+ cam_bayer_clk_active: cam-bayer-clk-active {
+ samsung,pins = "gpg2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ isp_uart: isp-uart {
+ samsung,pins = "gpe1-0", "gpe1-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ cam_i2c0: cam-i2c0 {
+ samsung,pins = "gpf0-0", "gpf0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ cam_i2c1: cam-i2c1 {
+ samsung,pins = "gpf0-2", "gpf0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
};
pinctrl_3: pinctrl@03680000 {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
old mode 100644
new mode 100755
index 356e014..0a2da64
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -92,6 +92,7 @@
m5mols@1f {
compatible = "fujitsu,m-5mols";
+ status = "disabled";
reg = <0x1F>;
gpios = <&gpx3 3 0xf>, <&gpx1 2 1>;
clock-frequency = <24000000>;
@@ -242,7 +243,7 @@
csis_0: csis@13C20000 {
status = "okay";
- clock-frequency = <166000000>;
+ clock-frequency = <267000000>; /* s5k4e5 */
#address-cells = <1>;
#size-cells = <0>;
@@ -250,7 +251,7 @@
port@3 {
reg = <3>;
csis0_ep: endpoint {
- remote-endpoint = <&m5mols_ep>;
+ remote-endpoint = <&is_s5k4e5_ep>;
data-lanes = <1 2 3 4>;
samsung,csis-hs-settle = <12>;
samsung,csis-wclk;
@@ -258,5 +259,54 @@
};
};
+ csis_1: csis@13C30000 {
+ status = "okay";
+ clock-frequency = <160000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Camera D (4) MIPI CSI-2 (CSIS1) */
+ port@4 {
+ reg = <4>;
+ csis1_ep: endpoint {
+ remote-endpoint = <&is_s5k6a3_ep>;
+ data-lanes = <1>;
+ samsung,csis-hs-settle = <18>;
+ samsung,csis-wclk;
+ };
+ };
+ };
+
+ fimc-is@13000000 {
+ status = "okay";
+ pinctrl-0 =
+ <&cam_port_a_clk_active
+ &cam_bayer_clk_active
+ &isp_uart
+ &cam_i2c0
+ &cam_i2c1>;
+ pinctrl-names = "default";
+ s5k4e5 {
+ compatible = "samsung,s5k4e5";
+ gpios = <&gpx1 2 1>;
+ clock-frequency = <24000000>;
+ port {
+ is_s5k4e5_ep: endpoint {
+ remote-endpoint = <&csis0_ep>;
+ };
+ };
+ };
+ s5k6a3 {
+ compatible = "samsung,s5k6a3";
+ gpios = <&gpx1 0 1>;
+ clock-frequency = <24000000>;
+ port {
+ is_s5k6a3_ep: endpoint {
+ remote-endpoint = <&csis1_ep>;
+ };
+ };
+ };
+ };
+
};
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
old mode 100644
new mode 100755
index 564c05f..e18df49
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -410,5 +410,13 @@
bus-width = <2>;
status = "disabled";
};
+
+ fimc_is: fimc-is@13000000 {
+ compatible = "samsung,exynos5250-fimc-is";
+ reg = <0x13000000 0x200000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <19 1>;
+ status = "disabled";
+ };
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes
2013-03-08 14:59 ` [RFC 01/12] exynos-fimc-is: Adding device tree nodes Arun Kumar K
@ 2013-03-23 13:14 ` Sylwester Nawrocki
2013-03-26 12:17 ` Arun Kumar K
0 siblings, 1 reply; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-23 13:14 UTC (permalink / raw)
To: Arun Kumar K
Cc: linux-media, linux-samsung-soc, devicetree-discuss, s.nawrocki,
kgene.kim, kilyeon.im, arunkk.samsung
On 03/08/2013 03:59 PM, Arun Kumar K wrote:
> Add the fimc-is node and the required pinctrl nodes for
> fimc-is driver for Exynos5. Also adds the DT binding documentation
> for the new fimc-is node.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
> .../devicetree/bindings/media/soc/exynos5-is.txt | 81 ++++++++++++++++++++
> arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 60 +++++++++++++++
> arch/arm/boot/dts/exynos5250-smdk5250.dts | 54 ++++++++++++-
> arch/arm/boot/dts/exynos5250.dtsi | 8 ++
> 4 files changed, 201 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/media/soc/exynos5-is.txt
> mode change 100644 => 100755 arch/arm/boot/dts/exynos5250-smdk5250.dts
> mode change 100644 => 100755 arch/arm/boot/dts/exynos5250.dtsi
I suspect this mode change wasn't intentional.
> diff --git a/Documentation/devicetree/bindings/media/soc/exynos5-is.txt b/Documentation/devicetree/bindings/media/soc/exynos5-is.txt
> new file mode 100644
> index 0000000..e0fdf02
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/soc/exynos5-is.txt
> @@ -0,0 +1,81 @@
> +Samsung EXYNOS SoC Camera Subsystem
> +-----------------------------------
> +
> +The camera subsystem on Samsung Exynos5 SoC has some changes relative
> +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
> +FIMC-LITE IPs but removed the FIMC-CAPTURE. Instead it has an improved
s/FIMC-CAPTURE/FIMC IPs (IP blocks) ?
> +FIMC-IS which can provide imate data DMA output.
s/imate/image
Not sure if this is true. FIMC (camera host interface and video
post-processor)
IPs have been removed, but I think they were replaced with GSCALER.
There is
FIMC-IS on both Exynos4 and Exynos5 series.
> +
> +The device tree binding remain similar to the Exynos4 bindings which can
> +be seen at samsung-fimc.txt with the addition of fimc-is sub-node which will
> +be explained here.
> +
> +fimc-is subnode of camera node
> +------------------------------
> +
> +Required properties:
> +
> +- compatible : must be "samsung,exynos5250-fimc-is"
> +- reg : physical base address and size of the memory mapped
> + registers
> +- interrupt-parent : Parent interrupt controller
> +- interrupts : fimc-is interrupt to the parent combiner
> +
> +Board specific properties:
> +
> +- pinctrl-names : pinctrl names for camera port pinmux control, at least
> + "default" needs to be specified.
> +- pinctrl-0...N : pinctrl properties corresponding to pinctrl-names
> +
> +Sensor sub-nodes:
> +
> +FIMC-IS IP supports custom built sensors to be controlled exclusively by
> +the FIMC-IS firmware. These sensor properties are to be defined here.
What this means is that the software architecture defines how we describe
the hardware. I have serious doubts about this approach. I do recall this
concept was used in an early version of code I shared with you. But then
I decided to describe the I2C bus controllers (other bus controllers could
be probably added later when required) in usual way, as fimc-is node child
nodes or standalone, at root level.
The reason is that all these peripheral bus controllers are accessible in
same way by the FIMC-IS and the host CPU. Their interrupts are routed to
both, and registers regions are visible to both CPUs as well. AFAIK ISP I2C
bus controllers are directly compatible with s3c2440, so on some systems
that do not use the IS these I2C controllers should in theory work without
problems with current i2c-s3c2410 I2C bus driver.
Defining image sensor nodes in a standard way as ISP I2C bus controller
nodes has an disadvantage that we need dummy I2C bus controller driver,
at least this is how I have written the driver for Exynos4x12. In some
version of it I had sensor nodes put in a isp-i2c fimc-is sub-node, but
then there was an issue that this was not a fully specified I2C bus
controller node.
You can refer to my exynos4 fimc-is patch series for details on how this
is now implemented.
Handling the image sensor in a standard way, as regular I2C client devices
has an advantage that we can put pinctrl properties in relevant device
nodes,
where available, which more closely describes the hardware structure.
I'm not really sure in 100% if all this complication is required. It would
allow to use same DT blob for different Imaging Subsystem SW architecture.
For example some parts of functionality handled currently by FIMC-IS (ARM
Cortex-A5) could be moved to host CPU, without any change in the device
tree structure. The kernel could decide e.g. if it uses image sensor driver
implemented in the ISP firmware, or a driver run on the host CPU.
What do you think ?
Thanks,
Sylwester
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes
2013-03-23 13:14 ` Sylwester Nawrocki
@ 2013-03-26 12:17 ` Arun Kumar K
2013-03-26 22:51 ` Sylwester Nawrocki
0 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-26 12:17 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: Arun Kumar K, LMML, linux-samsung-soc, devicetree-discuss,
Sylwester Nawrocki, kgene.kim, kilyeon.im
Hi Sylwester,
Thank you for the review.
>> +Sensor sub-nodes:
>> +
>> +FIMC-IS IP supports custom built sensors to be controlled exclusively by
>> +the FIMC-IS firmware. These sensor properties are to be defined here.
>
[snip]
>
> Defining image sensor nodes in a standard way as ISP I2C bus controller
> nodes has an disadvantage that we need dummy I2C bus controller driver,
> at least this is how I have written the driver for Exynos4x12. In some
> version of it I had sensor nodes put in a isp-i2c fimc-is sub-node, but
> then there was an issue that this was not a fully specified I2C bus
> controller node.
>
> You can refer to my exynos4 fimc-is patch series for details on how this
> is now implemented.
>
> Handling the image sensor in a standard way, as regular I2C client devices
> has an advantage that we can put pinctrl properties in relevant device
> nodes,
> where available, which more closely describes the hardware structure.
>
> I'm not really sure in 100% if all this complication is required. It would
> allow to use same DT blob for different Imaging Subsystem SW architecture.
> For example some parts of functionality handled currently by FIMC-IS (ARM
> Cortex-A5) could be moved to host CPU, without any change in the device
> tree structure. The kernel could decide e.g. if it uses image sensor driver
> implemented in the ISP firmware, or a driver run on the host CPU.
>
> What do you think ?
>
I have seen your Exynos4 FIMC-IS patchset and you have made a dummy
I2C sensor driver there.
That mode would work fine in Exynos4 since the sensor and ISP will be used
by the same media controller pipeline. So the ISP component in the pipeline
will ensure that the HW is initialized and sensor is working.
But in Exynos5, we are using sensor in pipeline0 and ISP in pipeline1.
So there is a possibility of using sensor subdev independently
without using pipeline1 ISP components.
So with the driver I sent, the pipeline0 can still work like this -->
ISP sensor ---> MIPI-CSIS ---> FIMC-LITE ---> Memory
This cannot be done if a dummy I2C driver is made for ISP sensor.
What is your suggestion on this?
Regards
Arun
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes
2013-03-26 12:17 ` Arun Kumar K
@ 2013-03-26 22:51 ` Sylwester Nawrocki
2013-03-27 4:31 ` Arun Kumar K
0 siblings, 1 reply; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-26 22:51 UTC (permalink / raw)
To: Arun Kumar K
Cc: Sylwester Nawrocki, Arun Kumar K, LMML, linux-samsung-soc,
devicetree-discuss, Sylwester Nawrocki, kgene.kim, kilyeon.im
On 03/26/2013 01:17 PM, Arun Kumar K wrote:
>>> +Sensor sub-nodes:
>>> +
>>> +FIMC-IS IP supports custom built sensors to be controlled exclusively by
>>> +the FIMC-IS firmware. These sensor properties are to be defined here.
>
> [snip]
>
>> Defining image sensor nodes in a standard way as ISP I2C bus controller
>> nodes has an disadvantage that we need dummy I2C bus controller driver,
>> at least this is how I have written the driver for Exynos4x12. In some
>> version of it I had sensor nodes put in a isp-i2c fimc-is sub-node, but
>> then there was an issue that this was not a fully specified I2C bus
>> controller node.
>>
>> You can refer to my exynos4 fimc-is patch series for details on how this
>> is now implemented.
>>
>> Handling the image sensor in a standard way, as regular I2C client devices
>> has an advantage that we can put pinctrl properties in relevant device
>> nodes,
>> where available, which more closely describes the hardware structure.
>>
>> I'm not really sure in 100% if all this complication is required. It would
>> allow to use same DT blob for different Imaging Subsystem SW architecture.
>> For example some parts of functionality handled currently by FIMC-IS (ARM
>> Cortex-A5) could be moved to host CPU, without any change in the device
>> tree structure. The kernel could decide e.g. if it uses image sensor driver
>> implemented in the ISP firmware, or a driver run on the host CPU.
>>
>> What do you think ?
>
> I have seen your Exynos4 FIMC-IS patchset and you have made a dummy
> I2C sensor driver there.
> That mode would work fine in Exynos4 since the sensor and ISP will be used
> by the same media controller pipeline. So the ISP component in the pipeline
> will ensure that the HW is initialized and sensor is working.
>
> But in Exynos5, we are using sensor in pipeline0 and ISP in pipeline1.
> So there is a possibility of using sensor subdev independently
> without using pipeline1 ISP components.
>
> So with the driver I sent, the pipeline0 can still work like this -->
>
> ISP sensor ---> MIPI-CSIS ---> FIMC-LITE ---> Memory
>
> This cannot be done if a dummy I2C driver is made for ISP sensor.
Why not ? I'm not sure what the problem is here.
I realize that describing image sensors in DT as standard I2C slave devices
is not helpful with current firmware architecture. It adds some unnecessary
complication, OTOH it could simplify the sensors registration and media
graph
initialization code, by unifying it for the firmware based ISP specific
sensors and the external ones with a built-in ISP. Also we could avoid
having
the bindings defined by current architecture of the driver.
Nevertheless, coming back to your question, the I2C controller driver would
be in same module as the FIMC-IS driver. From user space perspective nothing
changes when you add I2C bus driver and register the sensor in a
standard way.
What exactly couldn't be done in the kernel ?
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes
2013-03-26 22:51 ` Sylwester Nawrocki
@ 2013-03-27 4:31 ` Arun Kumar K
2013-03-27 13:47 ` Sylwester Nawrocki
0 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-27 4:31 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: Arun Kumar K, LMML, linux-samsung-soc, devicetree-discuss,
Sylwester Nawrocki, kgene.kim, kilyeon.im
On Wed, Mar 27, 2013 at 4:21 AM, Sylwester Nawrocki
<sylvester.nawrocki@gmail.com> wrote:
> On 03/26/2013 01:17 PM, Arun Kumar K wrote:
>>>>
>>>> +Sensor sub-nodes:
>>>> +
>>>> +FIMC-IS IP supports custom built sensors to be controlled exclusively
>>>> by
>>>> +the FIMC-IS firmware. These sensor properties are to be defined here.
>>
>>
>> [snip]
>>
>>> Defining image sensor nodes in a standard way as ISP I2C bus controller
>>> nodes has an disadvantage that we need dummy I2C bus controller driver,
>>> at least this is how I have written the driver for Exynos4x12. In some
>>> version of it I had sensor nodes put in a isp-i2c fimc-is sub-node, but
>>> then there was an issue that this was not a fully specified I2C bus
>>> controller node.
>>>
>>> You can refer to my exynos4 fimc-is patch series for details on how this
>>> is now implemented.
>>>
>>> Handling the image sensor in a standard way, as regular I2C client
>>> devices
>>> has an advantage that we can put pinctrl properties in relevant device
>>> nodes,
>>> where available, which more closely describes the hardware structure.
>>>
>>> I'm not really sure in 100% if all this complication is required. It
>>> would
>>> allow to use same DT blob for different Imaging Subsystem SW
>>> architecture.
>>> For example some parts of functionality handled currently by FIMC-IS (ARM
>>> Cortex-A5) could be moved to host CPU, without any change in the device
>>> tree structure. The kernel could decide e.g. if it uses image sensor
>>> driver
>>> implemented in the ISP firmware, or a driver run on the host CPU.
>>>
>>> What do you think ?
>>
>>
>> I have seen your Exynos4 FIMC-IS patchset and you have made a dummy
>> I2C sensor driver there.
>> That mode would work fine in Exynos4 since the sensor and ISP will be used
>> by the same media controller pipeline. So the ISP component in the
>> pipeline
>> will ensure that the HW is initialized and sensor is working.
>>
>> But in Exynos5, we are using sensor in pipeline0 and ISP in pipeline1.
>> So there is a possibility of using sensor subdev independently
>> without using pipeline1 ISP components.
>>
>> So with the driver I sent, the pipeline0 can still work like this -->
>>
>> ISP sensor ---> MIPI-CSIS ---> FIMC-LITE ---> Memory
>>
>> This cannot be done if a dummy I2C driver is made for ISP sensor.
>
>
> Why not ? I'm not sure what the problem is here.
>
> I realize that describing image sensors in DT as standard I2C slave devices
> is not helpful with current firmware architecture. It adds some unnecessary
> complication, OTOH it could simplify the sensors registration and media
> graph
> initialization code, by unifying it for the firmware based ISP specific
> sensors and the external ones with a built-in ISP. Also we could avoid
> having
> the bindings defined by current architecture of the driver.
>
> Nevertheless, coming back to your question, the I2C controller driver would
> be in same module as the FIMC-IS driver. From user space perspective nothing
> changes when you add I2C bus driver and register the sensor in a standard
> way.
> What exactly couldn't be done in the kernel ?
Only issue is with the context sharing.
Right now you can see that the fimc-is context is shared between all
the subdevs.
As all of them are part of the same driver, it is possible.
If sensor is made as an independent i2c device, a separate probe will
be called for it.
For ISP sensor subdev to work independently, it needs to call the
fimc_is_pipeline_* calls
for FW initialization and other configurations for which it needs the
fimc-is main context.
Now there is a workaround here by calling a get_context() macro in
sensor's probe
to get the fimc-is context. This will cause the same context to be
shared and updated by
2 drivers though both are part of fimc-is.
Is this acceptable? Or am I missing some other simple solution of implementing
it in a better way?
Regards
Arun
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes
2013-03-27 4:31 ` Arun Kumar K
@ 2013-03-27 13:47 ` Sylwester Nawrocki
2013-03-28 5:10 ` Arun Kumar K
0 siblings, 1 reply; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-27 13:47 UTC (permalink / raw)
To: Arun Kumar K
Cc: Sylwester Nawrocki, Arun Kumar K, LMML, linux-samsung-soc,
devicetree-discuss, kgene.kim, kilyeon.im
On 03/27/2013 05:31 AM, Arun Kumar K wrote:
> On Wed, Mar 27, 2013 at 4:21 AM, Sylwester Nawrocki
> <sylvester.nawrocki@gmail.com> wrote:
>> On 03/26/2013 01:17 PM, Arun Kumar K wrote:
[...]
> Only issue is with the context sharing.
> Right now you can see that the fimc-is context is shared between all
> the subdevs.
> As all of them are part of the same driver, it is possible.
> If sensor is made as an independent i2c device, a separate probe will
> be called for it.
> For ISP sensor subdev to work independently, it needs to call the
> fimc_is_pipeline_* calls
> for FW initialization and other configurations for which it needs the
> fimc-is main context.
>
> Now there is a workaround here by calling a get_context() macro in
> sensor's probe
> to get the fimc-is context. This will cause the same context to be
> shared and updated by
> 2 drivers though both are part of fimc-is.
> Is this acceptable? Or am I missing some other simple solution of implementing
> it in a better way?
OK, thanks for the explanation.
I can think of at least one possible way to get hold of the fimc-is
context in the subdev. For instance, in subdev's .registered callback
you get a pointer to struct v4l2_device, which is normally embedded
in a top level driver's private data. Then with container_of()
you could get hold of required data at the fimc-is driver.
But... to make the subdev drivers reuse possible subdevs should
normally not be required to know the internals of a host driver they
are registered to. And it looks a bit unusual to have fimc_pipeline_*
calls in the sensor's operation handlers.
I thought that the subdevs could provide basic methods and it would
be the top level media driver that would resolve any dependencies
in calling required subdev ops, according to media graph configuration
done by the user on /dev/media?.
The media driver has a list of media entities (subdevices and video
nodes) and I though it could coordinate any requests involving whole
video/image processing pipeline originating from /dev/video ioctls/fops.
So for instance if /dev/video in this pipeline is opened
sensor (sd) -> mipi-csis (sd) -> fimc-lite (sd) -> memory (/dev/video)
it would call s_power operation on the above subdevs and additionally
on e.g. the isp subdev (or any other we choose as a main subdev
implementing the FIMC-IS slave interface).
Then couldn't it be done that video node ioctls invoke pipeline
operations, and the media device resolves any dependencies/calls
order, as in case of the exynos4 driver ?
As a side note, I'm working on adding a generic method to get any
v4l2_subdev/video_device from a struct media_entity instance, so
it is easier to handle link_notify events, power/streaming enable/
disable sequences, etc. Currently I have a data structure like:
struct exynos_iss_entity {
struct video_device vdev;
struct v4l2_subdev subdev;
struct exynos_iss_pipeline pipe;
};
Regards,
Sylwester
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes
2013-03-27 13:47 ` Sylwester Nawrocki
@ 2013-03-28 5:10 ` Arun Kumar K
2013-03-29 0:30 ` Sylwester Nawrocki
0 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-28 5:10 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: Sylwester Nawrocki, Arun Kumar K, LMML, linux-samsung-soc,
devicetree-discuss, kgene.kim, kilyeon.im, shaik.ameer
On Wed, Mar 27, 2013 at 7:17 PM, Sylwester Nawrocki
<s.nawrocki@samsung.com> wrote:
> On 03/27/2013 05:31 AM, Arun Kumar K wrote:
>> On Wed, Mar 27, 2013 at 4:21 AM, Sylwester Nawrocki
>> <sylvester.nawrocki@gmail.com> wrote:
>>> On 03/26/2013 01:17 PM, Arun Kumar K wrote:
> [...]
>> Only issue is with the context sharing.
>> Right now you can see that the fimc-is context is shared between all
>> the subdevs.
>> As all of them are part of the same driver, it is possible.
>> If sensor is made as an independent i2c device, a separate probe will
>> be called for it.
>> For ISP sensor subdev to work independently, it needs to call the
>> fimc_is_pipeline_* calls
>> for FW initialization and other configurations for which it needs the
>> fimc-is main context.
>>
>> Now there is a workaround here by calling a get_context() macro in
>> sensor's probe
>> to get the fimc-is context. This will cause the same context to be
>> shared and updated by
>> 2 drivers though both are part of fimc-is.
>> Is this acceptable? Or am I missing some other simple solution of implementing
>> it in a better way?
>
> OK, thanks for the explanation.
>
> I can think of at least one possible way to get hold of the fimc-is
> context in the subdev. For instance, in subdev's .registered callback
> you get a pointer to struct v4l2_device, which is normally embedded
> in a top level driver's private data. Then with container_of()
> you could get hold of required data at the fimc-is driver.
But as per current implementation, it is not the fimc-is driver that is
registering the ISP subdevs. It will be registered from the
media controller driver. So fimc-is context cannot be obtained by
just using container_of().
>
> But... to make the subdev drivers reuse possible subdevs should
> normally not be required to know the internals of a host driver they
> are registered to. And it looks a bit unusual to have fimc_pipeline_*
> calls in the sensor's operation handlers.
fimc_pipeline_* I mentioned is not the media controller pipeline.
In the fimc-is driver, all the subdevs just implement the interface part.
All the core functionalities happen in fimc-is-pipeline.c and
fimc-is-interface.c.
Since these ISP subdevs (sensor, isp, scc, scp) are not independent
devices, all are controlled by the ISP firmware whose configuration and
interface is done from the fimc_is_pipeline_* and fimc_is_itf_* functions.
So all the ISP subdevs including sensor need to call these functions.
>
> I thought that the subdevs could provide basic methods and it would
> be the top level media driver that would resolve any dependencies
> in calling required subdev ops, according to media graph configuration
> done by the user on /dev/media?.
>
In case of ISP subdevs (isp, scc and scp), there is not much configuration
that the media device can do. Only control possible is to turn on/off
specific scaler DMA outputs which can be done via the video node ioctls.
The role of media device here is mostly to convey the pipeline structure
to the user. For eg. it is not possible to directly connect isp (sd)
--> scp (sd).
In the media controller pipeline1 implementation, we were planning to
put immutable links between these subdevs. Is that acceptable?
> The media driver has a list of media entities (subdevices and video
> nodes) and I though it could coordinate any requests involving whole
> video/image processing pipeline originating from /dev/video ioctls/fops.
>
> So for instance if /dev/video in this pipeline is opened
>
> sensor (sd) -> mipi-csis (sd) -> fimc-lite (sd) -> memory (/dev/video)
>
> it would call s_power operation on the above subdevs and additionally
> on e.g. the isp subdev (or any other we choose as a main subdev
> implementing the FIMC-IS slave interface).
>
> Then couldn't it be done that video node ioctls invoke pipeline
> operations, and the media device resolves any dependencies/calls
> order, as in case of the exynos4 driver ?
On Exynos4 subdevs, it is well and good since all the subdevs are
independent IPs. Here in ISP since the same IP can take one input and
provide multiple outputs, we designed them as separate subdevs. So
here we cannot make the subdevs independent of each other where only
the sequence / dependencies is controlled from the media device.
Regards
Arun
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes
2013-03-28 5:10 ` Arun Kumar K
@ 2013-03-29 0:30 ` Sylwester Nawrocki
2013-04-10 4:32 ` Arun Kumar K
0 siblings, 1 reply; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-29 0:30 UTC (permalink / raw)
To: Arun Kumar K
Cc: Sylwester Nawrocki, Arun Kumar K, LMML, linux-samsung-soc,
devicetree-discuss, kgene.kim, kilyeon.im, shaik.ameer
Hi Arun,
On 03/28/2013 06:10 AM, Arun Kumar K wrote:
> On Wed, Mar 27, 2013 at 7:17 PM, Sylwester Nawrocki
> <s.nawrocki@samsung.com> wrote:
>> On 03/27/2013 05:31 AM, Arun Kumar K wrote:
>>> On Wed, Mar 27, 2013 at 4:21 AM, Sylwester Nawrocki
>>> <sylvester.nawrocki@gmail.com> wrote:
>>>> On 03/26/2013 01:17 PM, Arun Kumar K wrote:
>> [...]
>>> Only issue is with the context sharing.
>>> Right now you can see that the fimc-is context is shared between all
>>> the subdevs.
>>> As all of them are part of the same driver, it is possible.
>>> If sensor is made as an independent i2c device, a separate probe will
>>> be called for it.
>>> For ISP sensor subdev to work independently, it needs to call the
>>> fimc_is_pipeline_* calls
>>> for FW initialization and other configurations for which it needs the
>>> fimc-is main context.
>>>
>>> Now there is a workaround here by calling a get_context() macro in
>>> sensor's probe
>>> to get the fimc-is context. This will cause the same context to be
>>> shared and updated by
>>> 2 drivers though both are part of fimc-is.
>>> Is this acceptable? Or am I missing some other simple solution of implementing
>>> it in a better way?
>>
>> OK, thanks for the explanation.
>>
>> I can think of at least one possible way to get hold of the fimc-is
>> context in the subdev. For instance, in subdev's .registered callback
>> you get a pointer to struct v4l2_device, which is normally embedded
>> in a top level driver's private data. Then with container_of()
>> you could get hold of required data at the fimc-is driver.
>
> But as per current implementation, it is not the fimc-is driver that is
> registering the ISP subdevs. It will be registered from the
> media controller driver. So fimc-is context cannot be obtained by
> just using container_of().
I guess best option would be to have a function to get the IS slave
interface driver context at the sensor subdev exported by the IS driver
module, as you suggested previously.
You still could obtain the fimc-is object from the media device private
data structure, since the media device has normally a list of its all
entities in one form or the other. But the sensor would need to know
details of the media device, which makes it a bit pointless.
Nevertheless, my main concern is the DT binding. Sharing the sensor
subdev driver might not be that important at the moment, we are talking
about 300..500 lines of code per ISP driver currently anyway.
More important is to have the hardware described in a standard way, so
when the firmware changes there is no need to change the DT bindings.
>> But... to make the subdev drivers reuse possible subdevs should
>> normally not be required to know the internals of a host driver they
>> are registered to. And it looks a bit unusual to have fimc_pipeline_*
>> calls in the sensor's operation handlers.
>
> fimc_pipeline_* I mentioned is not the media controller pipeline.
Ok, I admit I got confused a bit, since the word "pipeline" refers in the
code to both: the internal ISP chain, and the data processing chain
containing the FIMC-IS and other devices like CSI-2 receiver or GScaler.
> In the fimc-is driver, all the subdevs just implement the interface part.
> All the core functionalities happen in fimc-is-pipeline.c and
> fimc-is-interface.c.
> Since these ISP subdevs (sensor, isp, scc, scp) are not independent
> devices, all are controlled by the ISP firmware whose configuration and
> interface is done from the fimc_is_pipeline_* and fimc_is_itf_* functions.
> So all the ISP subdevs including sensor need to call these functions.
>
>>
>> I thought that the subdevs could provide basic methods and it would
>> be the top level media driver that would resolve any dependencies
>> in calling required subdev ops, according to media graph configuration
>> done by the user on /dev/media?.
>>
>
> In case of ISP subdevs (isp, scc and scp), there is not much configuration
> that the media device can do. Only control possible is to turn on/off
> specific scaler DMA outputs which can be done via the video node ioctls.
> The role of media device here is mostly to convey the pipeline structure
> to the user. For eg. it is not possible to directly connect isp (sd)
> --> scp (sd).
> In the media controller pipeline1 implementation, we were planning to
> put immutable links between these subdevs. Is that acceptable?
Not sure I understand which links you mean exactly. Could you post the
media graph generated by media-ctl (--print-dot) ?
If you're talking about the on-the-fly (FIFO) links, then it probably
makes sense. The media device driver should respond to the link_notify
events and not to allow data links unsupported in the hardware. If you
create immutable OTF links, then how would you switch between DMA and
OTF interfaces ? Or can all processing blocks of the ISP chain work
simultaneously with the DMA and OTF ? The FD block, for instance, can fed
data from memory _or_ from previous processing block in the chain, right ?
You will need a user interface to control which input is used and the
links configuration seems most natural here.
>> The media driver has a list of media entities (subdevices and video
>> nodes) and I though it could coordinate any requests involving whole
>> video/image processing pipeline originating from /dev/video ioctls/fops.
>>
>> So for instance if /dev/video in this pipeline is opened
>>
>> sensor (sd) -> mipi-csis (sd) -> fimc-lite (sd) -> memory (/dev/video)
>>
>> it would call s_power operation on the above subdevs and additionally
>> on e.g. the isp subdev (or any other we choose as a main subdev
>> implementing the FIMC-IS slave interface).
>>
>> Then couldn't it be done that video node ioctls invoke pipeline
>> operations, and the media device resolves any dependencies/calls
>> order, as in case of the exynos4 driver ?
>
> On Exynos4 subdevs, it is well and good since all the subdevs are
> independent IPs. Here in ISP since the same IP can take one input and
Not really, there are going to be 2 subdevs exposed by the fimc-is: ISP
and FD. However FD is still not supported in my last patch series. I was
planning this for a subsequent kernel release.
> provide multiple outputs, we designed them as separate subdevs. So
> here we cannot make the subdevs independent of each other where only
> the sequence / dependencies is controlled from the media device.
I'm not asking you to make the FIMC-IS subdevs more self-contained,
it's of course perfectly fine to have multiple (logical) subdevs exposed
by a complex device like that. I have been thinking only about the
sensor driver, since the sensors are normally shared across ISPs from
various chip manufacturers. But let us leave this topic for now.
BTW, in my interpretation FIMC-IS is a collection of IPs/peripheral
devices, not a single black box, including an image sensor. And the
firmware should not be the most significant factor how we expose
the whole subsystem to the user. All elements of the ISP chain, i.e.
an IP control registers are visible to both, the main CPU and the
FIMC-IS (Cortex-A5) MCU. Still, it would be possible to create v4l2
subdevs dynamically, depending on the firmware architecture.
---
Regards,
Sylwester
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [RFC 01/12] exynos-fimc-is: Adding device tree nodes
2013-03-29 0:30 ` Sylwester Nawrocki
@ 2013-04-10 4:32 ` Arun Kumar K
0 siblings, 0 replies; 31+ messages in thread
From: Arun Kumar K @ 2013-04-10 4:32 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: Sylwester Nawrocki, Arun Kumar K, LMML, linux-samsung-soc,
devicetree-discuss, kgene.kim, kilyeon.im, shaik.ameer
Hi Sylwester,
Sorry for the late reply.
>>>
>>> OK, thanks for the explanation.
>>>
>>> I can think of at least one possible way to get hold of the fimc-is
>>> context in the subdev. For instance, in subdev's .registered callback
>>> you get a pointer to struct v4l2_device, which is normally embedded
>>> in a top level driver's private data. Then with container_of()
>>> you could get hold of required data at the fimc-is driver.
>>
>>
>> But as per current implementation, it is not the fimc-is driver that is
>> registering the ISP subdevs. It will be registered from the
>> media controller driver. So fimc-is context cannot be obtained by
>> just using container_of().
>
>
> I guess best option would be to have a function to get the IS slave
> interface driver context at the sensor subdev exported by the IS driver
> module, as you suggested previously.
Ok I will make the sensor as i2c device and check what is the best
way to get the IS context in sensor subdev.
>
> You still could obtain the fimc-is object from the media device private
> data structure, since the media device has normally a list of its all
> entities in one form or the other. But the sensor would need to know
> details of the media device, which makes it a bit pointless.
>
> Nevertheless, my main concern is the DT binding. Sharing the sensor
> subdev driver might not be that important at the moment, we are talking
> about 300..500 lines of code per ISP driver currently anyway.
>
> More important is to have the hardware described in a standard way, so
> when the firmware changes there is no need to change the DT bindings.
>
Yes that's right. Need to define the hardware in a generic way regardless
of what the firmware is doing.
>>>
>>
>> In case of ISP subdevs (isp, scc and scp), there is not much configuration
>> that the media device can do. Only control possible is to turn on/off
>> specific scaler DMA outputs which can be done via the video node ioctls.
>> The role of media device here is mostly to convey the pipeline structure
>> to the user. For eg. it is not possible to directly connect isp (sd)
>> --> scp (sd).
>> In the media controller pipeline1 implementation, we were planning to
>> put immutable links between these subdevs. Is that acceptable?
>
>
> Not sure I understand which links you mean exactly. Could you post the
> media graph generated by media-ctl (--print-dot) ?
>
> If you're talking about the on-the-fly (FIFO) links, then it probably
> makes sense. The media device driver should respond to the link_notify
> events and not to allow data links unsupported in the hardware. If you
> create immutable OTF links, then how would you switch between DMA and
> OTF interfaces ? Or can all processing blocks of the ISP chain work
> simultaneously with the DMA and OTF ? The FD block, for instance, can fed
> data from memory _or_ from previous processing block in the chain, right ?
> You will need a user interface to control which input is used and the
> links configuration seems most natural here.
Yes I agree to that. Though in the current driver, there are no subdevs which
can change between DMA <-> OTF inputs, in future versions we might add it.
So link configuration option will be provided.
>
>
>>> The media driver has a list of media entities (subdevices and video
>>> nodes) and I though it could coordinate any requests involving whole
>>> video/image processing pipeline originating from /dev/video ioctls/fops.
>>>
>>> So for instance if /dev/video in this pipeline is opened
>>>
>>> sensor (sd) -> mipi-csis (sd) -> fimc-lite (sd) -> memory (/dev/video)
>>>
>>> it would call s_power operation on the above subdevs and additionally
>>> on e.g. the isp subdev (or any other we choose as a main subdev
>>> implementing the FIMC-IS slave interface).
>>>
>>> Then couldn't it be done that video node ioctls invoke pipeline
>>> operations, and the media device resolves any dependencies/calls
>>> order, as in case of the exynos4 driver ?
>>
>>
>> On Exynos4 subdevs, it is well and good since all the subdevs are
>> independent IPs. Here in ISP since the same IP can take one input and
>
>
> Not really, there are going to be 2 subdevs exposed by the fimc-is: ISP
> and FD. However FD is still not supported in my last patch series. I was
> planning this for a subsequent kernel release.
>
>
>> provide multiple outputs, we designed them as separate subdevs. So
>> here we cannot make the subdevs independent of each other where only
>> the sequence / dependencies is controlled from the media device.
>
>
> I'm not asking you to make the FIMC-IS subdevs more self-contained,
> it's of course perfectly fine to have multiple (logical) subdevs exposed
> by a complex device like that. I have been thinking only about the
> sensor driver, since the sensors are normally shared across ISPs from
> various chip manufacturers. But let us leave this topic for now.
>
> BTW, in my interpretation FIMC-IS is a collection of IPs/peripheral
> devices, not a single black box, including an image sensor. And the
> firmware should not be the most significant factor how we expose
> the whole subsystem to the user. All elements of the ISP chain, i.e.
> an IP control registers are visible to both, the main CPU and the
> FIMC-IS (Cortex-A5) MCU. Still, it would be possible to create v4l2
> subdevs dynamically, depending on the firmware architecture.
>
Ok. I will address all these comments and work on v2 patchset.
Thanks for the excellent help :)
Regards
Arun
^ permalink raw reply [flat|nested] 31+ messages in thread
* [RFC 02/12] exynos-fimc-is: Adding ARCH support for fimc-is
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
2013-03-08 14:59 ` [RFC 01/12] exynos-fimc-is: Adding device tree nodes Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-08 14:59 ` [RFC 03/12] exynos-fimc-is: Adds fimc-is driver core files Arun Kumar K
` (9 subsequent siblings)
11 siblings, 0 replies; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
Adds new clocks needed for ISP submodules in the camera
subsystem of Exynos5250. Also adds the AUXDATA entry in
mach-exynos5-dt.c.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
arch/arm/mach-exynos/clock-exynos5.c | 129 ++++++++++++++++++++++++
arch/arm/mach-exynos/include/mach/map.h | 2 +
arch/arm/mach-exynos/include/mach/regs-clock.h | 7 ++
arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +
4 files changed, 140 insertions(+)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 4536515..b2c0825 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -28,6 +28,8 @@
#include "common.h"
+#define FIMC_IS_NAME "exynos5-fimc-is"
+
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos5_clock_save[] = {
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
@@ -863,6 +865,16 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 4),
}, {
+ .name = "fimc-is0",
+ .devname = FIMC_IS_NAME,
+ .enable = exynos5_clk_ip_isp0_ctrl,
+ .ctrlbit = (0xFFC << 20) | (0xFF << 0),
+ }, {
+ .name = "fimc-is1",
+ .devname = FIMC_IS_NAME,
+ .enable = exynos5_clk_ip_isp1_ctrl,
+ .ctrlbit = (0x3 << 12) | (0x7 << 0)
+ }, {
.name = "csis",
.devname = "s5p-mipi-csis.0",
.enable = exynos5_clk_ip_gscl_ctrl,
@@ -1248,6 +1260,107 @@ static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
};
+/* For ACLK_400_ISP */
+static struct clksrc_clk exynos5_clk_mout_aclk_400_isp = {
+ .clk = {
+ .name = "mout_aclk_400_isp",
+ .parent = &exynos5_clk_mout_mpll_user.clk,
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_400_isp = {
+ .clk = {
+ .name = "dout_aclk_400_isp",
+ .parent = &exynos5_clk_mout_aclk_400_isp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 20, .size = 3 },
+};
+
+static struct clk *exynos5_clkset_aclk_400_isp_list[] = {
+ [0] = &clk_ext_xtal_mux,
+ [1] = &exynos5_clk_dout_aclk_400_isp.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_400_isp = {
+ .sources = exynos5_clkset_aclk_400_isp_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_400_isp_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400_isp = {
+ .clk = {
+ .name = "aclk_400_isp",
+ .devname = FIMC_IS_NAME,
+ },
+ .sources = &exynos5_clkset_aclk_400_isp,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp = {
+ .clk = {
+ .name = "aclk_266_isp",
+ .devname = FIMC_IS_NAME,
+
+ },
+ .sources = &clk_src_gscl_266,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp_div0 = {
+ .clk = {
+ .name = "aclk_266_isp_div0",
+ .devname = FIMC_IS_NAME,
+ .parent = &exynos5_clk_aclk_266_isp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp_div1 = {
+ .clk = {
+ .name = "aclk_266_isp_div1",
+ .devname = FIMC_IS_NAME,
+ .parent = &exynos5_clk_aclk_266_isp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp_divmpwm = {
+ .clk = {
+ .name = "aclk_266_isp_divmpwm",
+ .devname = FIMC_IS_NAME,
+ .parent = &exynos5_clk_aclk_266_isp_div1.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ISP2, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400_isp_div0 = {
+ .clk = {
+ .name = "aclk_400_isp_div0",
+ .devname = FIMC_IS_NAME,
+ .parent = &exynos5_clk_aclk_400_isp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ISP1, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400_isp_div1 = {
+ .clk = {
+ .name = "aclk_400_isp_div1",
+ .devname = FIMC_IS_NAME,
+ .parent = &exynos5_clk_aclk_400_isp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ISP1, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_gscl = {
+ .clk = {
+ .name = "aclk_266_gscl",
+ .parent = &exynos5_clk_aclk_266.clk,
+ },
+ .sources = &clk_src_gscl_266,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
+};
+
static struct clksrc_clk exynos5_clksrcs[] = {
{
.clk = {
@@ -1299,6 +1412,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
}, {
.clk = {
+ .name = "sclk_bayer",
+ .enable = exynos5_clksrc_mask_gscl_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 12, .size = 4 },
+ }, {
+ .clk = {
.name = "sclk_cam0",
.enable = exynos5_clksrc_mask_gscl_ctrl,
.ctrlbit = (1 << 16),
@@ -1367,6 +1489,13 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mdout_spi1,
&exynos5_clk_mdout_spi2,
&exynos5_clk_sclk_fimd1,
+ &exynos5_clk_aclk_400_isp,
+ &exynos5_clk_aclk_400_isp_div0,
+ &exynos5_clk_aclk_400_isp_div1,
+ &exynos5_clk_aclk_266_isp,
+ &exynos5_clk_aclk_266_isp_div0,
+ &exynos5_clk_aclk_266_isp_div1,
+ &exynos5_clk_aclk_266_isp_divmpwm,
};
static struct clk *exynos5_clk_cdev[] = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 5bfc744..64bd07d 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -125,6 +125,8 @@
#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
+#define EXYNOS5_PA_FIMC_IS 0x13000000
+
#define EXYNOS5_PA_FIMC_LITE0 0x13C00000
#define EXYNOS5_PA_FIMC_LITE1 0x13C10000
#define EXYNOS5_PA_FIMC_LITE2 0x13C90000
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index d36ad76..2a09c9f 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -345,6 +345,13 @@
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
+#define EXYNOS5_CLKDIV2_RATIO0 EXYNOS_CLKREG(0x10590)
+#define EXYNOS5_CLKDIV2_RATIO1 EXYNOS_CLKREG(0x10594)
+#define EXYNOS5_CLKDIV4_RATIO EXYNOS_CLKREG(0x105A0)
+#define EXYNOS5_CLKDIV_ISP0 EXYNOS_CLKREG(0x0C300)
+#define EXYNOS5_CLKDIV_ISP1 EXYNOS_CLKREG(0x0C304)
+#define EXYNOS5_CLKDIV_ISP2 EXYNOS_CLKREG(0x0C308)
+
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f6c3223..4df9929 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -114,6 +114,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"exynos5-fimc-lite.1", NULL),
OF_DEV_AUXDATA("samsung,exynos5250-fimc-lite", EXYNOS5_PA_FIMC_LITE2,
"exynos5-fimc-lite.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5250-fimc-is", EXYNOS5_PA_FIMC_IS,
+ "exynos5-fimc-is", NULL),
{},
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* [RFC 03/12] exynos-fimc-is: Adds fimc-is driver core files
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
2013-03-08 14:59 ` [RFC 01/12] exynos-fimc-is: Adding device tree nodes Arun Kumar K
2013-03-08 14:59 ` [RFC 02/12] exynos-fimc-is: Adding ARCH support for fimc-is Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-23 13:41 ` Sylwester Nawrocki
2013-03-08 14:59 ` [RFC 04/12] exynos-fimc-is: Adds common driver header files Arun Kumar K
` (8 subsequent siblings)
11 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
drivers/media/platform/exynos5-is/fimc-is-core.c | 421 ++++++++++++++++++++++
drivers/media/platform/exynos5-is/fimc-is-core.h | 140 +++++++
2 files changed, 561 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 0000000..2a257c5
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,421 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/bug.h>
+#include <linux/ctype.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/firmware.h>
+#include <linux/fs.h>
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/videodev2.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
+
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-of.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "fimc-is.h"
+
+int fimc_is_debug;
+module_param(fimc_is_debug, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(fimc_is_debug, "Debug level for exynos-fimc-is driver");
+
+static char *fimc_is_clock_name[] = {
+ [IS_CLK_GATE0] = "fimc-is0",
+ [IS_CLK_GATE1] = "fimc-is1",
+ [IS_CLK_266] = "aclk_266_isp",
+ [IS_CLK_266_DIV0] = "aclk_266_isp_div0",
+ [IS_CLK_266_DIV1] = "aclk_266_isp_div1",
+ [IS_CLK_266_DIV_MPWM] = "aclk_266_isp_divmpwm",
+ [IS_CLK_400] = "aclk_400_isp",
+ [IS_CLK_400_DIV0] = "aclk_400_isp_div0",
+ [IS_CLK_400_DIV1] = "aclk_400_isp_div1",
+};
+
+static int fimc_is_create_sensor_subdevs(struct fimc_is *is)
+{
+ struct fimc_is_platdata *pdata = is->pdata;
+ int ret;
+
+ if (pdata->sensor_data[SENSOR_CAM0].enabled) {
+ /* Sensor0 */
+ ret = fimc_is_sensor_subdev_create(&is->sensor[SENSOR_CAM0],
+ &pdata->sensor_data[SENSOR_CAM0],
+ &is->pipeline);
+ if (ret < 0)
+ is_err("Error creating sensor0 subdev");
+ }
+
+ if (pdata->sensor_data[SENSOR_CAM1].enabled) {
+ /* Sensor1 */
+ ret = fimc_is_sensor_subdev_create(&is->sensor[SENSOR_CAM1],
+ &pdata->sensor_data[SENSOR_CAM1],
+ &is->pipeline);
+ if (ret < 0)
+ is_err("Error creating sensor1 subdev");
+ }
+
+ return 0;
+}
+
+static int fimc_is_unregister_sensor_subdevs(struct fimc_is *is)
+{
+ struct fimc_is_platdata *pdata = is->pdata;
+
+ if (pdata->sensor_data[SENSOR_CAM0].enabled)
+ fimc_is_sensor_subdev_destroy(&is->sensor[SENSOR_CAM0]);
+ if (pdata->sensor_data[SENSOR_CAM1].enabled)
+ fimc_is_sensor_subdev_destroy(&is->sensor[SENSOR_CAM1]);
+
+ return 0;
+}
+
+static struct fimc_is_platdata *fimc_is_parse_dt(struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ struct device_node *child, *ep, *port;
+ struct fimc_is_platdata *pdata;
+ struct fimc_is_sensor_data *sensor_data;
+ struct v4l2_of_endpoint endpoint;
+ unsigned int i, snum;
+ int num_gpios;
+
+ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ is_err("Memory allocation for pdata failed\n");
+ return NULL;
+ }
+
+ /* Parse sensor properties */
+ for (snum = 0; snum < FIMC_IS_NUM_SENSORS; snum++) {
+
+ child = of_get_next_child(np, child);
+ if (!child) {
+ is_err("Child node not found\n");
+ continue;
+ }
+
+ sensor_data = &pdata->sensor_data[snum];
+ num_gpios = of_gpio_named_count(child, "gpios");
+ if (num_gpios < 0) {
+ is_err("Sensor gpio property not found\n");
+ of_node_put(child);
+ goto exit;
+ }
+ sensor_data->num_gpios = num_gpios;
+ of_property_read_string(child, "compatible",
+ (const char **)&sensor_data->name);
+ is_dbg(1, "Rear sensor name : %s\n", sensor_data->name);
+ for (i = 0; i < num_gpios; i++) {
+ sensor_data->gpios[i] =
+ of_get_named_gpio(child, "gpios", i);
+ }
+ sensor_data->enabled = 1;
+
+ /* Parse ports */
+ ep = child;
+ while ((ep = of_get_next_child(ep, NULL))) {
+ if (!of_node_cmp(ep->name, "endpoint"))
+ break;
+ of_node_put(ep);
+ };
+ if (!ep) {
+ is_err("Sensor end point not defined\n");
+ continue;
+ }
+ port = of_parse_phandle(ep, "remote-endpoint", 0);
+ if (port) {
+ v4l2_of_parse_endpoint(port, &endpoint);
+ sensor_data->csi_id = endpoint.port;
+ }
+
+ of_node_put(port);
+ of_node_put(ep);
+ of_node_put(child);
+ }
+exit:
+ return pdata;
+}
+
+static void fimc_is_clk_put(struct fimc_is *is)
+{
+ int i;
+
+ for (i = 0; i < IS_CLK_MAX_NUM; i++) {
+ if (IS_ERR_OR_NULL(is->clock[i]))
+ continue;
+ clk_unprepare(is->clock[i]);
+ clk_put(is->clock[i]);
+ is->clock[i] = NULL;
+ }
+}
+
+static int fimc_is_clk_get(struct fimc_is *is)
+{
+ struct device *dev = &is->pdev->dev;
+ int i, ret;
+
+ for (i = 0; i < IS_CLK_MAX_NUM; i++) {
+ is->clock[i] = clk_get(dev, fimc_is_clock_name[i]);
+ if (IS_ERR(is->clock[i]))
+ goto err;
+ ret = clk_prepare(is->clock[i]);
+ if (ret < 0) {
+ clk_put(is->clock[i]);
+ is->clock[i] = NULL;
+ goto err;
+ }
+ }
+ return 0;
+err:
+ fimc_is_clk_put(is);
+ is_err("Failed to get clock: %s\n", fimc_is_clock_name[i]);
+ return -ENXIO;
+}
+
+static int fimc_is_clk_cfg(struct fimc_is *is)
+{
+ int ret;
+
+ ret = fimc_is_clk_get(is);
+ if (ret)
+ return ret;
+
+ /* Set rates */
+ ret = clk_set_rate(is->clock[IS_CLK_400_DIV0], 200 * 1000000);
+ ret |= clk_set_rate(is->clock[IS_CLK_400_DIV1], 100 * 1000000);
+ ret |= clk_set_rate(is->clock[IS_CLK_266_DIV0], 134 * 1000000);
+ ret |= clk_set_rate(is->clock[IS_CLK_266_DIV1], 68 * 1000000);
+ ret |= clk_set_rate(is->clock[IS_CLK_266_DIV_MPWM], 34 * 1000000);
+
+ if (ret)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int __devinit fimc_is_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct fimc_is_platdata *pdata;
+ struct resource *res;
+ struct fimc_is *is;
+ struct pinctrl *pctrl;
+ void __iomem *regs;
+ int irq, ret;
+
+ pr_debug("FIMC-IS Probe Enter\n");
+
+ pctrl = devm_pinctrl_get_select_default(dev);
+ if (IS_ERR(pctrl)) {
+ dev_err(dev, "Pinctrl configuration failed\n");
+ return -EINVAL;
+ }
+
+ if (!pdev->dev.of_node) {
+ dev_err(dev, "Null platform data\n");
+ return -EINVAL;
+ }
+
+ pdata = fimc_is_parse_dt(dev);
+ if (!pdata) {
+ dev_err(dev, "Parse DT failed\n");
+ return -EINVAL;
+ }
+
+ is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
+ if (!is)
+ return -ENOMEM;
+
+ is->pdev = pdev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ regs = devm_request_and_ioremap(dev, res);
+ if (regs == NULL) {
+ dev_err(dev, "Failed to obtain io memory\n");
+ return -ENOENT;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(dev, "Failed to get IRQ\n");
+ return irq;
+ }
+
+ ret = fimc_is_clk_cfg(is);
+ if (ret < 0) {
+ dev_err(dev, "Clock config failed\n");
+ goto err_clk;
+ }
+
+ platform_set_drvdata(pdev, is);
+ pm_runtime_enable(dev);
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0)
+ goto err_clk;
+
+ is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
+ if (IS_ERR(is->alloc_ctx)) {
+ ret = PTR_ERR(is->alloc_ctx);
+ goto err_pm;
+ }
+
+ /* Create sensor subdevs */
+ is->pdata = pdata;
+ ret = fimc_is_create_sensor_subdevs(is);
+ if (ret < 0)
+ goto err_sensor_sd;
+
+ /* Init FIMC Pipeline */
+ ret = fimc_is_pipeline_init(&is->pipeline, 0, is);
+ if (ret < 0)
+ goto err_sd;
+
+ /* Init FIMC Interface */
+ ret = fimc_is_interface_init(&is->interface, regs, irq);
+ if (ret < 0)
+ goto err_sd;
+
+ dev_dbg(dev, "FIMC-IS registered successfully\n");
+
+ return 0;
+
+err_sd:
+ fimc_is_pipeline_destroy(&is->pipeline);
+err_sensor_sd:
+ fimc_is_unregister_sensor_subdevs(is);
+err_vb:
+ vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
+err_pm:
+ pm_runtime_put(dev);
+err_clk:
+ fimc_is_clk_put(is);
+
+ return ret;
+}
+
+int fimc_is_clk_enable(struct fimc_is *is)
+{
+ clk_enable(is->clock[IS_CLK_GATE0]);
+ clk_enable(is->clock[IS_CLK_GATE1]);
+ return 0;
+}
+
+void fimc_is_clk_disable(struct fimc_is *is)
+{
+ clk_disable(is->clock[IS_CLK_GATE0]);
+ clk_disable(is->clock[IS_CLK_GATE1]);
+}
+
+static int fimc_is_pm_resume(struct device *dev)
+{
+ struct fimc_is *is = dev_get_drvdata(dev);
+ int ret;
+
+ ret = fimc_is_clk_enable(is);
+ if (ret < 0)
+ dev_err(dev, "Could not enable clocks\n");
+
+ return 0;
+}
+
+static int fimc_is_pm_suspend(struct device *dev)
+{
+ struct fimc_is *is = dev_get_drvdata(dev);
+
+ fimc_is_clk_disable(is);
+ return 0;
+}
+
+static int fimc_is_runtime_resume(struct device *dev)
+{
+ return fimc_is_pm_resume(dev);
+}
+
+static int fimc_is_runtime_suspend(struct device *dev)
+{
+ return fimc_is_pm_suspend(dev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int fimc_is_resume(struct device *dev)
+{
+ return fimc_is_pm_resume(dev);
+}
+
+static int fimc_is_suspend(struct device *dev)
+{
+ return fimc_is_pm_suspend(dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static int fimc_is_remove(struct platform_device *pdev)
+{
+ struct fimc_is *is = platform_get_drvdata(pdev);
+ struct device *dev = &pdev->dev;
+
+ pm_runtime_disable(dev);
+ pm_runtime_set_suspended(dev);
+ fimc_is_pipeline_destroy(&is->pipeline);
+ fimc_is_unregister_sensor_subdevs(is);
+ vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
+ fimc_is_clk_put(is);
+
+ return 0;
+}
+
+static struct platform_device_id fimc_is_driver_ids[] = {
+ {
+ .name = "exynos5-fimc-is",
+ .driver_data = 0,
+ },
+};
+MODULE_DEVICE_TABLE(platform, fimc_is_driver_ids);
+
+static const struct dev_pm_ops fimc_is_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
+ SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
+ NULL)
+};
+
+static struct platform_driver fimc_is_driver = {
+ .probe = fimc_is_probe,
+ .remove = fimc_is_remove,
+ .id_table = fimc_is_driver_ids,
+ .driver = {
+ .name = FIMC_IS_DRV_NAME,
+ .owner = THIS_MODULE,
+ .pm = &fimc_is_pm_ops,
+ }
+};
+module_platform_driver(fimc_is_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Arun Kumar K <arun.kk@samsung.com>");
+MODULE_DESCRIPTION("Samsung Exynos5 (FIMC-IS) Imaging Subsystem driver");
diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.h b/drivers/media/platform/exynos5-is/fimc-is-core.h
new file mode 100644
index 0000000..9e09bea
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.h
@@ -0,0 +1,140 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_CORE_H_
+#define FIMC_IS_CORE_H_
+
+#include <linux/bug.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/firmware.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/videodev2.h>
+
+#include <asm/barrier.h>
+#include <linux/sizes.h>
+#include <linux/io.h>
+#include <linux/irqreturn.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+
+#include <media/media-entity.h>
+#include <media/videobuf2-core.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-mediabus.h>
+#include <media/s5p_fimc.h>
+
+#define FIMC_IS_DRV_NAME "exynos5-fimc-is"
+#define FIMC_IS_CLK_NAME "fimc_is"
+
+#define FIMC_IS_DEBUG_MSG 0x3f
+#define FIMC_IS_DEBUG_LEVEL 3
+
+#define FIMC_IS_COMMAND_TIMEOUT (3*HZ)
+#define FIMC_IS_STARTUP_TIMEOUT (3*HZ)
+#define FIMC_IS_SHUTDOWN_TIMEOUT (10*HZ)
+
+#define FW_SHARED_OFFSET (0x8C0000)
+#define DEBUG_CNT (500*1024)
+#define DEBUG_OFFSET (0x840000)
+#define DEBUGCTL_OFFSET (0x8BD000)
+#define DEBUG_FCOUNT (0x8C64C0)
+
+#define FIMC_IS_MAX_INSTANCES 1
+
+#define FIMC_IS_MAX_GPIOS 32
+#define FIMC_IS_NUM_SENSORS 2
+
+#define FIMC_IS_MAX_PLANES 3
+#define FIMC_IS_NUM_SCALERS 2
+
+enum fimc_is_clks {
+ IS_CLK_GATE0,
+ IS_CLK_GATE1,
+ IS_CLK_266,
+ IS_CLK_266_DIV0,
+ IS_CLK_266_DIV1,
+ IS_CLK_266_DIV_MPWM,
+ IS_CLK_400,
+ IS_CLK_400_DIV0,
+ IS_CLK_400_DIV1,
+ IS_CLK_MAX_NUM,
+};
+
+/* Video capture states */
+enum fimc_is_video_state {
+ STATE_INIT,
+ STATE_BUFS_ALLOCATED,
+ STATE_RUNNING,
+};
+
+enum fimc_is_scaler_id {
+ SCALER_SCC,
+ SCALER_SCP
+};
+
+enum fimc_is_sensor_pos {
+ SENSOR_CAM0,
+ SENSOR_CAM1
+};
+
+struct fimc_is_buf {
+ struct list_head list;
+ struct vb2_buffer *vb;
+ unsigned int paddr[FIMC_IS_MAX_PLANES];
+};
+
+struct fimc_is_meminfo {
+ unsigned int fw_paddr;
+ unsigned int fw_vaddr;
+ unsigned int region_paddr;
+ unsigned int region_vaddr;
+ unsigned int shared_paddr;
+ unsigned int shared_vaddr;
+};
+
+/**
+ * struct fimc_is_fmt - the driver's internal color format data
+ * @name: format description
+ * @fourcc: the fourcc code for this format
+ * @depth: number of bytes per pixel
+ * @num_planes: number of planes for this color format
+ */
+struct fimc_is_fmt {
+ char *name;
+ unsigned int fourcc;
+ unsigned int depth[FIMC_IS_MAX_PLANES];
+ unsigned int num_planes;
+};
+
+struct fimc_is_sensor_data {
+ int enabled;
+ char *name;
+ unsigned int num_gpios;
+ int gpios[FIMC_IS_MAX_GPIOS];
+ unsigned int csi_id;
+};
+
+struct fimc_is_platdata {
+ struct fimc_is_sensor_data sensor_data[FIMC_IS_NUM_SENSORS];
+};
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [RFC 03/12] exynos-fimc-is: Adds fimc-is driver core files
2013-03-08 14:59 ` [RFC 03/12] exynos-fimc-is: Adds fimc-is driver core files Arun Kumar K
@ 2013-03-23 13:41 ` Sylwester Nawrocki
0 siblings, 0 replies; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-23 13:41 UTC (permalink / raw)
To: Arun Kumar K
Cc: linux-media, linux-samsung-soc, devicetree-discuss, s.nawrocki,
kgene.kim, kilyeon.im, arunkk.samsung
On 03/08/2013 03:59 PM, Arun Kumar K wrote:
> This driver is for the FIMC-IS IP available in Samsung Exynos5
> SoC onwards. This patch adds the core files for the new driver.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
> drivers/media/platform/exynos5-is/fimc-is-core.c | 421 ++++++++++++++++++++++
> drivers/media/platform/exynos5-is/fimc-is-core.h | 140 +++++++
> 2 files changed, 561 insertions(+)
[...]
> +static int __devinit fimc_is_probe(struct platform_device *pdev)
You need to remove this attribute, that's not supported in recent kernels
any more.
> +{
> + struct device *dev =&pdev->dev;
> + struct fimc_is_platdata *pdata;
> + struct resource *res;
> + struct fimc_is *is;
> + struct pinctrl *pctrl;
> + void __iomem *regs;
> + int irq, ret;
> +
> + pr_debug("FIMC-IS Probe Enter\n");
> +
> + pctrl = devm_pinctrl_get_select_default(dev);
> + if (IS_ERR(pctrl)) {
> + dev_err(dev, "Pinctrl configuration failed\n");
> + return -EINVAL;
> + }
This is not needed any more. If you work with not latest kernel I suggest
to cherry pick
commit ab78029ecc347debbd737f06688d788bd9d60c1d
drivers/pinctrl: grab default handles from device core
and remove those devm_pinctrl_get_select_default() calls from drivers.
> + if (!pdev->dev.of_node) {
> + dev_err(dev, "Null platform data\n");
Huh ? Since this driver is for dt-only platforms, is there a need to check
pdev->dev.of_node at all ? Probably you want to just return -ENODEV if it
is NULL.
> + return -EINVAL;
> + }
> +
> + pdata = fimc_is_parse_dt(dev);
> + if (!pdata) {
> + dev_err(dev, "Parse DT failed\n");
> + return -EINVAL;
> + }
> +
> + is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
> + if (!is)
> + return -ENOMEM;
> +
> + is->pdev = pdev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + regs = devm_request_and_ioremap(dev, res);
> + if (regs == NULL) {
> + dev_err(dev, "Failed to obtain io memory\n");
> + return -ENOENT;
> + }
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq< 0) {
> + dev_err(dev, "Failed to get IRQ\n");
> + return irq;
> + }
> +
> + ret = fimc_is_clk_cfg(is);
> + if (ret< 0) {
> + dev_err(dev, "Clock config failed\n");
> + goto err_clk;
> + }
> +
> + platform_set_drvdata(pdev, is);
> + pm_runtime_enable(dev);
> +
> + ret = pm_runtime_get_sync(dev);
> + if (ret< 0)
> + goto err_clk;
> +
> + is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
> + if (IS_ERR(is->alloc_ctx)) {
> + ret = PTR_ERR(is->alloc_ctx);
> + goto err_pm;
> + }
> +
> + /* Create sensor subdevs */
> + is->pdata = pdata;
> + ret = fimc_is_create_sensor_subdevs(is);
> + if (ret< 0)
> + goto err_sensor_sd;
> +
> + /* Init FIMC Pipeline */
> + ret = fimc_is_pipeline_init(&is->pipeline, 0, is);
> + if (ret< 0)
> + goto err_sd;
> +
> + /* Init FIMC Interface */
> + ret = fimc_is_interface_init(&is->interface, regs, irq);
> + if (ret< 0)
> + goto err_sd;
> +
> + dev_dbg(dev, "FIMC-IS registered successfully\n");
Shouldn't there be pm_runtime_put() ?
> +
> + return 0;
> +
> +err_sd:
> + fimc_is_pipeline_destroy(&is->pipeline);
> +err_sensor_sd:
> + fimc_is_unregister_sensor_subdevs(is);
> +err_vb:
> + vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
> +err_pm:
> + pm_runtime_put(dev);
> +err_clk:
> + fimc_is_clk_put(is);
> +
> + return ret;
> +}
> +
> +int fimc_is_clk_enable(struct fimc_is *is)
> +{
> + clk_enable(is->clock[IS_CLK_GATE0]);
> + clk_enable(is->clock[IS_CLK_GATE1]);
No need to check return value ?
> + return 0;
> +}
> +
> +void fimc_is_clk_disable(struct fimc_is *is)
> +{
> + clk_disable(is->clock[IS_CLK_GATE0]);
> + clk_disable(is->clock[IS_CLK_GATE1]);
> +}
> +
> +static int fimc_is_pm_resume(struct device *dev)
> +{
> + struct fimc_is *is = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = fimc_is_clk_enable(is);
> + if (ret< 0)
> + dev_err(dev, "Could not enable clocks\n");
> +
> + return 0;
> +}
> +
> +static int fimc_is_pm_suspend(struct device *dev)
> +{
> + struct fimc_is *is = dev_get_drvdata(dev);
> +
> + fimc_is_clk_disable(is);
> + return 0;
> +}
> +
> +static int fimc_is_runtime_resume(struct device *dev)
> +{
> + return fimc_is_pm_resume(dev);
> +}
> +
> +static int fimc_is_runtime_suspend(struct device *dev)
> +{
> + return fimc_is_pm_suspend(dev);
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int fimc_is_resume(struct device *dev)
> +{
> + return fimc_is_pm_resume(dev);
> +}
> +
> +static int fimc_is_suspend(struct device *dev)
> +{
> + return fimc_is_pm_suspend(dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static int fimc_is_remove(struct platform_device *pdev)
> +{
> + struct fimc_is *is = platform_get_drvdata(pdev);
> + struct device *dev =&pdev->dev;
> +
> + pm_runtime_disable(dev);
> + pm_runtime_set_suspended(dev);
> + fimc_is_pipeline_destroy(&is->pipeline);
> + fimc_is_unregister_sensor_subdevs(is);
> + vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
> + fimc_is_clk_put(is);
> +
> + return 0;
> +}
> +
> +static struct platform_device_id fimc_is_driver_ids[] = {
> + {
> + .name = "exynos5-fimc-is",
> + .driver_data = 0,
This line doesn't change anything, I would just remove it.
But is this fimc_is_driver_ids[] array needed at all ?
> + },
> +};
> +MODULE_DEVICE_TABLE(platform, fimc_is_driver_ids);
> +
> +static const struct dev_pm_ops fimc_is_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
> + SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
> + NULL)
> +};
> +
> +static struct platform_driver fimc_is_driver = {
> + .probe = fimc_is_probe,
> + .remove = fimc_is_remove,
> + .id_table = fimc_is_driver_ids,
> + .driver = {
> + .name = FIMC_IS_DRV_NAME,
> + .owner = THIS_MODULE,
> + .pm =&fimc_is_pm_ops,
How is this driver instantiated from the device tree when there
is no of_match_table ? I didn't find any chunk adding it further
in this series.
> + }
> +};
> +module_platform_driver(fimc_is_driver);
I forgot to say that in general this patch series looks very clean
to me. I'm really happy to see this driver in such a good shape.
Thanks,
Sylwester
^ permalink raw reply [flat|nested] 31+ messages in thread
* [RFC 04/12] exynos-fimc-is: Adds common driver header files
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
` (2 preceding siblings ...)
2013-03-08 14:59 ` [RFC 03/12] exynos-fimc-is: Adds fimc-is driver core files Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-23 14:05 ` Sylwester Nawrocki
2013-03-08 14:59 ` [RFC 05/12] exynos-fimc-is: Adds the register definition and context header Arun Kumar K
` (7 subsequent siblings)
11 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
This patch adds all the common header files used by the fimc-is
driver. It includes the commands for interfacing with the firmware
and error codes from IS firmware, metadata and command parameter
definitions.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
drivers/media/platform/exynos5-is/fimc-is-cmd.h | 211 ++
drivers/media/platform/exynos5-is/fimc-is-err.h | 258 +++
.../media/platform/exynos5-is/fimc-is-metadata.h | 771 +++++++
drivers/media/platform/exynos5-is/fimc-is-param.h | 2163 ++++++++++++++++++++
4 files changed, 3403 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-cmd.h b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
new file mode 100644
index 0000000..f117f41
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
@@ -0,0 +1,211 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_CMD_H
+#define FIMC_IS_CMD_H
+
+#define IS_COMMAND_VER 122 /* IS COMMAND VERSION 1.22 */
+
+enum is_cmd {
+ /* HOST -> IS */
+ HIC_PREVIEW_STILL = 0x1,
+ HIC_PREVIEW_VIDEO,
+ HIC_CAPTURE_STILL,
+ HIC_CAPTURE_VIDEO,
+ HIC_PROCESS_START,
+ HIC_PROCESS_STOP,
+ HIC_STREAM_ON,
+ HIC_STREAM_OFF,
+ HIC_SHOT,
+ HIC_GET_STATIC_METADATA,
+ HIC_SET_CAM_CONTROL,
+ HIC_GET_CAM_CONTROL,
+ HIC_SET_PARAMETER,
+ HIC_GET_PARAMETER,
+ HIC_SET_A5_MEM_ACCESS,
+ RESERVED2,
+ HIC_GET_STATUS,
+ /* SENSOR PART*/
+ HIC_OPEN_SENSOR,
+ HIC_CLOSE_SENSOR,
+ HIC_SIMMIAN_INIT,
+ HIC_SIMMIAN_WRITE,
+ HIC_SIMMIAN_READ,
+ HIC_POWER_DOWN,
+ HIC_GET_SET_FILE_ADDR,
+ HIC_LOAD_SET_FILE,
+ HIC_MSG_CONFIG,
+ HIC_MSG_TEST,
+ /* IS -> HOST */
+ IHC_GET_SENSOR_NUMBER = 0x1000,
+ /* Parameter1 : Address of space to copy a setfile */
+ /* Parameter2 : Space szie */
+ IHC_SET_SHOT_MARK,
+ /* PARAM1 : a frame number */
+ /* PARAM2 : confidence level(smile 0~100) */
+ /* PARMA3 : confidence level(blink 0~100) */
+ IHC_SET_FACE_MARK,
+ /* PARAM1 : coordinate count */
+ /* PARAM2 : coordinate buffer address */
+ IHC_FRAME_DONE,
+ /* PARAM1 : frame start number */
+ /* PARAM2 : frame count */
+ IHC_AA_DONE,
+ IHC_NOT_READY,
+ IHC_FLASH_READY
+};
+
+enum is_reply {
+ ISR_DONE = 0x2000,
+ ISR_NDONE
+};
+
+enum is_scenario_id {
+ ISS_PREVIEW_STILL,
+ ISS_PREVIEW_VIDEO,
+ ISS_CAPTURE_STILL,
+ ISS_CAPTURE_VIDEO,
+ ISS_END
+};
+
+enum is_subscenario_id {
+ ISS_SUB_SCENARIO_STILL,
+ ISS_SUB_SCENARIO_VIDEO,
+ ISS_SUB_SCENARIO_SCENE1,
+ ISS_SUB_SCENARIO_SCENE2,
+ ISS_SUB_SCENARIO_SCENE3,
+ ISS_SUB_END
+};
+
+struct is_setfile_header_element {
+ u32 binary_addr;
+ u32 binary_size;
+};
+
+struct is_setfile_header {
+ struct is_setfile_header_element isp[ISS_END];
+ struct is_setfile_header_element drc[ISS_END];
+ struct is_setfile_header_element fd[ISS_END];
+};
+
+#define HOST_SET_INT_BIT 0x00000001
+#define HOST_CLR_INT_BIT 0x00000001
+#define IS_SET_INT_BIT 0x00000001
+#define IS_CLR_INT_BIT 0x00000001
+
+#define HOST_SET_INTERRUPT(base) (base->uiINTGR0 |= HOST_SET_INT_BIT)
+#define HOST_CLR_INTERRUPT(base) (base->uiINTCR0 |= HOST_CLR_INT_BIT)
+#define IS_SET_INTERRUPT(base) (base->uiINTGR1 |= IS_SET_INT_BIT)
+#define IS_CLR_INTERRUPT(base) (base->uiINTCR1 |= IS_CLR_INT_BIT)
+
+struct is_common_reg {
+ u32 hicmd;
+ u32 hic_sensorid;
+ u32 hic_param1;
+ u32 hic_param2;
+ u32 hic_param3;
+ u32 hic_param4;
+
+ u32 reserved1[3];
+
+ u32 ihcmd_iflag;
+ u32 ihcmd;
+ u32 ihc_sensorid;
+ u32 ihc_param1;
+ u32 ihc_param2;
+ u32 ihc_param3;
+ u32 ihc_param4;
+
+ u32 reserved2[3];
+
+ u32 isp_bayer_iflag;
+ u32 isp_bayer_sensor_id;
+ u32 isp_bayer_param1;
+ u32 isp_bayer_param2;
+
+ u32 reserved3[4];
+
+ u32 scc_iflag;
+ u32 scc_sensor_id;
+ u32 scc_param1;
+ u32 scc_param2;
+ u32 scc_param3;
+
+ u32 reserved4[3];
+
+ u32 dnr_iflag;
+ u32 dnr_sensor_id;
+ u32 dnr_param1;
+ u32 dnr_param2;
+
+ u32 reserved5[4];
+
+ u32 scp_iflag;
+ u32 scp_sensor_id;
+ u32 scp_param1;
+ u32 scp_param2;
+ u32 scp_param3;
+
+ u32 reserved6[1];
+
+ u32 isp_yuv_iflag;
+ u32 isp_yuv_sensor_id;
+ u32 isp_yuv_param1;
+ u32 isp_yuv_param2;
+
+ u32 reserved7[1];
+
+ u32 shot_iflag;
+ u32 shot_sensor_id;
+ u32 shot_param1;
+ u32 shot_param2;
+
+ u32 reserved8[1];
+
+ u32 meta_iflag;
+ u32 meta_sensor_id;
+ u32 meta_param1;
+
+ u32 reserved9[1];
+
+ u32 fcount;
+};
+
+struct is_mcuctl_reg {
+ u32 mcuctl;
+ u32 bboar;
+
+ u32 intgr0;
+ u32 intcr0;
+ u32 intmr0;
+ u32 intsr0;
+ u32 intmsr0;
+
+ u32 intgr1;
+ u32 intcr1;
+ u32 intmr1;
+ u32 intsr1;
+ u32 intmsr1;
+
+ u32 intcr2;
+ u32 intmr2;
+ u32 intsr2;
+ u32 intmsr2;
+
+ u32 gpoctrl;
+ u32 cpoenctlr;
+ u32 gpictlr;
+
+ u32 pad[0xD];
+
+ struct is_common_reg common_reg;
+};
+#endif
diff --git a/drivers/media/platform/exynos5-is/fimc-is-err.h b/drivers/media/platform/exynos5-is/fimc-is-err.h
new file mode 100644
index 0000000..76472a9
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-err.h
@@ -0,0 +1,258 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_ERR_H
+#define FIMC_IS_ERR_H
+
+#define IS_ERROR_VER 012 /* IS ERROR VERSION 0.07 */
+
+#define IS_ERROR_SUCCESS 0
+/* General 1 ~ 100 */
+#define IS_ERROR_INVALID_COMMAND (IS_ERROR_SUCCESS+1)
+#define IS_ERROR_REQUEST_FAIL (IS_ERROR_INVALID_COMMAND+1)
+#define IS_ERROR_INVALID_SCENARIO (IS_ERROR_REQUEST_FAIL+1)
+#define IS_ERROR_INVALID_SENSORID (IS_ERROR_INVALID_SCENARIO+1)
+#define IS_ERROR_INVALID_MODE_CHANGE (IS_ERROR_INVALID_SENSORID+1)
+#define IS_ERROR_INVALID_MAGIC_NUMBER (IS_ERROR_INVALID_MODE_CHANGE+1)
+#define IS_ERROR_INVALID_SETFILE_HDR (IS_ERROR_INVALID_MAGIC_NUMBER+1)
+#define IS_ERROR_ISP_SETFILE_VERSION_MISMATCH (IS_ERROR_INVALID_SETFILE_HDR+1)
+#define IS_ERROR_ISP_SETFILE_REVISION_MISMATCH\
+ (IS_ERROR_ISP_SETFILE_VERSION_MISMATCH+1)
+#define IS_ERROR_BUSY (IS_ERROR_ISP_SETFILE_REVISION_MISMATCH+1)
+#define IS_ERROR_SET_PARAMETER (IS_ERROR_BUSY+1)
+#define IS_ERROR_INVALID_PATH (IS_ERROR_SET_PARAMETER+1)
+#define IS_ERROR_OPEN_SENSOR_FAIL (IS_ERROR_INVALID_PATH+1)
+#define IS_ERROR_ENTRY_MSG_THREAD_DOWN (IS_ERROR_OPEN_SENSOR_FAIL+1)
+#define IS_ERROR_ISP_FRAME_END_NOT_DONE (IS_ERROR_ENTRY_MSG_THREAD_DOWN+1)
+#define IS_ERROR_DRC_FRAME_END_NOT_DONE (IS_ERROR_ISP_FRAME_END_NOT_DONE+1)
+#define IS_ERROR_SCALERC_FRAME_END_NOT_DONE (IS_ERROR_DRC_FRAME_END_NOT_DONE+1)
+#define IS_ERROR_ODC_FRAME_END_NOT_DONE (IS_ERROR_SCALERC_FRAME_END_NOT_DONE+1)
+#define IS_ERROR_DIS_FRAME_END_NOT_DONE (IS_ERROR_ODC_FRAME_END_NOT_DONE+1)
+#define IS_ERROR_TDNR_FRAME_END_NOT_DONE (IS_ERROR_DIS_FRAME_END_NOT_DONE+1)
+#define IS_ERROR_SCALERP_FRAME_END_NOT_DONE (IS_ERROR_TDNR_FRAME_END_NOT_DONE+1)
+#define IS_ERROR_WAIT_STREAM_OFF_NOT_DONE\
+ (IS_ERROR_SCALERP_FRAME_END_NOT_DONE+1)
+#define IS_ERROR_NO_MSG_IS_RECEIVED (IS_ERROR_WAIT_STREAM_OFF_NOT_DONE+1)
+#define IS_ERROR_SENSOR_MSG_FAIL (IS_ERROR_NO_MSG_IS_RECEIVED+1)
+#define IS_ERROR_ISP_MSG_FAIL (IS_ERROR_SENSOR_MSG_FAIL+1)
+#define IS_ERROR_DRC_MSG_FAIL (IS_ERROR_ISP_MSG_FAIL+1)
+#define IS_ERROR_SCALERC_MSG_FAIL (IS_ERROR_DRC_MSG_FAIL+1)
+#define IS_ERROR_ODC_MSG_FAIL (IS_ERROR_SCALERC_MSG_FAIL+1)
+#define IS_ERROR_DIS_MSG_FAIL (IS_ERROR_ODC_MSG_FAIL+1)
+#define IS_ERROR_TDNR_MSG_FAIL (IS_ERROR_DIS_MSG_FAIL+1)
+#define IS_ERROR_SCALERP_MSG_FAIL (IS_ERROR_TDNR_MSG_FAIL+1)
+#define IS_ERROR_LHFD_MSG_FAIL (IS_ERROR_SCALERP_MSG_FAIL+1)
+#define IS_ERROR_INTERNAL_STOP (IS_ERROR_LHFD_MSG_FAIL+1)
+#define IS_ERROR_UNKNOWN 1000
+#define IS_ERROR_TIME_OUT_FLAG 0x80000000
+
+/* Sensor 100 ~ 200 */
+#define IS_ERROR_SENSOR_PWRDN_FAIL 100
+#define IS_ERROR_SENSOR_STREAM_ON_FAIL (IS_ERROR_SENSOR_PWRDN_FAIL+1)
+#define IS_ERROR_SENSOR_STREAM_OFF_FAIL (IS_ERROR_SENSOR_STREAM_ON_FAIL+1)
+
+/* ISP 200 ~ 300 */
+#define IS_ERROR_ISP_PWRDN_FAIL 200
+#define IS_ERROR_ISP_MULTIPLE_INPUT (IS_ERROR_ISP_PWRDN_FAIL+1)
+#define IS_ERROR_ISP_ABSENT_INPUT (IS_ERROR_ISP_MULTIPLE_INPUT+1)
+#define IS_ERROR_ISP_ABSENT_OUTPUT (IS_ERROR_ISP_ABSENT_INPUT+1)
+#define IS_ERROR_ISP_NONADJACENT_OUTPUT (IS_ERROR_ISP_ABSENT_OUTPUT+1)
+#define IS_ERROR_ISP_FORMAT_MISMATCH (IS_ERROR_ISP_NONADJACENT_OUTPUT+1)
+#define IS_ERROR_ISP_WIDTH_MISMATCH (IS_ERROR_ISP_FORMAT_MISMATCH+1)
+#define IS_ERROR_ISP_HEIGHT_MISMATCH (IS_ERROR_ISP_WIDTH_MISMATCH+1)
+#define IS_ERROR_ISP_BITWIDTH_MISMATCH (IS_ERROR_ISP_HEIGHT_MISMATCH+1)
+#define IS_ERROR_ISP_FRAME_END_TIME_OUT (IS_ERROR_ISP_BITWIDTH_MISMATCH+1)
+
+/* DRC 300 ~ 400 */
+#define IS_ERROR_DRC_PWRDN_FAIL 300
+#define IS_ERROR_DRC_MULTIPLE_INPUT (IS_ERROR_DRC_PWRDN_FAIL+1)
+#define IS_ERROR_DRC_ABSENT_INPUT (IS_ERROR_DRC_MULTIPLE_INPUT+1)
+#define IS_ERROR_DRC_NONADJACENT_INTPUT (IS_ERROR_DRC_ABSENT_INPUT+1)
+#define IS_ERROR_DRC_ABSENT_OUTPUT (IS_ERROR_DRC_NONADJACENT_INTPUT+1)
+#define IS_ERROR_DRC_NONADJACENT_OUTPUT (IS_ERROR_DRC_ABSENT_OUTPUT+1)
+#define IS_ERROR_DRC_FORMAT_MISMATCH (IS_ERROR_DRC_NONADJACENT_OUTPUT+1)
+#define IS_ERROR_DRC_WIDTH_MISMATCH (IS_ERROR_DRC_FORMAT_MISMATCH+1)
+#define IS_ERROR_DRC_HEIGHT_MISMATCH (IS_ERROR_DRC_WIDTH_MISMATCH+1)
+#define IS_ERROR_DRC_BITWIDTH_MISMATCH (IS_ERROR_DRC_HEIGHT_MISMATCH+1)
+#define IS_ERROR_DRC_FRAME_END_TIME_OUT (IS_ERROR_DRC_BITWIDTH_MISMATCH+1)
+
+/*SCALERC(400~500)*/
+#define IS_ERROR_SCALERC_PWRDN_FAIL 400
+
+/*ODC(500~600)*/
+#define IS_ERROR_ODC_PWRDN_FAIL 500
+
+/*DIS(600~700)*/
+#define IS_ERROR_DIS_PWRDN_FAIL 600
+
+/*TDNR(700~800)*/
+#define IS_ERROR_TDNR_PWRDN_FAIL 700
+
+/*SCALERP(800~900)*/
+#define IS_ERROR_SCALERP_PWRDN_FAIL 800
+
+/*FD(900~1000)*/
+#define IS_ERROR_FD_PWRDN_FAIL 900
+#define IS_ERROR_FD_MULTIPLE_INPUT (IS_ERROR_FD_PWRDN_FAIL+1)
+#define IS_ERROR_FD_ABSENT_INPUT (IS_ERROR_FD_MULTIPLE_INPUT+1)
+#define IS_ERROR_FD_NONADJACENT_INPUT (IS_ERROR_FD_ABSENT_INPUT+1)
+#define IS_ERROR_LHFD_FRAME_END_TIME_OUT \
+ (IS_ERROR_FD_NONADJACENT_INPUT+1)
+
+/* Set parameter error enum */
+enum error {
+ /* Common error (0~99) */
+ ERROR_COMMON_NO = 0,
+ ERROR_COMMON_CMD = 1, /* Invalid command*/
+ ERROR_COMMON_PARAMETER = 2, /* Invalid parameter*/
+ /* setfile is not loaded before adjusting */
+ ERROR_COMMON_SETFILE_LOAD = 3,
+ /* setfile is not Adjusted before runnng. */
+ ERROR_COMMON_SETFILE_ADJUST = 4,
+ /* index of setfile is not valid. */
+ ERROR_COMMON_SETFILE_INDEX = 5,
+ /* Input path can be changed in ready state(stop) */
+ ERROR_COMMON_INPUT_PATH = 6,
+ /* IP can not start if input path is not set */
+ ERROR_COMMON_INPUT_INIT = 7,
+ /* Output path can be changed in ready state(stop) */
+ ERROR_COMMON_OUTPUT_PATH = 8,
+ /* IP can not start if output path is not set */
+ ERROR_COMMON_OUTPUT_INIT = 9,
+
+ ERROR_CONTROL_NO = ERROR_COMMON_NO,
+ ERROR_CONTROL_BYPASS = 11, /* Enable or Disable */
+ ERROR_CONTROL_BUF = 12, /* invalid buffer info */
+
+ ERROR_OTF_INPUT_NO = ERROR_COMMON_NO,
+ /* invalid command */
+ ERROR_OTF_INPUT_CMD = 21,
+ /* invalid format (DRC: YUV444, FD: YUV444, 422, 420) */
+ ERROR_OTF_INPUT_FORMAT = 22,
+ /* invalid width (DRC: 128~8192, FD: 32~8190) */
+ ERROR_OTF_INPUT_WIDTH = 23,
+ /* invalid height (DRC: 64~8192, FD: 16~8190) */
+ ERROR_OTF_INPUT_HEIGHT = 24,
+ /* invalid bit-width (DRC: 8~12bits, FD: 8bit) */
+ ERROR_OTF_INPUT_BIT_WIDTH = 25,
+ /* invalid frame time for ISP */
+ ERROR_OTF_INPUT_USER_FRAMETILE = 26,
+
+ ERROR_DMA_INPUT_NO = ERROR_COMMON_NO,
+ /* invalid width (DRC: 128~8192, FD: 32~8190) */
+ ERROR_DMA_INPUT_WIDTH = 31,
+ /* invalid height (DRC: 64~8192, FD: 16~8190) */
+ ERROR_DMA_INPUT_HEIGHT = 32,
+ /* invalid format (DRC: YUV444 or YUV422, FD: YUV444, 422, 420) */
+ ERROR_DMA_INPUT_FORMAT = 33,
+ /* invalid bit-width (DRC: 8~12bit, FD: 8bit) */
+ ERROR_DMA_INPUT_BIT_WIDTH = 34,
+ /* invalid order(DRC: YYCbCrorYCbYCr, FD:NO,YYCbCr,YCbYCr,CbCr,CrCb) */
+ ERROR_DMA_INPUT_ORDER = 35,
+ /* invalid palne (DRC: 3, FD: 1, 2, 3) */
+ ERROR_DMA_INPUT_PLANE = 36,
+
+ ERROR_OTF_OUTPUT_NO = ERROR_COMMON_NO,
+ /* invalid width (DRC: 128~8192) */
+ ERROR_OTF_OUTPUT_WIDTH = 41,
+ /* invalid height (DRC: 64~8192) */
+ ERROR_OTF_OUTPUT_HEIGHT = 42,
+ /* invalid format (DRC: YUV444) */
+ ERROR_OTF_OUTPUT_FORMAT = 43,
+ /* invalid bit-width (DRC: 8~12bits) */
+ ERROR_OTF_OUTPUT_BIT_WIDTH = 44,
+ /* invalid crop size (ODC: left>2, right>10) */
+ ERROR_OTF_OUTPUT_CROP = 45,
+
+ ERROR_DMA_OUTPUT_NO = ERROR_COMMON_NO,
+ ERROR_DMA_OUTPUT_WIDTH = 51, /* invalid width */
+ ERROR_DMA_OUTPUT_HEIGHT = 52, /* invalid height */
+ ERROR_DMA_OUTPUT_FORMAT = 53, /* invalid format */
+ ERROR_DMA_OUTPUT_BIT_WIDTH = 54, /* invalid bit-width */
+ ERROR_DMA_OUTPUT_PLANE = 55, /* invalid plane */
+ ERROR_DMA_OUTPUT_ORDER = 56, /* invalid order */
+ ERROR_DMA_OUTPUT_BUF = 57, /* invalid buffer info */
+
+ ERROR_GLOBAL_SHOTMODE_NO = ERROR_COMMON_NO,
+
+ /* SENSOR Error(100~199) */
+ ERROR_SENSOR_NO = ERROR_COMMON_NO,
+ ERROR_SENSOR_I2C_FAIL = 101,
+ ERROR_SENSOR_INVALID_FRAMERATE,
+ ERROR_SENSOR_INVALID_EXPOSURETIME,
+ ERROR_SENSOR_INVALID_SIZE,
+ ERROR_SENSOR_ACTURATOR_INIT_FAIL,
+ ERROR_SENSOR_INVALID_AF_POS,
+ ERROR_SENSOR_UNSUPPORT_FUNC,
+ ERROR_SENSOR_UNSUPPORT_PERI,
+ ERROR_SENSOR_UNSUPPORT_AF,
+ ERROR_SENSOR_FLASH_FAIL,
+ ERROR_SENSOR_START_FAIL,
+ ERROR_SENSOR_STOP_FAIL,
+
+ /* ISP Error (200~299) */
+ ERROR_ISP_AF_NO = ERROR_COMMON_NO,
+ ERROR_ISP_AF_BUSY = 201,
+ ERROR_ISP_AF_INVALID_COMMAND = 202,
+ ERROR_ISP_AF_INVALID_MODE = 203,
+ ERROR_ISP_FLASH_NO = ERROR_COMMON_NO,
+ ERROR_ISP_AWB_NO = ERROR_COMMON_NO,
+ ERROR_ISP_IMAGE_EFFECT_NO = ERROR_COMMON_NO,
+ ERROR_ISP_IMAGE_EFFECT_INVALID = 231,
+ ERROR_ISP_ISO_NO = ERROR_COMMON_NO,
+ ERROR_ISP_ADJUST_NO = ERROR_COMMON_NO,
+ ERROR_ISP_METERING_NO = ERROR_COMMON_NO,
+ ERROR_ISP_AFC_NO = ERROR_COMMON_NO,
+
+ /* DRC Error (300~399) */
+
+ /* FD Error (400~499) */
+ ERROR_FD_NO = ERROR_COMMON_NO,
+ /* Invalid max number (1~16) */
+ ERROR_FD_CONFIG_MAX_NUMBER_STATE = 401,
+ ERROR_FD_CONFIG_MAX_NUMBER_INVALID = 402,
+ ERROR_FD_CONFIG_YAW_ANGLE_STATE = 403,
+ ERROR_FD_CONFIG_YAW_ANGLE_INVALID = 404,
+ ERROR_FD_CONFIG_ROLL_ANGLE_STATE = 405,
+ ERROR_FD_CONFIG_ROLL_ANGLE_INVALID = 406,
+ ERROR_FD_CONFIG_SMILE_MODE_INVALID = 407,
+ ERROR_FD_CONFIG_BLINK_MODE_INVALID = 408,
+ ERROR_FD_CONFIG_EYES_DETECT_INVALID = 409,
+ ERROR_FD_CONFIG_MOUTH_DETECT_INVALID = 410,
+ ERROR_FD_CONFIG_ORIENTATION_STATE = 411,
+ ERROR_FD_CONFIG_ORIENTATION_INVALID = 412,
+ ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID = 413,
+ /* PARAM_FdResultStr can be only applied
+ * in ready-state or stream off */
+ ERROR_FD_RESULT = 414,
+ /* PARAM_FdModeStr can be only applied
+ * in ready-state or stream off */
+ ERROR_FD_MODE = 415,
+
+ /*SCALER ERR(500~599)*/
+ ERROR_SCALER_NO = ERROR_COMMON_NO,
+ ERROR_SCALER_DMA_OUTSEL = 501,
+ ERROR_SCALER_H_RATIO = 502,
+ ERROR_SCALER_V_RATIO = 503,
+ ERROR_SCALER_FRAME_BUFFER_SEQ = 504,
+
+ ERROR_SCALER_IMAGE_EFFECT = 510,
+
+ ERROR_SCALER_ROTATE = 520,
+ ERROR_SCALER_FLIP = 521,
+
+};
+
+#define ENOBASE_IS 0x10000
+#define ENOSHOT (ENOBASE_IS + 1) /* shot error */
+#define ENOMDONE (ENOBASE_IS + 2) /* meta done error */
+
+#endif
diff --git a/drivers/media/platform/exynos5-is/fimc-is-metadata.h b/drivers/media/platform/exynos5-is/fimc-is-metadata.h
new file mode 100644
index 0000000..9738d7d
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-metadata.h
@@ -0,0 +1,771 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_METADATA_H_
+#define FIMC_IS_METADATA_H_
+
+struct rational {
+ uint32_t num;
+ uint32_t den;
+};
+
+#define CAMERA2_MAX_AVAILABLE_MODE 21
+#define CAMERA2_MAX_FACES 16
+
+/*
+ *controls/dynamic metadata
+*/
+
+enum metadata_mode {
+ METADATA_MODE_NONE,
+ METADATA_MODE_FULL
+};
+
+struct camera2_request_ctl {
+ uint32_t id;
+ enum metadata_mode metadatamode;
+ uint8_t outputstreams[16];
+ uint32_t framecount;
+};
+
+struct camera2_request_dm {
+ uint32_t id;
+ enum metadata_mode metadatamode;
+ uint32_t framecount;
+};
+
+
+
+enum optical_stabilization_mode {
+ OPTICAL_STABILIZATION_MODE_OFF,
+ OPTICAL_STABILIZATION_MODE_ON
+};
+
+enum lens_facing {
+ LENS_FACING_BACK,
+ LENS_FACING_FRONT
+};
+
+struct camera2_lens_ctl {
+ uint32_t focusdistance;
+ float aperture;
+ float focallength;
+ float filterdensity;
+ enum optical_stabilization_mode opticalstabilizationmode;
+
+};
+
+struct camera2_lens_dm {
+ uint32_t focusdistance;
+ float aperture;
+ float focalilength;
+ float filterdensity;
+ enum optical_stabilization_mode opticalstabilizationmode;
+ float focusrange[2];
+};
+
+struct camera2_lens_sm {
+ float minimumfocusdistance;
+ float hyperfocaldistance;
+ float availablefocalLength[2];
+ float availableapertures;
+ /*assuming 1 aperture*/
+ float availablefilterdensities;
+ /*assuming 1 ND filter value*/
+ enum optical_stabilization_mode availableopticalstabilization;
+ /*assuming 1*/
+ uint32_t shadingmapsize;
+ float shadingmap[3][40][30];
+ uint32_t geometriccorrectionmapsize;
+ float geometriccorrectionmap[2][3][40][30];
+ enum lens_facing facing;
+ float position[2];
+};
+
+enum sensor_colorfilterarrangement {
+ SENSOR_COLORFILTERARRANGEMENT_RGGB,
+ SENSOR_COLORFILTERARRANGEMENT_GRBG,
+ SENSOR_COLORFILTERARRANGEMENT_GBRG,
+ SENSOR_COLORFILTERARRANGEMENT_BGGR,
+ SENSOR_COLORFILTERARRANGEMENT_RGB
+};
+
+enum sensor_ref_illuminant {
+ SENSOR_ILLUMINANT_DAYLIGHT = 1,
+ SENSOR_ILLUMINANT_FLUORESCENT = 2,
+ SENSOR_ILLUMINANT_TUNGSTEN = 3,
+ SENSOR_ILLUMINANT_FLASH = 4,
+ SENSOR_ILLUMINANT_FINE_WEATHER = 9,
+ SENSOR_ILLUMINANT_CLOUDY_WEATHER = 10,
+ SENSOR_ILLUMINANT_SHADE = 11,
+ SENSOR_ILLUMINANT_DAYLIGHT_FLUORESCENT = 12,
+ SENSOR_ILLUMINANT_DAY_WHITE_FLUORESCENT = 13,
+ SENSOR_ILLUMINANT_COOL_WHITE_FLUORESCENT = 14,
+ SENSOR_ILLUMINANT_WHITE_FLUORESCENT = 15,
+ SENSOR_ILLUMINANT_STANDARD_A = 17,
+ SENSOR_ILLUMINANT_STANDARD_B = 18,
+ SENSOR_ILLUMINANT_STANDARD_C = 19,
+ SENSOR_ILLUMINANT_D55 = 20,
+ SENSOR_ILLUMINANT_D65 = 21,
+ SENSOR_ILLUMINANT_D75 = 22,
+ SENSOR_ILLUMINANT_D50 = 23,
+ SENSOR_ILLUMINANT_ISO_STUDIO_TUNGSTEN = 24
+};
+
+struct camera2_sensor_ctl {
+ /* unit : nano */
+ uint64_t exposuretime;
+ /* unit : nano(It's min frame duration */
+ uint64_t frameduration;
+ /* unit : percent(need to change ISO value?) */
+ uint32_t sensitivity;
+};
+
+struct camera2_sensor_dm {
+ uint64_t exposuretime;
+ uint64_t frameduration;
+ uint32_t sensitivity;
+ uint64_t timestamp;
+};
+
+struct camera2_sensor_sm {
+ uint32_t exposuretimerange[2];
+ uint32_t maxframeduration;
+ /* list of available sensitivities. */
+ uint32_t availablesensitivities[10];
+ enum sensor_colorfilterarrangement colorfilterarrangement;
+ float physicalsize[2];
+ uint32_t pixelarraysize[2];
+ uint32_t activearraysize[4];
+ uint32_t whitelevel;
+ uint32_t blacklevelpattern[4];
+ struct rational colortransform1[9];
+ struct rational colortransform2[9];
+ enum sensor_ref_illuminant referenceilluminant1;
+ enum sensor_ref_illuminant referenceilluminant2;
+ struct rational forwardmatrix1[9];
+ struct rational forwardmatrix2[9];
+ struct rational calibrationtransform1[9];
+ struct rational calibrationtransform2[9];
+ struct rational basegainfactor;
+ uint32_t maxanalogsensitivity;
+ float noisemodelcoefficients[2];
+ uint32_t orientation;
+};
+
+
+
+enum flash_mode {
+ CAM2_FLASH_MODE_OFF = 1,
+ CAM2_FLASH_MODE_SINGLE,
+ CAM2_FLASH_MODE_TORCH,
+ CAM2_FLASH_MODE_BEST
+};
+
+struct camera2_flash_ctl {
+ enum flash_mode flashmode;
+ uint32_t firingpower;
+ uint64_t firingtime;
+};
+
+struct camera2_flash_dm {
+ enum flash_mode flashmode;
+ /*10 is max power*/
+ uint32_t firingpower;
+ /*unit : microseconds*/
+ uint64_t firingtime;
+ /*1 : stable, 0 : unstable*/
+ uint32_t firingstable;
+ /*1 : success, 0 : fail*/
+ uint32_t decision;
+};
+
+struct camera2_flash_sm {
+ uint32_t available;
+ uint64_t chargeduration;
+};
+
+enum processing_mode {
+ PROCESSING_MODE_OFF = 1,
+ PROCESSING_MODE_FAST,
+ PROCESSING_MODE_HIGH_QUALITY
+};
+
+
+struct camera2_hotpixel_ctl {
+ enum processing_mode mode;
+};
+
+struct camera2_hotpixel_dm {
+ enum processing_mode mode;
+};
+
+struct camera2_demosaic_ctl {
+ enum processing_mode mode;
+};
+
+struct camera2_demosaic_dm {
+ enum processing_mode mode;
+};
+
+struct camera2_noisereduction_ctl {
+ enum processing_mode mode;
+ uint32_t strength;
+};
+
+struct camera2_noisereduction_dm {
+ enum processing_mode mode;
+ uint32_t strength;
+};
+
+struct camera2_shading_ctl {
+ enum processing_mode mode;
+};
+
+struct camera2_shading_dm {
+ enum processing_mode mode;
+};
+
+struct camera2_geometric_ctl {
+ enum processing_mode mode;
+};
+
+struct camera2_geometric_dm {
+ enum processing_mode mode;
+};
+
+enum colorcorrection_mode {
+ COLORCORRECTION_MODE_FAST = 1,
+ COLORCORRECTION_MODE_HIGH_QUALITY,
+ COLORCORRECTION_MODE_TRANSFORM_MATRIX,
+ COLORCORRECTION_MODE_EFFECT_MONO,
+ COLORCORRECTION_MODE_EFFECT_NEGATIVE,
+ COLORCORRECTION_MODE_EFFECT_SOLARIZE,
+ COLORCORRECTION_MODE_EFFECT_SEPIA,
+ COLORCORRECTION_MODE_EFFECT_POSTERIZE,
+ COLORCORRECTION_MODE_EFFECT_WHITEBOARD,
+ COLORCORRECTION_MODE_EFFECT_BLACKBOARD,
+ COLORCORRECTION_MODE_EFFECT_AQUA
+};
+
+
+struct camera2_colorcorrection_ctl {
+ enum colorcorrection_mode mode;
+ float transform[9];
+ uint32_t hue;
+ uint32_t saturation;
+ uint32_t brightness;
+};
+
+struct camera2_colorcorrection_dm {
+ enum colorcorrection_mode mode;
+ float transform[9];
+ uint32_t hue;
+ uint32_t saturation;
+ uint32_t brightness;
+};
+
+struct camera2_colorcorrection_sm {
+ /*assuming 10 supported modes*/
+ uint8_t availablemodes[CAMERA2_MAX_AVAILABLE_MODE];
+ uint32_t huerange[2];
+ uint32_t saturationrange[2];
+ uint32_t brightnessrange[2];
+};
+
+enum tonemap_mode {
+ TONEMAP_MODE_FAST = 1,
+ TONEMAP_MODE_HIGH_QUALITY,
+ TONEMAP_MODE_CONTRAST_CURVE
+};
+
+struct camera2_tonemap_ctl {
+ enum tonemap_mode mode;
+ /* assuming maxCurvePoints = 64 */
+ float curvered[64];
+ float curvegreen[64];
+ float curveblue[64];
+};
+
+struct camera2_tonemap_dm {
+ enum tonemap_mode mode;
+ /* assuming maxCurvePoints = 64 */
+ float curvered[64];
+ float curvegreen[64];
+ float curveblue[64];
+};
+
+struct camera2_tonemap_sm {
+ uint32_t maxcurvepoints;
+};
+
+struct camera2_edge_ctl {
+ enum processing_mode mode;
+ uint32_t strength;
+};
+
+struct camera2_edge_dm {
+ enum processing_mode mode;
+ uint32_t strength;
+};
+
+enum scaler_availableformats {
+ SCALER_FORMAT_BAYER_RAW,
+ SCALER_FORMAT_YV12,
+ SCALER_FORMAT_NV21,
+ SCALER_FORMAT_JPEG,
+ SCALER_FORMAT_UNKNOWN
+};
+
+struct camera2_scaler_ctl {
+ uint32_t cropregion[3];
+};
+
+struct camera2_scaler_dm {
+ uint32_t cropregion[3];
+};
+
+struct camera2_scaler_sm {
+ enum scaler_availableformats availableformats[4];
+ /*assuming # of availableFormats = 4*/
+ uint32_t availablerawsizes;
+ uint64_t availablerawmindurations;
+ /* needs check */
+ uint32_t availableprocessedsizes[8];
+ uint64_t availableprocessedmindurations[8];
+ uint32_t availablejpegsizes[8][2];
+ uint64_t availablejpegmindurations[8];
+ uint32_t availablemaxdigitalzoom[8];
+};
+
+struct camera2_jpeg_ctl {
+ uint32_t quality;
+ uint32_t thumbnailsize[2];
+ uint32_t thumbnailquality;
+ double gpscoordinates[3];
+ uint32_t gpsprocessingcethod;
+ uint64_t gpstimestamp;
+ uint32_t orientation;
+};
+
+struct camera2_jpeg_dm {
+ uint32_t quality;
+ uint32_t thumbnailsize[2];
+ uint32_t thumbnailquality;
+ double gpscoordinates[3];
+ uint32_t gpsprocessingmethod;
+ uint64_t gpstimestamp;
+ uint32_t orientation;
+};
+
+struct camera2_jpeg_sm {
+ uint32_t availablethumbnailsizes[8][2];
+ uint32_t maxsize;
+ /*assuming supported size=8*/
+};
+
+enum facedetect_mode {
+ FACEDETECT_MODE_OFF = 1,
+ FACEDETECT_MODE_SIMPLE,
+ FACEDETECT_MODE_FULL
+};
+
+enum stats_mode {
+ STATS_MODE_OFF = 1,
+ STATS_MODE_ON
+};
+
+struct camera2_stats_ctl {
+ enum facedetect_mode facedetectmode;
+ enum stats_mode histogrammode;
+ enum stats_mode sharpnessmapmode;
+};
+
+
+struct camera2_stats_dm {
+ enum facedetect_mode facedetectmode;
+ uint32_t facerectangles[CAMERA2_MAX_FACES][4];
+ uint8_t facescores[CAMERA2_MAX_FACES];
+ uint32_t facelandmarks[CAMERA2_MAX_FACES][6];
+ uint32_t faceids[CAMERA2_MAX_FACES];
+ enum stats_mode histogrammode;
+ uint32_t histogram[3 * 256];
+ enum stats_mode sharpnessmapmode;
+};
+
+
+struct camera2_stats_sm {
+ uint8_t availablefacedetectmodes[CAMERA2_MAX_AVAILABLE_MODE];
+ /*assuming supported modes = 3;*/
+ uint32_t maxfacecount;
+ uint32_t histogrambucketcount;
+ uint32_t maxhistogramcount;
+ uint32_t sharpnessmapsize[2];
+ uint32_t maxsharpnessmapvalue;
+};
+
+enum aa_capture_intent {
+ AA_CAPTURE_INTENT_CUSTOM = 0,
+ AA_CAPTURE_INTENT_PREVIEW,
+ AA_CAPTURE_INTENT_STILL_CAPTURE,
+ AA_CAPTURE_INTENT_VIDEO_RECORD,
+ AA_CAPTURE_INTENT_VIDEO_SNAPSHOT,
+ AA_CAPTURE_INTENT_ZERO_SHUTTER_LAG
+};
+
+enum aa_mode {
+ AA_CONTROL_OFF = 1,
+ AA_CONTROL_AUTO,
+ AA_CONTROL_USE_SCENE_MODE
+};
+
+enum aa_scene_mode {
+ AA_SCENE_MODE_UNSUPPORTED = 1,
+ AA_SCENE_MODE_FACE_PRIORITY,
+ AA_SCENE_MODE_ACTION,
+ AA_SCENE_MODE_PORTRAIT,
+ AA_SCENE_MODE_LANDSCAPE,
+ AA_SCENE_MODE_NIGHT,
+ AA_SCENE_MODE_NIGHT_PORTRAIT,
+ AA_SCENE_MODE_THEATRE,
+ AA_SCENE_MODE_BEACH,
+ AA_SCENE_MODE_SNOW,
+ AA_SCENE_MODE_SUNSET,
+ AA_SCENE_MODE_STEADYPHOTO,
+ AA_SCENE_MODE_FIREWORKS,
+ AA_SCENE_MODE_SPORTS,
+ AA_SCENE_MODE_PARTY,
+ AA_SCENE_MODE_CANDLELIGHT,
+ AA_SCENE_MODE_BARCODE,
+ AA_SCENE_MODE_NIGHT_CAPTURE
+};
+
+enum aa_effect_mode {
+ AA_EFFECT_OFF = 1,
+ AA_EFFECT_MONO,
+ AA_EFFECT_NEGATIVE,
+ AA_EFFECT_SOLARIZE,
+ AA_EFFECT_SEPIA,
+ AA_EFFECT_POSTERIZE,
+ AA_EFFECT_WHITEBOARD,
+ AA_EFFECT_BLACKBOARD,
+ AA_EFFECT_AQUA
+};
+
+enum aa_aemode {
+ AA_AEMODE_OFF = 1,
+ AA_AEMODE_LOCKED,
+ AA_AEMODE_ON,
+ AA_AEMODE_ON_AUTO_FLASH,
+ AA_AEMODE_ON_ALWAYS_FLASH,
+ AA_AEMODE_ON_AUTO_FLASH_REDEYE
+};
+
+enum aa_ae_flashmode {
+ /*all flash control stop*/
+ AA_FLASHMODE_OFF = 1,
+ /*internal 3A can control flash*/
+ AA_FLASHMODE_ON,
+ /*internal 3A can do auto flash algorithm*/
+ AA_FLASHMODE_AUTO,
+ /*internal 3A can fire flash by auto result*/
+ AA_FLASHMODE_CAPTURE,
+ /*internal 3A can control flash forced*/
+ AA_FLASHMODE_ON_ALWAYS
+
+};
+
+enum aa_ae_antibanding_mode {
+ AA_AE_ANTIBANDING_OFF = 1,
+ AA_AE_ANTIBANDING_50HZ,
+ AA_AE_ANTIBANDING_60HZ,
+ AA_AE_ANTIBANDING_AUTO
+};
+
+enum aa_awbmode {
+ AA_AWBMODE_OFF = 1,
+ AA_AWBMODE_LOCKED,
+ AA_AWBMODE_WB_AUTO,
+ AA_AWBMODE_WB_INCANDESCENT,
+ AA_AWBMODE_WB_FLUORESCENT,
+ AA_AWBMODE_WB_WARM_FLUORESCENT,
+ AA_AWBMODE_WB_DAYLIGHT,
+ AA_AWBMODE_WB_CLOUDY_DAYLIGHT,
+ AA_AWBMODE_WB_TWILIGHT,
+ AA_AWBMODE_WB_SHADE
+};
+
+enum aa_afmode {
+ AA_AFMODE_OFF = 1,
+ AA_AFMODE_AUTO,
+ AA_AFMODE_MACRO,
+ AA_AFMODE_CONTINUOUS_VIDEO,
+ AA_AFMODE_CONTINUOUS_PICTURE,
+ AA_AFMODE_EDOF
+};
+
+enum aa_afstate {
+ AA_AFSTATE_INACTIVE = 1,
+ AA_AFSTATE_PASSIVE_SCAN,
+ AA_AFSTATE_ACTIVE_SCAN,
+ AA_AFSTATE_AF_ACQUIRED_FOCUS,
+ AA_AFSTATE_AF_FAILED_FOCUS
+};
+
+enum ae_state {
+ AE_STATE_INACTIVE = 1,
+ AE_STATE_SEARCHING,
+ AE_STATE_CONVERGED,
+ AE_STATE_LOCKED,
+ AE_STATE_FLASH_REQUIRED,
+ AE_STATE_PRECAPTURE
+};
+
+enum awb_state {
+ AWB_STATE_INACTIVE = 1,
+ AWB_STATE_SEARCHING,
+ AWB_STATE_CONVERGED,
+ AWB_STATE_LOCKED
+};
+
+enum aa_isomode {
+ AA_ISOMODE_AUTO = 1,
+ AA_ISOMODE_MANUAL,
+};
+
+struct camera2_aa_ctl {
+ enum aa_capture_intent captureintent;
+ enum aa_mode mode;
+ /*enum aa_effect_mode effectMode;*/
+ enum aa_scene_mode scenemode;
+ uint32_t videostabilizationmode;
+ enum aa_aemode aemode;
+ uint32_t aeregions[5];
+ /*5 per region(x1,y1,x2,y2,weight). currently assuming 1 region.*/
+ int32_t aeexpcompensation;
+ uint32_t aetargetfpsrange[2];
+ enum aa_ae_antibanding_mode aeantibandingmode;
+ enum aa_ae_flashmode aeflashmode;
+ enum aa_awbmode awbmode;
+ uint32_t awbregions[5];
+ /*5 per region(x1,y1,x2,y2,weight). currently assuming 1 region.*/
+ enum aa_afmode afmode;
+ uint32_t afregions[5];
+ /*5 per region(x1,y1,x2,y2,weight). currently assuming 1 region.*/
+ uint32_t aftrigger;
+ enum aa_isomode isomode;
+ uint32_t isovalue;
+
+};
+
+struct camera2_aa_dm {
+ enum aa_mode mode;
+ enum aa_effect_mode effectmode;
+ enum aa_scene_mode scenemode;
+ uint32_t videostabilizationmode;
+ enum aa_aemode aemode;
+ /*needs check*/
+ uint32_t aeregions[5];
+ /*5 per region(x1,y1,x2,y2,weight). currently assuming 1 region.*/
+ enum ae_state aestate;
+ enum aa_ae_flashmode aeflashmode;
+ /*needs check*/
+ enum aa_awbmode awbmode;
+ uint32_t awbregions[5];
+ enum awb_state awbstate;
+ /*5 per region(x1,y1,x2,y2,weight). currently assuming 1 region.*/
+ enum aa_afmode afmode;
+ uint32_t afregions[5];
+ /*5 per region(x1,y1,x2,y2,weight). currently assuming 1 region*/
+ enum aa_afstate afstate;
+ enum aa_isomode isomode;
+ uint32_t isovalue;
+};
+
+struct camera2_aa_sm {
+ uint8_t availablescenemodes[CAMERA2_MAX_AVAILABLE_MODE];
+ uint8_t availableeffects[CAMERA2_MAX_AVAILABLE_MODE];
+ /*assuming # of available scene modes = 10*/
+ uint32_t maxregions;
+ uint8_t aeavailablemodes[CAMERA2_MAX_AVAILABLE_MODE];
+ /*assuming # of available ae modes = 8*/
+ struct rational aecompensationstep;
+ int32_t aecompensationrange[2];
+ uint32_t aeavailabletargetfpsranges[CAMERA2_MAX_AVAILABLE_MODE][2];
+ uint8_t aeavailableantibandingmodes[CAMERA2_MAX_AVAILABLE_MODE];
+ uint8_t awbavailablemodes[CAMERA2_MAX_AVAILABLE_MODE];
+ /*assuming # of awbAvailableModes = 10*/
+ uint8_t afavailablemodes[CAMERA2_MAX_AVAILABLE_MODE];
+ /*assuming # of afAvailableModes = 4*/
+ uint8_t availablevideostabilizationmodes[4];
+ /*assuming # of availableVideoStabilizationModes = 4*/
+ uint32_t isorange[2];
+};
+
+struct camera2_lens_usm {
+ /** Frame delay between sending command and applying frame data */
+ uint32_t focusdistanceframedelay;
+};
+
+struct camera2_sensor_usm {
+ /** Frame delay between sending command and applying frame data */
+ uint32_t exposuretimeframedelay;
+ uint32_t framedurationframedelay;
+ uint32_t sensitivityframedelay;
+};
+
+struct camera2_flash_usm {
+ /** Frame delay between sending command and applying frame data */
+ uint32_t flashmodeframedelay;
+ uint32_t firingpowerframedelay;
+ uint64_t firingtimeframedelay;
+};
+
+struct camera2_ctl {
+ struct camera2_request_ctl request;
+ struct camera2_lens_ctl lens;
+ struct camera2_sensor_ctl sensor;
+ struct camera2_flash_ctl flash;
+ struct camera2_hotpixel_ctl hotpixel;
+ struct camera2_demosaic_ctl demosaic;
+ struct camera2_noisereduction_ctl noise;
+ struct camera2_shading_ctl shading;
+ struct camera2_geometric_ctl geometric;
+ struct camera2_colorcorrection_ctl color;
+ struct camera2_tonemap_ctl tonemap;
+ struct camera2_edge_ctl edge;
+ struct camera2_scaler_ctl scaler;
+ struct camera2_jpeg_ctl jpeg;
+ struct camera2_stats_ctl stats;
+ struct camera2_aa_ctl aa;
+};
+
+struct camera2_dm {
+ struct camera2_request_dm request;
+ struct camera2_lens_dm lens;
+ struct camera2_sensor_dm sensor;
+ struct camera2_flash_dm flash;
+ struct camera2_hotpixel_dm hotpixel;
+ struct camera2_demosaic_dm demosaic;
+ struct camera2_noisereduction_dm noise;
+ struct camera2_shading_dm shading;
+ struct camera2_geometric_dm geometric;
+ struct camera2_colorcorrection_dm color;
+ struct camera2_tonemap_dm tonemap;
+ struct camera2_edge_dm edge;
+ struct camera2_scaler_dm scaler;
+ struct camera2_jpeg_dm jpeg;
+ struct camera2_stats_dm stats;
+ struct camera2_aa_dm aa;
+};
+
+struct camera2_sm {
+ struct camera2_lens_sm lens;
+ struct camera2_sensor_sm sensor;
+ struct camera2_flash_sm flash;
+ struct camera2_colorcorrection_sm color;
+ struct camera2_tonemap_sm tonemap;
+ struct camera2_scaler_sm scaler;
+ struct camera2_jpeg_sm jpeg;
+ struct camera2_stats_sm stats;
+ struct camera2_aa_sm aa;
+
+ /** User-defined(ispfw specific) static metadata. */
+ struct camera2_lens_usm lensud;
+ struct camera2_sensor_usm sensorud;
+ struct camera2_flash_usm flashud;
+};
+
+/**
+ User-defined control for lens.
+*/
+struct camera2_lens_uctl {
+ struct camera2_lens_ctl ctl;
+
+ /** It depends by af algorithm(normally 255 or 1023) */
+ uint32_t maxpos;
+ /** Some actuator support slew rate control. */
+ uint32_t slewrate;
+};
+
+/**
+ User-defined metadata for lens.
+*/
+struct camera2_lens_udm {
+ /** It depends by af algorithm(normally 255 or 1023) */
+ uint32_t maxpos;
+ /** Some actuator support slew rate control. */
+ uint32_t slewrate;
+};
+
+/**
+ User-defined control for sensor.
+*/
+struct camera2_sensor_uctl {
+ struct camera2_sensor_ctl ctl;
+ /** Dynamic frame duration.
+ This feature is decided to max. value between
+ 'sensor.exposureTime'+alpha and 'sensor.frameDuration'.
+ */
+ uint64_t dynamicrrameduration;
+};
+
+struct camera2_scaler_uctl {
+ /* target address for next frame.
+ [0] invalid address, stop
+ [others] valid address
+ */
+ uint32_t scctargetaddress[4];
+ uint32_t scptargetaddress[4];
+};
+
+struct camera2_flash_uctl {
+ struct camera2_flash_ctl ctl;
+};
+
+struct camera2_uctl {
+ /* Set sensor, lens, flash control for next frame.
+ This flag can be combined.
+ [0 bit] lens
+ [1 bit] sensor
+ [2 bit] flash
+ */
+ uint32_t uupdatebitmap;
+
+ /** For debugging */
+ uint32_t uframenumber;
+
+ /** isp fw specific control(user-defined) of lens. */
+ struct camera2_lens_uctl lensud;
+ /** isp fw specific control(user-defined) of sensor. */
+ struct camera2_sensor_uctl sensorud;
+ /** isp fw specific control(user-defined) of flash. */
+ struct camera2_flash_uctl flashud;
+
+ struct camera2_scaler_uctl scalerud;
+};
+
+struct camera2_udm {
+ struct camera2_lens_udm lens;
+};
+
+struct camera2_shot {
+ /*standard area*/
+ struct camera2_ctl ctl;
+ struct camera2_dm dm;
+ /*user defined area*/
+ struct camera2_uctl uctl;
+ struct camera2_udm udm;
+ /*magic : 23456789*/
+ uint32_t magicnumber;
+};
+#endif
diff --git a/drivers/media/platform/exynos5-is/fimc-is-param.h b/drivers/media/platform/exynos5-is/fimc-is-param.h
new file mode 100644
index 0000000..63eb8d9
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-param.h
@@ -0,0 +1,2163 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_PARAM_H
+#define FIMC_IS_PARAM_H
+
+#define IS_REGION_VER 145 /* IS REGION VERSION 1.45 */
+
+/* MACROs */
+#define IS_SET_PARAM_BIT(dev, num) \
+ (num >= 32 ? set_bit((num-32), &dev->p_region_index2) \
+ : set_bit(num, &dev->p_region_index1))
+#define IS_INC_PARAM_NUM(dev) atomic_inc(&dev->p_region_num)
+
+#define IS_PARAM_GLOBAL(dev) (dev->is_p_region->parameter.global)
+#define IS_PARAM_ISP(dev) (dev->is_p_region->parameter.isp)
+#define IS_PARAM_DRC(dev) (dev->is_p_region->parameter.drc)
+#define IS_PARAM_FD(dev) (dev->is_p_region->parameter.fd)
+#define IS_HEADER(dev) (dev->is_p_region->header)
+#define IS_FACE(dev) (dev->is_p_region->face)
+#define IS_SHARED(dev) (dev->is_shared_region)
+#define IS_PARAM_SIZE (FIMC_IS_REGION_SIZE + 1)
+
+/* Global control */
+#define IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, x) \
+ (dev->is_p_region->parameter.global.shotmode.cmd = x)
+#define IS_SET_PARAM_GLOBAL_SHOTMODE_SKIPFRAMES(dev, x) \
+ (dev->is_p_region->parameter.global.shotmode.skip_frames = x)
+
+/* Sensor control */
+#define IS_SENSOR_SET_FRAME_RATE(dev, x) \
+ (dev->is_p_region->parameter.sensor.frame_rate.frame_rate = x)
+
+/* ISP Macros */
+#define IS_ISP_SET_PARAM_CONTROL_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.control.cmd = x)
+#define IS_ISP_SET_PARAM_CONTROL_BYPASS(dev, x) \
+ (dev->is_p_region->parameter.isp.control.bypass = x)
+#define IS_ISP_SET_PARAM_CONTROL_RUNMODE(dev, x) \
+ (dev->is_p_region->parameter.isp.control.run_mode = x)
+#define IS_ISP_SET_PARAM_CONTROL_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.control.err = x)
+
+#define IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.cmd = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.width = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.height = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.format = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.bitwidth = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.order = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.crop_offset_x = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.crop_offset_y = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.crop_width = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.crop_height = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.frametime_min = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.frametime_max = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_input.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_INPUT1_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_input.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_input.width = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_input.height = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_input.format = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_input.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_PLANE(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_input.plane = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_ORDER(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_input.order = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERNUM(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_input.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERADDR(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_input.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_input.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_INPUT2_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_input.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_input.width = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_input.height = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_input.format = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_input.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_PLANE(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_input.plane = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_ORDER(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_input.order = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERNUM(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_input.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERADDR(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_input.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_input.err = x)
+
+#define IS_ISP_SET_PARAM_AA_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.aa.cmd = x)
+#define IS_ISP_SET_PARAM_AA_TARGET(dev, x) \
+ (dev->is_p_region->parameter.isp.aa.target = x)
+#define IS_ISP_SET_PARAM_AA_MODE(dev, x) \
+ (dev->is_p_region->parameter.isp.aa.mode = x)
+#define IS_ISP_SET_PARAM_AA_SCENE(dev, x) \
+ (dev->is_p_region->parameter.isp.aa.scene = x)
+#define IS_ISP_SET_PARAM_AA_SLEEP(dev, x) \
+ (dev->is_p_region->parameter.isp.aa.sleep = x)
+#define IS_ISP_SET_PARAM_AA_FACE(dev, x) \
+ (dev->is_p_region->parameter.isp.aa.uiafface = x)
+#define IS_ISP_SET_PARAM_AA_TOUCH_X(dev, x) \
+ (dev->is_p_region->parameter.isp.aa.touch_x = x)
+#define IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, x) \
+ (dev->is_p_region->parameter.isp.aa.touch_y = x)
+#define IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, x) \
+ (dev->is_p_region->parameter.isp.aa.manual_af_setting = x)
+#define IS_ISP_SET_PARAM_AA_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.aa.err = x)
+
+#define IS_ISP_SET_PARAM_FLASH_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.flash.cmd = x)
+#define IS_ISP_SET_PARAM_FLASH_REDEYE(dev, x) \
+ (dev->is_p_region->parameter.isp.flash.redeye = x)
+#define IS_ISP_SET_PARAM_FLASH_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.flash.err = x)
+
+#define IS_ISP_SET_PARAM_AWB_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.awb.cmd = x)
+#define IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev, x) \
+ (dev->is_p_region->parameter.isp.awb.illumination = x)
+#define IS_ISP_SET_PARAM_AWB_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.awb.err = x)
+
+#define IS_ISP_SET_PARAM_EFFECT_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.effect.cmd = x)
+#define IS_ISP_SET_PARAM_EFFECT_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.effect.err = x)
+
+#define IS_ISP_SET_PARAM_ISO_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.iso.cmd = x)
+#define IS_ISP_SET_PARAM_ISO_VALUE(dev, x) \
+ (dev->is_p_region->parameter.isp.iso.value = x)
+#define IS_ISP_SET_PARAM_ISO_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.iso.err = x)
+
+#define IS_ISP_SET_PARAM_ADJUST_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.adjust.cmd = x)
+#define IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, x) \
+ (dev->is_p_region->parameter.isp.adjust.contrast = x)
+#define IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, x) \
+ (dev->is_p_region->parameter.isp.adjust.saturation = x)
+#define IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, x) \
+ (dev->is_p_region->parameter.isp.adjust.sharpness = x)
+#define IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, x) \
+ (dev->is_p_region->parameter.isp.adjust.exposure = x)
+#define IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, x) \
+ (dev->is_p_region->parameter.isp.adjust.brightness = x)
+#define IS_ISP_SET_PARAM_ADJUST_HUE(dev, x) \
+ (dev->is_p_region->parameter.isp.adjust.hue = x)
+#define IS_ISP_SET_PARAM_ADJUST_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.adjust.err = x)
+
+#define IS_ISP_SET_PARAM_METERING_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.metering.cmd = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, x) \
+ (dev->is_p_region->parameter.isp.metering.win_pos_x = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, x) \
+ (dev->is_p_region->parameter.isp.metering.win_pos_y = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.metering.win_width = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.isp.metering.win_height = x)
+#define IS_ISP_SET_PARAM_METERING_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.metering.err = x)
+
+#define IS_ISP_SET_PARAM_AFC_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.afc.cmd = x)
+#define IS_ISP_SET_PARAM_AFC_MANUAL(dev, x) \
+ (dev->is_p_region->parameter.isp.afc.manual = x)
+#define IS_ISP_SET_PARAM_AFC_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.afc.err = x)
+
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_output.cmd = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_output.width = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_output.height = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_output.format = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_output.bitwidth = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_output.order = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.otf_output.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.width = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.height = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.format = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_PLANE(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.plane = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_ORDER(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.order = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_MASK(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.dma_out_mask = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.dma1_output.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.width = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.height = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.format = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.plane = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.order = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_MASK(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.dma_out_mask = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_DMA_DONE(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.notify_dma_done = x)
+
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_ERR(dev, x) \
+ (dev->is_p_region->parameter.isp.dma2_output.err = x)
+
+/* DRC Macros */
+#define IS_DRC_SET_PARAM_CONTROL_CMD(dev, x) \
+ (dev->is_p_region->parameter.drc.control.cmd = x)
+#define IS_DRC_SET_PARAM_CONTROL_BYPASS(dev, x) \
+ (dev->is_p_region->parameter.drc.control.bypass = x)
+#define IS_DRC_SET_PARAM_CONTROL_ERR(dev, x) \
+ (dev->is_p_region->parameter.drc.control.err = x)
+
+#define IS_DRC_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_input.cmd = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_input.width = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_input.height = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_input.format = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_input.bitwidth = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_input.order = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_input.err = x)
+
+#define IS_DRC_SET_PARAM_DMA_INPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.drc.dma_input.cmd = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.drc.dma_input.width = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.drc.dma_input.height = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.drc.dma_input.format = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.drc.dma_input.bitwidth = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_PLANE(dev, x) \
+ (dev->is_p_region->parameter.drc.dma_input.plane = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.drc.dma_input.order = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_BUFFERNUM(dev, x) \
+ (dev->is_p_region->parameter.drc.dma_input.buffer_number = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_BUFFERADDR(dev, x) \
+ (dev->is_p_region->parameter.drc.dma_input.buffer_address = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.drc.dma_input.err = x)
+
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_output.cmd = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_output.width = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_output.height = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_output.format = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_output.bitwidth = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_output.order = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.drc.otf_output.err = x)
+
+/* SCALER-C Macros */
+#define IS_SCALERC_SET_PARAM_CONTROL_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerc.control.cmd = x)
+#define IS_SCALERC_SET_PARAM_CONTROL_BYPASS(dev, x) \
+ (dev->is_p_region->parameter.scalerc.control.bypass = x)
+#define IS_SCALERC_SET_PARAM_CONTROL_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerc.control.err = x)
+
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_input.cmd = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_input.width = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_input.height = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_input.format = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_input.bitwidth = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_input.order = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_input.err = x)
+
+#define IS_SCALERC_SET_PARAM_EFFECT_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerc.effect.cmd = x)
+#define IS_SCALERC_SET_PARAM_EFFECT_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerc.effect.err = x)
+
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerc.input_crop.cmd = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_POS_X(dev, x) \
+ (dev->is_p_region->parameter.scalerc.input_crop.pos_x = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_POS_Y(dev, x) \
+ (dev->is_p_region->parameter.scalerc.input_crop.pos_y = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.input_crop.crop_width = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.input_crop.crop_height = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_IN_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.input_crop.in_width = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.input_crop.in_height = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.input_crop.out_width = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.input_crop.out_height = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerc.input_crop.err = x)
+
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerc.output_crop.cmd = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_POS_X(dev, x) \
+ (dev->is_p_region->parameter.scalerc.output_crop.pos_x = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_POS_Y(dev, x) \
+ (dev->is_p_region->parameter.scalerc.output_crop.pos_y = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.output_crop.crop_width = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.output_crop.crop_height = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROPG_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.output_crop.format = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerc.output_crop.err = x)
+
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_output.cmd = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_output.width = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_output.height = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_output.format = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_output.bitwidth = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_output.order = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerc.otf_output.err = x)
+
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.cmd = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.width = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.height = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.format = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.bitwidth = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_PLANE(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.plane = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.order = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.buffer_number = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.buffer_address = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_MASK(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.dma_out_mask = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_OUTPATH(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.reserved[0] = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerc.dma_output.err = x)
+
+/* ODC Macros */
+#define IS_ODC_SET_PARAM_CONTROL_CMD(dev, x) \
+ (dev->is_p_region->parameter.odc.control.cmd = x)
+#define IS_ODC_SET_PARAM_CONTROL_BUFFERNUM(dev, x) \
+ (dev->is_p_region->parameter.odc.control.buffer_number = x)
+#define IS_ODC_SET_PARAM_CONTROL_BUFFERADDR(dev, x) \
+ (dev->is_p_region->parameter.odc.control.buffer_address = x)
+#define IS_ODC_SET_PARAM_CONTROL_BYPASS(dev, x) \
+ (dev->is_p_region->parameter.odc.control.bypass = x)
+#define IS_ODC_SET_PARAM_CONTROL_ERR(dev, x) \
+ (dev->is_p_region->parameter.odc.control.err = x)
+
+#define IS_ODC_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_input.cmd = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_input.width = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_input.height = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_input.format = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_input.bitwidth = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_input.order = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_input.err = x)
+
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_output.cmd = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_output.width = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_output.height = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_output.format = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_output.bitwidth = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_output.order = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.odc.otf_output.err = x)
+
+/* DIS Macros */
+#define IS_DIS_SET_PARAM_CONTROL_CMD(dev, x) \
+ (dev->is_p_region->parameter.dis.control.cmd = x)
+#define IS_DIS_SET_PARAM_CONTROL_BUFFERNUM(dev, x) \
+ (dev->is_p_region->parameter.dis.control.buffer_number = x)
+#define IS_DIS_SET_PARAM_CONTROL_BUFFERADDR(dev, x) \
+ (dev->is_p_region->parameter.dis.control.buffer_address = x)
+#define IS_DIS_SET_PARAM_CONTROL_BYPASS(dev, x) \
+ (dev->is_p_region->parameter.dis.control.bypass = x)
+#define IS_DIS_SET_PARAM_CONTROL_ERR(dev, x) \
+ (dev->is_p_region->parameter.dis.control.err = x)
+
+#define IS_DIS_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_input.cmd = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_input.width = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_input.height = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_input.format = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_input.bitwidth = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_input.order = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_input.err = x)
+
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_output.cmd = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_output.width = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_output.height = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_output.format = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_output.bitwidth = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_output.order = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.dis.otf_output.err = x)
+
+/* TDNR Macros */
+#define IS_TDNR_SET_PARAM_CONTROL_CMD(dev, x) \
+ (dev->is_p_region->parameter.tdnr.control.cmd = x)
+#define IS_TDNR_SET_PARAM_CONTROL_BYPASS(dev, x) \
+ (dev->is_p_region->parameter.tdnr.control.bypass = x)
+#define IS_TDNR_SET_PARAM_CONTROL_BUFFERNUM(dev, x) \
+ (dev->is_p_region->parameter.tdnr.control.buffer_number = x)
+#define IS_TDNR_SET_PARAM_CONTROL_BUFFERADDR(dev, x) \
+ (dev->is_p_region->parameter.tdnr.control.buffer_address = x)
+#define IS_TDNR_SET_PARAM_CONTROL_ERR(dev, x) \
+ (dev->is_p_region->parameter.tdnr.control.err = x)
+
+#define IS_TDNR_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_input.cmd = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_input.width = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_input.height = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_input.format = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_input.bitwidth = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_input.order = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_input.err = x)
+
+#define IS_TDNR_SET_PARAM_FRAME_CMD(dev, x) \
+ (dev->is_p_region->parameter.tdnr.frame.cmd = x)
+#define IS_TDNR_SET_PARAM_FRAME_ERR(dev, x) \
+ (dev->is_p_region->parameter.tdnr.frame.err = x)
+
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_output.cmd = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_output.width = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_output.height = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_output.format = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_output.bitwidth = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_output.order = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.tdnr.otf_output.err = x)
+
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.cmd = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.width = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.height = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.format = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.bitwidth = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_PLANE(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.plane = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.order = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.buffer_number = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.buffer_address = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_MASK(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.dma_out_mask = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.tdnr.dma_output.err = x)
+
+/* SCALER-P Macros */
+#define IS_SCALERP_SET_PARAM_CONTROL_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerp.control.cmd = x)
+#define IS_SCALERP_SET_PARAM_CONTROL_BYPASS(dev, x) \
+ (dev->is_p_region->parameter.scalerp.control.bypass = x)
+#define IS_SCALERP_SET_PARAM_CONTROL_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerp.control.err = x)
+
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_input.cmd = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_input.width = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_input.height = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_input.format = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_input.bitwidth = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_input.order = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_input.err = x)
+
+#define IS_SCALERP_SET_PARAM_EFFECT_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerp.effect.cmd = x)
+#define IS_SCALERP_SET_PARAM_EFFECT_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerp.effect.err = x)
+
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerp.input_crop.cmd = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_POS_X(dev, x) \
+ (dev->is_p_region->parameter.scalerp.input_crop.pos_x = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_POS_Y(dev, x) \
+ (dev->is_p_region->parameter.scalerp.input_crop.pos_y = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerp.input_crop.crop_width = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.input_crop.crop_height = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_IN_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerp.input_crop.in_width = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.input_crop.in_height = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerp.input_crop.out_width = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.input_crop.out_height = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerp.input_crop.err = x)
+
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerp.output_crop.cmd = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_POS_X(dev, x) \
+ (dev->is_p_region->parameter.scalerp.output_crop.pos_x = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_POS_Y(dev, x) \
+ (dev->is_p_region->parameter.scalerp.output_crop.pos_y = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerp.output_crop.crop_width = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.output_crop.crop_height = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROPG_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.output_crop.format = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerp.output_crop.err = x)
+
+#define IS_SCALERP_SET_PARAM_ROTATION_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerp.rotation.cmd = x)
+#define IS_SCALERP_SET_PARAM_ROTATION_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerp.rotation.err = x)
+
+#define IS_SCALERP_SET_PARAM_FLIP_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerp.flip.cmd = x)
+#define IS_SCALERP_SET_PARAM_FLIP_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerp.flip.err = x)
+
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_output.cmd = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_output.width = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_output.height = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_output.format = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_output.bitwidth = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_output.order = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerp.otf_output.err = x)
+
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.cmd = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.width = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.height = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.format = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.bitwidth = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_PLANE(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.plane = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.order = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.buffer_number = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.buffer_address = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_MASK(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.dma_out_mask = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.scalerp.dma_output.err = x)
+
+/* FD Macros */
+#define IS_FD_SET_PARAM_CONTROL_CMD(dev, x) \
+ (dev->is_p_region->parameter.fd.control.cmd = x)
+#define IS_FD_SET_PARAM_CONTROL_BYPASS(dev, x) \
+ (dev->is_p_region->parameter.fd.control.bypass = x)
+#define IS_FD_SET_PARAM_CONTROL_ERR(dev, x) \
+ (dev->is_p_region->parameter.fd.control.err = x)
+
+#define IS_FD_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.fd.otf_input.cmd = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.fd.otf_input.width = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.fd.otf_input.height = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.fd.otf_input.format = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.fd.otf_input.bitwidth = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.fd.otf_input.order = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.fd.otf_input.err = x)
+
+#define IS_FD_SET_PARAM_DMA_INPUT_CMD(dev, x) \
+ (dev->is_p_region->parameter.fd.dma_input.cmd = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_WIDTH(dev, x) \
+ (dev->is_p_region->parameter.fd.dma_input.width = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_HEIGHT(dev, x) \
+ (dev->is_p_region->parameter.fd.dma_input.height = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_FORMAT(dev, x) \
+ (dev->is_p_region->parameter.fd.dma_input.format = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_BITWIDTH(dev, x) \
+ (dev->is_p_region->parameter.fd.dma_input.bitwidth = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_PLANE(dev, x) \
+ (dev->is_p_region->parameter.fd.dma_input.plane = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_ORDER(dev, x) \
+ (dev->is_p_region->parameter.fd.dma_input.order = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_BUFFERNUM(dev, x) \
+ (dev->is_p_region->parameter.fd.dma_input.buffer_number = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_BUFFERADDR(dev, x) \
+ (dev->is_p_region->parameter.fd.dma_input.buffer_address = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_ERR(dev, x) \
+ (dev->is_p_region->parameter.fd.dma_input.err = x)
+
+#define IS_FD_SET_PARAM_FD_CONFIG_CMD(dev, x) \
+ (dev->is_p_region->parameter.fd.config.cmd = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(dev, x) \
+ (dev->is_p_region->parameter.fd.config.max_number = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev, x) \
+ (dev->is_p_region->parameter.fd.config.roll_angle = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev, x) \
+ (dev->is_p_region->parameter.fd.config.yaw_angle = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev, x) \
+ (dev->is_p_region->parameter.fd.config.smile_mode = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev, x) \
+ (dev->is_p_region->parameter.fd.config.blink_mode = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev, x) \
+ (dev->is_p_region->parameter.fd.config.eye_detect = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev, x) \
+ (dev->is_p_region->parameter.fd.config.mouth_detect = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev, x) \
+ (dev->is_p_region->parameter.fd.config.orientation = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev, x) \
+ (dev->is_p_region->parameter.fd.config.orientation_value = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ERR(dev, x) \
+ (dev->is_p_region->parameter.fd.config.err = x)
+
+#ifndef BIT0
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+#define BIT32 0x0000000100000000ULL
+#define BIT33 0x0000000200000000ULL
+#define BIT34 0x0000000400000000ULL
+#define BIT35 0x0000000800000000ULL
+#define BIT36 0x0000001000000000ULL
+#define BIT37 0x0000002000000000ULL
+#define BIT38 0x0000004000000000ULL
+#define BIT39 0x0000008000000000ULL
+#define BIT40 0x0000010000000000ULL
+#define BIT41 0x0000020000000000ULL
+#define BIT42 0x0000040000000000ULL
+#define BIT43 0x0000080000000000ULL
+#define BIT44 0x0000100000000000ULL
+#define BIT45 0x0000200000000000ULL
+#define BIT46 0x0000400000000000ULL
+#define BIT47 0x0000800000000000ULL
+#define BIT48 0x0001000000000000ULL
+#define BIT49 0x0002000000000000ULL
+#define BIT50 0x0004000000000000ULL
+#define BIT51 0x0008000000000000ULL
+#define BIT52 0x0010000000000000ULL
+#define BIT53 0x0020000000000000ULL
+#define BIT54 0x0040000000000000ULL
+#define BIT55 0x0080000000000000ULL
+#define BIT56 0x0100000000000000ULL
+#define BIT57 0x0200000000000000ULL
+#define BIT58 0x0400000000000000ULL
+#define BIT59 0x0800000000000000ULL
+#define BIT60 0x1000000000000000ULL
+#define BIT61 0x2000000000000000ULL
+#define BIT62 0x4000000000000000ULL
+#define BIT63 0x8000000000000000ULL
+#define INC_BIT(bit) (bit<<1)
+#define INC_NUM(bit) (bit + 1)
+#endif
+
+#define MAGIC_NUMBER 0x01020304
+
+#define PARAMETER_MAX_SIZE 128 /* in byte */
+#define PARAMETER_MAX_MEMBER (PARAMETER_MAX_SIZE/4)
+
+enum is_entry {
+ ENTRY_GLOBAL,
+ ENTRY_BUFFER,
+ ENTRY_SENSOR,
+ ENTRY_ISP,
+ ENTRY_DRC,
+ ENTRY_SCALERC,
+ ENTRY_ODC,
+ ENTRY_DIS,
+ ENTRY_TDNR,
+ ENTRY_SCALERP,
+ ENTRY_LHFD, /* 10 */
+ ENTRY_END
+};
+
+enum is_param_set_bit {
+ PARAM_GLOBAL_SHOTMODE = 0,
+ PARAM_SENSOR_CONTROL,
+ PARAM_SENSOR_OTF_INPUT,
+ PARAM_SENSOR_OTF_OUTPUT,
+ PARAM_SENSOR_FRAME_RATE,
+ PARAM_SENSOR_DMA_OUTPUT,
+ PARAM_BUFFER_CONTROL,
+ PARAM_BUFFER_OTF_INPUT,
+ PARAM_BUFFER_OTF_OUTPUT,
+ PARAM_ISP_CONTROL,
+ PARAM_ISP_OTF_INPUT = 10,
+ PARAM_ISP_DMA1_INPUT,
+ PARAM_ISP_DMA2_INPUT,
+ PARAM_ISP_AA,
+ PARAM_ISP_FLASH,
+ PARAM_ISP_AWB,
+ PARAM_ISP_IMAGE_EFFECT,
+ PARAM_ISP_ISO,
+ PARAM_ISP_ADJUST,
+ PARAM_ISP_METERING,
+ PARAM_ISP_AFC = 20,
+ PARAM_ISP_OTF_OUTPUT,
+ PARAM_ISP_DMA1_OUTPUT,
+ PARAM_ISP_DMA2_OUTPUT,
+ PARAM_DRC_CONTROL,
+ PARAM_DRC_OTF_INPUT,
+ PARAM_DRC_DMA_INPUT,
+ PARAM_DRC_OTF_OUTPUT,
+ PARAM_SCALERC_CONTROL,
+ PARAM_SCALERC_OTF_INPUT,
+ PARAM_SCALERC_IMAGE_EFFECT = 30,
+ PARAM_SCALERC_INPUT_CROP,
+ PARAM_SCALERC_OUTPUT_CROP,
+ PARAM_SCALERC_OTF_OUTPUT,
+ PARAM_SCALERC_DMA_OUTPUT = 34,
+ PARAM_ODC_CONTROL,
+ PARAM_ODC_OTF_INPUT,
+ PARAM_ODC_OTF_OUTPUT,
+ PARAM_DIS_CONTROL,
+ PARAM_DIS_OTF_INPUT,
+ PARAM_DIS_OTF_OUTPUT = 40,
+ PARAM_TDNR_CONTROL,
+ PARAM_TDNR_OTF_INPUT,
+ PARAM_TDNR_1ST_FRAME,
+ PARAM_TDNR_OTF_OUTPUT,
+ PARAM_TDNR_DMA_OUTPUT,
+ PARAM_SCALERP_CONTROL,
+ PARAM_SCALERP_OTF_INPUT,
+ PARAM_SCALERP_IMAGE_EFFECT,
+ PARAM_SCALERP_INPUT_CROP,
+ PARAM_SCALERP_OUTPUT_CROP = 50,
+ PARAM_SCALERP_ROTATION,
+ PARAM_SCALERP_FLIP,
+ PARAM_SCALERP_OTF_OUTPUT,
+ PARAM_SCALERP_DMA_OUTPUT,
+ PARAM_FD_CONTROL,
+ PARAM_FD_OTF_INPUT,
+ PARAM_FD_DMA_INPUT,
+ PARAM_FD_CONFIG = 58,
+ PARAM_END,
+};
+
+#define ADDRESS_TO_OFFSET(start, end) ((uint32)end - (uint32)start)
+#define OFFSET_TO_NUM(offset) ((offset)>>6)
+#define IS_OFFSET_LOWBIT(offset) (OFFSET_TO_NUM(offset) >= \
+ 32 ? false : true)
+#define OFFSET_TO_BIT(offset) \
+ {(IS_OFFSET_LOWBIT(offset) ? (1<<OFFSET_TO_NUM(offset)) \
+ : (1<<(OFFSET_TO_NUM(offset)-32))}
+#define LOWBIT_OF_NUM(num) (num >= 32 ? 0 : BIT0<<num)
+#define HIGHBIT_OF_NUM(num) (num >= 32 ? BIT0<<(num-32) : 0)
+
+/* 0~31 */
+#define PARAM_GLOBAL_SHOTMODE 0
+#define PARAM_SENSOR_CONTROL INC_NUM(PARAM_GLOBAL_SHOTMODE)
+#define PARAM_SENSOR_OTF_INPUT INC_NUM(PARAM_SENSOR_CONTROL)
+#define PARAM_SENSOR_OTF_OUTPUT INC_NUM(PARAM_SENSOR_OTF_INPUT)
+#define PARAM_SENSOR_FRAME_RATE INC_NUM(PARAM_SENSOR_OTF_OUTPUT)
+#define PARAM_SENSOR_DMA_OUTPUT INC_NUM(PARAM_SENSOR_FRAME_RATE)
+#define PARAM_BUFFER_CONTROL INC_NUM(PARAM_SENSOR_DMA_OUTPUT)
+#define PARAM_BUFFER_OTF_INPUT INC_NUM(PARAM_BUFFER_CONTROL)
+#define PARAM_BUFFER_OTF_OUTPUT INC_NUM(PARAM_BUFFER_OTF_INPUT)
+#define PARAM_ISP_CONTROL INC_NUM(PARAM_BUFFER_OTF_OUTPUT)
+#define PARAM_ISP_OTF_INPUT INC_NUM(PARAM_ISP_CONTROL)
+#define PARAM_ISP_DMA1_INPUT INC_NUM(PARAM_ISP_OTF_INPUT)
+#define PARAM_ISP_DMA2_INPUT INC_NUM(PARAM_ISP_DMA1_INPUT)
+#define PARAM_ISP_AA INC_NUM(PARAM_ISP_DMA2_INPUT)
+#define PARAM_ISP_FLASH INC_NUM(PARAM_ISP_AA)
+#define PARAM_ISP_AWB INC_NUM(PARAM_ISP_FLASH)
+#define PARAM_ISP_IMAGE_EFFECT INC_NUM(PARAM_ISP_AWB)
+#define PARAM_ISP_ISO INC_NUM(PARAM_ISP_IMAGE_EFFECT)
+#define PARAM_ISP_ADJUST INC_NUM(PARAM_ISP_ISO)
+#define PARAM_ISP_METERING INC_NUM(PARAM_ISP_ADJUST)
+#define PARAM_ISP_AFC INC_NUM(PARAM_ISP_METERING)
+#define PARAM_ISP_OTF_OUTPUT INC_NUM(PARAM_ISP_AFC)
+#define PARAM_ISP_DMA1_OUTPUT INC_NUM(PARAM_ISP_OTF_OUTPUT)
+#define PARAM_ISP_DMA2_OUTPUT INC_NUM(PARAM_ISP_DMA1_OUTPUT)
+#define PARAM_DRC_CONTROL INC_NUM(PARAM_ISP_DMA2_OUTPUT)
+#define PARAM_DRC_OTF_INPUT INC_NUM(PARAM_DRC_CONTROL)
+#define PARAM_DRC_DMA_INPUT INC_NUM(PARAM_DRC_OTF_INPUT)
+#define PARAM_DRC_OTF_OUTPUT INC_NUM(PARAM_DRC_DMA_INPUT)
+#define PARAM_SCALERC_CONTROL INC_NUM(PARAM_DRC_OTF_OUTPUT)
+#define PARAM_SCALERC_OTF_INPUT INC_NUM(PARAM_SCALERC_CONTROL)
+#define PARAM_SCALERC_IMAGE_EFFECT INC_NUM(PARAM_SCALERC_OTF_INPUT)
+#define PARAM_SCALERC_INPUT_CROP INC_NUM(PARAM_SCALERC_IMAGE_EFFECT)
+#define PARAM_SCALERC_OUTPUT_CROP INC_NUM(PARAM_SCALERC_INPUT_CROP)
+#define PARAM_SCALERC_OTF_OUTPUT INC_NUM(PARAM_SCALERC_OUTPUT_CROP)
+
+/* 32~63 */
+#define PARAM_SCALERC_DMA_OUTPUT INC_NUM(PARAM_SCALERC_OTF_OUTPUT)
+#define PARAM_ODC_CONTROL INC_NUM(PARAM_SCALERC_DMA_OUTPUT)
+#define PARAM_ODC_OTF_INPUT INC_NUM(PARAM_ODC_CONTROL)
+#define PARAM_ODC_OTF_OUTPUT INC_NUM(PARAM_ODC_OTF_INPUT)
+#define PARAM_DIS_CONTROL INC_NUM(PARAM_ODC_OTF_OUTPUT)
+#define PARAM_DIS_OTF_INPUT INC_NUM(PARAM_DIS_CONTROL)
+#define PARAM_DIS_OTF_OUTPUT INC_NUM(PARAM_DIS_OTF_INPUT)
+#define PARAM_TDNR_CONTROL INC_NUM(PARAM_DIS_OTF_OUTPUT)
+#define PARAM_TDNR_OTF_INPUT INC_NUM(PARAM_TDNR_CONTROL)
+#define PARAM_TDNR_1ST_FRAME INC_NUM(PARAM_TDNR_OTF_INPUT)
+#define PARAM_TDNR_OTF_OUTPUT INC_NUM(PARAM_TDNR_1ST_FRAME)
+#define PARAM_TDNR_DMA_OUTPUT INC_NUM(PARAM_TDNR_OTF_OUTPUT)
+#define PARAM_SCALERP_CONTROL INC_NUM(PARAM_TDNR_DMA_OUTPUT)
+#define PARAM_SCALERP_OTF_INPUT INC_NUM(PARAM_SCALERP_CONTROL)
+#define PARAM_SCALERP_IMAGE_EFFECT INC_NUM(PARAM_SCALERP_OTF_INPUT)
+#define PARAM_SCALERP_INPUT_CROP INC_NUM(PARAM_SCALERP_IMAGE_EFFECT)
+#define PARAM_SCALERP_OUTPUT_CROP INC_NUM(PARAM_SCALERP_INPUT_CROP)
+#define PARAM_SCALERP_ROTATION INC_NUM(PARAM_SCALERP_OUTPUT_CROP)
+#define PARAM_SCALERP_FLIP INC_NUM(PARAM_SCALERP_ROTATION)
+#define PARAM_SCALERP_OTF_OUTPUT INC_NUM(PARAM_SCALERP_FLIP)
+#define PARAM_SCALERP_DMA_OUTPUT INC_NUM(PARAM_SCALERP_OTF_OUTPUT)
+#define PARAM_FD_CONTROL INC_NUM(PARAM_SCALERP_DMA_OUTPUT)
+#define PARAM_FD_OTF_INPUT INC_NUM(PARAM_FD_CONTROL)
+#define PARAM_FD_DMA_INPUT INC_NUM(PARAM_FD_OTF_INPUT)
+#define PARAM_FD_CONFIG INC_NUM(PARAM_FD_DMA_INPUT)
+#define PARAM_END INC_NUM(PARAM_FD_CONFIG)
+
+#define PARAM_STRNUM_GLOBAL (PARAM_GLOBAL_SHOTMODE)
+#define PARAM_RANGE_GLOBAL 1
+#define PARAM_STRNUM_SENSOR (PARAM_SENSOR_BYPASS)
+#define PARAM_RANGE_SENSOR 5
+#define PARAM_STRNUM_BUFFER (PARAM_BUFFER_BYPASS)
+#define PARAM_RANGE_BUFFER 3
+#define PARAM_STRNUM_ISP (PARAM_ISP_BYPASS)
+#define PARAM_RANGE_ISP 15
+#define PARAM_STRNUM_DRC (PARAM_DRC_BYPASS)
+#define PARAM_RANGE_DRC 4
+#define PARAM_STRNUM_SCALERC (PARAM_SCALERC_BYPASS)
+#define PARAM_RANGE_SCALERC 7
+#define PARAM_STRNUM_ODC (PARAM_ODC_BYPASS)
+#define PARAM_RANGE_ODC 3
+#define PARAM_STRNUM_DIS (PARAM_DIS_BYPASS)
+#define PARAM_RANGE_DIS 3
+#define PARAM_STRNUM_TDNR (PARAM_TDNR_BYPASS)
+#define PARAM_RANGE_TDNR 5
+#define PARAM_STRNUM_SCALERP (PARAM_SCALERP_BYPASS)
+#define PARAM_RANGE_SCALERP 9
+#define PARAM_STRNUM_LHFD (PARAM_FD_BYPASS)
+#define PARAM_RANGE_LHFD 4
+
+#define PARAM_LOW_MASK (0xFFFFFFFF)
+#define PARAM_HIGH_MASK (0x07FFFFFF)
+
+/* Enumerations
+*
+*/
+
+/* ---------------------- Input ----------------------------------- */
+enum control_command {
+ CONTROL_COMMAND_STOP = 0,
+ CONTROL_COMMAND_START = 1,
+ CONTROL_COMMAND_TEST = 2
+};
+
+enum bypass_command {
+ CONTROL_BYPASS_DISABLE = 0,
+ CONTROL_BYPASS_ENABLE = 1
+};
+
+enum control_error {
+ CONTROL_ERROR_NO = 0
+};
+
+enum otf_input_command {
+ OTF_INPUT_COMMAND_DISABLE = 0,
+ OTF_INPUT_COMMAND_ENABLE = 1
+};
+
+enum otf_input_format {
+ OTF_INPUT_FORMAT_BAYER = 0, /* 1 Channel */
+ OTF_INPUT_FORMAT_YUV444 = 1, /* 3 Channel */
+ OTF_INPUT_FORMAT_YUV422 = 2, /* 3 Channel */
+ OTF_INPUT_FORMAT_YUV420 = 3, /* 3 Channel */
+ OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER = 10,
+ OTF_INPUT_FORMAT_BAYER_DMA = 11,
+};
+
+enum otf_input_bitwidth {
+ OTF_INPUT_BIT_WIDTH_14BIT = 14,
+ OTF_INPUT_BIT_WIDTH_12BIT = 12,
+ OTF_INPUT_BIT_WIDTH_11BIT = 11,
+ OTF_INPUT_BIT_WIDTH_10BIT = 10,
+ OTF_INPUT_BIT_WIDTH_9BIT = 9,
+ OTF_INPUT_BIT_WIDTH_8BIT = 8
+};
+
+enum otf_input_order {
+ OTF_INPUT_ORDER_BAYER_GR_BG = 0,
+ OTF_INPUT_ORDER_BAYER_RG_GB = 1,
+ OTF_INPUT_ORDER_BAYER_BG_GR = 2,
+ OTF_INPUT_ORDER_BAYER_GB_RG = 3
+};
+
+enum otf_intput_error {
+ OTF_INPUT_ERROR_NO = 0 /* Input setting is done */
+};
+
+enum dma_input_command {
+ DMA_INPUT_COMMAND_DISABLE = 0,
+ DMA_INPUT_COMMAND_ENABLE = 1,
+ DMA_INPUT_COMMAND_BUF_MNGR = 2,
+ DMA_INPUT_COMMAND_RUN_SINGLE = 3,
+};
+
+enum dma_inut_format {
+ DMA_INPUT_FORMAT_BAYER = 0,
+ DMA_INPUT_FORMAT_YUV444 = 1,
+ DMA_INPUT_FORMAT_YUV422 = 2,
+ DMA_INPUT_FORMAT_YUV420 = 3,
+};
+
+enum dma_input_bitwidth {
+ DMA_INPUT_BIT_WIDTH_14BIT = 14,
+ DMA_INPUT_BIT_WIDTH_12BIT = 12,
+ DMA_INPUT_BIT_WIDTH_11BIT = 11,
+ DMA_INPUT_BIT_WIDTH_10BIT = 10,
+ DMA_INPUT_BIT_WIDTH_9BIT = 9,
+ DMA_INPUT_BIT_WIDTH_8BIT = 8
+};
+
+enum dma_input_plane {
+ DMA_INPUT_PLANE_3 = 3,
+ DMA_INPUT_PLANE_2 = 2,
+ DMA_INPUT_PLANE_1 = 1
+};
+
+enum dma_input_order {
+ /* (for DMA_INPUT_PLANE_3) */
+ DMA_INPUT_ORDER_NO = 0,
+ /* (only valid at DMA_INPUT_PLANE_2) */
+ DMA_INPUT_ORDER_CBCR = 1,
+ /* (only valid at DMA_INPUT_PLANE_2) */
+ DMA_INPUT_ORDER_CRCB = 2,
+ /* (only valid at DMA_INPUT_PLANE_1 & DMA_INPUT_FORMAT_YUV444) */
+ DMA_INPUT_ORDER_YCBCR = 3,
+ /* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+ DMA_INPUT_ORDER_YYCBCR = 4,
+ /* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+ DMA_INPUT_ORDER_YCBYCR = 5,
+ /* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+ DMA_INPUT_ORDER_YCRYCB = 6,
+ /* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+ DMA_INPUT_ORDER_CBYCRY = 7,
+ /* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+ DMA_INPUT_ORDER_CRYCBY = 8,
+ /* (only valid at DMA_INPUT_FORMAT_BAYER) */
+ DMA_INPUT_ORDER_GR_BG = 9
+};
+
+enum dma_input_error {
+ DMA_INPUT_ERROR_NO = 0 /* DMA input setting is done */
+};
+
+/* ---------------------- Output ----------------------------------- */
+enum otf_output_crop {
+ OTF_OUTPUT_CROP_DISABLE = 0,
+ OTF_OUTPUT_CROP_ENABLE = 1
+};
+
+enum otf_output_command {
+ OTF_OUTPUT_COMMAND_DISABLE = 0,
+ OTF_OUTPUT_COMMAND_ENABLE = 1
+};
+
+enum orf_output_format {
+ OTF_OUTPUT_FORMAT_YUV444 = 1,
+ OTF_OUTPUT_FORMAT_YUV422 = 2,
+ OTF_OUTPUT_FORMAT_YUV420 = 3,
+ OTF_OUTPUT_FORMAT_RGB = 4
+};
+
+enum otf_output_bitwidth {
+ OTF_OUTPUT_BIT_WIDTH_14BIT = 14,
+ OTF_OUTPUT_BIT_WIDTH_12BIT = 12,
+ OTF_OUTPUT_BIT_WIDTH_11BIT = 11,
+ OTF_OUTPUT_BIT_WIDTH_10BIT = 10,
+ OTF_OUTPUT_BIT_WIDTH_9BIT = 9,
+ OTF_OUTPUT_BIT_WIDTH_8BIT = 8
+};
+
+enum otf_output_order {
+ OTF_OUTPUT_ORDER_BAYER_GR_BG = 0,
+};
+
+enum otf_output_error {
+ OTF_OUTPUT_ERROR_NO = 0 /* Output Setting is done */
+};
+
+enum dma_output_command {
+ DMA_OUTPUT_COMMAND_DISABLE = 0,
+ DMA_OUTPUT_COMMAND_ENABLE = 1,
+ DMA_OUTPUT_COMMAND_BUF_MNGR = 2,
+ DMA_OUTPUT_UPDATE_MASK_BITS = 3
+};
+
+enum dma_output_format {
+ DMA_OUTPUT_FORMAT_BAYER = 0,
+ DMA_OUTPUT_FORMAT_YUV444 = 1,
+ DMA_OUTPUT_FORMAT_YUV422 = 2,
+ DMA_OUTPUT_FORMAT_YUV420 = 3,
+ DMA_OUTPUT_FORMAT_RGB = 4
+};
+
+enum dma_output_bitwidth {
+ DMA_OUTPUT_BIT_WIDTH_14BIT = 14,
+ DMA_OUTPUT_BIT_WIDTH_12BIT = 12,
+ DMA_OUTPUT_BIT_WIDTH_11BIT = 11,
+ DMA_OUTPUT_BIT_WIDTH_10BIT = 10,
+ DMA_OUTPUT_BIT_WIDTH_9BIT = 9,
+ DMA_OUTPUT_BIT_WIDTH_8BIT = 8
+};
+
+enum dma_output_plane {
+ DMA_OUTPUT_PLANE_3 = 3,
+ DMA_OUTPUT_PLANE_2 = 2,
+ DMA_OUTPUT_PLANE_1 = 1
+};
+
+enum dma_output_order {
+ DMA_OUTPUT_ORDER_NO = 0,
+ /* (for DMA_OUTPUT_PLANE_3) */
+ DMA_OUTPUT_ORDER_CBCR = 1,
+ /* (only valid at DMA_INPUT_PLANE_2) */
+ DMA_OUTPUT_ORDER_CRCB = 2,
+ /* (only valid at DMA_OUTPUT_PLANE_2) */
+ DMA_OUTPUT_ORDER_YYCBCR = 3,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_YCBYCR = 4,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_YCRYCB = 5,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_CBYCRY = 6,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_CRYCBY = 7,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_YCBCR = 8,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_CRYCB = 9,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_CRCBY = 10,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_CBYCR = 11,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_YCRCB = 12,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_CBCRY = 13,
+ /* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+ DMA_OUTPUT_ORDER_BGR = 14,
+ /* (only valid at DMA_OUTPUT_FORMAT_RGB) */
+ DMA_OUTPUT_ORDER_GB_BG = 15
+ /* (only valid at DMA_OUTPUT_FORMAT_BAYER) */
+};
+
+enum dma_output_notify_dma_done {
+ DMA_OUTPUT_NOTIFY_DMA_DONE_DISABLE = 0,
+ DMA_OUTPUT_NOTIFY_DMA_DONE_ENBABLE = 1,
+};
+
+enum dma_output_error {
+ DMA_OUTPUT_ERROR_NO = 0 /* DMA output setting is done */
+};
+
+/* ---------------------- Global ----------------------------------- */
+enum global_shotmode_error {
+ GLOBAL_SHOTMODE_ERROR_NO = 0 /* shot-mode setting is done */
+};
+
+/* ------------------------- AA ------------------------------------ */
+enum isp_lock_command {
+ ISP_AA_COMMAND_START = 0,
+ ISP_AA_COMMAND_STOP = 1
+};
+
+enum isp_lock_target {
+ ISP_AA_TARGET_AF = 1,
+ ISP_AA_TARGET_AE = 2,
+ ISP_AA_TARGET_AWB = 4
+};
+
+enum isp_af_mode {
+ ISP_AF_MANUAL = 0,
+ ISP_AF_SINGLE,
+ ISP_AF_CONTINUOUS,
+ ISP_AF_REGION,
+ ISP_AF_SLEEP,
+ ISP_AF_INIT,
+ ISP_AF_SET_CENTER_WINDOW,
+ ISP_AF_SET_TOUCH_WINDOW,
+ ISP_AF_SET_FACE_WINDOW
+};
+
+enum isp_af_scene {
+ ISP_AF_SCENE_NORMAL = 0,
+ ISP_AF_SCENE_MACRO = 1
+};
+
+enum isp_af_touch {
+ ISP_AF_TOUCH_DISABLE = 0,
+ ISP_AF_TOUCH_ENABLE
+};
+
+enum isp_af_face {
+ ISP_AF_FACE_DISABLE = 0,
+ ISP_AF_FACE_ENABLE
+};
+
+enum isp_af_reponse {
+ ISP_AF_RESPONSE_PREVIEW = 0,
+ ISP_AF_RESPONSE_MOVIE
+};
+
+enum isp_af_sleep {
+ ISP_AF_SLEEP_OFF = 0,
+ ISP_AF_SLEEP_ON = 1
+};
+
+enum isp_af_continuous {
+ ISP_AF_CONTINUOUS_DISABLE = 0,
+ ISP_AF_CONTINUOUS_ENABLE = 1
+};
+
+enum isp_af_error {
+ ISP_AF_ERROR_NO = 0, /* AF mode change is done */
+ ISP_AF_EROOR_NO_LOCK_DONE = 1 /* AF lock is done */
+};
+
+/* ------------------------- Flash ------------------------------------- */
+enum isp_flash_command {
+ ISP_FLASH_COMMAND_DISABLE = 0,
+ ISP_FLASH_COMMAND_MANUALON = 1, /* (forced flash) */
+ ISP_FLASH_COMMAND_AUTO = 2,
+ ISP_FLASH_COMMAND_TORCH = 3, /* 3 sec */
+ ISP_FLASH_COMMAND_FLASH_ON = 4,
+ ISP_FLASH_COMMAND_CAPTURE = 5,
+ ISP_FLASH_COMMAND_TRIGGER = 6,
+ ISP_FLASH_COMMAND_CALIBRATION = 7
+};
+
+enum isp_flash_redeye {
+ ISP_FLASH_REDEYE_DISABLE = 0,
+ ISP_FLASH_REDEYE_ENABLE = 1
+};
+
+enum isp_flash_error {
+ ISP_FLASH_ERROR_NO = 0 /* Flash setting is done */
+};
+
+/* -------------------------- AWB ------------------------------------ */
+enum isp_awb_command {
+ ISP_AWB_COMMAND_AUTO = 0,
+ ISP_AWB_COMMAND_ILLUMINATION = 1,
+ ISP_AWB_COMMAND_MANUAL = 2
+};
+
+enum isp_awb_illumination {
+ ISP_AWB_ILLUMINATION_DAYLIGHT = 0,
+ ISP_AWB_ILLUMINATION_CLOUDY = 1,
+ ISP_AWB_ILLUMINATION_TUNGSTEN = 2,
+ ISP_AWB_ILLUMINATION_FLUORESCENT = 3
+};
+
+enum isp_awb_error {
+ ISP_AWB_ERROR_NO = 0 /* AWB setting is done */
+};
+
+/* -------------------------- Effect ----------------------------------- */
+enum isp_imageeffect_command {
+ ISP_IMAGE_EFFECT_DISABLE = 0,
+ ISP_IMAGE_EFFECT_MONOCHROME = 1,
+ ISP_IMAGE_EFFECT_NEGATIVE_MONO = 2,
+ ISP_IMAGE_EFFECT_NEGATIVE_COLOR = 3,
+ ISP_IMAGE_EFFECT_SEPIA = 4,
+ ISP_IMAGE_EFFECT_AQUA = 5,
+ ISP_IMAGE_EFFECT_EMBOSS = 6,
+ ISP_IMAGE_EFFECT_EMBOSS_MONO = 7,
+ ISP_IMAGE_EFFECT_SKETCH = 8,
+ ISP_IMAGE_EFFECT_RED_YELLOW_POINT = 9,
+ ISP_IMAGE_EFFECT_GREEN_POINT = 10,
+ ISP_IMAGE_EFFECT_BLUE_POINT = 11,
+ ISP_IMAGE_EFFECT_MAGENTA_POINT = 12,
+ ISP_IMAGE_EFFECT_WARM_VINTAGE = 13,
+ ISP_IMAGE_EFFECT_COLD_VINTAGE = 14,
+ ISP_IMAGE_EFFECT_POSTERIZE = 15,
+ ISP_IMAGE_EFFECT_SOLARIZE = 16,
+ ISP_IMAGE_EFFECT_WASHED = 17,
+ ISP_IMAGE_EFFECT_CCM = 18,
+};
+
+enum isp_imageeffect_error {
+ ISP_IMAGE_EFFECT_ERROR_NO = 0 /* Image effect setting is done */
+};
+
+/* --------------------------- ISO ------------------------------------ */
+enum isp_iso_command {
+ ISP_ISO_COMMAND_AUTO = 0,
+ ISP_ISO_COMMAND_MANUAL = 1
+};
+
+enum iso_error {
+ ISP_ISO_ERROR_NO = 0 /* ISO setting is done */
+};
+
+/* -------------------------- Adjust ----------------------------------- */
+enum iso_adjust_command {
+ ISP_ADJUST_COMMAND_AUTO = 0,
+ ISP_ADJUST_COMMAND_MANUAL_CONTRAST = (1 << 0),
+ ISP_ADJUST_COMMAND_MANUAL_SATURATION = (1 << 1),
+ ISP_ADJUST_COMMAND_MANUAL_SHARPNESS = (1 << 2),
+ ISP_ADJUST_COMMAND_MANUAL_EXPOSURE = (1 << 3),
+ ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS = (1 << 4),
+ ISP_ADJUST_COMMAND_MANUAL_HUE = (1 << 5),
+ ISP_ADJUST_COMMAND_MANUAL_HOTPIXEL = (1 << 6),
+ ISP_ADJUST_COMMAND_MANUAL_NOISEREDUCTION = (1 << 7),
+ ISP_ADJUST_COMMAND_MANUAL_SHADING = (1 << 8),
+ ISP_ADJUST_COMMAND_MANUAL_GAMMA = (1 << 9),
+ ISP_ADJUST_COMMAND_MANUAL_EDGEENHANCEMENT = (1 << 10),
+ ISP_ADJUST_COMMAND_MANUAL_SCENE = (1 << 11),
+ ISP_ADJUST_COMMAND_MANUAL_FRAMETIME = (1 << 12),
+ ISP_ADJUST_COMMAND_MANUAL_ALL = 0x1FFF
+};
+
+enum isp_adjust_scene_index {
+ ISP_ADJUST_SCENE_NORMAL = 0,
+ ISP_ADJUST_SCENE_NIGHT_PREVIEW = 1,
+ ISP_ADJUST_SCENE_NIGHT_CAPTURE = 2
+};
+
+
+enum isp_adjust_error {
+ ISP_ADJUST_ERROR_NO = 0 /* Adjust setting is done */
+};
+
+/* ------------------------- Metering ---------------------------------- */
+enum isp_metering_command {
+ ISP_METERING_COMMAND_AVERAGE = 0,
+ ISP_METERING_COMMAND_SPOT = 1,
+ ISP_METERING_COMMAND_MATRIX = 2,
+ ISP_METERING_COMMAND_CENTER = 3,
+ ISP_METERING_COMMAND_EXPOSURE_MODE = (1 << 8)
+};
+
+enum isp_exposure_mode {
+ ISP_EXPOSUREMODE_OFF = 1,
+ ISP_EXPOSUREMODE_AUTO = 2
+};
+
+enum isp_metering_error {
+ ISP_METERING_ERROR_NO = 0 /* Metering setting is done */
+};
+
+/* -------------------------- AFC ----------------------------------- */
+enum isp_afc_command {
+ ISP_AFC_COMMAND_DISABLE = 0,
+ ISP_AFC_COMMAND_AUTO = 1,
+ ISP_AFC_COMMAND_MANUAL = 2
+};
+
+enum isp_afc_manual {
+ ISP_AFC_MANUAL_50HZ = 50,
+ ISP_AFC_MANUAL_60HZ = 60
+};
+
+enum isp_afc_error {
+ ISP_AFC_ERROR_NO = 0 /* AFC setting is done */
+};
+
+enum isp_scene_command {
+ ISP_SCENE_NONE = 0,
+ ISP_SCENE_PORTRAIT = 1,
+ ISP_SCENE_LANDSCAPE = 2,
+ ISP_SCENE_SPORTS = 3,
+ ISP_SCENE_PARTYINDOOR = 4,
+ ISP_SCENE_BEACHSNOW = 5,
+ ISP_SCENE_SUNSET = 6,
+ ISP_SCENE_DAWN = 7,
+ ISP_SCENE_FALL = 8,
+ ISP_SCENE_NIGHT = 9,
+ ISP_SCENE_AGAINSTLIGHTWLIGHT = 10,
+ ISP_SCENE_AGAINSTLIGHTWOLIGHT = 11,
+ ISP_SCENE_FIRE = 12,
+ ISP_SCENE_TEXT = 13,
+ ISP_SCENE_CANDLE = 14
+};
+
+/* -------------------------- Scaler --------------------------------- */
+enum scaler_imageeffect_command {
+ SCALER_IMAGE_EFFECT_COMMNAD_DISABLE = 0,
+ SCALER_IMAGE_EFFECT_COMMNAD_SEPIA_CB = 1,
+ SCALER_IMAGE_EFFECT_COMMAND_SEPIA_CR = 2,
+ SCALER_IMAGE_EFFECT_COMMAND_NEGATIVE = 3,
+ SCALER_IMAGE_EFFECT_COMMAND_ARTFREEZE = 4,
+ SCALER_IMAGE_EFFECT_COMMAND_EMBOSSING = 5,
+ SCALER_IMAGE_EFFECT_COMMAND_SILHOUETTE = 6
+};
+
+enum scaler_imageeffect_error {
+ SCALER_IMAGE_EFFECT_ERROR_NO = 0
+};
+
+enum scaler_crop_command {
+ SCALER_CROP_COMMAND_DISABLE = 0,
+ SCALER_CROP_COMMAND_ENABLE = 1
+};
+
+enum scaler_crop_error {
+ SCALER_CROP_ERROR_NO = 0 /* crop setting is done */
+};
+
+enum scaler_scaling_command {
+ SCALER_SCALING_COMMNAD_DISABLE = 0,
+ SCALER_SCALING_COMMAND_UP = 1,
+ SCALER_SCALING_COMMAND_DOWN = 2
+};
+
+enum scaler_scaling_error {
+ SCALER_SCALING_ERROR_NO = 0
+};
+
+enum scaler_rotation_command {
+ SCALER_ROTATION_COMMAND_DISABLE = 0,
+ SCALER_ROTATION_COMMAND_CLOCKWISE90 = 1
+};
+
+enum scaler_rotation_error {
+ SCALER_ROTATION_ERROR_NO = 0
+};
+
+enum scaler_flip_command {
+ SCALER_FLIP_COMMAND_NORMAL = 0,
+ SCALER_FLIP_COMMAND_X_MIRROR = 1,
+ SCALER_FLIP_COMMAND_Y_MIRROR = 2,
+ SCALER_FLIP_COMMAND_XY_MIRROR = 3 /* (180 rotation) */
+};
+
+enum scaler_flip_error {
+ SCALER_FLIP_ERROR_NO = 0 /* flip setting is done */
+};
+
+/* -------------------------- 3DNR ----------------------------------- */
+enum tdnr_1st_frame_command {
+ TDNR_1ST_FRAME_COMMAND_NOPROCESSING = 0,
+ TDNR_1ST_FRAME_COMMAND_2DNR = 1
+};
+
+enum tdnr_1st_frame_error {
+ TDNR_1ST_FRAME_ERROR_NO = 0
+ /*1st frame setting is done*/
+};
+
+/* ---------------------------- FD ------------------------------------- */
+enum fd_config_command {
+ FD_CONFIG_COMMAND_MAXIMUM_NUMBER = 0x1,
+ FD_CONFIG_COMMAND_ROLL_ANGLE = 0x2,
+ FD_CONFIG_COMMAND_YAW_ANGLE = 0x4,
+ FD_CONFIG_COMMAND_SMILE_MODE = 0x8,
+ FD_CONFIG_COMMAND_BLINK_MODE = 0x10,
+ FD_CONFIG_COMMAND_EYES_DETECT = 0x20,
+ FD_CONFIG_COMMAND_MOUTH_DETECT = 0x40,
+ FD_CONFIG_COMMAND_ORIENTATION = 0x80,
+ FD_CONFIG_COMMAND_ORIENTATION_VALUE = 0x100
+};
+
+enum fd_config_roll_angle {
+ FD_CONFIG_ROLL_ANGLE_BASIC = 0,
+ FD_CONFIG_ROLL_ANGLE_PRECISE_BASIC = 1,
+ FD_CONFIG_ROLL_ANGLE_SIDES = 2,
+ FD_CONFIG_ROLL_ANGLE_PRECISE_SIDES = 3,
+ FD_CONFIG_ROLL_ANGLE_FULL = 4,
+ FD_CONFIG_ROLL_ANGLE_PRECISE_FULL = 5,
+};
+
+enum fd_config_yaw_angle {
+ FD_CONFIG_YAW_ANGLE_0 = 0,
+ FD_CONFIG_YAW_ANGLE_45 = 1,
+ FD_CONFIG_YAW_ANGLE_90 = 2,
+ FD_CONFIG_YAW_ANGLE_45_90 = 3,
+};
+
+enum fd_config_smile_mode {
+ FD_CONFIG_SMILE_MODE_DISABLE = 0,
+ FD_CONFIG_SMILE_MODE_ENABLE = 1
+};
+
+enum fd_config_blink_mode {
+ FD_CONFIG_BLINK_MODE_DISABLE = 0,
+ FD_CONFIG_BLINK_MODE_ENABLE = 1
+};
+
+enum fd_config_eye_result {
+ FD_CONFIG_EYES_DETECT_DISABLE = 0,
+ FD_CONFIG_EYES_DETECT_ENABLE = 1
+};
+
+enum fd_config_mouth_result {
+ FD_CONFIG_MOUTH_DETECT_DISABLE = 0,
+ FD_CONFIG_MOUTH_DETECT_ENABLE = 1
+};
+
+enum fd_config_orientation {
+ FD_CONFIG_ORIENTATION_DISABLE = 0,
+ FD_CONFIG_ORIENTATION_ENABLE = 1
+};
+
+struct param_control {
+ u32 cmd;
+ u32 bypass;
+ u32 buffer_address;
+ u32 buffer_number;
+ /* 0: continuous, 1: single */
+ u32 run_mode;
+ u32 reserved[PARAMETER_MAX_MEMBER-6];
+ u32 err;
+};
+
+struct param_otf_input {
+ u32 cmd;
+ u32 width;
+ u32 height;
+ u32 format;
+ u32 bitwidth;
+ u32 order;
+ u32 crop_offset_x;
+ u32 crop_offset_y;
+ u32 crop_width;
+ u32 crop_height;
+ u32 frametime_min;
+ u32 frametime_max;
+ u32 reserved[PARAMETER_MAX_MEMBER-13];
+ u32 err;
+};
+
+struct param_dma_input {
+ u32 cmd;
+ u32 width;
+ u32 height;
+ u32 format;
+ u32 bitwidth;
+ u32 plane;
+ u32 order;
+ u32 buffer_number;
+ u32 buffer_address;
+ u32 uibayercropoffsetx;
+ u32 uibayercropoffsety;
+ u32 uibayercropwidth;
+ u32 uibayercropheight;
+ u32 uidmacropoffsetx;
+ u32 uidmacropoffsety;
+ u32 uidmacropwidth;
+ u32 uidmacropheight;
+ u32 uiuserminframetime;
+ u32 uiusermaxframetime;
+ u32 uiwideframegap;
+ u32 uiframegap;
+ u32 uilinegap;
+ u32 uireserved[PARAMETER_MAX_MEMBER-23];
+ u32 err;
+};
+
+struct param_otf_output {
+ u32 cmd;
+ u32 width;
+ u32 height;
+ u32 format;
+ u32 bitwidth;
+ u32 order;
+ u32 uicropoffsetx;
+ u32 uicropoffsety;
+ u32 reserved[PARAMETER_MAX_MEMBER-9];
+ u32 err;
+};
+
+struct param_dma_output {
+ u32 cmd;
+ u32 width;
+ u32 height;
+ u32 format;
+ u32 bitwidth;
+ u32 plane;
+ u32 order;
+ u32 buffer_number;
+ u32 buffer_address;
+ u32 notify_dma_done;
+ u32 dma_out_mask;
+ u32 reserved[PARAMETER_MAX_MEMBER-12];
+ u32 err;
+};
+
+struct param_global_shotmode {
+ u32 cmd;
+ u32 skip_frames;
+ u32 reserved[PARAMETER_MAX_MEMBER-3];
+ u32 err;
+};
+
+struct param_sensor_framerate {
+ u32 frame_rate;
+ u32 reserved[PARAMETER_MAX_MEMBER-2];
+ u32 err;
+};
+
+struct param_isp_aa {
+ u32 cmd;
+ u32 target;
+ u32 mode;
+ u32 scene;
+ u32 uiaftouch;
+ u32 uiafface;
+ u32 uiafresponse;
+ u32 sleep;
+ u32 touch_x;
+ u32 touch_y;
+ u32 manual_af_setting;
+ /*0: Legacy, 1: Camera 2.0*/
+ u32 uicamapi2p0;
+ /* For android.control.afRegions in Camera 2.0,
+ Resolution based on YUV output size*/
+ u32 uiafregionleft;
+ /* For android.control.afRegions in Camera 2.0,
+ Resolution based on YUV output size*/
+ u32 uiafregiontop;
+ /* For android.control.afRegions in Camera 2.0,
+ Resolution based on YUV output size*/
+ u32 uiafregionright;
+ /* For android.control.afRegions in Camera 2.0,
+ Resolution based on YUV output size*/
+ u32 uiafregionbottom;
+ u32 reserved[PARAMETER_MAX_MEMBER-17];
+ u32 err;
+};
+
+struct param_isp_flash {
+ u32 cmd;
+ u32 redeye;
+ u32 flashintensity;
+ u32 reserved[PARAMETER_MAX_MEMBER-4];
+ u32 err;
+};
+
+struct param_isp_awb {
+ u32 cmd;
+ u32 illumination;
+ u32 reserved[PARAMETER_MAX_MEMBER-3];
+ u32 err;
+};
+
+struct param_isp_imageeffect {
+ u32 cmd;
+ u32 reserved[PARAMETER_MAX_MEMBER-2];
+ u32 err;
+};
+
+struct param_isp_iso {
+ u32 cmd;
+ u32 value;
+ u32 reserved[PARAMETER_MAX_MEMBER-3];
+ u32 err;
+};
+
+struct param_isp_adjust {
+ u32 cmd;
+ s32 contrast;
+ s32 saturation;
+ s32 sharpness;
+ s32 exposure;
+ s32 brightness;
+ s32 hue;
+ /* 0 or 1 */
+ u32 uihotpixelenable;
+ /* -127 ~ 127 */
+ s32 uinoisereductionstrength;
+ /* 0 or 1 */
+ u32 uishadingcorrectionenable;
+ /* 0 or 1 */
+ u32 uiusergammaenable;
+ /* -127 ~ 127 */
+ s32 uiedgeenhancementstrength;
+ /* ISP_AdjustSceneIndexEnum */
+ u32 uiuserscenemode;
+ u32 uiminframetime;
+ u32 uimaxframetime;
+ u32 uireserved[PARAMETER_MAX_MEMBER-16];
+ u32 err;
+};
+
+struct param_isp_metering {
+ u32 cmd;
+ u32 win_pos_x;
+ u32 win_pos_y;
+ u32 win_width;
+ u32 win_height;
+ u32 exposure_mode;
+ /* 0: Legacy, 1: Camera 2.0 */
+ u32 uiCamApi2P0;
+ u32 reserved[PARAMETER_MAX_MEMBER-8];
+ u32 err;
+};
+
+struct param_isp_afc {
+ u32 cmd;
+ u32 manual;
+ u32 reserved[PARAMETER_MAX_MEMBER-3];
+ u32 err;
+};
+
+struct param_scaler_imageeffect {
+ u32 cmd;
+ u32 reserved[PARAMETER_MAX_MEMBER-2];
+ u32 err;
+};
+
+struct param_scaler_input_crop {
+ u32 cmd;
+ u32 pos_x;
+ u32 pos_y;
+ u32 crop_width;
+ u32 crop_height;
+ u32 in_width;
+ u32 in_height;
+ u32 out_width;
+ u32 out_height;
+ u32 reserved[PARAMETER_MAX_MEMBER-10];
+ u32 err;
+};
+
+struct param_scaler_output_crop {
+ u32 cmd;
+ u32 pos_x;
+ u32 pos_y;
+ u32 crop_width;
+ u32 crop_height;
+ u32 format;
+ u32 reserved[PARAMETER_MAX_MEMBER-7];
+ u32 err;
+};
+
+struct param_scaler_rotation {
+ u32 cmd;
+ u32 reserved[PARAMETER_MAX_MEMBER-2];
+ u32 err;
+};
+
+struct param_scaler_flip {
+ u32 cmd;
+ u32 reserved[PARAMETER_MAX_MEMBER-2];
+ u32 err;
+};
+
+struct param_3dnr_1stframe {
+ u32 cmd;
+ u32 reserved[PARAMETER_MAX_MEMBER-2];
+ u32 err;
+};
+
+struct param_fd_config {
+ u32 cmd;
+ u32 max_number;
+ u32 roll_angle;
+ u32 yaw_angle;
+ s32 smile_mode;
+ s32 blink_mode;
+ u32 eye_detect;
+ u32 mouth_detect;
+ u32 orientation;
+ u32 orientation_value;
+ u32 reserved[PARAMETER_MAX_MEMBER-11];
+ u32 err;
+};
+
+struct global_param {
+ struct param_global_shotmode shotmode; /* 0 */
+};
+
+/* To be added */
+struct sensor_param {
+ struct param_control control;
+ struct param_otf_input otf_input;
+ struct param_otf_output otf_output;
+ struct param_sensor_framerate frame_rate;
+ struct param_dma_output dma_output;
+};
+
+struct buffer_param {
+ struct param_control control;
+ struct param_otf_input otf_input;
+ struct param_otf_output otf_output;
+};
+
+struct isp_param {
+ struct param_control control;
+ struct param_otf_input otf_input;
+ struct param_dma_input dma1_input;
+ struct param_dma_input dma2_input;
+ struct param_isp_aa aa;
+ struct param_isp_flash flash;
+ struct param_isp_awb awb;
+ struct param_isp_imageeffect effect;
+ struct param_isp_iso iso;
+ struct param_isp_adjust adjust;
+ struct param_isp_metering metering;
+ struct param_isp_afc afc;
+ struct param_otf_output otf_output;
+ struct param_dma_output dma1_output;
+ struct param_dma_output dma2_output;
+};
+
+struct drc_param {
+ struct param_control control;
+ struct param_otf_input otf_input;
+ struct param_dma_input dma_input;
+ struct param_otf_output otf_output;
+};
+
+struct scalerc_param {
+ struct param_control control;
+ struct param_otf_input otf_input;
+ struct param_scaler_imageeffect effect;
+ struct param_scaler_input_crop input_crop;
+ struct param_scaler_output_crop output_crop;
+ struct param_otf_output otf_output;
+ struct param_dma_output dma_output;
+};
+
+struct odc_param {
+ struct param_control control;
+ struct param_otf_input otf_input;
+ struct param_otf_output otf_output;
+};
+
+struct dis_param {
+ struct param_control control;
+ struct param_otf_input otf_input;
+ struct param_otf_output otf_output;
+};
+
+struct tdnr_param {
+ struct param_control control;
+ struct param_otf_input otf_input;
+ struct param_3dnr_1stframe frame;
+ struct param_otf_output otf_output;
+ struct param_dma_output dma_output;
+};
+
+struct scalerp_param {
+ struct param_control control;
+ struct param_otf_input otf_input;
+ struct param_scaler_imageeffect effect;
+ struct param_scaler_input_crop input_crop;
+ struct param_scaler_output_crop output_crop;
+ struct param_scaler_rotation rotation;
+ struct param_scaler_flip flip;
+ struct param_otf_output otf_output;
+ struct param_dma_output dma_output;
+};
+
+struct fd_param {
+ struct param_control control;
+ struct param_otf_input otf_input;
+ struct param_dma_input dma_input;
+ struct param_fd_config config;
+};
+
+struct is_param_region {
+ struct global_param global;
+ struct sensor_param sensor;
+ struct buffer_param buf;
+ struct isp_param isp;
+ struct drc_param drc;
+ struct scalerc_param scalerc;
+ struct odc_param odc;
+ struct dis_param dis;
+ struct tdnr_param tdnr;
+ struct scalerp_param scalerp;
+ struct fd_param fd;
+};
+
+#define NUMBER_OF_GAMMA_CURVE_POINTS 32
+
+struct is_sensor_tune {
+ u32 exposure;
+ u32 analog_gain;
+ u32 frame_rate;
+ u32 actuator_pos;
+};
+
+struct is_tune_gammacurve {
+ u32 num_pts_x[NUMBER_OF_GAMMA_CURVE_POINTS];
+ u32 num_pts_y_r[NUMBER_OF_GAMMA_CURVE_POINTS];
+ u32 num_pts_y_g[NUMBER_OF_GAMMA_CURVE_POINTS];
+ u32 num_pts_y_b[NUMBER_OF_GAMMA_CURVE_POINTS];
+};
+
+struct is_isp_tune {
+ /* Brightness level : range 0~100, default : 7 */
+ u32 brightness_level;
+ /* Contrast level : range -127~127, default : 0 */
+ s32 contrast_level;
+ /* Saturation level : range -127~127, default : 0 */
+ s32 saturation_level;
+ s32 gamma_level;
+ struct is_tune_gammacurve gamma_curve[4];
+ /* Hue : range -127~127, default : 0 */
+ s32 hue;
+ /* Sharpness blur : range -127~127, default : 0 */
+ s32 sharpness_blur;
+ /* Despeckle : range -127~127, default : 0 */
+ s32 despeckle;
+ /* Edge color supression : range -127~127, default : 0 */
+ s32 edge_color_supression;
+ /* Noise reduction : range -127~127, default : 0 */
+ s32 noise_reduction;
+ /* (32*4 + 9)*4 = 548 bytes */
+};
+
+struct is_tune_region {
+ struct is_sensor_tune sensor_tune;
+ struct is_isp_tune isp_tune;
+};
+
+struct rational_t {
+ u32 num;
+ u32 den;
+};
+
+struct srational_t {
+ s32 num;
+ s32 den;
+};
+
+#define FLASH_FIRED_SHIFT 0
+#define FLASH_NOT_FIRED 0
+#define FLASH_FIRED 1
+
+#define FLASH_STROBE_SHIFT 1
+#define FLASH_STROBE_NO_DETECTION 0
+#define FLASH_STROBE_RESERVED 1
+#define FLASH_STROBE_RETURN_LIGHT_NOT_DETECTED 2
+#define FLASH_STROBE_RETURN_LIGHT_DETECTED 3
+
+#define FLASH_MODE_SHIFT 3
+#define FLASH_MODE_UNKNOWN 0
+#define FLASH_MODE_COMPULSORY_FLASH_FIRING 1
+#define FLASH_MODE_COMPULSORY_FLASH_SUPPRESSION 2
+#define FLASH_MODE_AUTO_MODE 3
+
+#define FLASH_FUNCTION_SHIFT 5
+#define FLASH_FUNCTION_PRESENT 0
+#define FLASH_FUNCTION_NONE 1
+
+#define FLASH_RED_EYE_SHIFT 6
+#define FLASH_RED_EYE_DISABLED 0
+#define FLASH_RED_EYE_SUPPORTED 1
+
+enum apex_aperture_value {
+ F1_0 = 0,
+ F1_4 = 1,
+ F2_0 = 2,
+ F2_8 = 3,
+ F4_0 = 4,
+ F5_6 = 5,
+ F8_9 = 6,
+ F11_0 = 7,
+ F16_0 = 8,
+ F22_0 = 9,
+ F32_0 = 10,
+};
+
+struct exif_attribute {
+ struct rational_t exposure_time;
+ struct srational_t shutter_speed;
+ u32 iso_speed_rating;
+ u32 flash;
+ struct srational_t brightness;
+};
+
+struct is_frame_header {
+ u32 valid;
+ u32 bad_mark;
+ u32 captured;
+ u32 frame_number;
+ struct exif_attribute exif;
+};
+
+struct is_fd_rect {
+ u32 offset_x;
+ u32 offset_y;
+ u32 width;
+ u32 height;
+};
+
+struct is_face_marker {
+ u32 frame_number;
+ struct is_fd_rect face;
+ struct is_fd_rect left_eye;
+ struct is_fd_rect right_eye;
+ struct is_fd_rect mouth;
+ u32 roll_angle;
+ u32 yaw_angle;
+ u32 confidence;
+ u32 uiistracked;
+ u32 uitrackedfaceid;
+ u32 smile_level;
+ u32 blink_level;
+};
+
+#define MAX_FRAME_COUNT 8
+#define MAX_FRAME_COUNT_PREVIEW 4
+#define MAX_FRAME_COUNT_CAPTURE 1
+#define MAX_FACE_COUNT 16
+
+#define MAX_SHARED_COUNT 500
+
+struct is_region {
+ struct is_param_region parameter;
+ struct is_tune_region tune;
+ struct is_frame_header header[MAX_FRAME_COUNT];
+ struct is_face_marker face[MAX_FACE_COUNT];
+ u32 shared[MAX_SHARED_COUNT];
+};
+
+struct is_time_measure_us {
+ u32 min_time_us;
+ u32 max_time_us;
+ u32 avrg_time_us;
+ u32 current_time_us;
+};
+
+struct is_debug_frame_descriptor {
+ u32 sensor_frame_time;
+ u32 sensor_exposure_time;
+ u32 sensor_analog_gain;
+ u32 req_lei;
+};
+
+#define MAX_FRAMEDESCRIPTOR_CONTEXT_NUM (30 * 20) /* 600 frame */
+#define MAX_VERSION_DISPLAY_BUF (32)
+
+struct is_share_region {
+ u32 frame_time;
+ u32 exposure_time;
+ u32 analog_gain;
+
+ u32 r_gain;
+ u32 g_gain;
+ u32 b_gain;
+
+ u32 af_position;
+ u32 af_status;
+ u32 af_scene_type;
+
+ u32 frame_descp_onoff_control;
+ u32 frame_descp_update_done;
+ u32 frame_descp_idx;
+ u32 frame_descp_max_idx;
+
+ struct is_debug_frame_descriptor
+ dbg_frame_descp_ctx[MAX_FRAMEDESCRIPTOR_CONTEXT_NUM];
+
+ u32 chip_id;
+ u32 chip_rev_no;
+ u8 ispfw_version_no[MAX_VERSION_DISPLAY_BUF];
+ u8 ispfw_version_date[MAX_VERSION_DISPLAY_BUF];
+ u8 sirc_sdk_version_no[MAX_VERSION_DISPLAY_BUF];
+ u8 sirc_sdk_revsion_no[MAX_VERSION_DISPLAY_BUF];
+ u8 sirc_sdk_version_date[MAX_VERSION_DISPLAY_BUF];
+
+ /*measure timing*/
+ struct is_time_measure_us isp_sdk_time;
+};
+
+struct is_debug_control {
+ u32 write_point; /* 0~500KB boundary*/
+ u32 assert_flag; /* 0:Not Inovked, 1:Invoked*/
+ u32 pabort_flag; /* 0:Not Inovked, 1:Invoked*/
+ u32 dabort_flag; /* 0:Not Inovked, 1:Invoked*/
+ u32 pd_ready_flag; /* 0:Normal, 1:EnterIdle(Ready to power down)*/
+ u32 isp_frameerr; /* Frame Error Count.*/
+ u32 drc_frame_err; /* Frame Error Count.*/
+ u32 scc_frame_err; /* Frame Error Count.*/
+ u32 odc_frame_err; /* Frame Error Count.*/
+ u32 dis_frame_err; /* Frame Error Count.*/
+ u32 tdnr_frame_err; /* Frame Error Count.*/
+ u32 scp_frame_err; /* Frame Error Count.*/
+ u32 fd_frame_err; /* Frame Error Count.*/
+ u32 isp_frame_drop; /* Frame Drop Count.*/
+ u32 drc_frame_drop; /* Frame Drop Count.*/
+ u32 dis_frame_drop; /* Frame Drop Count.*/
+ u32 uifdframedrop;
+};
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [RFC 04/12] exynos-fimc-is: Adds common driver header files
2013-03-08 14:59 ` [RFC 04/12] exynos-fimc-is: Adds common driver header files Arun Kumar K
@ 2013-03-23 14:05 ` Sylwester Nawrocki
0 siblings, 0 replies; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-23 14:05 UTC (permalink / raw)
To: Arun Kumar K
Cc: linux-media, linux-samsung-soc, devicetree-discuss, s.nawrocki,
kgene.kim, kilyeon.im, arunkk.samsung
On 03/08/2013 03:59 PM, Arun Kumar K wrote:
> This patch adds all the common header files used by the fimc-is
> driver. It includes the commands for interfacing with the firmware
> and error codes from IS firmware, metadata and command parameter
> definitions.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
> drivers/media/platform/exynos5-is/fimc-is-cmd.h | 211 ++
> drivers/media/platform/exynos5-is/fimc-is-err.h | 258 +++
> .../media/platform/exynos5-is/fimc-is-metadata.h | 771 +++++++
> drivers/media/platform/exynos5-is/fimc-is-param.h | 2163 ++++++++++++++++++++
> 4 files changed, 3403 insertions(+)
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-cmd.h b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
> new file mode 100644
> index 0000000..f117f41
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
[...]
> +#define HOST_SET_INT_BIT 0x00000001
> +#define HOST_CLR_INT_BIT 0x00000001
> +#define IS_SET_INT_BIT 0x00000001
> +#define IS_CLR_INT_BIT 0x00000001
> +
> +#define HOST_SET_INTERRUPT(base) (base->uiINTGR0 |= HOST_SET_INT_BIT)
> +#define HOST_CLR_INTERRUPT(base) (base->uiINTCR0 |= HOST_CLR_INT_BIT)
> +#define IS_SET_INTERRUPT(base) (base->uiINTGR1 |= IS_SET_INT_BIT)
> +#define IS_CLR_INTERRUPT(base) (base->uiINTCR1 |= IS_CLR_INT_BIT)
These 8 appear to be all unused unused definitions. Probably can be removed.
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-err.h b/drivers/media/platform/exynos5-is/fimc-is-err.h
> new file mode 100644
> index 0000000..76472a9
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-err.h
> @@ -0,0 +1,258 @@
> +/*
> + * Samsung Exynos5 SoC series FIMC-IS driver
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd
> + * Kil-yeon Lim<kilyeon.im@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef FIMC_IS_ERR_H
> +#define FIMC_IS_ERR_H
> +
> +#define IS_ERROR_VER 012 /* IS ERROR VERSION 0.07 */
> +
> +#define IS_ERROR_SUCCESS 0
> +/* General 1 ~ 100 */
> +#define IS_ERROR_INVALID_COMMAND (IS_ERROR_SUCCESS+1)
> +#define IS_ERROR_REQUEST_FAIL (IS_ERROR_INVALID_COMMAND+1)
> +#define IS_ERROR_INVALID_SCENARIO (IS_ERROR_REQUEST_FAIL+1)
> +#define IS_ERROR_INVALID_SENSORID (IS_ERROR_INVALID_SCENARIO+1)
> +#define IS_ERROR_INVALID_MODE_CHANGE (IS_ERROR_INVALID_SENSORID+1)
> +#define IS_ERROR_INVALID_MAGIC_NUMBER (IS_ERROR_INVALID_MODE_CHANGE+1)
> +#define IS_ERROR_INVALID_SETFILE_HDR (IS_ERROR_INVALID_MAGIC_NUMBER+1)
> +#define IS_ERROR_ISP_SETFILE_VERSION_MISMATCH (IS_ERROR_INVALID_SETFILE_HDR+1)
> +#define IS_ERROR_ISP_SETFILE_REVISION_MISMATCH\
> + (IS_ERROR_ISP_SETFILE_VERSION_MISMATCH+1)
> +#define IS_ERROR_BUSY (IS_ERROR_ISP_SETFILE_REVISION_MISMATCH+1)
> +#define IS_ERROR_SET_PARAMETER (IS_ERROR_BUSY+1)
> +#define IS_ERROR_INVALID_PATH (IS_ERROR_SET_PARAMETER+1)
> +#define IS_ERROR_OPEN_SENSOR_FAIL (IS_ERROR_INVALID_PATH+1)
> +#define IS_ERROR_ENTRY_MSG_THREAD_DOWN (IS_ERROR_OPEN_SENSOR_FAIL+1)
> +#define IS_ERROR_ISP_FRAME_END_NOT_DONE (IS_ERROR_ENTRY_MSG_THREAD_DOWN+1)
> +#define IS_ERROR_DRC_FRAME_END_NOT_DONE (IS_ERROR_ISP_FRAME_END_NOT_DONE+1)
> +#define IS_ERROR_SCALERC_FRAME_END_NOT_DONE (IS_ERROR_DRC_FRAME_END_NOT_DONE+1)
> +#define IS_ERROR_ODC_FRAME_END_NOT_DONE (IS_ERROR_SCALERC_FRAME_END_NOT_DONE+1)
> +#define IS_ERROR_DIS_FRAME_END_NOT_DONE (IS_ERROR_ODC_FRAME_END_NOT_DONE+1)
> +#define IS_ERROR_TDNR_FRAME_END_NOT_DONE (IS_ERROR_DIS_FRAME_END_NOT_DONE+1)
> +#define IS_ERROR_SCALERP_FRAME_END_NOT_DONE (IS_ERROR_TDNR_FRAME_END_NOT_DONE+1)
> +#define IS_ERROR_WAIT_STREAM_OFF_NOT_DONE\
> + (IS_ERROR_SCALERP_FRAME_END_NOT_DONE+1)
> +#define IS_ERROR_NO_MSG_IS_RECEIVED (IS_ERROR_WAIT_STREAM_OFF_NOT_DONE+1)
> +#define IS_ERROR_SENSOR_MSG_FAIL (IS_ERROR_NO_MSG_IS_RECEIVED+1)
> +#define IS_ERROR_ISP_MSG_FAIL (IS_ERROR_SENSOR_MSG_FAIL+1)
> +#define IS_ERROR_DRC_MSG_FAIL (IS_ERROR_ISP_MSG_FAIL+1)
> +#define IS_ERROR_SCALERC_MSG_FAIL (IS_ERROR_DRC_MSG_FAIL+1)
> +#define IS_ERROR_ODC_MSG_FAIL (IS_ERROR_SCALERC_MSG_FAIL+1)
> +#define IS_ERROR_DIS_MSG_FAIL (IS_ERROR_ODC_MSG_FAIL+1)
> +#define IS_ERROR_TDNR_MSG_FAIL (IS_ERROR_DIS_MSG_FAIL+1)
> +#define IS_ERROR_SCALERP_MSG_FAIL (IS_ERROR_TDNR_MSG_FAIL+1)
> +#define IS_ERROR_LHFD_MSG_FAIL (IS_ERROR_SCALERP_MSG_FAIL+1)
> +#define IS_ERROR_INTERNAL_STOP (IS_ERROR_LHFD_MSG_FAIL+1)
> +#define IS_ERROR_UNKNOWN 1000
> +#define IS_ERROR_TIME_OUT_FLAG 0x80000000
> +
> +/* Sensor 100 ~ 200 */
> +#define IS_ERROR_SENSOR_PWRDN_FAIL 100
> +#define IS_ERROR_SENSOR_STREAM_ON_FAIL (IS_ERROR_SENSOR_PWRDN_FAIL+1)
> +#define IS_ERROR_SENSOR_STREAM_OFF_FAIL (IS_ERROR_SENSOR_STREAM_ON_FAIL+1)
> +
> +/* ISP 200 ~ 300 */
> +#define IS_ERROR_ISP_PWRDN_FAIL 200
> +#define IS_ERROR_ISP_MULTIPLE_INPUT (IS_ERROR_ISP_PWRDN_FAIL+1)
> +#define IS_ERROR_ISP_ABSENT_INPUT (IS_ERROR_ISP_MULTIPLE_INPUT+1)
> +#define IS_ERROR_ISP_ABSENT_OUTPUT (IS_ERROR_ISP_ABSENT_INPUT+1)
> +#define IS_ERROR_ISP_NONADJACENT_OUTPUT (IS_ERROR_ISP_ABSENT_OUTPUT+1)
> +#define IS_ERROR_ISP_FORMAT_MISMATCH (IS_ERROR_ISP_NONADJACENT_OUTPUT+1)
> +#define IS_ERROR_ISP_WIDTH_MISMATCH (IS_ERROR_ISP_FORMAT_MISMATCH+1)
> +#define IS_ERROR_ISP_HEIGHT_MISMATCH (IS_ERROR_ISP_WIDTH_MISMATCH+1)
> +#define IS_ERROR_ISP_BITWIDTH_MISMATCH (IS_ERROR_ISP_HEIGHT_MISMATCH+1)
> +#define IS_ERROR_ISP_FRAME_END_TIME_OUT (IS_ERROR_ISP_BITWIDTH_MISMATCH+1)
> +
> +/* DRC 300 ~ 400 */
> +#define IS_ERROR_DRC_PWRDN_FAIL 300
> +#define IS_ERROR_DRC_MULTIPLE_INPUT (IS_ERROR_DRC_PWRDN_FAIL+1)
> +#define IS_ERROR_DRC_ABSENT_INPUT (IS_ERROR_DRC_MULTIPLE_INPUT+1)
> +#define IS_ERROR_DRC_NONADJACENT_INTPUT (IS_ERROR_DRC_ABSENT_INPUT+1)
> +#define IS_ERROR_DRC_ABSENT_OUTPUT (IS_ERROR_DRC_NONADJACENT_INTPUT+1)
> +#define IS_ERROR_DRC_NONADJACENT_OUTPUT (IS_ERROR_DRC_ABSENT_OUTPUT+1)
> +#define IS_ERROR_DRC_FORMAT_MISMATCH (IS_ERROR_DRC_NONADJACENT_OUTPUT+1)
> +#define IS_ERROR_DRC_WIDTH_MISMATCH (IS_ERROR_DRC_FORMAT_MISMATCH+1)
> +#define IS_ERROR_DRC_HEIGHT_MISMATCH (IS_ERROR_DRC_WIDTH_MISMATCH+1)
> +#define IS_ERROR_DRC_BITWIDTH_MISMATCH (IS_ERROR_DRC_HEIGHT_MISMATCH+1)
> +#define IS_ERROR_DRC_FRAME_END_TIME_OUT (IS_ERROR_DRC_BITWIDTH_MISMATCH+1)
> +
> +/*SCALERC(400~500)*/
> +#define IS_ERROR_SCALERC_PWRDN_FAIL 400
> +
> +/*ODC(500~600)*/
> +#define IS_ERROR_ODC_PWRDN_FAIL 500
> +
> +/*DIS(600~700)*/
> +#define IS_ERROR_DIS_PWRDN_FAIL 600
> +
> +/*TDNR(700~800)*/
> +#define IS_ERROR_TDNR_PWRDN_FAIL 700
> +
> +/*SCALERP(800~900)*/
> +#define IS_ERROR_SCALERP_PWRDN_FAIL 800
> +
> +/*FD(900~1000)*/
> +#define IS_ERROR_FD_PWRDN_FAIL 900
> +#define IS_ERROR_FD_MULTIPLE_INPUT (IS_ERROR_FD_PWRDN_FAIL+1)
> +#define IS_ERROR_FD_ABSENT_INPUT (IS_ERROR_FD_MULTIPLE_INPUT+1)
> +#define IS_ERROR_FD_NONADJACENT_INPUT (IS_ERROR_FD_ABSENT_INPUT+1)
> +#define IS_ERROR_LHFD_FRAME_END_TIME_OUT \
> + (IS_ERROR_FD_NONADJACENT_INPUT+1)
nit: It feels an enum would be more appropriate for these.
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-param.h b/drivers/media/platform/exynos5-is/fimc-is-param.h
> new file mode 100644
> index 0000000..63eb8d9
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-param.h
> @@ -0,0 +1,2163 @@
> +/*
> + * Samsung Exynos5 SoC series FIMC-IS driver
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd
> + * Kil-yeon Lim<kilyeon.im@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef FIMC_IS_PARAM_H
> +#define FIMC_IS_PARAM_H
> +
> +#define IS_REGION_VER 145 /* IS REGION VERSION 1.45 */
> +
> +/* MACROs */
> +#define IS_SET_PARAM_BIT(dev, num) \
> + (num>= 32 ? set_bit((num-32),&dev->p_region_index2) \
> + : set_bit(num,&dev->p_region_index1))
> +#define IS_INC_PARAM_NUM(dev) atomic_inc(&dev->p_region_num)
> +
> +#define IS_PARAM_GLOBAL(dev) (dev->is_p_region->parameter.global)
> +#define IS_PARAM_ISP(dev) (dev->is_p_region->parameter.isp)
> +#define IS_PARAM_DRC(dev) (dev->is_p_region->parameter.drc)
> +#define IS_PARAM_FD(dev) (dev->is_p_region->parameter.fd)
> +#define IS_HEADER(dev) (dev->is_p_region->header)
> +#define IS_FACE(dev) (dev->is_p_region->face)
> +#define IS_SHARED(dev) (dev->is_shared_region)
> +#define IS_PARAM_SIZE (FIMC_IS_REGION_SIZE + 1)
> +
> +/* Global control */
> +#define IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, x) \
> + (dev->is_p_region->parameter.global.shotmode.cmd = x)
> +#define IS_SET_PARAM_GLOBAL_SHOTMODE_SKIPFRAMES(dev, x) \
> + (dev->is_p_region->parameter.global.shotmode.skip_frames = x)
> +
> +/* Sensor control */
> +#define IS_SENSOR_SET_FRAME_RATE(dev, x) \
> + (dev->is_p_region->parameter.sensor.frame_rate.frame_rate = x)
> +
> +/* ISP Macros */
> +#define IS_ISP_SET_PARAM_CONTROL_CMD(dev, x) \
> + (dev->is_p_region->parameter.isp.control.cmd = x)
Hmm, these macros look pretty ugly. They obfuscate what's really being done.
I would try to rewrite the code so we use pointers to target data structures
instead.
> +#ifndef BIT0
> +#define BIT0 0x00000001
> +#define BIT1 0x00000002
> +#define BIT2 0x00000004
> +#define BIT3 0x00000008
> +#define BIT4 0x00000010
> +#define BIT5 0x00000020
> +#define BIT6 0x00000040
> +#define BIT7 0x00000080
> +#define BIT8 0x00000100
> +#define BIT9 0x00000200
> +#define BIT10 0x00000400
> +#define BIT11 0x00000800
> +#define BIT12 0x00001000
> +#define BIT13 0x00002000
> +#define BIT14 0x00004000
> +#define BIT15 0x00008000
> +#define BIT16 0x00010000
> +#define BIT17 0x00020000
> +#define BIT18 0x00040000
> +#define BIT19 0x00080000
> +#define BIT20 0x00100000
> +#define BIT21 0x00200000
> +#define BIT22 0x00400000
> +#define BIT23 0x00800000
> +#define BIT24 0x01000000
> +#define BIT25 0x02000000
> +#define BIT26 0x04000000
> +#define BIT27 0x08000000
> +#define BIT28 0x10000000
> +#define BIT29 0x20000000
> +#define BIT30 0x40000000
> +#define BIT31 0x80000000
> +#define BIT32 0x0000000100000000ULL
> +#define BIT33 0x0000000200000000ULL
> +#define BIT34 0x0000000400000000ULL
> +#define BIT35 0x0000000800000000ULL
> +#define BIT36 0x0000001000000000ULL
> +#define BIT37 0x0000002000000000ULL
> +#define BIT38 0x0000004000000000ULL
> +#define BIT39 0x0000008000000000ULL
> +#define BIT40 0x0000010000000000ULL
> +#define BIT41 0x0000020000000000ULL
> +#define BIT42 0x0000040000000000ULL
> +#define BIT43 0x0000080000000000ULL
> +#define BIT44 0x0000100000000000ULL
> +#define BIT45 0x0000200000000000ULL
> +#define BIT46 0x0000400000000000ULL
> +#define BIT47 0x0000800000000000ULL
> +#define BIT48 0x0001000000000000ULL
> +#define BIT49 0x0002000000000000ULL
> +#define BIT50 0x0004000000000000ULL
> +#define BIT51 0x0008000000000000ULL
> +#define BIT52 0x0010000000000000ULL
> +#define BIT53 0x0020000000000000ULL
> +#define BIT54 0x0040000000000000ULL
> +#define BIT55 0x0080000000000000ULL
> +#define BIT56 0x0100000000000000ULL
> +#define BIT57 0x0200000000000000ULL
> +#define BIT58 0x0400000000000000ULL
> +#define BIT59 0x0800000000000000ULL
> +#define BIT60 0x1000000000000000ULL
> +#define BIT61 0x2000000000000000ULL
> +#define BIT62 0x4000000000000000ULL
> +#define BIT63 0x8000000000000000ULL
Are you sure this is a good idea ? What do you think BIT() macro available
in bitops.h does ? And are all these BIT definitions really used anywhere ?
> +#define INC_BIT(bit) (bit<<1)
> +#define INC_NUM(bit) (bit + 1)
> +#endif
> +
> +#define MAGIC_NUMBER 0x01020304
> +
> +#define PARAMETER_MAX_SIZE 128 /* in byte */
> +#define PARAMETER_MAX_MEMBER (PARAMETER_MAX_SIZE/4)
> +
> +enum is_entry {
> + ENTRY_GLOBAL,
> + ENTRY_BUFFER,
> + ENTRY_SENSOR,
> + ENTRY_ISP,
> + ENTRY_DRC,
> + ENTRY_SCALERC,
> + ENTRY_ODC,
> + ENTRY_DIS,
> + ENTRY_TDNR,
> + ENTRY_SCALERP,
> + ENTRY_LHFD, /* 10 */
> + ENTRY_END
Are these used somewhere ?
> +};
> +
> +enum is_param_set_bit {
> + PARAM_GLOBAL_SHOTMODE = 0,
> + PARAM_SENSOR_CONTROL,
> + PARAM_SENSOR_OTF_INPUT,
> + PARAM_SENSOR_OTF_OUTPUT,
> + PARAM_SENSOR_FRAME_RATE,
> + PARAM_SENSOR_DMA_OUTPUT,
> + PARAM_BUFFER_CONTROL,
> + PARAM_BUFFER_OTF_INPUT,
> + PARAM_BUFFER_OTF_OUTPUT,
> + PARAM_ISP_CONTROL,
> + PARAM_ISP_OTF_INPUT = 10,
> + PARAM_ISP_DMA1_INPUT,
> + PARAM_ISP_DMA2_INPUT,
> + PARAM_ISP_AA,
> + PARAM_ISP_FLASH,
> + PARAM_ISP_AWB,
> + PARAM_ISP_IMAGE_EFFECT,
> + PARAM_ISP_ISO,
> + PARAM_ISP_ADJUST,
> + PARAM_ISP_METERING,
> + PARAM_ISP_AFC = 20,
> + PARAM_ISP_OTF_OUTPUT,
> + PARAM_ISP_DMA1_OUTPUT,
> + PARAM_ISP_DMA2_OUTPUT,
> + PARAM_DRC_CONTROL,
> + PARAM_DRC_OTF_INPUT,
> + PARAM_DRC_DMA_INPUT,
> + PARAM_DRC_OTF_OUTPUT,
> + PARAM_SCALERC_CONTROL,
> + PARAM_SCALERC_OTF_INPUT,
> + PARAM_SCALERC_IMAGE_EFFECT = 30,
> + PARAM_SCALERC_INPUT_CROP,
> + PARAM_SCALERC_OUTPUT_CROP,
> + PARAM_SCALERC_OTF_OUTPUT,
> + PARAM_SCALERC_DMA_OUTPUT = 34,
> + PARAM_ODC_CONTROL,
> + PARAM_ODC_OTF_INPUT,
> + PARAM_ODC_OTF_OUTPUT,
> + PARAM_DIS_CONTROL,
> + PARAM_DIS_OTF_INPUT,
> + PARAM_DIS_OTF_OUTPUT = 40,
> + PARAM_TDNR_CONTROL,
> + PARAM_TDNR_OTF_INPUT,
> + PARAM_TDNR_1ST_FRAME,
> + PARAM_TDNR_OTF_OUTPUT,
> + PARAM_TDNR_DMA_OUTPUT,
> + PARAM_SCALERP_CONTROL,
> + PARAM_SCALERP_OTF_INPUT,
> + PARAM_SCALERP_IMAGE_EFFECT,
> + PARAM_SCALERP_INPUT_CROP,
> + PARAM_SCALERP_OUTPUT_CROP = 50,
> + PARAM_SCALERP_ROTATION,
> + PARAM_SCALERP_FLIP,
> + PARAM_SCALERP_OTF_OUTPUT,
> + PARAM_SCALERP_DMA_OUTPUT,
> + PARAM_FD_CONTROL,
> + PARAM_FD_OTF_INPUT,
> + PARAM_FD_DMA_INPUT,
> + PARAM_FD_CONFIG = 58,
> + PARAM_END,
> +};
> +
> +#define ADDRESS_TO_OFFSET(start, end) ((uint32)end - (uint32)start)
> +#define OFFSET_TO_NUM(offset) ((offset)>>6)
> +#define IS_OFFSET_LOWBIT(offset) (OFFSET_TO_NUM(offset)>= \
> + 32 ? false : true)
> +#define OFFSET_TO_BIT(offset) \
> + {(IS_OFFSET_LOWBIT(offset) ? (1<<OFFSET_TO_NUM(offset)) \
> + : (1<<(OFFSET_TO_NUM(offset)-32))}
> +#define LOWBIT_OF_NUM(num) (num>= 32 ? 0 : BIT0<<num)
> +#define HIGHBIT_OF_NUM(num) (num>= 32 ? BIT0<<(num-32) : 0)
> +
> +/* 0~31 */
> +#define PARAM_GLOBAL_SHOTMODE 0
> +#define PARAM_SENSOR_CONTROL INC_NUM(PARAM_GLOBAL_SHOTMODE)
> +#define PARAM_SENSOR_OTF_INPUT INC_NUM(PARAM_SENSOR_CONTROL)
> +#define PARAM_SENSOR_OTF_OUTPUT INC_NUM(PARAM_SENSOR_OTF_INPUT)
> +#define PARAM_SENSOR_FRAME_RATE INC_NUM(PARAM_SENSOR_OTF_OUTPUT)
> +#define PARAM_SENSOR_DMA_OUTPUT INC_NUM(PARAM_SENSOR_FRAME_RATE)
> +#define PARAM_BUFFER_CONTROL INC_NUM(PARAM_SENSOR_DMA_OUTPUT)
> +#define PARAM_BUFFER_OTF_INPUT INC_NUM(PARAM_BUFFER_CONTROL)
> +#define PARAM_BUFFER_OTF_OUTPUT INC_NUM(PARAM_BUFFER_OTF_INPUT)
> +#define PARAM_ISP_CONTROL INC_NUM(PARAM_BUFFER_OTF_OUTPUT)
> +#define PARAM_ISP_OTF_INPUT INC_NUM(PARAM_ISP_CONTROL)
> +#define PARAM_ISP_DMA1_INPUT INC_NUM(PARAM_ISP_OTF_INPUT)
> +#define PARAM_ISP_DMA2_INPUT INC_NUM(PARAM_ISP_DMA1_INPUT)
> +#define PARAM_ISP_AA INC_NUM(PARAM_ISP_DMA2_INPUT)
> +#define PARAM_ISP_FLASH INC_NUM(PARAM_ISP_AA)
> +#define PARAM_ISP_AWB INC_NUM(PARAM_ISP_FLASH)
> +#define PARAM_ISP_IMAGE_EFFECT INC_NUM(PARAM_ISP_AWB)
> +#define PARAM_ISP_ISO INC_NUM(PARAM_ISP_IMAGE_EFFECT)
> +#define PARAM_ISP_ADJUST INC_NUM(PARAM_ISP_ISO)
> +#define PARAM_ISP_METERING INC_NUM(PARAM_ISP_ADJUST)
> +#define PARAM_ISP_AFC INC_NUM(PARAM_ISP_METERING)
> +#define PARAM_ISP_OTF_OUTPUT INC_NUM(PARAM_ISP_AFC)
> +#define PARAM_ISP_DMA1_OUTPUT INC_NUM(PARAM_ISP_OTF_OUTPUT)
> +#define PARAM_ISP_DMA2_OUTPUT INC_NUM(PARAM_ISP_DMA1_OUTPUT)
> +#define PARAM_DRC_CONTROL INC_NUM(PARAM_ISP_DMA2_OUTPUT)
> +#define PARAM_DRC_OTF_INPUT INC_NUM(PARAM_DRC_CONTROL)
> +#define PARAM_DRC_DMA_INPUT INC_NUM(PARAM_DRC_OTF_INPUT)
> +#define PARAM_DRC_OTF_OUTPUT INC_NUM(PARAM_DRC_DMA_INPUT)
> +#define PARAM_SCALERC_CONTROL INC_NUM(PARAM_DRC_OTF_OUTPUT)
> +#define PARAM_SCALERC_OTF_INPUT INC_NUM(PARAM_SCALERC_CONTROL)
> +#define PARAM_SCALERC_IMAGE_EFFECT INC_NUM(PARAM_SCALERC_OTF_INPUT)
> +#define PARAM_SCALERC_INPUT_CROP INC_NUM(PARAM_SCALERC_IMAGE_EFFECT)
> +#define PARAM_SCALERC_OUTPUT_CROP INC_NUM(PARAM_SCALERC_INPUT_CROP)
> +#define PARAM_SCALERC_OTF_OUTPUT INC_NUM(PARAM_SCALERC_OUTPUT_CROP)
>
> +/* 32~63 */
> +#define PARAM_SCALERC_DMA_OUTPUT INC_NUM(PARAM_SCALERC_OTF_OUTPUT)
> +#define PARAM_ODC_CONTROL INC_NUM(PARAM_SCALERC_DMA_OUTPUT)
> +#define PARAM_ODC_OTF_INPUT INC_NUM(PARAM_ODC_CONTROL)
> +#define PARAM_ODC_OTF_OUTPUT INC_NUM(PARAM_ODC_OTF_INPUT)
> +#define PARAM_DIS_CONTROL INC_NUM(PARAM_ODC_OTF_OUTPUT)
> +#define PARAM_DIS_OTF_INPUT INC_NUM(PARAM_DIS_CONTROL)
> +#define PARAM_DIS_OTF_OUTPUT INC_NUM(PARAM_DIS_OTF_INPUT)
> +#define PARAM_TDNR_CONTROL INC_NUM(PARAM_DIS_OTF_OUTPUT)
> +#define PARAM_TDNR_OTF_INPUT INC_NUM(PARAM_TDNR_CONTROL)
> +#define PARAM_TDNR_1ST_FRAME INC_NUM(PARAM_TDNR_OTF_INPUT)
> +#define PARAM_TDNR_OTF_OUTPUT INC_NUM(PARAM_TDNR_1ST_FRAME)
> +#define PARAM_TDNR_DMA_OUTPUT INC_NUM(PARAM_TDNR_OTF_OUTPUT)
> +#define PARAM_SCALERP_CONTROL INC_NUM(PARAM_TDNR_DMA_OUTPUT)
> +#define PARAM_SCALERP_OTF_INPUT INC_NUM(PARAM_SCALERP_CONTROL)
> +#define PARAM_SCALERP_IMAGE_EFFECT INC_NUM(PARAM_SCALERP_OTF_INPUT)
> +#define PARAM_SCALERP_INPUT_CROP INC_NUM(PARAM_SCALERP_IMAGE_EFFECT)
> +#define PARAM_SCALERP_OUTPUT_CROP INC_NUM(PARAM_SCALERP_INPUT_CROP)
> +#define PARAM_SCALERP_ROTATION INC_NUM(PARAM_SCALERP_OUTPUT_CROP)
> +#define PARAM_SCALERP_FLIP INC_NUM(PARAM_SCALERP_ROTATION)
> +#define PARAM_SCALERP_OTF_OUTPUT INC_NUM(PARAM_SCALERP_FLIP)
> +#define PARAM_SCALERP_DMA_OUTPUT INC_NUM(PARAM_SCALERP_OTF_OUTPUT)
> +#define PARAM_FD_CONTROL INC_NUM(PARAM_SCALERP_DMA_OUTPUT)
> +#define PARAM_FD_OTF_INPUT INC_NUM(PARAM_FD_CONTROL)
> +#define PARAM_FD_DMA_INPUT INC_NUM(PARAM_FD_OTF_INPUT)
> +#define PARAM_FD_CONFIG INC_NUM(PARAM_FD_DMA_INPUT)
> +#define PARAM_END INC_NUM(PARAM_FD_CONFIG)
Isn't it much easier to define these as enum ?
> +#define PARAM_STRNUM_GLOBAL (PARAM_GLOBAL_SHOTMODE)
> +#define PARAM_RANGE_GLOBAL 1
> +#define PARAM_STRNUM_SENSOR (PARAM_SENSOR_BYPASS)
> +#define PARAM_RANGE_SENSOR 5
> +#define PARAM_STRNUM_BUFFER (PARAM_BUFFER_BYPASS)
> +#define PARAM_RANGE_BUFFER 3
> +#define PARAM_STRNUM_ISP (PARAM_ISP_BYPASS)
> +#define PARAM_RANGE_ISP 15
> +#define PARAM_STRNUM_DRC (PARAM_DRC_BYPASS)
> +#define PARAM_RANGE_DRC 4
> +#define PARAM_STRNUM_SCALERC (PARAM_SCALERC_BYPASS)
> +#define PARAM_RANGE_SCALERC 7
> +#define PARAM_STRNUM_ODC (PARAM_ODC_BYPASS)
> +#define PARAM_RANGE_ODC 3
> +#define PARAM_STRNUM_DIS (PARAM_DIS_BYPASS)
> +#define PARAM_RANGE_DIS 3
> +#define PARAM_STRNUM_TDNR (PARAM_TDNR_BYPASS)
> +#define PARAM_RANGE_TDNR 5
> +#define PARAM_STRNUM_SCALERP (PARAM_SCALERP_BYPASS)
> +#define PARAM_RANGE_SCALERP 9
> +#define PARAM_STRNUM_LHFD (PARAM_FD_BYPASS)
> +#define PARAM_RANGE_LHFD 4
Are these definitions used anywhere ?
> +#define PARAM_LOW_MASK (0xFFFFFFFF)
> +#define PARAM_HIGH_MASK (0x07FFFFFF)
> +
[...]
> +struct param_dma_input {
> + u32 cmd;
> + u32 width;
> + u32 height;
> + u32 format;
> + u32 bitwidth;
> + u32 plane;
> + u32 order;
> + u32 buffer_number;
> + u32 buffer_address;
> + u32 uibayercropoffsetx;
> + u32 uibayercropoffsety;
> + u32 uibayercropwidth;
> + u32 uibayercropheight;
> + u32 uidmacropoffsetx;
> + u32 uidmacropoffsety;
> + u32 uidmacropwidth;
> + u32 uidmacropheight;
> + u32 uiuserminframetime;
> + u32 uiusermaxframetime;
That is really hard to read. Perhaps we can have some underscores
added so it looks like ui_user_max_frametime ?
> + u32 uiwideframegap;
> + u32 uiframegap;
> + u32 uilinegap;
> + u32 uireserved[PARAMETER_MAX_MEMBER-23];
> + u32 err;
> +};
^ permalink raw reply [flat|nested] 31+ messages in thread
* [RFC 05/12] exynos-fimc-is: Adds the register definition and context header
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
` (3 preceding siblings ...)
2013-03-08 14:59 ` [RFC 04/12] exynos-fimc-is: Adds common driver header files Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-23 14:20 ` Sylwester Nawrocki
2013-03-08 14:59 ` [RFC 06/12] exynos-fimc-is: Adds the sensor subdev Arun Kumar K
` (6 subsequent siblings)
11 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
This patch adds the register definition file for the fimc-is driver
and also the header file containing the main context for the driver.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
drivers/media/platform/exynos5-is/fimc-is-regs.h | 352 ++++++++++++++++++++++
drivers/media/platform/exynos5-is/fimc-is.h | 151 ++++++++++
2 files changed, 503 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h
create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h b/drivers/media/platform/exynos5-is/fimc-is-regs.h
new file mode 100644
index 0000000..43ed011
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h
@@ -0,0 +1,352 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_REGS_H
+#define FIMC_IS_REGS_H
+
+#include <mach/map.h>
+
+/* WDT_ISP register */
+#define WDT 0x00170000
+/* MCUCTL register */
+#define MCUCTL 0x00180000
+/* MCU Controller Register */
+#define MCUCTLR (MCUCTL+0x00)
+#define MCUCTLR_AXI_ISPX_AWCACHE(x) ((x) << 16)
+#define MCUCTLR_AXI_ISPX_ARCACHE(x) ((x) << 12)
+#define MCUCTLR_MSWRST (1 << 0)
+/* Boot Base OFfset Address Register */
+#define BBOAR (MCUCTL+0x04)
+#define BBOAR_BBOA(x) ((x) << 0)
+/* Interrupt Generation Register 0 from Host CPU to VIC */
+#define INTGR0 (MCUCTL+0x08)
+#define INTGR0_INTGC9 (1 << 25)
+#define INTGR0_INTGC8 (1 << 24)
+#define INTGR0_INTGC7 (1 << 23)
+#define INTGR0_INTGC6 (1 << 22)
+#define INTGR0_INTGC5 (1 << 21)
+#define INTGR0_INTGC4 (1 << 20)
+#define INTGR0_INTGC3 (1 << 19)
+#define INTGR0_INTGC2 (1 << 18)
+#define INTGR0_INTGC1 (1 << 17)
+#define INTGR0_INTGC0 (1 << 16)
+#define INTGR0_INTGD5 (1 << 5)
+#define INTGR0_INTGD4 (1 << 4)
+#define INTGR0_INTGD3 (1 << 3)
+#define INTGR0_INTGD2 (1 << 2)
+#define INTGR0_INTGD1 (1 << 1)
+#define INTGR0_INTGD0 (1 << 0)
+/* Interrupt Clear Register 0 from Host CPU to VIC */
+#define INTCR0 (MCUCTL+0x0c)
+#define INTCR0_INTCC9 (1 << 25)
+#define INTCR0_INTCC8 (1 << 24)
+#define INTCR0_INTCC7 (1 << 23)
+#define INTCR0_INTCC6 (1 << 22)
+#define INTCR0_INTCC5 (1 << 21)
+#define INTCR0_INTCC4 (1 << 20)
+#define INTCR0_INTCC3 (1 << 19)
+#define INTCR0_INTCC2 (1 << 18)
+#define INTCR0_INTCC1 (1 << 17)
+#define INTCR0_INTCC0 (1 << 16)
+#define INTCR0_INTCD5 (1 << 5)
+#define INTCR0_INTCD4 (1 << 4)
+#define INTCR0_INTCD3 (1 << 3)
+#define INTCR0_INTCD2 (1 << 2)
+#define INTCR0_INTCD1 (1 << 1)
+#define INTCR0_INTCD0 (1 << 0)
+/* Interrupt Mask Register 0 from Host CPU to VIC */
+#define INTMR0 (MCUCTL+0x10)
+#define INTMR0_INTMC9 (1 << 25)
+#define INTMR0_INTMC8 (1 << 24)
+#define INTMR0_INTMC7 (1 << 23)
+#define INTMR0_INTMC6 (1 << 22)
+#define INTMR0_INTMC5 (1 << 21)
+#define INTMR0_INTMC4 (1 << 20)
+#define INTMR0_INTMC3 (1 << 19)
+#define INTMR0_INTMC2 (1 << 18)
+#define INTMR0_INTMC1 (1 << 17)
+#define INTMR0_INTMC0 (1 << 16)
+#define INTMR0_INTMD5 (1 << 5)
+#define INTMR0_INTMD4 (1 << 4)
+#define INTMR0_INTMD3 (1 << 3)
+#define INTMR0_INTMD2 (1 << 2)
+#define INTMR0_INTMD1 (1 << 1)
+#define INTMR0_INTMD0 (1 << 0)
+/* Interrupt Status Register 0 from Host CPU to VIC */
+#define INTSR0 (MCUCTL+0x14)
+#define INTSR0_GET_INTSD0(x) (((x) >> 0) & 0x1)
+#define INTSR0_GET_INTSD1(x) (((x) >> 1) & 0x1)
+#define INTSR0_GET_INTSD2(x) (((x) >> 2) & 0x1)
+#define INTSR0_GET_INTSD3(x) (((x) >> 3) & 0x1)
+#define INTSR0_GET_INTSD4(x) (((x) >> 4) & 0x1)
+#define INTSR0_GET_INTSC0(x) (((x) >> 16) & 0x1)
+#define INTSR0_GET_INTSC1(x) (((x) >> 17) & 0x1)
+#define INTSR0_GET_INTSC2(x) (((x) >> 18) & 0x1)
+#define INTSR0_GET_INTSC3(x) (((x) >> 19) & 0x1)
+#define INTSR0_GET_INTSC4(x) (((x) >> 20) & 0x1)
+#define INTSR0_GET_INTSC5(x) (((x) >> 21) & 0x1)
+#define INTSR0_GET_INTSC6(x) (((x) >> 22) & 0x1)
+#define INTSR0_GET_INTSC7(x) (((x) >> 23) & 0x1)
+#define INTSR0_GET_INTSC8(x) (((x) >> 24) & 0x1)
+#define INTSR0_GET_INTSC9(x) (((x) >> 25) & 0x1)
+/* Interrupt Mask Status Register 0 from Host CPU to VIC */
+#define INTMSR0 (MCUCTL+0x18)
+#define INTMSR0_GET_INTMSD0(x) (((x) >> 0) & 0x1)
+#define INTMSR0_GET_INTMSD1(x) (((x) >> 1) & 0x1)
+#define INTMSR0_GET_INTMSD2(x) (((x) >> 2) & 0x1)
+#define INTMSR0_GET_INTMSD3(x) (((x) >> 3) & 0x1)
+#define INTMSR0_GET_INTMSD4(x) (((x) >> 4) & 0x1)
+#define INTMSR0_GET_INTMSC0(x) (((x) >> 16) & 0x1)
+#define INTMSR0_GET_INTMSC1(x) (((x) >> 17) & 0x1)
+#define INTMSR0_GET_INTMSC2(x) (((x) >> 18) & 0x1)
+#define INTMSR0_GET_INTMSC3(x) (((x) >> 19) & 0x1)
+#define INTMSR0_GET_INTMSC4(x) (((x) >> 20) & 0x1)
+#define INTMSR0_GET_INTMSC5(x) (((x) >> 21) & 0x1)
+#define INTMSR0_GET_INTMSC6(x) (((x) >> 22) & 0x1)
+#define INTMSR0_GET_INTMSC7(x) (((x) >> 23) & 0x1)
+#define INTMSR0_GET_INTMSC8(x) (((x) >> 24) & 0x1)
+#define INTMSR0_GET_INTMSC9(x) (((x) >> 25) & 0x1)
+/* Interrupt Generation Register 1 from ISP CPU to Host IC */
+#define INTGR1 (MCUCTL+0x1c)
+#define INTGR1_INTGC9 (1 << 9)
+#define INTGR1_INTGC8 (1 << 8)
+#define INTGR1_INTGC7 (1 << 7)
+#define INTGR1_INTGC6 (1 << 6)
+#define INTGR1_INTGC5 (1 << 5)
+#define INTGR1_INTGC4 (1 << 4)
+#define INTGR1_INTGC3 (1 << 3)
+#define INTGR1_INTGC2 (1 << 2)
+#define INTGR1_INTGC1 (1 << 1)
+#define INTGR1_INTGC0 (1 << 0)
+/* Interrupt Clear Register 1 from ISP CPU to Host IC */
+#define INTCR1 (MCUCTL+0x20)
+#define INTCR1_INTCC9 (1 << 9)
+#define INTCR1_INTCC8 (1 << 8)
+#define INTCR1_INTCC7 (1 << 7)
+#define INTCR1_INTCC6 (1 << 6)
+#define INTCR1_INTCC5 (1 << 5)
+#define INTCR1_INTCC4 (1 << 4)
+#define INTCR1_INTCC3 (1 << 3)
+#define INTCR1_INTCC2 (1 << 2)
+#define INTCR1_INTCC1 (1 << 1)
+#define INTCR1_INTCC0 (1 << 0)
+/* Interrupt Mask Register 1 from ISP CPU to Host IC */
+#define INTMR1 (MCUCTL+0x24)
+#define INTMR1_INTMC9 (1 << 9)
+#define INTMR1_INTMC8 (1 << 8)
+#define INTMR1_INTMC7 (1 << 7)
+#define INTMR1_INTMC6 (1 << 6)
+#define INTMR1_INTMC5 (1 << 5)
+#define INTMR1_INTMC4 (1 << 4)
+#define INTMR1_INTMC3 (1 << 3)
+#define INTMR1_INTMC2 (1 << 2)
+#define INTMR1_INTMC1 (1 << 1)
+#define INTMR1_INTMC0 (1 << 0)
+/* Interrupt Status Register 1 from ISP CPU to Host IC */
+#define INTSR1 (MCUCTL+0x28)
+/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
+#define INTMSR1 (MCUCTL+0x2c)
+/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
+#define INTCR2 (MCUCTL+0x30)
+#define INTCR2_INTCC21 (1 << 21)
+#define INTCR2_INTCC20 (1 << 20)
+#define INTCR2_INTCC19 (1 << 19)
+#define INTCR2_INTCC18 (1 << 18)
+#define INTCR2_INTCC17 (1 << 17)
+#define INTCR2_INTCC16 (1 << 16)
+/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMR2 (MCUCTL+0x34)
+#define INTMR2_INTMCIS25 (1 << 25)
+#define INTMR2_INTMCIS24 (1 << 24)
+#define INTMR2_INTMCIS23 (1 << 23)
+#define INTMR2_INTMCIS22 (1 << 22)
+#define INTMR2_INTMCIS21 (1 << 21)
+#define INTMR2_INTMCIS20 (1 << 20)
+#define INTMR2_INTMCIS19 (1 << 19)
+#define INTMR2_INTMCIS18 (1 << 18)
+#define INTMR2_INTMCIS17 (1 << 17)
+#define INTMR2_INTMCIS16 (1 << 16)
+#define INTMR2_INTMCIS15 (1 << 15)
+#define INTMR2_INTMCIS14 (1 << 14)
+#define INTMR2_INTMCIS13 (1 << 13)
+#define INTMR2_INTMCIS12 (1 << 12)
+#define INTMR2_INTMCIS11 (1 << 11)
+#define INTMR2_INTMCIS10 (1 << 10)
+#define INTMR2_INTMCIS9 (1 << 9)
+#define INTMR2_INTMCIS8 (1 << 8)
+#define INTMR2_INTMCIS7 (1 << 7)
+#define INTMR2_INTMCIS6 (1 << 6)
+#define INTMR2_INTMCIS5 (1 << 5)
+#define INTMR2_INTMCIS4 (1 << 4)
+#define INTMR2_INTMCIS3 (1 << 3)
+#define INTMR2_INTMCIS2 (1 << 2)
+#define INTMR2_INTMCIS1 (1 << 1)
+#define INTMR2_INTMCIS0 (1 << 0)
+/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTSR2 (MCUCTL+0x38)
+/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMSR2 (MCUCTL+0x3c)
+/* General Purpose Output Control Register (0~17) */
+#define GPOCTLR (MCUCTL+0x40)
+#define GPOCTLR_GPOG17(x) ((x) << 17)
+#define GPOCTLR_GPOG16(x) ((x) << 16)
+#define GPOCTLR_GPOG15(x) ((x) << 15)
+#define GPOCTLR_GPOG14(x) ((x) << 14)
+#define GPOCTLR_GPOG13(x) ((x) << 13)
+#define GPOCTLR_GPOG12(x) ((x) << 12)
+#define GPOCTLR_GPOG11(x) ((x) << 11)
+#define GPOCTLR_GPOG10(x) ((x) << 10)
+#define GPOCTLR_GPOG9(x) ((x) << 9)
+#define GPOCTLR_GPOG8(x) ((x) << 8)
+#define GPOCTLR_GPOG7(x) ((x) << 7)
+#define GPOCTLR_GPOG6(x) ((x) << 6)
+#define GPOCTLR_GPOG5(x) ((x) << 5)
+#define GPOCTLR_GPOG4(x) ((x) << 4)
+#define GPOCTLR_GPOG3(x) ((x) << 3)
+#define GPOCTLR_GPOG2(x) ((x) << 2)
+#define GPOCTLR_GPOG1(x) ((x) << 1)
+#define GPOCTLR_GPOG0(x) ((x) << 0)
+/* General Purpose Pad Output Enable Register (0~17) */
+#define GPOENCTLR (MCUCTL+0x44)
+#define GPOENCTLR_GPOEN17(x) ((x) << 17)
+#define GPOENCTLR_GPOEN16(x) ((x) << 16)
+#define GPOENCTLR_GPOEN15(x) ((x) << 15)
+#define GPOENCTLR_GPOEN14(x) ((x) << 14)
+#define GPOENCTLR_GPOEN13(x) ((x) << 13)
+#define GPOENCTLR_GPOEN12(x) ((x) << 12)
+#define GPOENCTLR_GPOEN11(x) ((x) << 11)
+#define GPOENCTLR_GPOEN10(x) ((x) << 10)
+#define GPOENCTLR_GPOEN9(x) ((x) << 9)
+#define GPOENCTLR_GPOEN8(x) ((x) << 8)
+#define GPOENCTLR_GPOEN7(x) ((x) << 7)
+#define GPOENCTLR_GPOEN6(x) ((x) << 6)
+#define GPOENCTLR_GPOEN5(x) ((x) << 5)
+#define GPOENCTLR_GPOEN4(x) ((x) << 4)
+#define GPOENCTLR_GPOEN3(x) ((x) << 3)
+#define GPOENCTLR_GPOEN2(x) ((x) << 2)
+#define GPOENCTLR_GPOEN1(x) ((x) << 1)
+#define GPOENCTLR_GPOEN0(x) ((x) << 0)
+/* General Purpose Input Control Register (0~17) */
+#define GPICTLR (MCUCTL+0x48)
+/* IS Shared Register 0 between ISP CPU and HOST CPU */
+#define ISSR0 (MCUCTL+0x80)
+/* Command Host -> IS */
+/* IS Shared Register 1 between ISP CPU and HOST CPU */
+/* Sensor ID for Command */
+#define ISSR1 (MCUCTL+0x84)
+/* IS Shared Register 2 between ISP CPU and HOST CPU */
+/* Parameter 1 */
+#define ISSR2 (MCUCTL+0x88)
+/* IS Shared Register 3 between ISP CPU and HOST CPU */
+/* Parameter 2 */
+#define ISSR3 (MCUCTL+0x8c)
+/* IS Shared Register 4 between ISP CPU and HOST CPU */
+/* Parameter 3 */
+#define ISSR4 (MCUCTL+0x90)
+/* IS Shared Register 5 between ISP CPU and HOST CPU */
+/* Parameter 4 */
+#define ISSR5 (MCUCTL+0x94)
+#define ISSR6 (MCUCTL+0x98)
+#define ISSR7 (MCUCTL+0x9c)
+#define ISSR8 (MCUCTL+0xa0)
+#define ISSR9 (MCUCTL+0xa4)
+/* IS Shared Register 10 between ISP CPU and HOST CPU */
+/* Command IS -> Host */
+#define ISSR10 (MCUCTL+0xa8)
+/* IS Shared Register 11 between ISP CPU and HOST CPU */
+/* Sensor ID for Command */
+#define ISSR11 (MCUCTL+0xac)
+/* IS Shared Register 12 between ISP CPU and HOST CPU */
+/* Parameter 1 */
+#define ISSR12 (MCUCTL+0xb0)
+/* IS Shared Register 13 between ISP CPU and HOST CPU */
+/* Parameter 2 */
+#define ISSR13 (MCUCTL+0xb4)
+/* IS Shared Register 14 between ISP CPU and HOST CPU */
+/* Parameter 3 */
+#define ISSR14 (MCUCTL+0xb8)
+/* IS Shared Register 15 between ISP CPU and HOST CPU */
+/* Parameter 4 */
+#define ISSR15 (MCUCTL+0xbc)
+#define ISSR16 (MCUCTL+0xc0)
+#define ISSR17 (MCUCTL+0xc4)
+#define ISSR18 (MCUCTL+0xc8)
+#define ISSR19 (MCUCTL+0xcc)
+/* IS Shared Register 20 between ISP CPU and HOST CPU */
+/* ISP_FRAME_DONE : SENSOR ID */
+#define ISSR20 (MCUCTL+0xd0)
+/* IS Shared Register 21 between ISP CPU and HOST CPU */
+/* ISP_FRAME_DONE : PARAMETER 1 */
+#define ISSR21 (MCUCTL+0xd4)
+#define ISSR22 (MCUCTL+0xd8)
+#define ISSR23 (MCUCTL+0xdc)
+/* IS Shared Register 24 between ISP CPU and HOST CPU */
+/* SCALERC_FRAME_DONE : SENSOR ID */
+#define ISSR24 (MCUCTL+0xe0)
+/* IS Shared Register 25 between ISP CPU and HOST CPU */
+/* SCALERC_FRAME_DONE : PARAMETER 1 */
+#define ISSR25 (MCUCTL+0xe4)
+#define ISSR26 (MCUCTL+0xe8)
+#define ISSR27 (MCUCTL+0xec)
+/* IS Shared Register 28 between ISP CPU and HOST CPU */
+/* 3DNR_FRAME_DONE : SENSOR ID */
+#define ISSR28 (MCUCTL+0xf0)
+/* IS Shared Register 29 between ISP CPU and HOST CPU */
+/* 3DNR_FRAME_DONE : PARAMETER 1 */
+#define ISSR29 (MCUCTL+0xf4)
+#define ISSR30 (MCUCTL+0xf8)
+#define ISSR31 (MCUCTL+0xfc)
+/* IS Shared Register 32 between ISP CPU and HOST CPU */
+/* SCALERP_FRAME_DONE : SENSOR ID */
+#define ISSR32 (MCUCTL+0x100)
+/* IS Shared Register 33 between ISP CPU and HOST CPU */
+/* SCALERP_FRAME_DONE : PARAMETER 1 */
+#define ISSR33 (MCUCTL+0x104)
+#define ISSR34 (MCUCTL+0x108)
+#define ISSR35 (MCUCTL+0x10c)
+#define ISSR36 (MCUCTL+0x110)
+#define ISSR37 (MCUCTL+0x114)
+#define ISSR38 (MCUCTL+0x118)
+#define ISSR39 (MCUCTL+0x11c)
+#define ISSR40 (MCUCTL+0x120)
+#define ISSR41 (MCUCTL+0x124)
+#define ISSR42 (MCUCTL+0x128)
+#define ISSR43 (MCUCTL+0x12c)
+#define ISSR44 (MCUCTL+0x130)
+#define ISSR45 (MCUCTL+0x134)
+#define ISSR46 (MCUCTL+0x138)
+#define ISSR47 (MCUCTL+0x13c)
+#define ISSR48 (MCUCTL+0x140)
+#define ISSR49 (MCUCTL+0x144)
+#define ISSR50 (MCUCTL+0x148)
+#define ISSR51 (MCUCTL+0x14c)
+#define ISSR52 (MCUCTL+0x150)
+#define ISSR53 (MCUCTL+0x154)
+#define ISSR54 (MCUCTL+0x158)
+#define ISSR55 (MCUCTL+0x15c)
+#define ISSR56 (MCUCTL+0x160)
+#define ISSR57 (MCUCTL+0x164)
+#define ISSR58 (MCUCTL+0x168)
+#define ISSR59 (MCUCTL+0x16c)
+#define ISSR60 (MCUCTL+0x170)
+#define ISSR61 (MCUCTL+0x174)
+#define ISSR62 (MCUCTL+0x178)
+#define ISSR63 (MCUCTL+0x17c)
+
+/* PMU for FIMC-IS*/
+#define PMUREG_CMU_RESET_ISP_SYS_PWR_REG (S5P_VA_PMU + 0x1584)
+#define PMUREG_ISP_ARM_CONFIGURATION (S5P_VA_PMU + 0x2280)
+#define PMUREG_ISP_ARM_STATUS (S5P_VA_PMU + 0x2284)
+#define PMUREG_ISP_ARM_OPTION (S5P_VA_PMU + 0x2288)
+#define PMUREG_ISP_LOW_POWER_OFF (S5P_VA_PMU + 0x0004)
+#define PMUREG_ISP_CONFIGURATION (S5P_VA_PMU + 0x4020)
+#define PMUREG_ISP_STATUS (S5P_VA_PMU + 0x4024)
+
+#endif
diff --git a/drivers/media/platform/exynos5-is/fimc-is.h b/drivers/media/platform/exynos5-is/fimc-is.h
new file mode 100644
index 0000000..3558d19
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is.h
@@ -0,0 +1,151 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_H_
+#define FIMC_IS_H_
+
+#include "fimc-is-err.h"
+#include "fimc-is-core.h"
+#include "fimc-is-param.h"
+#include "fimc-is-pipeline.h"
+#include "fimc-is-interface.h"
+
+extern int fimc_is_debug;
+
+#define is_dbg(level, fmt, args...) \
+ do { \
+ if (fimc_is_debug >= level) \
+ pr_debug("%s:%d: " fmt, \
+ __func__, __LINE__, ##args); \
+ } while (0)
+#define is_err(fmt, args...) \
+ pr_err("%s:%d: " fmt, __func__, __LINE__, ##args); \
+
+#define fimc_pipeline_to_is(p) container_of(p, struct fimc_is, pipeline)
+#define fimc_interface_to_is(p) container_of(p, struct fimc_is, interface)
+#define fimc_sensor_to_is(p) container_of(p, struct fimc_is, sensor)
+#define fimc_isp_to_is(p) container_of(p, struct fimc_is, isp)
+#define fimc_scp_to_is(p) container_of(p, struct fimc_is, scp)
+
+/* Macros used by media dev to get the subdev and vfd */
+/* is --> driver data from pdev
+ * pid --> pipeline index */
+#define fimc_is_isp_get_sd(is, pid) (&is->pipeline.isp.subdev)
+#define fimc_is_isp_get_vfd(is, pid) (&is->pipeline.isp.vfd)
+#define fimc_is_scc_get_sd(is, pid) (&is->pipeline.scaler[SCALER_SCC].subdev)
+#define fimc_is_scc_get_vfd(is, pid) (&is->pipeline.scaler[SCALER_SCC].vfd)
+#define fimc_is_scp_get_sd(is, pid) (&is->pipeline.scaler[SCALER_SCP].subdev)
+#define fimc_is_scp_get_vfd(is, pid) (&is->pipeline.scaler[SCALER_SCP].vfd)
+/* is --> driver data from pdev
+ * sid --> sensor index */
+#define fimc_is_sensor_get_sd(is, sid) (&is->sensor[sid].subdev)
+
+
+/**
+ * struct fimc_is - fimc lite structure
+ * @pdev: pointer to FIMC-IS platform device
+ * @pdata: platform data for FIMC-IS
+ * @alloc_ctx: videobuf2 memory allocator context
+ * @clk: FIMC-IS clocks
+ * @minfo: internal memory organization info
+ * @sensor: FIMC-IS sensor context
+ * @pipeline: hardware pipeline context
+ * @interface: hardware interface context
+ */
+struct fimc_is {
+ struct platform_device *pdev;
+
+ struct fimc_is_platdata *pdata;
+ struct vb2_alloc_ctx *alloc_ctx;
+ struct clk *clock[IS_CLK_MAX_NUM];
+
+ struct fimc_is_meminfo minfo;
+
+ struct fimc_is_sensor sensor[FIMC_IS_NUM_SENSORS];
+ struct fimc_is_pipeline pipeline;
+ struct fimc_is_interface interface;
+};
+
+/* Queue operations for ISP */
+static inline void fimc_is_isp_wait_queue_add(struct fimc_is_isp *isp,
+ struct fimc_is_buf *buf)
+{
+ list_add_tail(&buf->list, &isp->wait_queue);
+ isp->wait_queue_cnt++;
+}
+
+static inline struct fimc_is_buf *fimc_is_isp_wait_queue_get(
+ struct fimc_is_isp *isp)
+{
+ struct fimc_is_buf *buf;
+ buf = list_entry(isp->wait_queue.next,
+ struct fimc_is_buf, list);
+ list_del(&buf->list);
+ isp->wait_queue_cnt--;
+ return buf;
+}
+
+static inline void fimc_is_isp_run_queue_add(struct fimc_is_isp *isp,
+ struct fimc_is_buf *buf)
+{
+ list_add_tail(&buf->list, &isp->run_queue);
+ isp->run_queue_cnt++;
+}
+
+static inline struct fimc_is_buf *fimc_is_isp_run_queue_get(
+ struct fimc_is_isp *isp)
+{
+ struct fimc_is_buf *buf;
+ buf = list_entry(isp->run_queue.next,
+ struct fimc_is_buf, list);
+ list_del(&buf->list);
+ isp->run_queue_cnt--;
+ return buf;
+}
+
+/* Queue operations for SCALER */
+static inline void fimc_is_scaler_wait_queue_add(struct fimc_is_scaler *scp,
+ struct fimc_is_buf *buf)
+{
+ list_add_tail(&buf->list, &scp->wait_queue);
+ scp->wait_queue_cnt++;
+}
+
+static inline struct fimc_is_buf *fimc_is_scaler_wait_queue_get(
+ struct fimc_is_scaler *scp)
+{
+ struct fimc_is_buf *buf;
+ buf = list_entry(scp->wait_queue.next,
+ struct fimc_is_buf, list);
+ list_del(&buf->list);
+ scp->wait_queue_cnt--;
+ return buf;
+}
+
+static inline void fimc_is_scaler_run_queue_add(struct fimc_is_scaler *scp,
+ struct fimc_is_buf *buf)
+{
+ list_add_tail(&buf->list, &scp->run_queue);
+ scp->run_queue_cnt++;
+}
+
+static inline struct fimc_is_buf *fimc_is_scaler_run_queue_get(
+ struct fimc_is_scaler *scp)
+{
+ struct fimc_is_buf *buf;
+ buf = list_entry(scp->run_queue.next,
+ struct fimc_is_buf, list);
+ list_del(&buf->list);
+ scp->run_queue_cnt--;
+ return buf;
+}
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [RFC 05/12] exynos-fimc-is: Adds the register definition and context header
2013-03-08 14:59 ` [RFC 05/12] exynos-fimc-is: Adds the register definition and context header Arun Kumar K
@ 2013-03-23 14:20 ` Sylwester Nawrocki
0 siblings, 0 replies; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-23 14:20 UTC (permalink / raw)
To: Arun Kumar K
Cc: linux-media, linux-samsung-soc, devicetree-discuss, s.nawrocki,
kgene.kim, kilyeon.im, arunkk.samsung
On 03/08/2013 03:59 PM, Arun Kumar K wrote:
> This patch adds the register definition file for the fimc-is driver
> and also the header file containing the main context for the driver.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
> drivers/media/platform/exynos5-is/fimc-is-regs.h | 352 ++++++++++++++++++++++
> drivers/media/platform/exynos5-is/fimc-is.h | 151 ++++++++++
> 2 files changed, 503 insertions(+)
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h b/drivers/media/platform/exynos5-is/fimc-is-regs.h
> new file mode 100644
> index 0000000..43ed011
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h
> @@ -0,0 +1,352 @@
> +/*
> + * Samsung Exynos5 SoC series FIMC-IS driver
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef FIMC_IS_REGS_H
> +#define FIMC_IS_REGS_H
> +
> +#include<mach/map.h>
> +
> +/* WDT_ISP register */
> +#define WDT 0x00170000
> +/* MCUCTL register */
> +#define MCUCTL 0x00180000
> +/* MCU Controller Register */
> +#define MCUCTLR (MCUCTL+0x00)
> +#define MCUCTLR_AXI_ISPX_AWCACHE(x) ((x)<< 16)
> +#define MCUCTLR_AXI_ISPX_ARCACHE(x) ((x)<< 12)
> +#define MCUCTLR_MSWRST (1<< 0)
> +/* Boot Base OFfset Address Register */
> +#define BBOAR (MCUCTL+0x04)
> +#define BBOAR_BBOA(x) ((x)<< 0)
> +/* Interrupt Generation Register 0 from Host CPU to VIC */
> +#define INTGR0 (MCUCTL+0x08)
> +#define INTGR0_INTGC9 (1<< 25)
> +#define INTGR0_INTGC8 (1<< 24)
> +#define INTGR0_INTGC7 (1<< 23)
> +#define INTGR0_INTGC6 (1<< 22)
> +#define INTGR0_INTGC5 (1<< 21)
> +#define INTGR0_INTGC4 (1<< 20)
> +#define INTGR0_INTGC3 (1<< 19)
> +#define INTGR0_INTGC2 (1<< 18)
> +#define INTGR0_INTGC1 (1<< 17)
> +#define INTGR0_INTGC0 (1<< 16)
Why don't you define these as
#define INTGR0_INTGC(n) (1 << ((n) + 16))
? Tens of lines could be eliminated from this header file by using
this method to other definitions as well.
> +#define INTGR0_INTGD5 (1<< 5)
> +#define INTGR0_INTGD4 (1<< 4)
> +#define INTGR0_INTGD3 (1<< 3)
> +#define INTGR0_INTGD2 (1<< 2)
> +#define INTGR0_INTGD1 (1<< 1)
> +#define INTGR0_INTGD0 (1<< 0)
> +/* Interrupt Clear Register 0 from Host CPU to VIC */
> +#define INTCR0 (MCUCTL+0x0c)
> +#define INTCR0_INTCC9 (1<< 25)
> +#define INTCR0_INTCC8 (1<< 24)
> +#define INTCR0_INTCC7 (1<< 23)
> +#define INTCR0_INTCC6 (1<< 22)
> +#define INTCR0_INTCC5 (1<< 21)
> +#define INTCR0_INTCC4 (1<< 20)
> +#define INTCR0_INTCC3 (1<< 19)
> +#define INTCR0_INTCC2 (1<< 18)
> +#define INTCR0_INTCC1 (1<< 17)
> +#define INTCR0_INTCC0 (1<< 16)
> +#define INTCR0_INTCD5 (1<< 5)
> +#define INTCR0_INTCD4 (1<< 4)
> +#define INTCR0_INTCD3 (1<< 3)
> +#define INTCR0_INTCD2 (1<< 2)
> +#define INTCR0_INTCD1 (1<< 1)
> +#define INTCR0_INTCD0 (1<< 0)
> +/* Interrupt Mask Register 0 from Host CPU to VIC */
> +#define INTMR0 (MCUCTL+0x10)
> +#define INTMR0_INTMC9 (1<< 25)
> +#define INTMR0_INTMC8 (1<< 24)
> +#define INTMR0_INTMC7 (1<< 23)
> +#define INTMR0_INTMC6 (1<< 22)
> +#define INTMR0_INTMC5 (1<< 21)
> +#define INTMR0_INTMC4 (1<< 20)
> +#define INTMR0_INTMC3 (1<< 19)
> +#define INTMR0_INTMC2 (1<< 18)
> +#define INTMR0_INTMC1 (1<< 17)
> +#define INTMR0_INTMC0 (1<< 16)
> +#define INTMR0_INTMD5 (1<< 5)
> +#define INTMR0_INTMD4 (1<< 4)
> +#define INTMR0_INTMD3 (1<< 3)
> +#define INTMR0_INTMD2 (1<< 2)
> +#define INTMR0_INTMD1 (1<< 1)
> +#define INTMR0_INTMD0 (1<< 0)
> +/* Interrupt Status Register 0 from Host CPU to VIC */
> +#define INTSR0 (MCUCTL+0x14)
> +#define INTSR0_GET_INTSD0(x) (((x)>> 0)& 0x1)
> +#define INTSR0_GET_INTSD1(x) (((x)>> 1)& 0x1)
> +#define INTSR0_GET_INTSD2(x) (((x)>> 2)& 0x1)
> +#define INTSR0_GET_INTSD3(x) (((x)>> 3)& 0x1)
> +#define INTSR0_GET_INTSD4(x) (((x)>> 4)& 0x1)
> +#define INTSR0_GET_INTSC0(x) (((x)>> 16)& 0x1)
> +#define INTSR0_GET_INTSC1(x) (((x)>> 17)& 0x1)
> +#define INTSR0_GET_INTSC2(x) (((x)>> 18)& 0x1)
> +#define INTSR0_GET_INTSC3(x) (((x)>> 19)& 0x1)
> +#define INTSR0_GET_INTSC4(x) (((x)>> 20)& 0x1)
> +#define INTSR0_GET_INTSC5(x) (((x)>> 21)& 0x1)
> +#define INTSR0_GET_INTSC6(x) (((x)>> 22)& 0x1)
> +#define INTSR0_GET_INTSC7(x) (((x)>> 23)& 0x1)
> +#define INTSR0_GET_INTSC8(x) (((x)>> 24)& 0x1)
> +#define INTSR0_GET_INTSC9(x) (((x)>> 25)& 0x1)
> +/* Interrupt Mask Status Register 0 from Host CPU to VIC */
> +#define INTMSR0 (MCUCTL+0x18)
> +#define INTMSR0_GET_INTMSD0(x) (((x)>> 0)& 0x1)
> +#define INTMSR0_GET_INTMSD1(x) (((x)>> 1)& 0x1)
> +#define INTMSR0_GET_INTMSD2(x) (((x)>> 2)& 0x1)
> +#define INTMSR0_GET_INTMSD3(x) (((x)>> 3)& 0x1)
> +#define INTMSR0_GET_INTMSD4(x) (((x)>> 4)& 0x1)
> +#define INTMSR0_GET_INTMSC0(x) (((x)>> 16)& 0x1)
> +#define INTMSR0_GET_INTMSC1(x) (((x)>> 17)& 0x1)
> +#define INTMSR0_GET_INTMSC2(x) (((x)>> 18)& 0x1)
> +#define INTMSR0_GET_INTMSC3(x) (((x)>> 19)& 0x1)
> +#define INTMSR0_GET_INTMSC4(x) (((x)>> 20)& 0x1)
> +#define INTMSR0_GET_INTMSC5(x) (((x)>> 21)& 0x1)
> +#define INTMSR0_GET_INTMSC6(x) (((x)>> 22)& 0x1)
> +#define INTMSR0_GET_INTMSC7(x) (((x)>> 23)& 0x1)
> +#define INTMSR0_GET_INTMSC8(x) (((x)>> 24)& 0x1)
> +#define INTMSR0_GET_INTMSC9(x) (((x)>> 25)& 0x1)
> +/* Interrupt Generation Register 1 from ISP CPU to Host IC */
> +#define INTGR1 (MCUCTL+0x1c)
> +#define INTGR1_INTGC9 (1<< 9)
> +#define INTGR1_INTGC8 (1<< 8)
> +#define INTGR1_INTGC7 (1<< 7)
> +#define INTGR1_INTGC6 (1<< 6)
> +#define INTGR1_INTGC5 (1<< 5)
> +#define INTGR1_INTGC4 (1<< 4)
> +#define INTGR1_INTGC3 (1<< 3)
> +#define INTGR1_INTGC2 (1<< 2)
> +#define INTGR1_INTGC1 (1<< 1)
> +#define INTGR1_INTGC0 (1<< 0)
> +/* Interrupt Clear Register 1 from ISP CPU to Host IC */
> +#define INTCR1 (MCUCTL+0x20)
> +#define INTCR1_INTCC9 (1<< 9)
> +#define INTCR1_INTCC8 (1<< 8)
> +#define INTCR1_INTCC7 (1<< 7)
> +#define INTCR1_INTCC6 (1<< 6)
> +#define INTCR1_INTCC5 (1<< 5)
> +#define INTCR1_INTCC4 (1<< 4)
> +#define INTCR1_INTCC3 (1<< 3)
> +#define INTCR1_INTCC2 (1<< 2)
> +#define INTCR1_INTCC1 (1<< 1)
> +#define INTCR1_INTCC0 (1<< 0)
> +/* Interrupt Mask Register 1 from ISP CPU to Host IC */
> +#define INTMR1 (MCUCTL+0x24)
> +#define INTMR1_INTMC9 (1<< 9)
> +#define INTMR1_INTMC8 (1<< 8)
> +#define INTMR1_INTMC7 (1<< 7)
> +#define INTMR1_INTMC6 (1<< 6)
> +#define INTMR1_INTMC5 (1<< 5)
> +#define INTMR1_INTMC4 (1<< 4)
> +#define INTMR1_INTMC3 (1<< 3)
> +#define INTMR1_INTMC2 (1<< 2)
> +#define INTMR1_INTMC1 (1<< 1)
> +#define INTMR1_INTMC0 (1<< 0)
> +/* Interrupt Status Register 1 from ISP CPU to Host IC */
> +#define INTSR1 (MCUCTL+0x28)
> +/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
> +#define INTMSR1 (MCUCTL+0x2c)
> +/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
> +#define INTCR2 (MCUCTL+0x30)
> +#define INTCR2_INTCC21 (1<< 21)
> +#define INTCR2_INTCC20 (1<< 20)
> +#define INTCR2_INTCC19 (1<< 19)
> +#define INTCR2_INTCC18 (1<< 18)
> +#define INTCR2_INTCC17 (1<< 17)
> +#define INTCR2_INTCC16 (1<< 16)
> +/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
> +#define INTMR2 (MCUCTL+0x34)
> +#define INTMR2_INTMCIS25 (1<< 25)
> +#define INTMR2_INTMCIS24 (1<< 24)
> +#define INTMR2_INTMCIS23 (1<< 23)
> +#define INTMR2_INTMCIS22 (1<< 22)
> +#define INTMR2_INTMCIS21 (1<< 21)
> +#define INTMR2_INTMCIS20 (1<< 20)
> +#define INTMR2_INTMCIS19 (1<< 19)
> +#define INTMR2_INTMCIS18 (1<< 18)
> +#define INTMR2_INTMCIS17 (1<< 17)
> +#define INTMR2_INTMCIS16 (1<< 16)
> +#define INTMR2_INTMCIS15 (1<< 15)
> +#define INTMR2_INTMCIS14 (1<< 14)
> +#define INTMR2_INTMCIS13 (1<< 13)
> +#define INTMR2_INTMCIS12 (1<< 12)
> +#define INTMR2_INTMCIS11 (1<< 11)
> +#define INTMR2_INTMCIS10 (1<< 10)
> +#define INTMR2_INTMCIS9 (1<< 9)
> +#define INTMR2_INTMCIS8 (1<< 8)
> +#define INTMR2_INTMCIS7 (1<< 7)
> +#define INTMR2_INTMCIS6 (1<< 6)
> +#define INTMR2_INTMCIS5 (1<< 5)
> +#define INTMR2_INTMCIS4 (1<< 4)
> +#define INTMR2_INTMCIS3 (1<< 3)
> +#define INTMR2_INTMCIS2 (1<< 2)
> +#define INTMR2_INTMCIS1 (1<< 1)
> +#define INTMR2_INTMCIS0 (1<< 0)
> +/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
> +#define INTSR2 (MCUCTL+0x38)
> +/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
> +#define INTMSR2 (MCUCTL+0x3c)
> +/* General Purpose Output Control Register (0~17) */
> +#define GPOCTLR (MCUCTL+0x40)
> +#define GPOCTLR_GPOG17(x) ((x)<< 17)
> +#define GPOCTLR_GPOG16(x) ((x)<< 16)
> +#define GPOCTLR_GPOG15(x) ((x)<< 15)
> +#define GPOCTLR_GPOG14(x) ((x)<< 14)
> +#define GPOCTLR_GPOG13(x) ((x)<< 13)
> +#define GPOCTLR_GPOG12(x) ((x)<< 12)
> +#define GPOCTLR_GPOG11(x) ((x)<< 11)
> +#define GPOCTLR_GPOG10(x) ((x)<< 10)
> +#define GPOCTLR_GPOG9(x) ((x)<< 9)
> +#define GPOCTLR_GPOG8(x) ((x)<< 8)
> +#define GPOCTLR_GPOG7(x) ((x)<< 7)
> +#define GPOCTLR_GPOG6(x) ((x)<< 6)
> +#define GPOCTLR_GPOG5(x) ((x)<< 5)
> +#define GPOCTLR_GPOG4(x) ((x)<< 4)
> +#define GPOCTLR_GPOG3(x) ((x)<< 3)
> +#define GPOCTLR_GPOG2(x) ((x)<< 2)
> +#define GPOCTLR_GPOG1(x) ((x)<< 1)
> +#define GPOCTLR_GPOG0(x) ((x)<< 0)
> +/* General Purpose Pad Output Enable Register (0~17) */
> +#define GPOENCTLR (MCUCTL+0x44)
> +#define GPOENCTLR_GPOEN17(x) ((x)<< 17)
> +#define GPOENCTLR_GPOEN16(x) ((x)<< 16)
> +#define GPOENCTLR_GPOEN15(x) ((x)<< 15)
> +#define GPOENCTLR_GPOEN14(x) ((x)<< 14)
> +#define GPOENCTLR_GPOEN13(x) ((x)<< 13)
> +#define GPOENCTLR_GPOEN12(x) ((x)<< 12)
> +#define GPOENCTLR_GPOEN11(x) ((x)<< 11)
> +#define GPOENCTLR_GPOEN10(x) ((x)<< 10)
> +#define GPOENCTLR_GPOEN9(x) ((x)<< 9)
> +#define GPOENCTLR_GPOEN8(x) ((x)<< 8)
> +#define GPOENCTLR_GPOEN7(x) ((x)<< 7)
> +#define GPOENCTLR_GPOEN6(x) ((x)<< 6)
> +#define GPOENCTLR_GPOEN5(x) ((x)<< 5)
> +#define GPOENCTLR_GPOEN4(x) ((x)<< 4)
> +#define GPOENCTLR_GPOEN3(x) ((x)<< 3)
> +#define GPOENCTLR_GPOEN2(x) ((x)<< 2)
> +#define GPOENCTLR_GPOEN1(x) ((x)<< 1)
> +#define GPOENCTLR_GPOEN0(x) ((x)<< 0)
> +/* General Purpose Input Control Register (0~17) */
> +#define GPICTLR (MCUCTL+0x48)
> +/* IS Shared Register 0 between ISP CPU and HOST CPU */
> +#define ISSR0 (MCUCTL+0x80)
> +/* Command Host -> IS */
> +/* IS Shared Register 1 between ISP CPU and HOST CPU */
> +/* Sensor ID for Command */
> +#define ISSR1 (MCUCTL+0x84)
> +/* IS Shared Register 2 between ISP CPU and HOST CPU */
> +/* Parameter 1 */
> +#define ISSR2 (MCUCTL+0x88)
> +/* IS Shared Register 3 between ISP CPU and HOST CPU */
> +/* Parameter 2 */
> +#define ISSR3 (MCUCTL+0x8c)
> +/* IS Shared Register 4 between ISP CPU and HOST CPU */
> +/* Parameter 3 */
> +#define ISSR4 (MCUCTL+0x90)
> +/* IS Shared Register 5 between ISP CPU and HOST CPU */
> +/* Parameter 4 */
> +#define ISSR5 (MCUCTL+0x94)
> +#define ISSR6 (MCUCTL+0x98)
> +#define ISSR7 (MCUCTL+0x9c)
> +#define ISSR8 (MCUCTL+0xa0)
> +#define ISSR9 (MCUCTL+0xa4)
> +/* IS Shared Register 10 between ISP CPU and HOST CPU */
> +/* Command IS -> Host */
> +#define ISSR10 (MCUCTL+0xa8)
> +/* IS Shared Register 11 between ISP CPU and HOST CPU */
> +/* Sensor ID for Command */
> +#define ISSR11 (MCUCTL+0xac)
> +/* IS Shared Register 12 between ISP CPU and HOST CPU */
> +/* Parameter 1 */
> +#define ISSR12 (MCUCTL+0xb0)
> +/* IS Shared Register 13 between ISP CPU and HOST CPU */
> +/* Parameter 2 */
> +#define ISSR13 (MCUCTL+0xb4)
> +/* IS Shared Register 14 between ISP CPU and HOST CPU */
> +/* Parameter 3 */
> +#define ISSR14 (MCUCTL+0xb8)
> +/* IS Shared Register 15 between ISP CPU and HOST CPU */
> +/* Parameter 4 */
> +#define ISSR15 (MCUCTL+0xbc)
> +#define ISSR16 (MCUCTL+0xc0)
> +#define ISSR17 (MCUCTL+0xc4)
> +#define ISSR18 (MCUCTL+0xc8)
> +#define ISSR19 (MCUCTL+0xcc)
> +/* IS Shared Register 20 between ISP CPU and HOST CPU */
> +/* ISP_FRAME_DONE : SENSOR ID */
> +#define ISSR20 (MCUCTL+0xd0)
> +/* IS Shared Register 21 between ISP CPU and HOST CPU */
> +/* ISP_FRAME_DONE : PARAMETER 1 */
> +#define ISSR21 (MCUCTL+0xd4)
> +#define ISSR22 (MCUCTL+0xd8)
> +#define ISSR23 (MCUCTL+0xdc)
> +/* IS Shared Register 24 between ISP CPU and HOST CPU */
> +/* SCALERC_FRAME_DONE : SENSOR ID */
> +#define ISSR24 (MCUCTL+0xe0)
> +/* IS Shared Register 25 between ISP CPU and HOST CPU */
> +/* SCALERC_FRAME_DONE : PARAMETER 1 */
> +#define ISSR25 (MCUCTL+0xe4)
> +#define ISSR26 (MCUCTL+0xe8)
> +#define ISSR27 (MCUCTL+0xec)
> +/* IS Shared Register 28 between ISP CPU and HOST CPU */
> +/* 3DNR_FRAME_DONE : SENSOR ID */
> +#define ISSR28 (MCUCTL+0xf0)
> +/* IS Shared Register 29 between ISP CPU and HOST CPU */
> +/* 3DNR_FRAME_DONE : PARAMETER 1 */
> +#define ISSR29 (MCUCTL+0xf4)
> +#define ISSR30 (MCUCTL+0xf8)
> +#define ISSR31 (MCUCTL+0xfc)
> +/* IS Shared Register 32 between ISP CPU and HOST CPU */
> +/* SCALERP_FRAME_DONE : SENSOR ID */
> +#define ISSR32 (MCUCTL+0x100)
> +/* IS Shared Register 33 between ISP CPU and HOST CPU */
> +/* SCALERP_FRAME_DONE : PARAMETER 1 */
> +#define ISSR33 (MCUCTL+0x104)
> +#define ISSR34 (MCUCTL+0x108)
> +#define ISSR35 (MCUCTL+0x10c)
> +#define ISSR36 (MCUCTL+0x110)
> +#define ISSR37 (MCUCTL+0x114)
> +#define ISSR38 (MCUCTL+0x118)
> +#define ISSR39 (MCUCTL+0x11c)
> +#define ISSR40 (MCUCTL+0x120)
> +#define ISSR41 (MCUCTL+0x124)
> +#define ISSR42 (MCUCTL+0x128)
> +#define ISSR43 (MCUCTL+0x12c)
> +#define ISSR44 (MCUCTL+0x130)
> +#define ISSR45 (MCUCTL+0x134)
> +#define ISSR46 (MCUCTL+0x138)
> +#define ISSR47 (MCUCTL+0x13c)
> +#define ISSR48 (MCUCTL+0x140)
> +#define ISSR49 (MCUCTL+0x144)
> +#define ISSR50 (MCUCTL+0x148)
> +#define ISSR51 (MCUCTL+0x14c)
> +#define ISSR52 (MCUCTL+0x150)
> +#define ISSR53 (MCUCTL+0x154)
> +#define ISSR54 (MCUCTL+0x158)
> +#define ISSR55 (MCUCTL+0x15c)
> +#define ISSR56 (MCUCTL+0x160)
> +#define ISSR57 (MCUCTL+0x164)
> +#define ISSR58 (MCUCTL+0x168)
> +#define ISSR59 (MCUCTL+0x16c)
> +#define ISSR60 (MCUCTL+0x170)
> +#define ISSR61 (MCUCTL+0x174)
> +#define ISSR62 (MCUCTL+0x178)
> +#define ISSR63 (MCUCTL+0x17c)
It should be safe to replace these 64 lines with this one
#define ISSR(n) (MCUCTL + 0x80 + (n))
Then users would need of course to be updated as well.
> +/* PMU for FIMC-IS*/
> +#define PMUREG_CMU_RESET_ISP_SYS_PWR_REG (S5P_VA_PMU + 0x1584)
> +#define PMUREG_ISP_ARM_CONFIGURATION (S5P_VA_PMU + 0x2280)
> +#define PMUREG_ISP_ARM_STATUS (S5P_VA_PMU + 0x2284)
> +#define PMUREG_ISP_ARM_OPTION (S5P_VA_PMU + 0x2288)
> +#define PMUREG_ISP_LOW_POWER_OFF (S5P_VA_PMU + 0x0004)
> +#define PMUREG_ISP_CONFIGURATION (S5P_VA_PMU + 0x4020)
> +#define PMUREG_ISP_STATUS (S5P_VA_PMU + 0x4024)
No more global statically mapped registers please. The better solution
could
be to define a DT subnode for the ISP PMU registers, to pass the register
memory region and then use offsets only with the mmaped region base. Please
see pmureg_read/write() functions in my Exynos4x12 patch series.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [RFC 06/12] exynos-fimc-is: Adds the sensor subdev
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
` (4 preceding siblings ...)
2013-03-08 14:59 ` [RFC 05/12] exynos-fimc-is: Adds the register definition and context header Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-23 14:48 ` Sylwester Nawrocki
2013-03-08 14:59 ` [RFC 07/12] exynos-fimc-is: Adds isp subdev Arun Kumar K
` (5 subsequent siblings)
11 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
FIMC-IS uses certain sensors which are exclusively controlled
from the IS firmware. This patch adds the sensor subdev for the
fimc-is sensors.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
drivers/media/platform/exynos5-is/fimc-is-sensor.c | 337 ++++++++++++++++++++
drivers/media/platform/exynos5-is/fimc-is-sensor.h | 170 ++++++++++
2 files changed, 507 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
new file mode 100644
index 0000000..c031493
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
@@ -0,0 +1,337 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include "fimc-is-sensor.h"
+#include "fimc-is.h"
+
+static char *sensor_clock_name[] = {
+ [SCLK_BAYER] = "sclk_bayer",
+ [SCLK_CAM0] = "sclk_cam0",
+ [SCLK_CAM1] = "sclk_cam1",
+};
+
+static struct fimc_is_sensor_info sensor_info[] = {
+ [SENSOR_S5K4E5] = {
+ .sensor_id = SENSOR_S5K4E5,
+ .sensor_name = "samsung,s5k4e5",
+ .pixel_width = SENSOR_4E5_WIDTH + 16,
+ .pixel_height = SENSOR_4E5_HEIGHT + 10,
+ .active_width = SENSOR_4E5_WIDTH,
+ .active_height = SENSOR_4E5_HEIGHT,
+ .max_framerate = 30,
+ .setfile_name = "setfile_4e5.bin",
+ .ext = {
+ .actuator_con = {
+ .product_name = ACTUATOR_NAME_DWXXXX,
+ .peri_type = SE_I2C,
+ .peri_setting.i2c.channel = SENSOR_CONTROL_I2C0,
+ },
+ .flash_con = {
+ .product_name = FLADRV_NAME_KTD267,
+ .peri_type = SE_GPIO,
+ .peri_setting.gpio.first_gpio_port_no = 1,
+ .peri_setting.gpio.second_gpio_port_no = 2,
+ },
+ .from_con.product_name = FROMDRV_NAME_NOTHING,
+ .mclk = 0,
+ .mipi_lane_num = 0,
+ .mipi_speed = 0,
+ .fast_open_sensor = 0,
+ .self_calibration_mode = 0,
+ },
+
+ },
+ [SENSOR_S5K6A3] = {
+ .sensor_id = SENSOR_S5K6A3,
+ .sensor_name = "samsung,s5k6a3",
+ .pixel_width = SENSOR_6A3_WIDTH + 16,
+ .pixel_height = SENSOR_6A3_HEIGHT + 10,
+ .active_width = SENSOR_6A3_WIDTH,
+ .active_height = SENSOR_6A3_HEIGHT,
+ .max_framerate = 30,
+ .setfile_name = "setfile_6a3.bin",
+ },
+};
+
+/* Sensor supported formats */
+static struct v4l2_mbus_framefmt sensor_formats[FIMC_IS_MAX_SENSORS] = {
+ [SENSOR_S5K4E5] = {
+ .width = SENSOR_4E5_WIDTH + 16,
+ .height = SENSOR_4E5_HEIGHT + 10,
+ .code = V4L2_MBUS_FMT_SGRBG10_1X10,
+ .field = V4L2_FIELD_NONE,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ },
+ [SENSOR_S5K6A3] = {
+ .width = SENSOR_6A3_WIDTH + 16,
+ .height = SENSOR_6A3_HEIGHT + 10,
+ .code = V4L2_MBUS_FMT_SGRBG10_1X10,
+ .field = V4L2_FIELD_NONE,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ },
+};
+
+static struct fimc_is_sensor *sd_to_fimc_is_sensor(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct fimc_is_sensor, subdev);
+}
+
+static void sensor_clk_put(struct fimc_is_sensor *sensor)
+{
+ int i;
+
+ for (i = 0; i < SCLK_MAX_NUM; i++) {
+ if (IS_ERR_OR_NULL(sensor->clock[i]))
+ continue;
+ clk_unprepare(sensor->clock[i]);
+ clk_put(sensor->clock[i]);
+ sensor->clock[i] = NULL;
+ }
+}
+
+static int sensor_clk_init(struct fimc_is_sensor *sensor)
+{
+ int i, ret;
+
+ /* Get CAM clocks */
+ for (i = 0; i < SCLK_MAX_NUM; i++) {
+ sensor->clock[i] = clk_get(NULL, sensor_clock_name[i]);
+ if (IS_ERR(sensor->clock[i]))
+ goto err;
+ ret = clk_prepare(sensor->clock[i]);
+ if (ret < 0) {
+ clk_put(sensor->clock[i]);
+ sensor->clock[i] = NULL;
+ goto err;
+ }
+ }
+
+ /* Set clock rates */
+ ret = clk_set_rate(sensor->clock[SCLK_CAM0], 24 * 1000000);
+ ret |= clk_set_rate(sensor->clock[SCLK_BAYER], 24 * 1000000);
+ if (ret) {
+ is_err("Failed to set cam clock rates\n");
+ goto err;
+ }
+ return 0;
+err:
+ sensor_clk_put(sensor);
+ is_err("Failed to init sensor clock\n");
+ return -ENXIO;
+}
+
+static int sensor_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
+ struct fimc_is_sensor_info *sinfo = sensor->sensor_info;
+
+ if (!code)
+ return -EINVAL;
+
+ code->code = sensor_formats[sinfo->sensor_id].code;
+ return 0;
+}
+
+static int sensor_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_format *fmt)
+{
+ struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
+ struct fimc_is_sensor_info *sinfo = sensor->sensor_info;
+ struct v4l2_mbus_framefmt *sfmt = &fmt->format;
+
+ if ((sfmt->width != sensor_formats[sinfo->sensor_id].width) ||
+ (sfmt->height != sensor_formats[sinfo->sensor_id].height) ||
+ (sfmt->code != sensor_formats[sinfo->sensor_id].code))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int sensor_get_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_format *fmt)
+{
+ struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
+ struct fimc_is_sensor_info *sinfo = sensor->sensor_info;
+
+ fmt->format = sensor_formats[sinfo->sensor_id];
+ return 0;
+}
+
+static struct v4l2_subdev_pad_ops sensor_pad_ops = {
+ .enum_mbus_code = sensor_enum_mbus_code,
+ .get_fmt = sensor_get_fmt,
+ .set_fmt = sensor_set_fmt,
+};
+
+static int sensor_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ return 0;
+}
+
+static const struct v4l2_subdev_internal_ops sensor_sd_internal_ops = {
+ .open = sensor_open,
+};
+
+static int sensor_s_power(struct v4l2_subdev *sd, int on)
+{
+ struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
+ struct fimc_is_sensor_data *sdata = sensor->sensor_data;
+
+ if (on) {
+ /* Power on sensor */
+ sensor_clk_init(sensor);
+ gpio_request(sdata->gpios[0], "fimc_is_sensor");
+ gpio_direction_output(sdata->gpios[0], 1);
+ gpio_free(sdata->gpios[0]);
+ } else {
+ /* Power off sensor */
+ gpio_request(sdata->gpios[0], "fimc_is_sensor");
+ gpio_direction_output(sdata->gpios[0], 0);
+ gpio_free(sdata->gpios[0]);
+ sensor_clk_put(sensor);
+ }
+ return 0;
+}
+
+static struct v4l2_subdev_core_ops sensor_core_ops = {
+ .s_power = sensor_s_power,
+};
+
+static int sensor_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
+ int ret;
+
+ if (enable) {
+ is_dbg(3, "Stream ON\n");
+ /* Open pipeline */
+ ret = fimc_is_pipeline_open(sensor->pipeline, sensor);
+ if (ret < 0) {
+ is_err("Pipeline already opened.\n");
+ return -EBUSY;
+ }
+
+ /* Start IS pipeline */
+ ret = fimc_is_pipeline_start(sensor->pipeline);
+ if (ret < 0) {
+ is_err("Pipeline start failed.\n");
+ return -EINVAL;
+ }
+ } else {
+ is_dbg(3, "Stream OFF\n");
+ /* Stop IS pipeline */
+ ret = fimc_is_pipeline_stop(sensor->pipeline);
+ if (ret < 0) {
+ is_err("Pipeline stop failed.\n");
+ return -EINVAL;
+ }
+
+ /* Close pipeline */
+ ret = fimc_is_pipeline_close(sensor->pipeline);
+ if (ret < 0) {
+ is_err("Pipeline close failed\n");
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
+static const struct v4l2_subdev_video_ops sensor_video_ops = {
+ .s_stream = sensor_s_stream,
+};
+
+static struct v4l2_subdev_ops sensor_subdev_ops = {
+ .core = &sensor_core_ops,
+ .pad = &sensor_pad_ops,
+ .video = &sensor_video_ops,
+};
+
+static int sensor_init(struct fimc_is_sensor *sensor)
+{
+ struct fimc_is_sensor_data *sensor_data;
+
+ sensor_data = sensor->sensor_data;
+ if (strcmp(sensor_data->name,
+ sensor_info[SENSOR_S5K4E5].sensor_name) == 0)
+ sensor->sensor_info = &sensor_info[SENSOR_S5K4E5];
+ else if (strcmp(sensor_data->name,
+ sensor_info[SENSOR_S5K6A3].sensor_name) == 0)
+ sensor->sensor_info = &sensor_info[SENSOR_S5K6A3];
+ else
+ sensor->sensor_info = NULL;
+
+ if (!sensor->sensor_info)
+ return -EINVAL;
+
+ sensor->sensor_info->csi_ch = sensor->sensor_info->i2c_ch =
+ (sensor_data->csi_id >> 2) & 0x1;
+ is_dbg(3, "Sensor csi channel : %d\n", sensor->sensor_info->csi_ch);
+
+ return 0;
+}
+
+int fimc_is_sensor_subdev_create(struct fimc_is_sensor *sensor,
+ struct fimc_is_sensor_data *sensor_data,
+ struct fimc_is_pipeline *pipeline)
+{
+ struct v4l2_subdev *sd = &sensor->subdev;
+ int ret;
+
+ is_err("\n");
+ if (!sensor_data->enabled) {
+ /* Sensor not present */
+ return -EINVAL;
+ }
+
+ sensor->sensor_data = sensor_data;
+ sensor->pipeline = pipeline;
+
+ v4l2_subdev_init(sd, &sensor_subdev_ops);
+ sensor->subdev.owner = THIS_MODULE;
+ if (strcmp(sensor_data->name,
+ sensor_info[SENSOR_S5K4E5].sensor_name) == 0)
+ strlcpy(sd->name, "fimc-is-sensor-4e5", sizeof(sd->name));
+ else if (strcmp(sensor_data->name,
+ sensor_info[SENSOR_S5K6A3].sensor_name) == 0)
+ strlcpy(sd->name, "fimc-is-sensor-6a3", sizeof(sd->name));
+ else
+ strlcpy(sd->name, "fimc-is-sensor-???", sizeof(sd->name));
+ sensor->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_init(&sd->entity, 1, &sensor->pad, 0);
+ if (ret < 0)
+ goto exit;
+
+ v4l2_set_subdevdata(sd, sensor);
+
+ /* Init sensor data */
+ ret = sensor_init(sensor);
+ if (ret < 0) {
+ is_err("Sensor init failed.\n");
+ goto exit;
+ }
+
+ return 0;
+exit:
+ return ret;
+}
+
+void fimc_is_sensor_subdev_destroy(struct fimc_is_sensor *sensor)
+{
+ media_entity_cleanup(&sensor->subdev.entity);
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.h b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
new file mode 100644
index 0000000..d147ff8
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
@@ -0,0 +1,170 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_SENSOR_H_
+#define FIMC_IS_SENSOR_H_
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-subdev.h>
+
+#include "fimc-is-pipeline.h"
+
+#define FIMC_IS_MAX_CAMIF_CLIENTS 2
+#define FIMC_IS_MAX_NAME_LEN 32
+#define FIMC_IS_MAX_GPIO_NUM 32
+#define UART_ISP_SEL 0
+#define UART_ISP_RATIO 1
+
+#define FIMC_IS_MAX_SENSORS 4
+
+#define SENSOR_4E5_WIDTH 2560
+#define SENSOR_4E5_HEIGHT 1920
+#define SENSOR_6A3_WIDTH 1392
+#define SENSOR_6A3_HEIGHT 1392
+
+enum sensor_id {
+ SENSOR_S5K3H2 = 1,
+ SENSOR_S5K6A3 = 2,
+ SENSOR_S5K4E5 = 3,
+ SENSOR_S5K3H7 = 4,
+ SENSOR_CUSTOM = 100,
+ SENSOR_END
+};
+
+enum sensor_channel {
+ SENSOR_CONTROL_I2C0 = 0,
+ SENSOR_CONTROL_I2C1 = 1
+};
+
+enum actuator_name {
+ ACTUATOR_NAME_AD5823 = 1,
+ ACTUATOR_NAME_DWXXXX = 2,
+ ACTUATOR_NAME_AK7343 = 3,
+ ACTUATOR_NAME_HYBRIDVCA = 4,
+ ACTUATOR_NAME_NOTHING = 100,
+ ACTUATOR_NAME_END
+};
+
+enum flash_drv_name {
+ FLADRV_NAME_KTD267 = 1,
+ FLADRV_NAME_NOTHING = 100,
+ FLADRV_NAME_END
+};
+
+enum from_name {
+ FROMDRV_NAME_W25Q80BW = 1,
+ FROMDRV_NAME_NOTHING
+};
+
+enum sensor_peri_type {
+ SE_I2C,
+ SE_SPI,
+ SE_GPIO,
+ SE_MPWM,
+ SE_ADC,
+ SE_NULL
+};
+
+struct i2c_type {
+ u32 channel;
+ u32 slave_address;
+ u32 speed;
+};
+
+struct spi_type {
+ u32 channel;
+};
+
+struct gpio_type {
+ u32 first_gpio_port_no;
+ u32 second_gpio_port_no;
+};
+
+union sensor_peri_format {
+ struct i2c_type i2c;
+ struct spi_type spi;
+ struct gpio_type gpio;
+};
+
+struct sensor_protocol {
+ unsigned int product_name;
+ enum sensor_peri_type peri_type;
+ union sensor_peri_format peri_setting;
+};
+
+struct fimc_is_sensor_ext {
+ struct sensor_protocol actuator_con;
+ struct sensor_protocol flash_con;
+ struct sensor_protocol from_con;
+
+ unsigned int mclk;
+ unsigned int mipi_lane_num;
+ unsigned int mipi_speed;
+ unsigned int fast_open_sensor;
+ unsigned int self_calibration_mode;
+};
+
+struct fimc_is_sensor_info {
+ unsigned int sensor_id;
+ char *sensor_name;
+ unsigned int pixel_width;
+ unsigned int pixel_height;
+ unsigned int active_width;
+ unsigned int active_height;
+ unsigned int max_framerate;
+ unsigned int csi_ch;
+ unsigned int flite_ch;
+ unsigned int i2c_ch;
+ struct fimc_is_sensor_ext ext;
+ char *setfile_name;
+};
+
+enum sensor_clks {
+ SCLK_BAYER,
+ SCLK_CAM0,
+ SCLK_CAM1,
+ SCLK_MAX_NUM,
+};
+
+struct sensor_pix_format {
+ enum v4l2_mbus_pixelcode code;
+};
+
+/**
+ * struct fimc_is_sensor - fimc-is sensor context
+ * @pad: media pad
+ * @subdev: sensor subdev
+ * @clock: sensor clocks array
+ * @pipeline: is pipeline context pointer
+ * @sensor_info: fimc-is sensor config information
+ * @sensor_data: platform data received for sensor
+ */
+struct fimc_is_sensor {
+ struct media_pad pad;
+ struct v4l2_subdev subdev;
+ struct clk *clock[SCLK_MAX_NUM];
+
+ struct fimc_is_pipeline *pipeline;
+ struct fimc_is_sensor_info *sensor_info;
+ struct fimc_is_sensor_data *sensor_data;
+};
+
+int fimc_is_sensor_subdev_create(struct fimc_is_sensor *sensor,
+ struct fimc_is_sensor_data *sensor_data,
+ struct fimc_is_pipeline *pipeline);
+void fimc_is_sensor_subdev_destroy(struct fimc_is_sensor *sensor);
+
+#endif /* FIMC_IS_SENSOR_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [RFC 06/12] exynos-fimc-is: Adds the sensor subdev
2013-03-08 14:59 ` [RFC 06/12] exynos-fimc-is: Adds the sensor subdev Arun Kumar K
@ 2013-03-23 14:48 ` Sylwester Nawrocki
0 siblings, 0 replies; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-23 14:48 UTC (permalink / raw)
To: Arun Kumar K
Cc: linux-media, linux-samsung-soc, devicetree-discuss, s.nawrocki,
kgene.kim, kilyeon.im, arunkk.samsung
On 03/08/2013 03:59 PM, Arun Kumar K wrote:
> FIMC-IS uses certain sensors which are exclusively controlled
> from the IS firmware. This patch adds the sensor subdev for the
> fimc-is sensors.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
> drivers/media/platform/exynos5-is/fimc-is-sensor.c | 337 ++++++++++++++++++++
> drivers/media/platform/exynos5-is/fimc-is-sensor.h | 170 ++++++++++
> 2 files changed, 507 insertions(+)
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
> new file mode 100644
> index 0000000..c031493
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
> @@ -0,0 +1,337 @@
> +/*
> + * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Arun Kumar K<arun.kk@samsung.com>
> + * Kil-yeon Lim<kilyeon.im@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include<linux/gpio.h>
> +#include "fimc-is-sensor.h"
> +#include "fimc-is.h"
> +
> +static char *sensor_clock_name[] = {
> + [SCLK_BAYER] = "sclk_bayer",
> + [SCLK_CAM0] = "sclk_cam0",
Aren't there any dependencies on other IP state for this clock ?
For example up to Exynos4412 "fimc" clocks needs to be enabled
to actually enable SCLK_CAM clocks through "sclk_cam0" and the
CAM power domain needs to be enabled.
> +/* Sensor supported formats */
> +static struct v4l2_mbus_framefmt sensor_formats[FIMC_IS_MAX_SENSORS] = {
> + [SENSOR_S5K4E5] = {
> + .width = SENSOR_4E5_WIDTH + 16,
> + .height = SENSOR_4E5_HEIGHT + 10,
> + .code = V4L2_MBUS_FMT_SGRBG10_1X10,
> + .field = V4L2_FIELD_NONE,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + },
> + [SENSOR_S5K6A3] = {
> + .width = SENSOR_6A3_WIDTH + 16,
> + .height = SENSOR_6A3_HEIGHT + 10,
> + .code = V4L2_MBUS_FMT_SGRBG10_1X10,
> + .field = V4L2_FIELD_NONE,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + },
> +};
> +
> +static struct fimc_is_sensor *sd_to_fimc_is_sensor(struct v4l2_subdev *sd)
> +{
> + return container_of(sd, struct fimc_is_sensor, subdev);
> +}
> +
> +static void sensor_clk_put(struct fimc_is_sensor *sensor)
> +{
> + int i;
> +
> + for (i = 0; i< SCLK_MAX_NUM; i++) {
> + if (IS_ERR_OR_NULL(sensor->clock[i]))
Please try to eliminate this IS_ERR_OR_NULL() usage, e.g. by filling
clock[] array with ERR_PTR(-EINVAL) at the very beginning of the driver's
initialization process.
> + continue;
> + clk_unprepare(sensor->clock[i]);
> + clk_put(sensor->clock[i]);
> + sensor->clock[i] = NULL;
sensor->clock[i] = ERR_PTR(-EINVAL);
> + }
> +}
> +
> +static int sensor_clk_init(struct fimc_is_sensor *sensor)
> +{
> + int i, ret;
> +
> + /* Get CAM clocks */
> + for (i = 0; i< SCLK_MAX_NUM; i++) {
> + sensor->clock[i] = clk_get(NULL, sensor_clock_name[i]);
> + if (IS_ERR(sensor->clock[i]))
> + goto err;
> + ret = clk_prepare(sensor->clock[i]);
> + if (ret< 0) {
> + clk_put(sensor->clock[i]);
> + sensor->clock[i] = NULL;
sensor->clock[i] = ERR_PTR(-EINVAL);
> + goto err;
> + }
> + }
> +
> + /* Set clock rates */
> + ret = clk_set_rate(sensor->clock[SCLK_CAM0], 24 * 1000000);
> + ret |= clk_set_rate(sensor->clock[SCLK_BAYER], 24 * 1000000);
> + if (ret) {
> + is_err("Failed to set cam clock rates\n");
> + goto err;
> + }
> + return 0;
> +err:
> + sensor_clk_put(sensor);
> + is_err("Failed to init sensor clock\n");
> + return -ENXIO;
> +}
> +
> +static int sensor_enum_mbus_code(struct v4l2_subdev *sd,
> + struct v4l2_subdev_fh *fh,
> + struct v4l2_subdev_mbus_code_enum *code)
> +{
> + struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
> + struct fimc_is_sensor_info *sinfo = sensor->sensor_info;
> +
> + if (!code)
> + return -EINVAL;
> +
> + code->code = sensor_formats[sinfo->sensor_id].code;
> + return 0;
> +}
> +
> +static int sensor_set_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_fh *fh,
> + struct v4l2_subdev_format *fmt)
> +{
> + struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
> + struct fimc_is_sensor_info *sinfo = sensor->sensor_info;
> + struct v4l2_mbus_framefmt *sfmt =&fmt->format;
> +
> + if ((sfmt->width != sensor_formats[sinfo->sensor_id].width) ||
> + (sfmt->height != sensor_formats[sinfo->sensor_id].height) ||
> + (sfmt->code != sensor_formats[sinfo->sensor_id].code))
> + return -EINVAL;
No, the driver should not return any errors here. Instead it should
adjust passed frame format to its capabilities. So it should be more
something like:
*sfmt = sensor_formats[sinfo->sensor_id];
But even now it is not optimal, it would be useful to be able to
set various resolutions at the sensor subdev, within supported range.
Anyway I'm fine with have it fixed temporarily. It all depends
on the firmware though, what sort of configuration is supported there.
> + return 0;
> +}
> +
> +static int sensor_get_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_fh *fh,
> + struct v4l2_subdev_format *fmt)
> +{
> + struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
> + struct fimc_is_sensor_info *sinfo = sensor->sensor_info;
> +
> + fmt->format = sensor_formats[sinfo->sensor_id];
> + return 0;
> +}
> +
> +static struct v4l2_subdev_pad_ops sensor_pad_ops = {
> + .enum_mbus_code = sensor_enum_mbus_code,
> + .get_fmt = sensor_get_fmt,
> + .set_fmt = sensor_set_fmt,
> +};
> +
> +static int sensor_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
> +{
> + return 0;
You should fill the TRY format data structure here, which is stored in fh.
> +}
> +
> +static const struct v4l2_subdev_internal_ops sensor_sd_internal_ops = {
> + .open = sensor_open,
> +};
> +
> +static int sensor_s_power(struct v4l2_subdev *sd, int on)
> +{
> + struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
> + struct fimc_is_sensor_data *sdata = sensor->sensor_data;
> +
> + if (on) {
> + /* Power on sensor */
> + sensor_clk_init(sensor);
Clocks should be initialized once. And here we only enable/disable them.
> + gpio_request(sdata->gpios[0], "fimc_is_sensor");
> + gpio_direction_output(sdata->gpios[0], 1);
> + gpio_free(sdata->gpios[0]);
Similar mistake with the GPIO. Why don't you request GPIO in probe/remove
functions ?
And why gpio_direction_output() is used to set state of an GPIO output ?
Are there some political reasons for which you choose to not use
gpio_set_value() ?
> + } else {
> + /* Power off sensor */
> + gpio_request(sdata->gpios[0], "fimc_is_sensor");
> + gpio_direction_output(sdata->gpios[0], 0);
> + gpio_free(sdata->gpios[0]);
> + sensor_clk_put(sensor);
> + }
> + return 0;
> +}
> +
> +static struct v4l2_subdev_core_ops sensor_core_ops = {
> + .s_power = sensor_s_power,
> +};
> +
> +static int sensor_s_stream(struct v4l2_subdev *sd, int enable)
> +{
> + struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
> + int ret;
> +
> + if (enable) {
> + is_dbg(3, "Stream ON\n");
> + /* Open pipeline */
> + ret = fimc_is_pipeline_open(sensor->pipeline, sensor);
> + if (ret< 0) {
> + is_err("Pipeline already opened.\n");
> + return -EBUSY;
> + }
> +
> + /* Start IS pipeline */
> + ret = fimc_is_pipeline_start(sensor->pipeline);
> + if (ret< 0) {
> + is_err("Pipeline start failed.\n");
> + return -EINVAL;
> + }
Hmm, because of those 2 pipelines dependent on each other :
sensor -> mipi-csis -> fimc-lite -> memory
memory -> is-isp -> scalerx -> memory
You need to initiate streaming from sensor driver level ? Normally this
is managed by /dev/video driver. I guess, it wouldn't work in your case ?
> + } else {
> + is_dbg(3, "Stream OFF\n");
> + /* Stop IS pipeline */
> + ret = fimc_is_pipeline_stop(sensor->pipeline);
> + if (ret< 0) {
> + is_err("Pipeline stop failed.\n");
> + return -EINVAL;
> + }
> +
> + /* Close pipeline */
> + ret = fimc_is_pipeline_close(sensor->pipeline);
> + if (ret< 0) {
> + is_err("Pipeline close failed\n");
> + return -EBUSY;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static const struct v4l2_subdev_video_ops sensor_video_ops = {
> + .s_stream = sensor_s_stream,
> +};
> +
> +static struct v4l2_subdev_ops sensor_subdev_ops = {
> + .core =&sensor_core_ops,
> + .pad =&sensor_pad_ops,
> + .video =&sensor_video_ops,
> +};
> +
> +static int sensor_init(struct fimc_is_sensor *sensor)
> +{
> + struct fimc_is_sensor_data *sensor_data;
> +
> + sensor_data = sensor->sensor_data;
> + if (strcmp(sensor_data->name,
> + sensor_info[SENSOR_S5K4E5].sensor_name) == 0)
> + sensor->sensor_info =&sensor_info[SENSOR_S5K4E5];
> + else if (strcmp(sensor_data->name,
> + sensor_info[SENSOR_S5K6A3].sensor_name) == 0)
> + sensor->sensor_info =&sensor_info[SENSOR_S5K6A3];
> + else
> + sensor->sensor_info = NULL;
I think such matching would better done through 'compatible' property.
> + if (!sensor->sensor_info)
> + return -EINVAL;
> +
> + sensor->sensor_info->csi_ch = sensor->sensor_info->i2c_ch =
> + (sensor_data->csi_id>> 2)& 0x1;
> + is_dbg(3, "Sensor csi channel : %d\n", sensor->sensor_info->csi_ch);
> +
> + return 0;
> +}
> +
> +int fimc_is_sensor_subdev_create(struct fimc_is_sensor *sensor,
> + struct fimc_is_sensor_data *sensor_data,
> + struct fimc_is_pipeline *pipeline)
> +{
> + struct v4l2_subdev *sd =&sensor->subdev;
> + int ret;
> +
> + is_err("\n");
Might be some debugging leftover. I would also suggest to avoid
custom driver-specific debug macros.
> + if (!sensor_data->enabled) {
> + /* Sensor not present */
> + return -EINVAL;
> + }
> +
> + sensor->sensor_data = sensor_data;
> + sensor->pipeline = pipeline;
> +
> + v4l2_subdev_init(sd,&sensor_subdev_ops);
> + sensor->subdev.owner = THIS_MODULE;
> + if (strcmp(sensor_data->name,
> + sensor_info[SENSOR_S5K4E5].sensor_name) == 0)
> + strlcpy(sd->name, "fimc-is-sensor-4e5", sizeof(sd->name));
> + else if (strcmp(sensor_data->name,
> + sensor_info[SENSOR_S5K6A3].sensor_name) == 0)
> + strlcpy(sd->name, "fimc-is-sensor-6a3", sizeof(sd->name));
> + else
> + strlcpy(sd->name, "fimc-is-sensor-???", sizeof(sd->name));
> + sensor->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> + sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
> + ret = media_entity_init(&sd->entity, 1,&sensor->pad, 0);
> + if (ret< 0)
> + goto exit;
> +
> + v4l2_set_subdevdata(sd, sensor);
> +
> + /* Init sensor data */
> + ret = sensor_init(sensor);
> + if (ret< 0) {
> + is_err("Sensor init failed.\n");
> + goto exit;
Just drop this goto...
> + }
> +
> + return 0;
return ret;
> +exit:
> + return ret;
And remove these 2 lines.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [RFC 07/12] exynos-fimc-is: Adds isp subdev
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
` (5 preceding siblings ...)
2013-03-08 14:59 ` [RFC 06/12] exynos-fimc-is: Adds the sensor subdev Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-23 18:38 ` Sylwester Nawrocki
2013-03-08 14:59 ` [RFC 08/12] exynos-fimc-is: Adds scaler subdev Arun Kumar K
` (4 subsequent siblings)
11 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
fimc-is driver takes video data input from the ISP video node
which is added in this patch. This node accepts Bayer input
buffers which is given from the IS sensors.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
drivers/media/platform/exynos5-is/fimc-is-isp.c | 546 +++++++++++++++++++++++
drivers/media/platform/exynos5-is/fimc-is-isp.h | 88 ++++
2 files changed, 634 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c b/drivers/media/platform/exynos5-is/fimc-is-isp.c
new file mode 100644
index 0000000..e68e936
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
@@ -0,0 +1,546 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "fimc-is.h"
+
+static struct fimc_is_fmt formats[] = {
+ {
+ .name = "Bayer GR-BG 8bits",
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .depth = {8},
+ .num_planes = 1,
+ },
+ {
+ .name = "Bayer GR-BG 10bits",
+ .fourcc = V4L2_PIX_FMT_SGRBG10,
+ .depth = {10},
+ .num_planes = 1,
+ },
+ {
+ .name = "Bayer GR-BG 12bits",
+ .fourcc = V4L2_PIX_FMT_SGRBG12,
+ .depth = {12},
+ .num_planes = 1,
+ },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i < NUM_FORMATS; i++) {
+ if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+ return &formats[i];
+ }
+ return NULL;
+}
+
+static int isp_video_output_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+ /* Set state to RUNNING */
+ set_bit(STATE_RUNNING, &isp->output_state);
+ return 0;
+}
+
+static int isp_video_output_stop_streaming(struct vb2_queue *vq)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+ clear_bit(STATE_RUNNING, &isp->output_state);
+ return 0;
+}
+
+static int isp_video_output_queue_setup(struct vb2_queue *vq,
+ const struct v4l2_format *pfmt,
+ unsigned int *num_buffers, unsigned int *num_planes,
+ unsigned int sizes[], void *allocators[])
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_fmt *fmt = isp->fmt;
+ unsigned int wh, i;
+
+ if (!fmt)
+ return -EINVAL;
+
+ *num_planes = fmt->num_planes;
+ wh = isp->width * isp->height;
+
+ for (i = 0; i < *num_planes; i++) {
+ allocators[i] = isp->alloc_ctx;
+ sizes[i] = (wh * fmt->depth[i]) / 8;
+ }
+ return 0;
+}
+
+static int isp_video_output_buffer_init(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+
+ buf = &isp->output_bufs[vb->v4l2_buf.index];
+ /* Initialize buffer */
+ buf->vb = vb;
+ buf->paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+ isp->out_buf_cnt++;
+ return 0;
+}
+
+static void isp_video_output_buffer_queue(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+
+ buf = &isp->output_bufs[vb->v4l2_buf.index];
+
+ fimc_is_pipeline_buf_lock(isp->pipeline);
+ fimc_is_isp_wait_queue_add(isp, buf);
+ fimc_is_pipeline_buf_unlock(isp->pipeline);
+
+ /* Call shot command */
+ fimc_is_pipeline_shot(isp->pipeline);
+}
+
+static void isp_lock(struct vb2_queue *vq)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ mutex_lock(&isp->video_lock);
+}
+
+static void isp_unlock(struct vb2_queue *vq)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ mutex_unlock(&isp->video_lock);
+}
+
+static const struct vb2_ops isp_video_output_qops = {
+ .queue_setup = isp_video_output_queue_setup,
+ .buf_init = isp_video_output_buffer_init,
+ .buf_queue = isp_video_output_buffer_queue,
+ .wait_prepare = isp_unlock,
+ .wait_finish = isp_lock,
+ .start_streaming = isp_video_output_start_streaming,
+ .stop_streaming = isp_video_output_stop_streaming,
+};
+
+static int isp_video_output_open(struct file *file)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ int ret = 0;
+
+ /* Check if opened before */
+ if (isp->refcount >= FIMC_IS_MAX_INSTANCES) {
+ is_err("All instances are in use.\n");
+ return -EBUSY;
+ }
+
+ INIT_LIST_HEAD(&isp->wait_queue);
+ isp->wait_queue_cnt = 0;
+ INIT_LIST_HEAD(&isp->run_queue);
+ isp->run_queue_cnt = 0;
+
+ isp->refcount++;
+ return ret;
+}
+
+static int isp_video_output_close(struct file *file)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ int ret = 0;
+
+ isp->refcount--;
+ vb2_queue_release(&isp->vbq);
+ isp->output_state = 0;
+ return ret;
+}
+
+static unsigned int isp_video_output_poll(struct file *file,
+ struct poll_table_struct *wait)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ int ret;
+
+ if (mutex_lock_interruptible(&isp->video_lock))
+ return POLL_ERR;
+
+ ret = vb2_poll(&isp->vbq, file, wait);
+ mutex_unlock(&isp->video_lock);
+
+ return ret;
+}
+
+static int isp_video_output_mmap(struct file *file, struct vm_area_struct *vma)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ int ret;
+
+ if (mutex_lock_interruptible(&isp->video_lock))
+ return -ERESTARTSYS;
+
+ ret = vb2_mmap(&isp->vbq, vma);
+ mutex_unlock(&isp->video_lock);
+
+ return ret;
+}
+
+static const struct v4l2_file_operations isp_video_output_fops = {
+ .owner = THIS_MODULE,
+ .open = isp_video_output_open,
+ .release = isp_video_output_close,
+ .poll = isp_video_output_poll,
+ .unlocked_ioctl = video_ioctl2,
+ .mmap = isp_video_output_mmap,
+};
+
+/*
+ * Video node ioctl operations
+ */
+static int isp_querycap_output(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ strlcpy(cap->driver, "fimc-is-isp", sizeof(cap->driver));
+ cap->bus_info[0] = 0;
+ cap->card[0] = 0;
+ cap->capabilities = V4L2_CAP_STREAMING;
+ return 0;
+}
+
+static int isp_enum_fmt_mplane(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ const struct fimc_is_fmt *fmt;
+
+ if (f->index >= NUM_FORMATS)
+ return -EINVAL;
+
+ fmt = &formats[f->index];
+ strlcpy(f->description, fmt->name, sizeof(f->description));
+ f->pixelformat = fmt->fourcc;
+
+ return 0;
+}
+
+static int isp_g_fmt_mplane(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
+ struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
+ const struct fimc_is_fmt *fmt = isp->fmt;
+
+ plane_fmt->bytesperline = (isp->width * fmt->depth[0]) / 8;
+ plane_fmt->sizeimage = plane_fmt->bytesperline * isp->height;
+
+ pixm->num_planes = fmt->num_planes;
+ pixm->pixelformat = fmt->fourcc;
+ pixm->width = isp->width;
+ pixm->height = isp->height;
+ pixm->field = V4L2_FIELD_NONE;
+ pixm->colorspace = V4L2_COLORSPACE_JPEG;
+
+ return 0;
+}
+
+static int isp_try_fmt_mplane(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct fimc_is_fmt *fmt;
+
+ if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+ return -EINVAL;
+
+ fmt = find_format(f);
+ if (!fmt) {
+ is_err("Format not supported.\n");
+ return -EINVAL;
+ }
+
+ if (fmt->num_planes != f->fmt.pix_mp.num_planes) {
+ is_err("Number of planes mismatch\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int isp_s_fmt_mplane(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ struct fimc_is_pipeline *p = isp->pipeline;
+ struct fimc_is_fmt *fmt;
+ unsigned int sensor_width, sensor_height;
+ int ret;
+
+ ret = isp_try_fmt_mplane(file, priv, f);
+ if (ret)
+ return ret;
+
+ /* Get format type */
+ fmt = find_format(f);
+ if (!fmt) {
+ is_err("Format not supported.\n");
+ return -EINVAL;
+ }
+
+ /* Check if same as sensor width & height */
+ sensor_width = p->sensor->sensor_info->pixel_width;
+ sensor_height = p->sensor->sensor_info->pixel_height;
+ if ((sensor_width != f->fmt.pix_mp.width) ||
+ (sensor_height != f->fmt.pix_mp.height)) {
+ is_err("ISP resolution should be same as sensor\n");
+ return -EINVAL;
+ }
+
+ isp->fmt = fmt;
+ isp->width = f->fmt.pix_mp.width;
+ isp->height = f->fmt.pix_mp.height;
+ isp->size_image = f->fmt.pix_mp.plane_fmt[0].sizeimage;
+ set_bit(STATE_INIT, &isp->output_state);
+ return 0;
+}
+
+static int isp_streamon(struct file *file, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ int ret;
+
+ ret = vb2_streamon(&isp->vbq, type);
+ return 0;
+}
+
+static int isp_streamoff(struct file *file, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ int ret;
+
+ ret = vb2_streamoff(&isp->vbq, type);
+ return 0;
+}
+
+static int isp_reqbufs(struct file *file, void *priv,
+ struct v4l2_requestbuffers *reqbufs)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ int ret;
+
+ if (!isp->fmt) {
+ is_err("Set format not done\n");
+ return -EINVAL;
+ }
+
+ /* Check whether buffers are already allocated */
+ if (test_bit(STATE_BUFS_ALLOCATED, &isp->output_state)) {
+ is_err("Buffers already allocated\n");
+ return -EINVAL;
+ }
+
+ ret = vb2_reqbufs(&isp->vbq, reqbufs);
+ if (ret) {
+ is_err("vb2 req buffers failed\n");
+ return ret;
+ }
+
+ isp->num_buffers = reqbufs->count;
+ isp->out_buf_cnt = 0;
+ set_bit(STATE_BUFS_ALLOCATED, &isp->output_state);
+ return 0;
+}
+
+static int isp_querybuf(struct file *file, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ return vb2_querybuf(&isp->vbq, buf);
+}
+
+static int isp_qbuf(struct file *file, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ return vb2_qbuf(&isp->vbq, buf);
+}
+
+static int isp_dqbuf(struct file *file, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct fimc_is_isp *isp = video_drvdata(file);
+ return vb2_dqbuf(&isp->vbq, buf,
+ file->f_flags & O_NONBLOCK);
+}
+
+static const struct v4l2_ioctl_ops isp_video_output_ioctl_ops = {
+ .vidioc_querycap = isp_querycap_output,
+ .vidioc_enum_fmt_vid_out_mplane = isp_enum_fmt_mplane,
+ .vidioc_try_fmt_vid_out_mplane = isp_try_fmt_mplane,
+ .vidioc_s_fmt_vid_out_mplane = isp_s_fmt_mplane,
+ .vidioc_g_fmt_vid_out_mplane = isp_g_fmt_mplane,
+ .vidioc_reqbufs = isp_reqbufs,
+ .vidioc_querybuf = isp_querybuf,
+ .vidioc_qbuf = isp_qbuf,
+ .vidioc_dqbuf = isp_dqbuf,
+ .vidioc_streamon = isp_streamon,
+ .vidioc_streamoff = isp_streamoff,
+};
+
+static int isp_subdev_s_stream(struct v4l2_subdev *sd, int on)
+{
+ /* Nothing to do.*/
+ return 0;
+}
+
+static int isp_subdev_s_power(struct v4l2_subdev *sd, int on)
+{
+ /* Nothing to do here as everything is turned on from sensor */
+ return 0;
+}
+
+static int isp_subdev_registered(struct v4l2_subdev *sd)
+{
+ struct fimc_is_isp *isp = v4l2_get_subdevdata(sd);
+ struct vb2_queue *q = &isp->vbq;
+ struct video_device *vfd = &isp->vfd;
+ int ret;
+
+ mutex_init(&isp->video_lock);
+
+ memset(vfd, 0, sizeof(*vfd));
+ snprintf(vfd->name, sizeof(vfd->name), "fimc-is-isp.output");
+
+ vfd->fops = &isp_video_output_fops;
+ vfd->ioctl_ops = &isp_video_output_ioctl_ops;
+ vfd->v4l2_dev = sd->v4l2_dev;
+ vfd->minor = -1;
+ vfd->release = video_device_release_empty;
+ vfd->lock = &isp->video_lock;
+ vfd->vfl_dir = VFL_DIR_TX;
+
+ memset(q, 0, sizeof(*q));
+ q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+ q->io_modes = VB2_MMAP | VB2_DMABUF;
+ q->ops = &isp_video_output_qops;
+ q->mem_ops = &vb2_dma_contig_memops;
+ q->drv_priv = isp;
+
+ ret = vb2_queue_init(q);
+ if (ret < 0)
+ return ret;
+
+ isp->vd_pad.flags = MEDIA_PAD_FL_SINK;
+ ret = media_entity_init(&vfd->entity, 1, &isp->vd_pad, 0);
+ if (ret < 0)
+ return ret;
+
+ video_set_drvdata(vfd, isp);
+
+ ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
+ if (ret < 0) {
+ media_entity_cleanup(&vfd->entity);
+ return ret;
+ }
+
+ v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
+ vfd->name, video_device_node_name(vfd));
+ return 0;
+}
+
+static void isp_subdev_unregistered(struct v4l2_subdev *sd)
+{
+ struct fimc_is_isp *isp = v4l2_get_subdevdata(sd);
+
+ if (isp && video_is_registered(&isp->vfd))
+ video_unregister_device(&isp->vfd);
+}
+
+static const struct v4l2_subdev_internal_ops isp_subdev_internal_ops = {
+ .registered = isp_subdev_registered,
+ .unregistered = isp_subdev_unregistered,
+};
+
+static const struct v4l2_subdev_video_ops isp_subdev_video_ops = {
+ .s_stream = isp_subdev_s_stream,
+};
+
+static const struct v4l2_subdev_core_ops isp_core_ops = {
+ .s_power = isp_subdev_s_power,
+};
+
+static struct v4l2_subdev_ops isp_subdev_ops = {
+ .core = &isp_core_ops,
+ .video = &isp_subdev_video_ops,
+};
+
+static int isp_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ return 0;
+}
+
+static const struct v4l2_ctrl_ops isp_ctrl_ops = {
+ .s_ctrl = isp_s_ctrl,
+};
+
+int fimc_is_isp_subdev_create(struct fimc_is_isp *isp,
+ struct vb2_alloc_ctx *alloc_ctx,
+ struct fimc_is_pipeline *pipeline)
+{
+ struct v4l2_ctrl_handler *handler = &isp->ctrl_handler;
+ struct v4l2_subdev *sd = &isp->subdev;
+ int ret;
+
+ /* Init context vars */
+ isp->alloc_ctx = alloc_ctx;
+ isp->pipeline = pipeline;
+ isp->refcount = 0;
+ isp->fmt = &formats[1];
+
+ v4l2_subdev_init(sd, &isp_subdev_ops);
+ sd->owner = THIS_MODULE;
+ sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+ snprintf(sd->name, sizeof(sd->name), "fimc-is-isp");
+
+ isp->subdev_pads[ISP_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+ isp->subdev_pads[ISP_SD_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_init(&sd->entity, ISP_SD_PADS_NUM,
+ isp->subdev_pads, 0);
+ if (ret < 0)
+ return ret;
+
+ v4l2_ctrl_handler_init(handler, 1);
+ if (handler->error)
+ return handler->error;
+
+ sd->ctrl_handler = handler;
+ sd->internal_ops = &isp_subdev_internal_ops;
+ v4l2_set_subdevdata(sd, isp);
+
+ return 0;
+}
+
+void fimc_is_isp_subdev_destroy(struct fimc_is_isp *isp)
+{
+ struct v4l2_subdev *sd = &isp->subdev;
+
+ v4l2_device_unregister_subdev(sd);
+ media_entity_cleanup(&sd->entity);
+ v4l2_ctrl_handler_free(&isp->ctrl_handler);
+ v4l2_set_subdevdata(sd, NULL);
+}
+
diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.h b/drivers/media/platform/exynos5-is/fimc-is-isp.h
new file mode 100644
index 0000000..be6289f
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.h
@@ -0,0 +1,88 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_ISP_H_
+#define FIMC_IS_ISP_H_
+
+#include "fimc-is-core.h"
+#include "fimc-is-pipeline.h"
+
+#define FIMC_IS_ISP_REQ_BUFS_MIN 2
+
+#define ISP_SD_PAD_SINK 0
+#define ISP_SD_PAD_SRC 1
+#define ISP_SD_PADS_NUM 2
+
+#define ISP_MAX_BUFS 2
+
+/**
+ * struct fimc_is_isp - ISP context
+ * @vfd: video device node
+ * @fh: v4l2 file handle
+ * @alloc_ctx: videobuf2 memory allocator context
+ * @subdev: fimc-is-isp subdev
+ * @vd_pad: media pad for the output video node
+ * @subdev_pads: the subdev media pads
+ * @ctrl_handler: v4l2 control handler
+ * @video_lock: video lock mutex
+ * @refcount: keeps track of number of instances opened
+ * @pipeline: pipeline instance for this isp context
+ * @vbq: vb2 buffers queue for ISP output video node
+ * @wait_queue: list holding buffers waiting to be queued to HW
+ * @wait_queue_cnt: wait queue number of buffers
+ * @run_queue: list holding buffers queued to HW
+ * @run_queue_cnt: run queue number of buffers
+ * @output_bufs: isp output buffers array
+ * @out_buf_cnt: number of output buffers in use
+ * @fmt: output plane format for isp
+ * @width: user configured input width
+ * @height: user configured input height
+ * @num_buffers: number of output plane buffers in use
+ * @size_image: image size in bytes
+ * @output_state: state of the output video node operations
+ */
+struct fimc_is_isp {
+ struct video_device vfd;
+ struct v4l2_fh fh;
+ struct vb2_alloc_ctx *alloc_ctx;
+ struct v4l2_subdev subdev;
+ struct media_pad vd_pad;
+ struct media_pad subdev_pads[ISP_SD_PADS_NUM];
+ struct v4l2_ctrl_handler ctrl_handler;
+
+ struct mutex video_lock;
+
+ unsigned int refcount;
+
+ struct fimc_is_pipeline *pipeline;
+
+ struct vb2_queue vbq;
+ struct list_head wait_queue;
+ unsigned int wait_queue_cnt;
+ struct list_head run_queue;
+ unsigned int run_queue_cnt;
+
+ struct fimc_is_buf output_bufs[ISP_MAX_BUFS];
+ unsigned int out_buf_cnt;
+
+ struct fimc_is_fmt *fmt;
+ unsigned int width;
+ unsigned int height;
+ unsigned int num_buffers;
+ unsigned int size_image;
+ unsigned long output_state;
+};
+
+int fimc_is_isp_subdev_create(struct fimc_is_isp *isp,
+ struct vb2_alloc_ctx *alloc_ctx,
+ struct fimc_is_pipeline *pipeline);
+void fimc_is_isp_subdev_destroy(struct fimc_is_isp *isp);
+
+#endif /* FIMC_IS_ISP_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [RFC 07/12] exynos-fimc-is: Adds isp subdev
2013-03-08 14:59 ` [RFC 07/12] exynos-fimc-is: Adds isp subdev Arun Kumar K
@ 2013-03-23 18:38 ` Sylwester Nawrocki
0 siblings, 0 replies; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-23 18:38 UTC (permalink / raw)
To: Arun Kumar K
Cc: linux-media, linux-samsung-soc, devicetree-discuss, s.nawrocki,
kgene.kim, kilyeon.im, arunkk.samsung
On 03/08/2013 03:59 PM, Arun Kumar K wrote:
> fimc-is driver takes video data input from the ISP video node
> which is added in this patch. This node accepts Bayer input
> buffers which is given from the IS sensors.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
> drivers/media/platform/exynos5-is/fimc-is-isp.c | 546 +++++++++++++++++++++++
> drivers/media/platform/exynos5-is/fimc-is-isp.h | 88 ++++
> 2 files changed, 634 insertions(+)
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c b/drivers/media/platform/exynos5-is/fimc-is-isp.c
> new file mode 100644
> index 0000000..e68e936
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
> @@ -0,0 +1,546 @@
> +/*
> + * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include<media/v4l2-ioctl.h>
> +#include<media/videobuf2-dma-contig.h>
> +
> +#include "fimc-is.h"
> +
> +static struct fimc_is_fmt formats[] = {
static const ?
> + {
> + .name = "Bayer GR-BG 8bits",
> + .fourcc = V4L2_PIX_FMT_SGRBG8,
> + .depth = {8},
nit:
> + .num_planes = 1,
> + },
> + {
> + .name = "Bayer GR-BG 10bits",
> + .fourcc = V4L2_PIX_FMT_SGRBG10,
> + .depth = {10},
> + .num_planes = 1,
> + },
> + {
> + .name = "Bayer GR-BG 12bits",
> + .fourcc = V4L2_PIX_FMT_SGRBG12,
> + .depth = {12},
> + .num_planes = 1,
> + },
> +};
> +#define NUM_FORMATS ARRAY_SIZE(formats)
[...]
> +static int isp_video_output_open(struct file *file)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + int ret = 0;
> +
> + /* Check if opened before */
> + if (isp->refcount>= FIMC_IS_MAX_INSTANCES) {
> + is_err("All instances are in use.\n");
> + return -EBUSY;
> + }
> +
> + INIT_LIST_HEAD(&isp->wait_queue);
> + isp->wait_queue_cnt = 0;
> + INIT_LIST_HEAD(&isp->run_queue);
> + isp->run_queue_cnt = 0;
> +
> + isp->refcount++;
> + return ret;
> +}
> +
> +static int isp_video_output_close(struct file *file)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + int ret = 0;
> +
> + isp->refcount--;
> + vb2_queue_release(&isp->vbq);
> + isp->output_state = 0;
> + return ret;
> +}
> +
> +static unsigned int isp_video_output_poll(struct file *file,
> + struct poll_table_struct *wait)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + int ret;
> +
> + if (mutex_lock_interruptible(&isp->video_lock))
> + return POLL_ERR;
> +
> + ret = vb2_poll(&isp->vbq, file, wait);
> + mutex_unlock(&isp->video_lock);
> +
> + return ret;
> +}
> +
> +static int isp_video_output_mmap(struct file *file, struct vm_area_struct *vma)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + int ret;
> +
> + if (mutex_lock_interruptible(&isp->video_lock))
> + return -ERESTARTSYS;
> +
> + ret = vb2_mmap(&isp->vbq, vma);
> + mutex_unlock(&isp->video_lock);
> +
> + return ret;
> +}
> +
> +static const struct v4l2_file_operations isp_video_output_fops = {
> + .owner = THIS_MODULE,
> + .open = isp_video_output_open,
> + .release = isp_video_output_close,
> + .poll = isp_video_output_poll,
> + .unlocked_ioctl = video_ioctl2,
> + .mmap = isp_video_output_mmap,
I suggest to use vb2_fop_poll/mmap/release, v4l2_fh_open where possible.
> +};
> +
> +/*
> + * Video node ioctl operations
> + */
> +static int isp_querycap_output(struct file *file, void *priv,
> + struct v4l2_capability *cap)
> +{
> + strlcpy(cap->driver, "fimc-is-isp", sizeof(cap->driver));
> + cap->bus_info[0] = 0;
bus_info must not be empty, it could be fimc-is platform device name.
> + cap->card[0] = 0;
> + cap->capabilities = V4L2_CAP_STREAMING;
Please set cap->device_caps as well.
> + return 0;
> +}
> +static int isp_try_fmt_mplane(struct file *file, void *fh,
> + struct v4l2_format *f)
> +{
> + struct fimc_is_fmt *fmt;
> +
> + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
> + return -EINVAL;
This check is not needed.
> + fmt = find_format(f);
> + if (!fmt) {
> + is_err("Format not supported.\n");
> + return -EINVAL;
Instead some default format should be picked, and no error returned here.
> + }
> +
> + if (fmt->num_planes != f->fmt.pix_mp.num_planes) {
Again, the kernel is supposed to adjust and fill in the format data
structure with valid values. So you should just do
f->fmt.pix_mp.num_planes = fmt->num_planes;
And no error must be returned.
> + is_err("Number of planes mismatch\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int isp_s_fmt_mplane(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + struct fimc_is_pipeline *p = isp->pipeline;
> + struct fimc_is_fmt *fmt;
> + unsigned int sensor_width, sensor_height;
> + int ret;
> +
> + ret = isp_try_fmt_mplane(file, priv, f);
> + if (ret)
> + return ret;
> +
> + /* Get format type */
> + fmt = find_format(f);
> + if (!fmt) {
> + is_err("Format not supported.\n");
> + return -EINVAL;
Same as above, just pick some default format.
> + }
> +
> + /* Check if same as sensor width& height */
> + sensor_width = p->sensor->sensor_info->pixel_width;
> + sensor_height = p->sensor->sensor_info->pixel_height;
> + if ((sensor_width != f->fmt.pix_mp.width) ||
> + (sensor_height != f->fmt.pix_mp.height)) {
> + is_err("ISP resolution should be same as sensor\n");
If these resolutions need to match then you may want to do:
f->fmt.pix_mp.width = sensor_width;
f->fmt.pix_mp.height = sensor_height;
> + return -EINVAL;
No, this is incorrect.
> + }
> +
> + isp->fmt = fmt;
> + isp->width = f->fmt.pix_mp.width;
> + isp->height = f->fmt.pix_mp.height;
> + isp->size_image = f->fmt.pix_mp.plane_fmt[0].sizeimage;
> + set_bit(STATE_INIT,&isp->output_state);
The driver should have some initial default values, so the configuration
is valid right after initialization. rather than tracking which calls
took place in user space.
> + return 0;
> +}
> +
> +static int isp_streamon(struct file *file, void *priv,
> + enum v4l2_buf_type type)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + int ret;
> +
> + ret = vb2_streamon(&isp->vbq, type);
> + return 0;
> +}
> +
> +static int isp_streamoff(struct file *file, void *priv,
> + enum v4l2_buf_type type)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + int ret;
> +
> + ret = vb2_streamoff(&isp->vbq, type);
> + return 0;
> +}
I suggest you to use vb2_ioctl_* helpers where possible. Lots of such
boilerplate code can be removed when you switch to use those.
> +static int isp_reqbufs(struct file *file, void *priv,
> + struct v4l2_requestbuffers *reqbufs)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + int ret;
> +
> + if (!isp->fmt) {
> + is_err("Set format not done\n");
> + return -EINVAL;
That's wrong. As mentioned above, there must be some initial valid
configuration (image format), so you can call reqbufs ioctl right
after opening /dev/video.
Whether the whole processing pipeline is consistent or not should be
checked
in streamon ioctl.
> + }
> +
> + /* Check whether buffers are already allocated */
> + if (test_bit(STATE_BUFS_ALLOCATED,&isp->output_state)) {
> + is_err("Buffers already allocated\n");
> + return -EINVAL;
What happens when reqbufs->count == 0 ? How is this code supposed to
allow to
actually free buffers ?
I don't think you need this kind of checks in this ioctl handler. videobuf2
is supposed to handle that sort of things.
> + }
> +
> + ret = vb2_reqbufs(&isp->vbq, reqbufs);
> + if (ret) {
> + is_err("vb2 req buffers failed\n");
Would be better to use standard error logging APIs, e.g. v4l2_err().
> + return ret;
> + }
> +
> + isp->num_buffers = reqbufs->count;
> + isp->out_buf_cnt = 0;
> + set_bit(STATE_BUFS_ALLOCATED,&isp->output_state);
> + return 0;
> +}
> +static int isp_querybuf(struct file *file, void *priv,
> + struct v4l2_buffer *buf)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + return vb2_querybuf(&isp->vbq, buf);
> +}
> +
> +static int isp_qbuf(struct file *file, void *priv,
> + struct v4l2_buffer *buf)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + return vb2_qbuf(&isp->vbq, buf);
> +}
> +
> +static int isp_dqbuf(struct file *file, void *priv,
> + struct v4l2_buffer *buf)
> +{
> + struct fimc_is_isp *isp = video_drvdata(file);
> + return vb2_dqbuf(&isp->vbq, buf,
> + file->f_flags& O_NONBLOCK);
> +}
These are all good candidates for replacing with vb2_ioctl_* helpers.
> +static const struct v4l2_ioctl_ops isp_video_output_ioctl_ops = {
> + .vidioc_querycap = isp_querycap_output,
> + .vidioc_enum_fmt_vid_out_mplane = isp_enum_fmt_mplane,
> + .vidioc_try_fmt_vid_out_mplane = isp_try_fmt_mplane,
> + .vidioc_s_fmt_vid_out_mplane = isp_s_fmt_mplane,
> + .vidioc_g_fmt_vid_out_mplane = isp_g_fmt_mplane,
> + .vidioc_reqbufs = isp_reqbufs,
> + .vidioc_querybuf = isp_querybuf,
> + .vidioc_qbuf = isp_qbuf,
> + .vidioc_dqbuf = isp_dqbuf,
> + .vidioc_streamon = isp_streamon,
> + .vidioc_streamoff = isp_streamoff,
> +};
> +
> +static int isp_subdev_s_stream(struct v4l2_subdev *sd, int on)
> +{
> + /* Nothing to do.*/
> + return 0;
> +}
> +
> +static int isp_subdev_s_power(struct v4l2_subdev *sd, int on)
> +{
> + /* Nothing to do here as everything is turned on from sensor */
Then please remove these empty functions.
> + return 0;
> +}
> +
[...]
> +int fimc_is_isp_subdev_create(struct fimc_is_isp *isp,
> + struct vb2_alloc_ctx *alloc_ctx,
> + struct fimc_is_pipeline *pipeline)
> +{
> + struct v4l2_ctrl_handler *handler =&isp->ctrl_handler;
> + struct v4l2_subdev *sd =&isp->subdev;
> + int ret;
> +
> + /* Init context vars */
> + isp->alloc_ctx = alloc_ctx;
> + isp->pipeline = pipeline;
> + isp->refcount = 0;
> + isp->fmt =&formats[1];
> +
> + v4l2_subdev_init(sd,&isp_subdev_ops);
> + sd->owner = THIS_MODULE;
> + sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
> + snprintf(sd->name, sizeof(sd->name), "fimc-is-isp");
> +
> + isp->subdev_pads[ISP_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
> + isp->subdev_pads[ISP_SD_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
> + ret = media_entity_init(&sd->entity, ISP_SD_PADS_NUM,
> + isp->subdev_pads, 0);
> + if (ret< 0)
> + return ret;
> +
> + v4l2_ctrl_handler_init(handler, 1);
> + if (handler->error)
> + return handler->error;
Memory leak due to missing media_entity_cleanup() and
v4l2_ctrl_handler_free()
calls.
> +
> + sd->ctrl_handler = handler;
> + sd->internal_ops =&isp_subdev_internal_ops;
> + v4l2_set_subdevdata(sd, isp);
> +
> + return 0;
> +}
> +
> +void fimc_is_isp_subdev_destroy(struct fimc_is_isp *isp)
> +{
> + struct v4l2_subdev *sd =&isp->subdev;
> +
> + v4l2_device_unregister_subdev(sd);
> + media_entity_cleanup(&sd->entity);
> + v4l2_ctrl_handler_free(&isp->ctrl_handler);
> + v4l2_set_subdevdata(sd, NULL);
> +}
> +
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.h b/drivers/media/platform/exynos5-is/fimc-is-isp.h
> new file mode 100644
> index 0000000..be6289f
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-isp.h
> @@ -0,0 +1,88 @@
> +/*
> + * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + * Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef FIMC_IS_ISP_H_
> +#define FIMC_IS_ISP_H_
> +
> +#include "fimc-is-core.h"
> +#include "fimc-is-pipeline.h"
> +
> +#define FIMC_IS_ISP_REQ_BUFS_MIN 2
> +
> +#define ISP_SD_PAD_SINK 0
> +#define ISP_SD_PAD_SRC 1
> +#define ISP_SD_PADS_NUM 2
What about the ISP video device entities ? To which ISP pads are these
connected ?
For Exynos4x12 there are two additional pads where the ISP video output and
capture entities are to be connected. Currently there are only SINK,
SRC_FIFO
and SRC_DMA pads, but SINK_DMA and an output video device could be added in
future if required.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [RFC 08/12] exynos-fimc-is: Adds scaler subdev
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
` (6 preceding siblings ...)
2013-03-08 14:59 ` [RFC 07/12] exynos-fimc-is: Adds isp subdev Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-08 14:59 ` [RFC 09/12] exynos-fimc-is: Adds the hardware pipeline control Arun Kumar K
` (3 subsequent siblings)
11 siblings, 0 replies; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
FIMC-IS has two hardware scalers named as scaler-codec and
scaler-preview. This patch adds the common code handling the
video nodes and subdevs of both the scalers.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
drivers/media/platform/exynos5-is/fimc-is-scaler.c | 595 ++++++++++++++++++++
drivers/media/platform/exynos5-is/fimc-is-scaler.h | 107 ++++
2 files changed, 702 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.c b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
new file mode 100644
index 0000000..86ac9b8
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
@@ -0,0 +1,595 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define DEBUG
+#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
+
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "fimc-is.h"
+
+static struct fimc_is_fmt formats[] = {
+ {
+ .name = "YUV 4:2:0 3p MultiPlanar",
+ .fourcc = V4L2_PIX_FMT_YUV420M,
+ .depth = {8, 2, 2},
+ .num_planes = 3,
+ },
+ {
+ .name = "YUV 4:2:0 2p MultiPlanar",
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .depth = {8, 4},
+ .num_planes = 2,
+ },
+ {
+ .name = "YUV 4:2:2 1p MultiPlanar",
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .depth = {16},
+ .num_planes = 1,
+ },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i < NUM_FORMATS; i++) {
+ if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+ return &formats[i];
+ }
+ return NULL;
+}
+
+static int scaler_video_capture_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ int ret;
+
+ /* Scaler start */
+ ret = fimc_is_pipeline_scaler_start(ctx->pipeline,
+ ctx->scaler_id,
+ (unsigned int **)ctx->buf_paddr,
+ ctx->num_buffers,
+ ctx->fmt->num_planes);
+ if (ret) {
+ is_err("Scaler start failed.\n");
+ return -EINVAL;
+ }
+
+ set_bit(STATE_RUNNING, &ctx->capture_state);
+ return 0;
+}
+
+static int scaler_video_capture_stop_streaming(struct vb2_queue *vq)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ int ret;
+
+ /* Scaler stop */
+ ret = fimc_is_pipeline_scaler_stop(ctx->pipeline, ctx->scaler_id);
+ if (ret)
+ is_dbg(3, "Scaler already stopped.\n");
+
+ clear_bit(STATE_RUNNING, &ctx->capture_state);
+ return 0;
+}
+
+static int scaler_video_capture_queue_setup(struct vb2_queue *vq,
+ const struct v4l2_format *pfmt,
+ unsigned int *num_buffers, unsigned int *num_planes,
+ unsigned int sizes[], void *allocators[])
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_fmt *fmt = ctx->fmt;
+ unsigned int wh;
+ int i;
+
+ if (!fmt)
+ return -EINVAL;
+
+ *num_planes = fmt->num_planes;
+ wh = ctx->width * ctx->height;
+
+ for (i = 0; i < *num_planes; i++) {
+ allocators[i] = ctx->alloc_ctx;
+ sizes[i] = (wh * fmt->depth[i]) / 8;
+ }
+ return 0;
+}
+
+static int scaler_video_capture_buffer_init(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+ struct fimc_is_fmt *fmt;
+ int i;
+
+ buf = &ctx->capture_bufs[vb->v4l2_buf.index];
+ /* Initialize buffer */
+ buf->vb = vb;
+ fmt = ctx->fmt;
+ for (i = 0; i < fmt->num_planes; i++)
+ buf->paddr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+
+ ctx->cap_buf_cnt++;
+ return 0;
+}
+
+static void scaler_video_capture_buffer_queue(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+
+ buf = &ctx->capture_bufs[vb->v4l2_buf.index];
+
+ /* Add buffer to the wait queue */
+ is_dbg(5, "Add buffer %d in Scaler %d\n",
+ vb->v4l2_buf.index, ctx->scaler_id);
+ fimc_is_pipeline_buf_lock(ctx->pipeline);
+ fimc_is_scaler_wait_queue_add(ctx, buf);
+ fimc_is_pipeline_buf_unlock(ctx->pipeline);
+}
+
+static void scaler_lock(struct vb2_queue *vq)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ mutex_lock(&ctx->video_lock);
+}
+
+static void scaler_unlock(struct vb2_queue *vq)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ mutex_unlock(&ctx->video_lock);
+}
+
+static const struct vb2_ops scaler_video_capture_qops = {
+ .queue_setup = scaler_video_capture_queue_setup,
+ .buf_init = scaler_video_capture_buffer_init,
+ .buf_queue = scaler_video_capture_buffer_queue,
+ .wait_prepare = scaler_unlock,
+ .wait_finish = scaler_lock,
+ .start_streaming = scaler_video_capture_start_streaming,
+ .stop_streaming = scaler_video_capture_stop_streaming,
+};
+
+static int scaler_video_capture_open(struct file *file)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+ int ret = 0;
+
+ /* Check if opened before */
+ if (ctx->refcount >= FIMC_IS_MAX_INSTANCES) {
+ is_err("All instances are in use.\n");
+ return -EBUSY;
+ }
+
+ INIT_LIST_HEAD(&ctx->wait_queue);
+ ctx->wait_queue_cnt = 0;
+ INIT_LIST_HEAD(&ctx->run_queue);
+ ctx->run_queue_cnt = 0;
+
+ ctx->fmt = NULL;
+ ctx->refcount++;
+
+ return ret;
+}
+
+static int scaler_video_capture_close(struct file *file)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+ int ret = 0;
+
+ vb2_queue_release(&ctx->vbq);
+ ctx->refcount--;
+ ctx->capture_state = 0;
+
+ return ret;
+}
+
+static unsigned int scaler_video_capture_poll(struct file *file,
+ struct poll_table_struct *wait)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+ int ret;
+
+ if (mutex_lock_interruptible(&ctx->video_lock))
+ return POLL_ERR;
+
+ ret = vb2_poll(&ctx->vbq, file, wait);
+ mutex_unlock(&ctx->video_lock);
+
+ return ret;
+}
+
+static int scaler_video_capture_mmap(struct file *file,
+ struct vm_area_struct *vma)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+ int ret;
+
+ if (mutex_lock_interruptible(&ctx->video_lock))
+ return -ERESTARTSYS;
+
+ ret = vb2_mmap(&ctx->vbq, vma);
+ mutex_unlock(&ctx->video_lock);
+
+ return ret;
+}
+
+static const struct v4l2_file_operations scaler_video_capture_fops = {
+ .owner = THIS_MODULE,
+ .open = scaler_video_capture_open,
+ .release = scaler_video_capture_close,
+ .poll = scaler_video_capture_poll,
+ .unlocked_ioctl = video_ioctl2,
+ .mmap = scaler_video_capture_mmap,
+};
+
+/*
+ * Video node ioctl operations
+ */
+static int scaler_querycap_capture(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ strlcpy(cap->driver, "fimc-is-scaler", sizeof(cap->driver));
+ cap->bus_info[0] = 0;
+ cap->card[0] = 0;
+ cap->capabilities = V4L2_CAP_STREAMING;
+ return 0;
+}
+
+static int scaler_enum_fmt_mplane(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ const struct fimc_is_fmt *fmt;
+
+ if (f->index >= NUM_FORMATS)
+ return -EINVAL;
+
+ fmt = &formats[f->index];
+ strlcpy(f->description, fmt->name, sizeof(f->description));
+ f->pixelformat = fmt->fourcc;
+ return 0;
+}
+
+static int scaler_g_fmt_mplane(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+ struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
+ struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
+ const struct fimc_is_fmt *fmt = ctx->fmt;
+
+ plane_fmt->bytesperline = (ctx->width * fmt->depth[0]) / 8;
+ plane_fmt->sizeimage = plane_fmt->bytesperline * ctx->height;
+
+ pixm->num_planes = fmt->num_planes;
+ pixm->pixelformat = fmt->fourcc;
+ pixm->width = ctx->width;
+ pixm->height = ctx->height;
+ pixm->field = V4L2_FIELD_NONE;
+ pixm->colorspace = V4L2_COLORSPACE_JPEG;
+
+ return 0;
+}
+
+static int scaler_try_fmt_mplane(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct fimc_is_fmt *fmt;
+
+ if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+ return -EINVAL;
+
+ fmt = find_format(f);
+ if (!fmt) {
+ is_err("Format not supported.\n");
+ return -EINVAL;
+ }
+
+ if (fmt->num_planes != f->fmt.pix_mp.num_planes) {
+ is_err("Number of planes mismatch\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int scaler_s_fmt_mplane(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+ struct fimc_is_fmt *fmt;
+ int ret;
+
+ ret = scaler_try_fmt_mplane(file, priv, f);
+ if (ret)
+ return ret;
+
+ /* Check width & height */
+ if (f->fmt.pix_mp.width > ctx->pipeline->sensor_width ||
+ f->fmt.pix_mp.height > ctx->pipeline->sensor_height) {
+ is_err("Too large width and height\n");
+ return -EINVAL;
+ }
+
+ /* Get format type */
+ fmt = find_format(f);
+ if (!fmt) {
+ is_err("Format not supported.\n");
+ return -EINVAL;
+ }
+
+ /* Save values to context */
+ ctx->fmt = fmt;
+ ctx->width = f->fmt.pix_mp.width;
+ ctx->height = f->fmt.pix_mp.height;
+ ctx->pipeline->scaler_width[ctx->scaler_id] = ctx->width;
+ ctx->pipeline->scaler_height[ctx->scaler_id] = ctx->height;
+ set_bit(STATE_INIT, &ctx->capture_state);
+ return 0;
+}
+
+static int scaler_streamon(struct file *file, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+
+ return vb2_streamon(&ctx->vbq, type);
+}
+
+static int scaler_streamoff(struct file *file, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+
+ return vb2_streamoff(&ctx->vbq, type);
+}
+
+static int scaler_reqbufs(struct file *file, void *priv,
+ struct v4l2_requestbuffers *reqbufs)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+ int ret;
+
+ if (reqbufs->memory != V4L2_MEMORY_MMAP &&
+ reqbufs->memory != V4L2_MEMORY_DMABUF) {
+ is_err("Memory type not supported\n");
+ return -EINVAL;
+ }
+
+ if (!ctx->fmt) {
+ is_err("Set format not done\n");
+ return -EINVAL;
+ }
+
+ /* Check whether buffers are already allocated */
+ if (test_bit(STATE_BUFS_ALLOCATED, &ctx->capture_state)) {
+ is_err("Buffers already allocated\n");
+ return -EINVAL;
+ }
+
+ ret = vb2_reqbufs(&ctx->vbq, reqbufs);
+ if (ret) {
+ is_err("vb2 req buffers failed\n");
+ return ret;
+ }
+
+ ctx->num_buffers = reqbufs->count;
+ ctx->cap_buf_cnt = 0;
+ set_bit(STATE_BUFS_ALLOCATED, &ctx->capture_state);
+ return 0;
+}
+
+static int scaler_querybuf(struct file *file, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+ return vb2_querybuf(&ctx->vbq, buf);
+}
+
+static int scaler_qbuf(struct file *file, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+ return vb2_qbuf(&ctx->vbq, buf);
+}
+
+static int scaler_dqbuf(struct file *file, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+ return vb2_dqbuf(&ctx->vbq, buf,
+ file->f_flags & O_NONBLOCK);
+}
+
+static int scaler_expbuf(struct file *file, void *priv,
+ struct v4l2_exportbuffer *eb)
+{
+ struct fimc_is_scaler *ctx = video_drvdata(file);
+
+ return vb2_expbuf(&ctx->vbq, eb);
+}
+
+static const struct v4l2_ioctl_ops scaler_video_capture_ioctl_ops = {
+ .vidioc_querycap = scaler_querycap_capture,
+ .vidioc_enum_fmt_vid_cap_mplane = scaler_enum_fmt_mplane,
+ .vidioc_try_fmt_vid_cap_mplane = scaler_try_fmt_mplane,
+ .vidioc_s_fmt_vid_cap_mplane = scaler_s_fmt_mplane,
+ .vidioc_g_fmt_vid_cap_mplane = scaler_g_fmt_mplane,
+ .vidioc_reqbufs = scaler_reqbufs,
+ .vidioc_querybuf = scaler_querybuf,
+ .vidioc_qbuf = scaler_qbuf,
+ .vidioc_dqbuf = scaler_dqbuf,
+ .vidioc_expbuf = scaler_expbuf,
+ .vidioc_streamon = scaler_streamon,
+ .vidioc_streamoff = scaler_streamoff,
+};
+
+static int scaler_subdev_s_stream(struct v4l2_subdev *sd, int on)
+{
+ return 0;
+}
+
+static int scaler_subdev_s_power(struct v4l2_subdev *sd, int on)
+{
+ /* Nothing to do as sensor has started the pipeline */
+ return 0;
+}
+
+static int scaler_subdev_registered(struct v4l2_subdev *sd)
+{
+ struct fimc_is_scaler *ctx = v4l2_get_subdevdata(sd);
+ struct vb2_queue *q = &ctx->vbq;
+ struct video_device *vfd = &ctx->vfd;
+ int ret;
+
+ mutex_init(&ctx->video_lock);
+
+ memset(vfd, 0, sizeof(*vfd));
+ if (ctx->scaler_id == SCALER_SCC)
+ snprintf(vfd->name, sizeof(vfd->name), "fimc-is-scaler.codec");
+ else
+ snprintf(vfd->name, sizeof(vfd->name),
+ "fimc-is-scaler.preview");
+
+ vfd->fops = &scaler_video_capture_fops;
+ vfd->ioctl_ops = &scaler_video_capture_ioctl_ops;
+ vfd->v4l2_dev = sd->v4l2_dev;
+ vfd->minor = -1;
+ vfd->release = video_device_release_empty;
+ vfd->lock = &ctx->video_lock;
+ vfd->vfl_dir = VFL_DIR_RX;
+
+ memset(q, 0, sizeof(*q));
+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+ q->io_modes = VB2_MMAP | VB2_DMABUF;
+ q->ops = &scaler_video_capture_qops;
+ q->mem_ops = &vb2_dma_contig_memops;
+ q->drv_priv = ctx;
+
+ ret = vb2_queue_init(q);
+ if (ret < 0)
+ return ret;
+
+ ctx->vd_pad.flags = MEDIA_PAD_FL_SINK;
+ ret = media_entity_init(&vfd->entity, 1, &ctx->vd_pad, 0);
+ if (ret < 0)
+ return ret;
+
+ video_set_drvdata(vfd, ctx);
+
+ ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
+ if (ret < 0) {
+ media_entity_cleanup(&vfd->entity);
+ return ret;
+ }
+
+ v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
+ vfd->name, video_device_node_name(vfd));
+ return 0;
+}
+
+static void scaler_subdev_unregistered(struct v4l2_subdev *sd)
+{
+ struct fimc_is_scaler *ctx = v4l2_get_subdevdata(sd);
+
+ if (ctx && video_is_registered(&ctx->vfd))
+ video_unregister_device(&ctx->vfd);
+}
+
+static const struct v4l2_subdev_internal_ops scaler_subdev_internal_ops = {
+ .registered = scaler_subdev_registered,
+ .unregistered = scaler_subdev_unregistered,
+};
+
+static const struct v4l2_subdev_video_ops scaler_subdev_video_ops = {
+ .s_stream = scaler_subdev_s_stream,
+};
+
+static const struct v4l2_subdev_core_ops scaler_core_ops = {
+ .s_power = scaler_subdev_s_power,
+};
+
+static struct v4l2_subdev_ops scaler_subdev_ops = {
+ .core = &scaler_core_ops,
+ .video = &scaler_subdev_video_ops,
+};
+
+static int scaler_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ return 0;
+}
+
+static const struct v4l2_ctrl_ops scaler_ctrl_ops = {
+ .s_ctrl = scaler_s_ctrl,
+};
+
+int fimc_is_scaler_subdev_create(struct fimc_is_scaler *ctx,
+ enum fimc_is_scaler_id scaler_id,
+ struct vb2_alloc_ctx *alloc_ctx,
+ struct fimc_is_pipeline *pipeline)
+{
+ struct v4l2_ctrl_handler *handler = &ctx->ctrl_handler;
+ struct v4l2_subdev *sd = &ctx->subdev;
+ int ret;
+
+ /* Set context data */
+ ctx->scaler_id = scaler_id;
+ ctx->alloc_ctx = alloc_ctx;
+ ctx->pipeline = pipeline;
+ ctx->fmt = &formats[0];
+ ctx->refcount = 0;
+ init_waitqueue_head(&ctx->event_q);
+
+ /* Initialize scaler subdev */
+ v4l2_subdev_init(sd, &scaler_subdev_ops);
+ sd->owner = THIS_MODULE;
+ sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+ if (scaler_id == SCALER_SCC)
+ snprintf(sd->name, sizeof(sd->name), "fimc-is-scc");
+ else
+ snprintf(sd->name, sizeof(sd->name), "fimc-is-scp");
+
+ ctx->subdev_pads[SCALER_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+ ctx->subdev_pads[SCALER_SD_PAD_SRC_FIFO].flags = MEDIA_PAD_FL_SOURCE;
+ ctx->subdev_pads[SCALER_SD_PAD_SRC_DMA].flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_init(&sd->entity, ISP_SD_PADS_NUM,
+ ctx->subdev_pads, 0);
+ if (ret < 0)
+ return ret;
+
+ v4l2_ctrl_handler_init(handler, 1);
+ if (handler->error)
+ return handler->error;
+
+ sd->ctrl_handler = handler;
+ sd->internal_ops = &scaler_subdev_internal_ops;
+ v4l2_set_subdevdata(sd, ctx);
+
+ return 0;
+}
+
+void fimc_is_scaler_subdev_destroy(struct fimc_is_scaler *ctx)
+{
+ struct v4l2_subdev *sd = &ctx->subdev;
+
+ v4l2_device_unregister_subdev(sd);
+ media_entity_cleanup(&sd->entity);
+ v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+ v4l2_set_subdevdata(sd, NULL);
+}
+
diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.h b/drivers/media/platform/exynos5-is/fimc-is-scaler.h
new file mode 100644
index 0000000..115e00a
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.h
@@ -0,0 +1,107 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_SCALER_H_
+#define FIMC_IS_SCALER_H_
+
+#include <linux/sizes.h>
+#include <linux/io.h>
+#include <linux/irqreturn.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+
+#include <media/media-entity.h>
+#include <media/videobuf2-core.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mediabus.h>
+#include <media/s5p_fimc.h>
+
+#include "fimc-is-core.h"
+
+#define SCALER_SD_PAD_SINK 0
+#define SCALER_SD_PAD_SRC_FIFO 1
+#define SCALER_SD_PAD_SRC_DMA 2
+#define SCALER_SD_PADS_NUM 3
+
+#define SCALER_MAX_BUFS 32
+#define SCALER_MAX_PLANES 3
+
+/**
+ * struct fimc_is_scaler - fimc-is scaler structure
+ * @vfd: video device node
+ * @fh: v4l2 file handle
+ * @alloc_ctx: videobuf2 memory allocator context
+ * @subdev: fimc-is-scaler subdev
+ * @vd_pad: media pad for the output video node
+ * @subdev_pads: the subdev media pads
+ * @ctrl_handler: v4l2 control handler
+ * @video_lock: video lock mutex
+ * @refcount: keeps track of number of instances opened
+ * @event_q: notifies scaler events
+ * @pipeline: pipeline instance for this scaler context
+ * @scaler_id: distinguishes scaler preview or scaler codec
+ * @vbq: vb2 buffers queue for ISP output video node
+ * @wait_queue: list holding buffers waiting to be queued to HW
+ * @wait_queue_cnt: wait queue number of buffers
+ * @run_queue: list holding buffers queued to HW
+ * @run_queue_cnt: run queue number of buffers
+ * @capture_bufs: scaler capture buffers array
+ * @cap_buf_cnt: number of capture buffers in use
+ * @fmt: capture plane format for scaler
+ * @width: user configured output width
+ * @height: user configured output height
+ * @num_buffers: number of capture plane buffers in use
+ * @capture_state: state of the capture video node operations
+ * @buf_paddr: holds the physical address of capture buffers
+ */
+struct fimc_is_scaler {
+ struct video_device vfd;
+ struct v4l2_fh fh;
+ struct vb2_alloc_ctx *alloc_ctx;
+ struct v4l2_subdev subdev;
+ struct media_pad vd_pad;
+ struct media_pad subdev_pads[SCALER_SD_PADS_NUM];
+ struct v4l2_mbus_framefmt subdev_fmt;
+ struct v4l2_ctrl_handler ctrl_handler;
+
+ struct mutex video_lock;
+ unsigned int refcount;
+ wait_queue_head_t event_q;
+
+ struct fimc_is_pipeline *pipeline;
+ enum fimc_is_scaler_id scaler_id;
+
+ struct vb2_queue vbq;
+ struct list_head wait_queue;
+ unsigned int wait_queue_cnt;
+ struct list_head run_queue;
+ unsigned int run_queue_cnt;
+
+ struct fimc_is_buf capture_bufs[SCALER_MAX_BUFS];
+ unsigned int cap_buf_cnt;
+
+ struct fimc_is_fmt *fmt;
+ unsigned int width;
+ unsigned int height;
+ unsigned int num_buffers;
+ unsigned long capture_state;
+ unsigned int buf_paddr[SCALER_MAX_BUFS][SCALER_MAX_PLANES];
+};
+
+int fimc_is_scaler_subdev_create(struct fimc_is_scaler *ctx,
+ enum fimc_is_scaler_id scaler_id,
+ struct vb2_alloc_ctx *alloc_ctx,
+ struct fimc_is_pipeline *pipeline);
+void fimc_is_scaler_subdev_destroy(struct fimc_is_scaler *scaler);
+
+#endif /* FIMC_IS_SCALER_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* [RFC 09/12] exynos-fimc-is: Adds the hardware pipeline control
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
` (7 preceding siblings ...)
2013-03-08 14:59 ` [RFC 08/12] exynos-fimc-is: Adds scaler subdev Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-08 14:59 ` [RFC 10/12] exynos-fimc-is: Adds the hardware interface module Arun Kumar K
` (2 subsequent siblings)
11 siblings, 0 replies; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
This patch adds the crucial hardware pipeline control for the
fimc-is driver. All the subdev nodes will call this pipeline
interfaces to reach the hardware. Responsibilities of this module
involves configuring and maintaining the hardware pipeline involving
multiple sub-ips like ISP, DRC, Scalers, ODC, 3DNR, FD etc.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
.../media/platform/exynos5-is/fimc-is-pipeline.c | 1961 ++++++++++++++++++++
.../media/platform/exynos5-is/fimc-is-pipeline.h | 129 ++
2 files changed, 2090 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-pipeline.c b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
new file mode 100644
index 0000000..66f0c50
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
@@ -0,0 +1,1961 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is.h"
+#include "fimc-is-pipeline.h"
+#include "fimc-is-metadata.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-cmd.h"
+#include <media/videobuf2-dma-contig.h>
+#include <linux/delay.h>
+
+/* Default setting values */
+#define DEFAULT_PREVIEW_STILL_WIDTH (1280) /* sensor margin : 16 */
+#define DEFAULT_PREVIEW_STILL_HEIGHT (720) /* sensor margin : 12 */
+#define DEFAULT_CAPTURE_VIDEO_WIDTH (1920)
+#define DEFAULT_CAPTURE_VIDEO_HEIGHT (1080)
+#define DEFAULT_CAPTURE_STILL_WIDTH (2560)
+#define DEFAULT_CAPTURE_STILL_HEIGHT (1920)
+#define DEFAULT_CAPTURE_STILL_CROP_WIDTH (2560)
+#define DEFAULT_CAPTURE_STILL_CROP_HEIGHT (1440)
+#define DEFAULT_PREVIEW_VIDEO_WIDTH (640)
+#define DEFAULT_PREVIEW_VIDEO_HEIGHT (480)
+
+static void *fw_cookie;
+static void *shot_cookie;
+
+/* Init params for pipeline devices */
+static const struct sensor_param init_sensor_param = {
+ .frame_rate = {
+ .frame_rate = 30,
+ },
+};
+
+static const struct isp_param init_isp_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_START,
+ .bypass = CONTROL_BYPASS_DISABLE,
+ .err = CONTROL_ERROR_NO,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_INPUT_FORMAT_BAYER,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .crop_offset_x = 0,
+ .crop_offset_y = 0,
+ .crop_width = 0,
+ .crop_height = 0,
+ .frametime_min = 0,
+ .frametime_max = 33333,
+ .err = OTF_INPUT_ERROR_NO,
+ },
+ .dma1_input = {
+ .cmd = DMA_INPUT_COMMAND_DISABLE,
+ .width = 0,
+ .height = 0,
+ .format = 0,
+ .bitwidth = 0,
+ .plane = 0,
+ .order = 0,
+ .buffer_number = 0,
+ .buffer_address = 0,
+ .err = 0,
+ },
+ .dma2_input = {
+ .cmd = DMA_INPUT_COMMAND_DISABLE,
+ .width = 0, .height = 0,
+ .format = 0, .bitwidth = 0, .plane = 0,
+ .order = 0, .buffer_number = 0, .buffer_address = 0,
+ .err = 0,
+ },
+ .aa = {
+ .cmd = ISP_AA_COMMAND_START,
+ .target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
+ ISP_AA_TARGET_AWB,
+ .mode = ISP_AF_CONTINUOUS,
+ .scene = 0,
+ .sleep = 0,
+ .uiafface = 0,
+ .touch_x = 0, .touch_y = 0,
+ .manual_af_setting = 0,
+ .err = ISP_AF_ERROR_NO,
+ },
+ .flash = {
+ .cmd = ISP_FLASH_COMMAND_DISABLE,
+ .redeye = ISP_FLASH_REDEYE_DISABLE,
+ .err = ISP_FLASH_ERROR_NO,
+ },
+ .awb = {
+ .cmd = ISP_AWB_COMMAND_AUTO,
+ .illumination = 0,
+ .err = ISP_AWB_ERROR_NO,
+ },
+ .effect = {
+ .cmd = ISP_IMAGE_EFFECT_DISABLE,
+ .err = ISP_IMAGE_EFFECT_ERROR_NO,
+ },
+ .iso = {
+ .cmd = ISP_ISO_COMMAND_AUTO,
+ .value = 0,
+ .err = ISP_ISO_ERROR_NO,
+ },
+ .adjust = {
+ .cmd = ISP_ADJUST_COMMAND_AUTO,
+ .contrast = 0,
+ .saturation = 0,
+ .sharpness = 0,
+ .exposure = 0,
+ .brightness = 0,
+ .hue = 0,
+ .err = ISP_ADJUST_ERROR_NO,
+ },
+ .metering = {
+ .cmd = ISP_METERING_COMMAND_CENTER,
+ .win_pos_x = 0, .win_pos_y = 0,
+ .win_width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .win_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .err = ISP_METERING_ERROR_NO,
+ },
+ .afc = {
+ .cmd = ISP_AFC_COMMAND_AUTO,
+ .manual = 0, .err = ISP_AFC_ERROR_NO,
+ },
+ .otf_output = {
+ .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV444,
+ .bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+ .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+ .uicropoffsetx = 0,
+ .uicropoffsety = 0,
+ .err = OTF_OUTPUT_ERROR_NO,
+ },
+ .dma1_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .dma_out_mask = 0,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = DMA_INPUT_FORMAT_YUV444,
+ .bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
+ .plane = DMA_INPUT_PLANE_1,
+ .order = DMA_INPUT_ORDER_YCBCR,
+ .buffer_number = 0,
+ .buffer_address = 0,
+ .err = DMA_OUTPUT_ERROR_NO,
+ },
+ .dma2_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = DMA_OUTPUT_FORMAT_BAYER,
+ .bitwidth = DMA_OUTPUT_BIT_WIDTH_12BIT,
+ .plane = DMA_OUTPUT_PLANE_1,
+ .order = DMA_OUTPUT_ORDER_GB_BG,
+ .buffer_number = 0,
+ .buffer_address = 0,
+ .dma_out_mask = 0xFFFFFFFF,
+ .err = DMA_OUTPUT_ERROR_NO,
+ },
+};
+
+static const struct drc_param init_drc_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_START,
+ .bypass = CONTROL_BYPASS_ENABLE,
+ .err = CONTROL_ERROR_NO,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_INPUT_FORMAT_YUV444,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .err = OTF_INPUT_ERROR_NO,
+ },
+ .dma_input = {
+ .cmd = DMA_INPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = DMA_INPUT_FORMAT_YUV444,
+ .bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
+ .plane = DMA_INPUT_PLANE_1,
+ .order = DMA_INPUT_ORDER_YCBCR,
+ .buffer_number = 0,
+ .buffer_address = 0,
+ .err = 0,
+ },
+ .otf_output = {
+ .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV444,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+ .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+ .uicropoffsetx = 0,
+ .uicropoffsety = 0,
+ .err = OTF_OUTPUT_ERROR_NO,
+ },
+};
+
+static const struct scalerc_param init_scalerc_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_START,
+ .bypass = CONTROL_BYPASS_ENABLE,
+ .err = CONTROL_ERROR_NO,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_INPUT_FORMAT_YUV444,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .crop_offset_x = 0,
+ .crop_offset_y = 0,
+ .crop_width = 0,
+ .crop_height = 0,
+ .err = OTF_INPUT_ERROR_NO,
+ },
+ .effect = {
+ .cmd = 0,
+ .err = 0,
+ },
+ .input_crop = {
+ .cmd = OTF_INPUT_COMMAND_ENABLE,
+ .pos_x = 0,
+ .pos_y = 0,
+ .crop_width = DEFAULT_CAPTURE_STILL_CROP_WIDTH,
+ .crop_height = DEFAULT_CAPTURE_STILL_CROP_HEIGHT,
+ .in_width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .in_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .out_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .out_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .err = 0,
+ },
+ .output_crop = {
+ .cmd = SCALER_CROP_COMMAND_DISABLE,
+ .pos_x = 0,
+ .pos_y = 0,
+ .crop_width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .crop_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = DMA_OUTPUT_FORMAT_YUV420,
+ .err = 0,
+ },
+ .otf_output = {
+ .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV444,
+ .bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+ .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+ .uicropoffsetx = 0,
+ .uicropoffsety = 0,
+ .err = OTF_OUTPUT_ERROR_NO,
+ },
+ .dma_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = DMA_OUTPUT_FORMAT_YUV420,
+ .bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+ .plane = DMA_OUTPUT_PLANE_3,
+ .order = DMA_OUTPUT_ORDER_NO,
+ .buffer_number = 0,
+ .buffer_address = 0,
+ .dma_out_mask = 0xffff,
+ .err = DMA_OUTPUT_ERROR_NO,
+ },
+};
+
+static const struct odc_param init_odc_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_START,
+ .bypass = CONTROL_BYPASS_ENABLE,
+ .err = CONTROL_ERROR_NO,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .format = OTF_INPUT_FORMAT_YUV444,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .crop_offset_x = 0,
+ .crop_offset_y = 0,
+ .crop_width = 0,
+ .crop_height = 0,
+ .err = OTF_INPUT_ERROR_NO,
+ },
+ .otf_output = {
+ .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV422,
+ .bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+ .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+ .uicropoffsetx = 0,
+ .uicropoffsety = 0,
+ .err = OTF_OUTPUT_ERROR_NO,
+ },
+};
+
+static const struct dis_param init_dis_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_START,
+ .bypass = CONTROL_BYPASS_ENABLE,
+ .err = CONTROL_ERROR_NO,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .format = OTF_INPUT_FORMAT_YUV422,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .crop_offset_x = 0,
+ .crop_offset_y = 0,
+ .crop_width = 0,
+ .crop_height = 0,
+ .err = OTF_INPUT_ERROR_NO,
+ },
+ .otf_output = {
+ .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV422,
+ .bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+ .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+ .uicropoffsetx = 0,
+ .uicropoffsety = 0,
+ .err = OTF_OUTPUT_ERROR_NO,
+ },
+};
+static const struct tdnr_param init_tdnr_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_START,
+ .bypass = CONTROL_BYPASS_ENABLE,
+ .err = CONTROL_ERROR_NO,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .format = OTF_INPUT_FORMAT_YUV422,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .err = OTF_INPUT_ERROR_NO,
+ },
+ .frame = {
+ .cmd = 0,
+ .err = 0,
+ },
+ .otf_output = {
+ .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV444,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+ .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+ .uicropoffsetx = 0,
+ .uicropoffsety = 0,
+ .err = OTF_OUTPUT_ERROR_NO,
+ },
+ .dma_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .format = DMA_OUTPUT_FORMAT_YUV420,
+ .bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+ .plane = DMA_OUTPUT_PLANE_2,
+ .order = DMA_OUTPUT_ORDER_CBCR,
+ .buffer_number = 0,
+ .buffer_address = 0,
+ .dma_out_mask = 0xffff,
+ .err = DMA_OUTPUT_ERROR_NO,
+ },
+};
+
+static const struct scalerp_param init_scalerp_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_START,
+ .bypass = CONTROL_BYPASS_ENABLE,
+ .err = CONTROL_ERROR_NO,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .format = OTF_INPUT_FORMAT_YUV444,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .crop_offset_x = 0,
+ .crop_offset_y = 0,
+ .crop_width = 0,
+ .crop_height = 0,
+ .err = OTF_INPUT_ERROR_NO,
+ },
+ .effect = {
+ .cmd = 0,
+ .err = 0,
+ },
+ .input_crop = {
+ .cmd = OTF_INPUT_COMMAND_ENABLE,
+ .pos_x = 0,
+ .pos_y = 0,
+ .crop_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .crop_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .in_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+ .in_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+ .out_width = DEFAULT_PREVIEW_STILL_WIDTH,
+ .out_height = DEFAULT_PREVIEW_STILL_HEIGHT,
+ .err = 0,
+ },
+ .output_crop = {
+ .cmd = SCALER_CROP_COMMAND_DISABLE,
+ .pos_x = 0,
+ .pos_y = 0,
+ .crop_width = DEFAULT_PREVIEW_STILL_WIDTH,
+ .crop_height = DEFAULT_PREVIEW_STILL_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV420,
+ .err = 0,
+ },
+ .rotation = {
+ .cmd = 0,
+ .err = 0,
+ },
+ .flip = {
+ .cmd = 0,
+ .err = 0,
+ },
+ .otf_output = {
+ .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+ .width = DEFAULT_PREVIEW_STILL_WIDTH,
+ .height = DEFAULT_PREVIEW_STILL_HEIGHT,
+ .format = OTF_INPUT_FORMAT_YUV444,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+ .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+ .uicropoffsetx = 0,
+ .uicropoffsety = 0,
+ .err = OTF_OUTPUT_ERROR_NO,
+ },
+ .dma_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .width = DEFAULT_PREVIEW_STILL_WIDTH,
+ .height = DEFAULT_PREVIEW_STILL_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV420,
+ .bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+ .plane = DMA_OUTPUT_PLANE_3,
+ .order = DMA_OUTPUT_ORDER_NO,
+ .buffer_number = 0,
+ .buffer_address = 0,
+ .dma_out_mask = 0xffff,
+ .err = DMA_OUTPUT_ERROR_NO,
+ },
+};
+
+static const struct fd_param init_fd_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_STOP,
+ .bypass = CONTROL_BYPASS_DISABLE,
+ .err = CONTROL_ERROR_NO,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_ENABLE,
+ .width = DEFAULT_PREVIEW_STILL_WIDTH,
+ .height = DEFAULT_PREVIEW_STILL_HEIGHT,
+ .format = OTF_INPUT_FORMAT_YUV444,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .err = OTF_INPUT_ERROR_NO,
+ },
+ .dma_input = {
+ .cmd = DMA_INPUT_COMMAND_DISABLE,
+ .width = 0, .height = 0,
+ .format = 0, .bitwidth = 0, .plane = 0,
+ .order = 0, .buffer_number = 0, .buffer_address = 0,
+ .err = 0,
+ },
+ .config = {
+ .cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER |
+ FD_CONFIG_COMMAND_ROLL_ANGLE |
+ FD_CONFIG_COMMAND_YAW_ANGLE |
+ FD_CONFIG_COMMAND_SMILE_MODE |
+ FD_CONFIG_COMMAND_BLINK_MODE |
+ FD_CONFIG_COMMAND_EYES_DETECT |
+ FD_CONFIG_COMMAND_MOUTH_DETECT |
+ FD_CONFIG_COMMAND_ORIENTATION |
+ FD_CONFIG_COMMAND_ORIENTATION_VALUE,
+ .max_number = CAMERA2_MAX_FACES,
+ .roll_angle = FD_CONFIG_ROLL_ANGLE_FULL,
+ .yaw_angle = FD_CONFIG_YAW_ANGLE_45_90,
+ .smile_mode = FD_CONFIG_SMILE_MODE_DISABLE,
+ .blink_mode = FD_CONFIG_BLINK_MODE_DISABLE,
+ .eye_detect = FD_CONFIG_EYES_DETECT_ENABLE,
+ .mouth_detect = FD_CONFIG_MOUTH_DETECT_DISABLE,
+ .orientation = FD_CONFIG_ORIENTATION_DISABLE,
+ .orientation_value = 0,
+ .err = ERROR_FD_NO,
+ },
+};
+
+static int fimc_is_pipeline_create_subdevs(struct fimc_is_pipeline *pipeline)
+{
+ struct fimc_is *is = pipeline->is;
+ int ret;
+
+ /* ISP */
+ ret = fimc_is_isp_subdev_create(&pipeline->isp,
+ is->alloc_ctx, pipeline);
+ if (ret < 0)
+ return ret;
+
+ /* SCC scaler */
+ ret = fimc_is_scaler_subdev_create(&pipeline->scaler[SCALER_SCC],
+ SCALER_SCC, is->alloc_ctx, pipeline);
+ if (ret < 0)
+ return ret;
+
+ /* SCP scaler */
+ ret = fimc_is_scaler_subdev_create(&pipeline->scaler[SCALER_SCP],
+ SCALER_SCP, is->alloc_ctx, pipeline);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
+static int fimc_is_pipeline_unregister_subdevs(struct fimc_is_pipeline *p)
+{
+ fimc_is_sensor_subdev_destroy(p->sensor);
+ fimc_is_isp_subdev_destroy(&p->isp);
+ fimc_is_scaler_subdev_destroy(&p->scaler[SCALER_SCC]);
+ fimc_is_scaler_subdev_destroy(&p->scaler[SCALER_SCP]);
+
+ return 0;
+}
+
+int fimc_is_pipeline_init(struct fimc_is_pipeline *pipeline,
+ unsigned int instance, void *is_ctx)
+{
+ struct fimc_is *is = is_ctx;
+ unsigned int i;
+ int ret;
+
+ if (test_bit(PIPELINE_INIT, &pipeline->state)) {
+ is_dbg(3, "Pipeline init already done.\n");
+ return -EINVAL;
+ }
+
+ /* Initialize context variables */
+ pipeline->instance = instance;
+ pipeline->is = is;
+ pipeline->minfo = &is->minfo;
+ pipeline->state = 0;
+ pipeline->force_down = false;
+ for (i = 0; i < FIMC_IS_NUM_COMPS; i++)
+ pipeline->comp_state[i] = 0;
+
+ spin_lock_init(&pipeline->slock_buf);
+ init_waitqueue_head(&pipeline->wait_q);
+ mutex_init(&pipeline->pipe_lock);
+ mutex_init(&pipeline->pipe_scl_lock);
+
+ ret = fimc_is_pipeline_create_subdevs(pipeline);
+ if (ret) {
+ is_err("Subdev creation failed\n");
+ return -EINVAL;
+ }
+
+ /* Setting default width & height for scc & scp */
+ pipeline->scaler_width[SCALER_SCC] = DEFAULT_CAPTURE_VIDEO_WIDTH;
+ pipeline->scaler_height[SCALER_SCC] = DEFAULT_CAPTURE_VIDEO_HEIGHT;
+ pipeline->scaler_width[SCALER_SCP] = DEFAULT_PREVIEW_VIDEO_WIDTH;
+ pipeline->scaler_height[SCALER_SCP] = DEFAULT_PREVIEW_VIDEO_HEIGHT;
+
+ set_bit(PIPELINE_INIT, &pipeline->state);
+ return 0;
+}
+
+int fimc_is_pipeline_destroy(struct fimc_is_pipeline *pipeline)
+{
+ if (!test_bit(PIPELINE_INIT, &pipeline->state)) {
+ is_dbg(3, "Pipeline not inited.\n");
+ return -EINVAL;
+ }
+ return fimc_is_pipeline_unregister_subdevs(pipeline);
+}
+
+static int fimc_is_pipeline_initmem(struct fimc_is_pipeline *pipeline,
+ struct vb2_alloc_ctx *alloc_ctx)
+{
+ struct fimc_is_meminfo *minfo = pipeline->minfo;
+ dma_addr_t *fw_phy_addr;
+ unsigned int offset;
+
+ /* Allocate memory */
+ is_dbg(3, "Allocating memory : %d\n",
+ FIMC_IS_A5_MEM_SIZE + FIMC_IS_A5_SEN_SIZE);
+ fw_cookie = vb2_dma_contig_memops.alloc(alloc_ctx,
+ FIMC_IS_A5_MEM_SIZE + FIMC_IS_A5_SEN_SIZE);
+
+ if (IS_ERR(fw_cookie)) {
+ is_err("Error in allocating FW memory.\n");
+ return -ENOMEM;
+ }
+
+ fw_phy_addr = vb2_dma_contig_memops.cookie(fw_cookie);
+ /* FW memory should be 64MB aligned */
+ if (*fw_phy_addr & FIMC_IS_FW_BASE_MASK) {
+ is_err("FW memory not 64MB aligned.\n");
+ vb2_dma_contig_memops.put(fw_cookie);
+ return -EIO;
+ }
+ minfo->fw_paddr = *fw_phy_addr;
+
+ minfo->fw_vaddr =
+ (unsigned int) vb2_dma_contig_memops.vaddr(fw_cookie);
+
+ is_dbg(3, "FW |Phy Addr : 0x%08x, Virt Addr : 0x%08x\n",
+ minfo->fw_paddr, minfo->fw_vaddr);
+
+ /* Assigning memory regions */
+ offset = FIMC_IS_A5_MEM_SIZE - FIMC_IS_REGION_SIZE;
+ minfo->region_paddr = minfo->fw_paddr + offset;
+ minfo->region_vaddr = minfo->fw_vaddr + offset;
+ pipeline->is_region = (struct is_region *)minfo->region_vaddr;
+
+ minfo->shared_paddr = minfo->fw_paddr +
+ ((unsigned int)&pipeline->is_region->shared[0] -
+ minfo->fw_vaddr);
+ minfo->shared_vaddr = minfo->fw_vaddr +
+ ((unsigned int)&pipeline->is_region->shared[0] -
+ minfo->fw_vaddr);
+
+ /* Allocate shot buffer */
+ shot_cookie = vb2_dma_contig_memops.alloc(alloc_ctx,
+ sizeof(struct camera2_shot));
+ if (IS_ERR(shot_cookie)) {
+ is_err("Error in allocating temp memory.\n");
+ return -ENOMEM;
+ }
+ fw_phy_addr = vb2_dma_contig_memops.cookie(shot_cookie);
+ pipeline->shot_paddr = *fw_phy_addr;
+ pipeline->shot_vaddr =
+ (unsigned int) vb2_dma_contig_memops.vaddr(shot_cookie);
+
+ return 0;
+}
+
+static void fimc_is_pipeline_freemem(struct fimc_is_pipeline *pipeline)
+{
+ if (fw_cookie)
+ vb2_dma_contig_memops.put(fw_cookie);
+ if (shot_cookie)
+ vb2_dma_contig_memops.put(shot_cookie);
+}
+
+static int fimc_is_pipeline_load_firmware(struct fimc_is_pipeline *pipeline)
+{
+ struct firmware *fw_blob;
+ struct fimc_is *is = pipeline->is;
+ int ret;
+
+ ret = request_firmware((const struct firmware **)&fw_blob,
+ "fimc-is-fw.bin", &is->pdev->dev);
+ if (ret != 0) {
+ is_err("Firmware file not found\n");
+ return -EINVAL;
+ }
+ is_dbg(3, "Firmware size : %d\n", fw_blob->size);
+ if (fw_blob->size > FIMC_IS_A5_MEM_SIZE + FIMC_IS_A5_SEN_SIZE) {
+ is_err("Firmware file too big.\n");
+ release_firmware(fw_blob);
+ return -ENOMEM;
+ }
+
+ memcpy((void *)pipeline->minfo->fw_vaddr, fw_blob->data, fw_blob->size);
+ wmb();
+ release_firmware(fw_blob);
+
+ return 0;
+}
+
+static void fimc_is_pipeline_forcedown(struct fimc_is_pipeline *pipeline,
+ bool on)
+{
+ if (on) {
+ is_dbg(3, "Set low poweroff mode\n");
+ writel(0x0, PMUREG_ISP_ARM_OPTION);
+ writel(0x1CF82000, PMUREG_ISP_LOW_POWER_OFF);
+ pipeline->force_down = true;
+ } else {
+ is_dbg(3, "Clear low poweroff mode\n");
+ writel(0xFFFFFFFF, PMUREG_ISP_ARM_OPTION);
+ writel(0x8, PMUREG_ISP_LOW_POWER_OFF);
+ pipeline->force_down = false;
+ }
+}
+
+static int fimc_is_pipeline_power(struct fimc_is_pipeline *pipeline, int on)
+{
+ int ret = 0;
+ u32 timeout;
+ struct fimc_is *is = pipeline->is;
+ struct device *dev = &is->pdev->dev;
+
+ if (on) {
+ /* force poweroff setting */
+ if (pipeline->force_down)
+ fimc_is_pipeline_forcedown(pipeline, false);
+
+ /* FIMC-IS local power enable */
+ ret = pm_runtime_get_sync(dev);
+
+ /* A5 start address setting */
+ writel(pipeline->minfo->fw_paddr, is->interface.regs + BBOAR);
+
+ /* A5 power on*/
+ writel(0x1, PMUREG_ISP_ARM_CONFIGURATION);
+
+ /* enable A5 */
+ writel(0x00018000, PMUREG_ISP_ARM_OPTION);
+ timeout = 1000;
+ while ((__raw_readl(PMUREG_ISP_ARM_STATUS) & 0x1) != 0x1) {
+ if (timeout == 0)
+ is_err("A5 power on failed\n");
+ timeout--;
+ udelay(1);
+ }
+ } else {
+ /* disable A5 */
+ writel(0x10000, PMUREG_ISP_ARM_OPTION);
+ /* A5 power off*/
+ writel(0x0, PMUREG_ISP_ARM_CONFIGURATION);
+
+ /* Check A5 power off status register */
+ timeout = 1000;
+ while (__raw_readl(PMUREG_ISP_ARM_STATUS) & 0x1) {
+ if (timeout == 0) {
+ is_err("A5 power off failed\n");
+ fimc_is_pipeline_forcedown(pipeline, true);
+ }
+ timeout--;
+ udelay(1);
+ }
+
+ writel(0x0, PMUREG_CMU_RESET_ISP_SYS_PWR_REG);
+
+ /* FIMC-IS local power down */
+ pm_runtime_put_sync(dev);
+ }
+
+ return ret;
+}
+
+static int fimc_is_pipeline_load_setfile(struct fimc_is_pipeline *pipeline,
+ unsigned int setfile_addr,
+ unsigned char *setfile_name)
+{
+ struct fimc_is *is = pipeline->is;
+ struct firmware *fw_blob;
+ int ret;
+
+ ret = request_firmware((const struct firmware **)&fw_blob,
+ setfile_name, &is->pdev->dev);
+ if (ret != 0) {
+ is_err("Setfile %s not found\n", setfile_name);
+ return -EINVAL;
+ }
+
+ memcpy((void *)pipeline->minfo->fw_vaddr + setfile_addr,
+ fw_blob->data, fw_blob->size);
+ wmb();
+ release_firmware(fw_blob);
+
+ return 0;
+}
+
+static int fimc_is_pipeline_setfile(struct fimc_is_pipeline *pipeline)
+{
+ struct fimc_is *is = pipeline->is;
+ struct fimc_is_sensor *sensor = pipeline->sensor;
+ int ret;
+ unsigned int setfile_addr;
+
+ /* Get setfile addr from HW */
+ ret = fimc_is_itf_get_setfile_addr(&is->interface,
+ pipeline->instance, &setfile_addr);
+ if (ret < 0) {
+ is_err("Get setfile addr failed.\n");
+ return ret;
+ }
+
+ /* Load setfile */
+ ret = fimc_is_pipeline_load_setfile(pipeline, setfile_addr,
+ sensor->sensor_info->setfile_name);
+ if (ret < 0) {
+ is_err("Load setfile failed.\n");
+ return ret;
+ }
+
+ /* Send HW command */
+ ret = fimc_is_itf_load_setfile(&is->interface, pipeline->instance);
+ if (ret < 0) {
+ is_err("HW Load setfile failed.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int fimc_is_pipeline_isp_setparams(struct fimc_is_pipeline *pipeline,
+ unsigned int enable)
+{
+ struct isp_param *isp_param = &pipeline->is_region->parameter.isp;
+ struct fimc_is *is = pipeline->is;
+ unsigned int indexes, lindex, hindex;
+ unsigned int sensor_width, sensor_height, scc_width, scc_height;
+ unsigned int crop_x, crop_y, isp_width, isp_height;
+ unsigned int sensor_ratio, output_ratio;
+ int ret;
+
+ /* Crop calculation */
+ sensor_width = pipeline->sensor_width;
+ sensor_height = pipeline->sensor_height;
+ scc_width = pipeline->scaler_width[SCALER_SCC];
+ scc_height = pipeline->scaler_height[SCALER_SCC];
+ isp_width = sensor_width;
+ isp_height = sensor_height;
+ crop_x = crop_y = 0;
+
+ sensor_ratio = sensor_width * 1000 / sensor_height;
+ output_ratio = scc_width * 1000 / scc_height;
+
+ if (sensor_ratio == output_ratio) {
+ isp_width = sensor_width;
+ isp_height = sensor_height;
+ } else if (sensor_ratio < output_ratio) {
+ isp_height = (sensor_width * scc_height) / scc_width;
+ isp_height = ALIGN(isp_height, 2);
+ crop_y = ((sensor_height - isp_height) >> 1) & 0xFFFFFFFE;
+ } else {
+ isp_width = (sensor_height * scc_width) / scc_height;
+ isp_width = ALIGN(isp_width, 4);
+ crop_x = ((sensor_width - isp_width) >> 1) & 0xFFFFFFFE;
+ }
+ pipeline->isp_width = isp_width;
+ pipeline->isp_height = isp_height;
+
+ indexes = hindex = lindex = 0;
+
+ isp_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
+ isp_param->otf_output.width = pipeline->sensor_width;
+ isp_param->otf_output.height = pipeline->sensor_height;
+ isp_param->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
+ isp_param->otf_output.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT;
+ isp_param->otf_output.order = OTF_INPUT_ORDER_BAYER_GR_BG;
+ lindex |= LOWBIT_OF(PARAM_ISP_OTF_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_ISP_OTF_OUTPUT);
+ indexes++;
+
+ isp_param->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
+ lindex |= LOWBIT_OF(PARAM_ISP_DMA1_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_ISP_DMA1_OUTPUT);
+ indexes++;
+
+ isp_param->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
+ lindex |= LOWBIT_OF(PARAM_ISP_DMA2_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_ISP_DMA2_OUTPUT);
+ indexes++;
+
+ if (enable)
+ isp_param->control.bypass = CONTROL_BYPASS_DISABLE;
+ else
+ isp_param->control.bypass = CONTROL_BYPASS_ENABLE;
+ isp_param->control.cmd = CONTROL_COMMAND_START;
+ isp_param->control.run_mode = 1;
+ lindex |= LOWBIT_OF(PARAM_ISP_CONTROL);
+ hindex |= HIGHBIT_OF(PARAM_ISP_CONTROL);
+ indexes++;
+
+ isp_param->dma1_input.cmd = DMA_INPUT_COMMAND_BUF_MNGR;
+ isp_param->dma1_input.width = sensor_width;
+ isp_param->dma1_input.height = sensor_height;
+ isp_param->dma1_input.uidmacropoffsetx = crop_x;
+ isp_param->dma1_input.uidmacropoffsety = crop_y;
+ isp_param->dma1_input.uidmacropwidth = isp_width;
+ isp_param->dma1_input.uidmacropheight = isp_height;
+ isp_param->dma1_input.uibayercropoffsetx = 0;
+ isp_param->dma1_input.uibayercropoffsety = 0;
+ isp_param->dma1_input.uibayercropwidth = 0;
+ isp_param->dma1_input.uibayercropheight = 0;
+ isp_param->dma1_input.uiuserminframetime = 0;
+ isp_param->dma1_input.uiusermaxframetime = 66666;
+ isp_param->dma1_input.uiwideframegap = 1;
+ isp_param->dma1_input.uiframegap = 4096;
+ isp_param->dma1_input.uilinegap = 45;
+ isp_param->dma1_input.order = DMA_INPUT_ORDER_GR_BG;
+ isp_param->dma1_input.plane = 1;
+ isp_param->dma1_input.buffer_number = 1;
+ isp_param->dma1_input.buffer_address = 0;
+ isp_param->dma1_input.uireserved[1] = 0;
+ isp_param->dma1_input.uireserved[2] = 0;
+ if (pipeline->isp.fmt->fourcc == V4L2_PIX_FMT_SGRBG8)
+ isp_param->dma1_input.bitwidth = DMA_INPUT_BIT_WIDTH_8BIT;
+ else if (pipeline->isp.fmt->fourcc == V4L2_PIX_FMT_SGRBG10)
+ isp_param->dma1_input.bitwidth = DMA_INPUT_BIT_WIDTH_10BIT;
+ else
+ isp_param->dma1_input.bitwidth = DMA_INPUT_BIT_WIDTH_12BIT;
+ lindex |= LOWBIT_OF(PARAM_ISP_DMA1_INPUT);
+ hindex |= HIGHBIT_OF(PARAM_ISP_DMA1_INPUT);
+ indexes++;
+
+ lindex = 0xFFFFFFFF;
+ hindex = 0xFFFFFFFF;
+
+ wmb();
+ ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+ indexes, lindex, hindex);
+ if (ret) {
+ is_err("fimc_is_itf_set_param failed\n");
+ return -EINVAL;
+ }
+
+ set_bit(COMP_ENABLE, &pipeline->comp_state[IS_ISP]);
+
+ return 0;
+}
+
+static int fimc_is_pipeline_drc_setparams(struct fimc_is_pipeline *pipeline,
+ unsigned int enable)
+{
+ struct drc_param *drc_param = &pipeline->is_region->parameter.drc;
+ struct fimc_is *is = pipeline->is;
+ int ret;
+ unsigned int indexes, lindex, hindex;
+
+ indexes = hindex = lindex = 0;
+ if (enable)
+ drc_param->control.bypass = CONTROL_BYPASS_DISABLE;
+ else
+ drc_param->control.bypass = CONTROL_BYPASS_ENABLE;
+ lindex |= LOWBIT_OF(PARAM_DRC_CONTROL);
+ hindex |= HIGHBIT_OF(PARAM_DRC_CONTROL);
+ indexes++;
+
+ drc_param->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
+ drc_param->otf_input.width = pipeline->isp_width;
+ drc_param->otf_input.height = pipeline->isp_height;
+ lindex |= LOWBIT_OF(PARAM_DRC_OTF_INPUT);
+ hindex |= HIGHBIT_OF(PARAM_DRC_OTF_INPUT);
+ indexes++;
+
+ drc_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
+ drc_param->otf_output.width = pipeline->isp_width;
+ drc_param->otf_output.height = pipeline->isp_height;
+ lindex |= LOWBIT_OF(PARAM_DRC_OTF_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_DRC_OTF_OUTPUT);
+ indexes++;
+
+ wmb();
+ ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+ indexes, lindex, hindex);
+ if (ret) {
+ is_err("fimc_is_itf_set_param failed\n");
+ return -EINVAL;
+ }
+ if (enable)
+ set_bit(COMP_ENABLE, &pipeline->comp_state[IS_DRC]);
+ else
+ clear_bit(COMP_ENABLE, &pipeline->comp_state[IS_DRC]);
+
+ return 0;
+}
+
+static int fimc_is_pipeline_scc_setparams(struct fimc_is_pipeline *pipeline,
+ unsigned int enable)
+{
+ struct scalerc_param *scc_param =
+ &pipeline->is_region->parameter.scalerc;
+ struct fimc_is *is = pipeline->is;
+ int ret;
+ unsigned int indexes, lindex, hindex;
+ unsigned int scc_width, scc_height;
+
+ scc_width = pipeline->scaler_width[SCALER_SCC];
+ scc_height = pipeline->scaler_height[SCALER_SCC];
+
+ indexes = hindex = lindex = 0;
+ if (enable)
+ scc_param->control.bypass = CONTROL_BYPASS_DISABLE;
+ else
+ scc_param->control.bypass = CONTROL_BYPASS_ENABLE;
+ lindex |= LOWBIT_OF(PARAM_SCALERC_CONTROL);
+ hindex |= HIGHBIT_OF(PARAM_SCALERC_CONTROL);
+ indexes++;
+
+ scc_param->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
+ scc_param->otf_input.width = pipeline->isp_width;
+ scc_param->otf_input.height = pipeline->isp_height;
+ lindex |= LOWBIT_OF(PARAM_SCALERC_OTF_INPUT);
+ hindex |= HIGHBIT_OF(PARAM_SCALERC_OTF_INPUT);
+ indexes++;
+
+ /* SCC OUTPUT */
+ scc_param->input_crop.cmd = SCALER_CROP_COMMAND_ENABLE;
+ scc_param->input_crop.pos_x = 0;
+ scc_param->input_crop.pos_y = 0;
+ scc_param->input_crop.crop_width = pipeline->isp_width;
+ scc_param->input_crop.crop_height = pipeline->isp_height;
+ scc_param->input_crop.in_width = pipeline->isp_width;
+ scc_param->input_crop.in_height = pipeline->isp_height;
+ scc_param->input_crop.out_width = scc_width;
+ scc_param->input_crop.out_height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_SCALERC_INPUT_CROP);
+ hindex |= HIGHBIT_OF(PARAM_SCALERC_INPUT_CROP);
+ indexes++;
+
+ scc_param->output_crop.cmd = SCALER_CROP_COMMAND_DISABLE;
+ scc_param->output_crop.pos_x = 0;
+ scc_param->output_crop.pos_y = 0;
+ scc_param->output_crop.crop_width = scc_width;
+ scc_param->output_crop.crop_height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_SCALERC_OUTPUT_CROP);
+ hindex |= HIGHBIT_OF(PARAM_SCALERC_OUTPUT_CROP);
+ indexes++;
+
+ scc_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
+ scc_param->otf_output.width = scc_width;
+ scc_param->otf_output.height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_SCALERC_OTF_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_SCALERC_OTF_OUTPUT);
+ indexes++;
+
+ scc_param->dma_output.width = scc_width;
+ scc_param->dma_output.height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+ indexes++;
+
+ wmb();
+ ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+ indexes, lindex, hindex);
+ if (ret) {
+ is_err("fimc_is_itf_set_param failed\n");
+ return -EINVAL;
+ }
+ set_bit(COMP_ENABLE, &pipeline->comp_state[IS_SCC]);
+ return 0;
+}
+
+static int fimc_is_pipeline_odc_setparams(struct fimc_is_pipeline *pipeline,
+ unsigned int enable)
+{
+ struct odc_param *odc_param = &pipeline->is_region->parameter.odc;
+ struct fimc_is *is = pipeline->is;
+ int ret;
+ unsigned int indexes, lindex, hindex;
+ unsigned int scc_width, scc_height;
+
+ scc_width = pipeline->scaler_width[SCALER_SCC];
+ scc_height = pipeline->scaler_height[SCALER_SCC];
+
+ indexes = hindex = lindex = 0;
+ if (enable)
+ odc_param->control.bypass = CONTROL_BYPASS_DISABLE;
+ else
+ odc_param->control.bypass = CONTROL_BYPASS_ENABLE;
+ lindex |= LOWBIT_OF(PARAM_ODC_CONTROL);
+ hindex |= HIGHBIT_OF(PARAM_ODC_CONTROL);
+ indexes++;
+
+ odc_param->otf_input.width = scc_width;
+ odc_param->otf_input.height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_ODC_OTF_INPUT);
+ hindex |= HIGHBIT_OF(PARAM_ODC_OTF_INPUT);
+ indexes++;
+
+ odc_param->otf_output.width = scc_width;
+ odc_param->otf_output.height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_ODC_OTF_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_ODC_OTF_OUTPUT);
+ indexes++;
+
+ wmb();
+ ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+ indexes, lindex, hindex);
+ if (ret) {
+ is_err("fimc_is_itf_set_param failed\n");
+ return -EINVAL;
+ }
+ if (enable)
+ set_bit(COMP_ENABLE, &pipeline->comp_state[IS_ODC]);
+ else
+ clear_bit(COMP_ENABLE, &pipeline->comp_state[IS_ODC]);
+
+ return 0;
+}
+
+static int fimc_is_pipeline_dis_setparams(struct fimc_is_pipeline *pipeline,
+ unsigned int enable)
+{
+ struct dis_param *dis_param = &pipeline->is_region->parameter.dis;
+ struct fimc_is *is = pipeline->is;
+ int ret;
+ unsigned int indexes, lindex, hindex;
+ unsigned int scc_width, scc_height;
+
+ scc_width = pipeline->scaler_width[SCALER_SCC];
+ scc_height = pipeline->scaler_height[SCALER_SCC];
+
+ indexes = hindex = lindex = 0;
+ if (enable)
+ dis_param->control.bypass = CONTROL_BYPASS_DISABLE;
+ else
+ dis_param->control.bypass = CONTROL_BYPASS_ENABLE;
+ lindex |= LOWBIT_OF(PARAM_DIS_CONTROL);
+ hindex |= HIGHBIT_OF(PARAM_DIS_CONTROL);
+ indexes++;
+
+ /* DIS INPUT */
+ dis_param->otf_input.width = scc_width;
+ dis_param->otf_input.height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_DIS_OTF_INPUT);
+ hindex |= HIGHBIT_OF(PARAM_DIS_OTF_INPUT);
+ indexes++;
+
+ /* DIS OUTPUT */
+ dis_param->otf_output.width = scc_width;
+ dis_param->otf_output.height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_DIS_OTF_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_DIS_OTF_OUTPUT);
+ indexes++;
+
+ wmb();
+ ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+ indexes, lindex, hindex);
+ if (ret) {
+ is_err("fimc_is_itf_set_param failed\n");
+ return -EINVAL;
+ }
+ if (enable)
+ set_bit(COMP_ENABLE, &pipeline->comp_state[IS_DIS]);
+ else
+ clear_bit(COMP_ENABLE, &pipeline->comp_state[IS_DIS]);
+
+ return 0;
+}
+
+static int fimc_is_pipeline_3dnr_setparams(struct fimc_is_pipeline *pipeline,
+ unsigned int enable)
+{
+ struct tdnr_param *tdnr_param = &pipeline->is_region->parameter.tdnr;
+ struct fimc_is *is = pipeline->is;
+ int ret;
+ unsigned int indexes, lindex, hindex;
+ unsigned int scc_width, scc_height;
+
+ scc_width = pipeline->scaler_width[SCALER_SCC];
+ scc_height = pipeline->scaler_height[SCALER_SCC];
+
+ indexes = hindex = lindex = 0;
+ if (enable)
+ tdnr_param->control.bypass = CONTROL_BYPASS_DISABLE;
+ else
+ tdnr_param->control.bypass = CONTROL_BYPASS_ENABLE;
+ lindex |= LOWBIT_OF(PARAM_TDNR_CONTROL);
+ hindex |= HIGHBIT_OF(PARAM_TDNR_CONTROL);
+ indexes++;
+
+ tdnr_param->otf_input.width = scc_width;
+ tdnr_param->otf_input.height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_TDNR_OTF_INPUT);
+ hindex |= HIGHBIT_OF(PARAM_TDNR_OTF_INPUT);
+ indexes++;
+
+ tdnr_param->dma_output.width = scc_width;
+ tdnr_param->dma_output.height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_TDNR_DMA_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_TDNR_DMA_OUTPUT);
+ indexes++;
+
+ tdnr_param->otf_output.width = scc_width;
+ tdnr_param->otf_output.height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_TDNR_OTF_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_TDNR_OTF_OUTPUT);
+ indexes++;
+
+ wmb();
+ ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+ indexes, lindex, hindex);
+ if (ret) {
+ is_err("fimc_is_itf_set_param failed\n");
+ return -EINVAL;
+ }
+ if (enable)
+ set_bit(COMP_ENABLE, &pipeline->comp_state[IS_TDNR]);
+ else
+ clear_bit(COMP_ENABLE, &pipeline->comp_state[IS_TDNR]);
+
+ return 0;
+}
+
+static int fimc_is_pipeline_scp_setparams(struct fimc_is_pipeline *pipeline,
+ unsigned int enable)
+{
+ struct scalerp_param *scp_param =
+ &pipeline->is_region->parameter.scalerp;
+ struct fimc_is *is = pipeline->is;
+ int ret;
+ unsigned int indexes, lindex, hindex;
+ unsigned int scc_width, scc_height;
+ unsigned int scp_width, scp_height;
+
+ scc_width = pipeline->scaler_width[SCALER_SCC];
+ scc_height = pipeline->scaler_height[SCALER_SCC];
+ scp_width = pipeline->scaler_width[SCALER_SCP];
+ scp_height = pipeline->scaler_height[SCALER_SCP];
+
+ indexes = hindex = lindex = 0;
+ if (enable)
+ scp_param->control.bypass = CONTROL_BYPASS_DISABLE;
+ else
+ scp_param->control.bypass = CONTROL_BYPASS_ENABLE;
+ lindex |= LOWBIT_OF(PARAM_SCALERP_CONTROL);
+ hindex |= HIGHBIT_OF(PARAM_SCALERP_CONTROL);
+ indexes++;
+
+ /* SCP Input */
+ scp_param->otf_input.width = scc_width;
+ scp_param->otf_input.height = scc_height;
+ lindex |= LOWBIT_OF(PARAM_SCALERP_OTF_INPUT);
+ hindex |= HIGHBIT_OF(PARAM_SCALERP_OTF_INPUT);
+ indexes++;
+
+ /* SCP Output */
+ scp_param->input_crop.cmd = SCALER_CROP_COMMAND_ENABLE;
+ scp_param->input_crop.pos_x = 0;
+ scp_param->input_crop.pos_y = 0;
+ scp_param->input_crop.crop_width = scc_width;
+ scp_param->input_crop.crop_height = scc_height;
+ scp_param->input_crop.in_width = scc_width;
+ scp_param->input_crop.in_height = scc_height;
+ scp_param->input_crop.out_width = scp_width;
+ scp_param->input_crop.out_height = scp_height;
+ lindex |= LOWBIT_OF(PARAM_SCALERP_INPUT_CROP);
+ hindex |= HIGHBIT_OF(PARAM_SCALERP_INPUT_CROP);
+ indexes++;
+
+ scp_param->output_crop.cmd = SCALER_CROP_COMMAND_DISABLE;
+ lindex |= LOWBIT_OF(PARAM_SCALERP_OUTPUT_CROP);
+ hindex |= HIGHBIT_OF(PARAM_SCALERP_OUTPUT_CROP);
+ indexes++;
+
+ scp_param->otf_output.width = scp_width;
+ scp_param->otf_output.height = scp_height;
+ lindex |= LOWBIT_OF(PARAM_SCALERP_OTF_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_SCALERP_OTF_OUTPUT);
+ indexes++;
+
+ scp_param->dma_output.width = scp_width;
+ scp_param->dma_output.height = scp_height;
+ lindex |= LOWBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+ indexes++;
+
+ wmb();
+ ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+ indexes, lindex, hindex);
+ if (ret) {
+ is_err("fimc_is_itf_set_param failed\n");
+ return -EINVAL;
+ }
+ set_bit(COMP_ENABLE, &pipeline->comp_state[IS_SCP]);
+
+ return 0;
+}
+
+static int fimc_is_pipeline_fd_setparams(struct fimc_is_pipeline *pipeline,
+ unsigned int enable)
+{
+ struct fd_param *fd_param = &pipeline->is_region->parameter.fd;
+ struct fimc_is *is = pipeline->is;
+ int ret;
+ unsigned int indexes, lindex, hindex;
+
+ indexes = hindex = lindex = 0;
+ if (enable)
+ fd_param->control.bypass = CONTROL_BYPASS_DISABLE;
+ else
+ fd_param->control.bypass = CONTROL_BYPASS_ENABLE;
+ lindex |= LOWBIT_OF(PARAM_FD_CONTROL);
+ hindex |= HIGHBIT_OF(PARAM_FD_CONTROL);
+ indexes++;
+
+ fd_param->otf_input.width = pipeline->scaler_width[SCALER_SCP];
+ fd_param->otf_input.height = pipeline->scaler_height[SCALER_SCP];
+ lindex |= LOWBIT_OF(PARAM_FD_OTF_INPUT);
+ hindex |= HIGHBIT_OF(PARAM_FD_OTF_INPUT);
+ indexes++;
+
+ wmb();
+ ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+ indexes, lindex, hindex);
+ if (ret) {
+ is_err("fimc_is_itf_set_param failed\n");
+ return -EINVAL;
+ }
+ if (enable)
+ set_bit(COMP_ENABLE, &pipeline->comp_state[IS_FD]);
+ else
+ clear_bit(COMP_ENABLE, &pipeline->comp_state[IS_FD]);
+
+ return 0;
+}
+
+void fimc_is_pipeline_buf_lock(struct fimc_is_pipeline *pipeline)
+{
+ spin_lock_irqsave(&pipeline->slock_buf, pipeline->slock_flags);
+}
+
+void fimc_is_pipeline_buf_unlock(struct fimc_is_pipeline *pipeline)
+{
+ spin_unlock_irqrestore(&pipeline->slock_buf, pipeline->slock_flags);
+}
+
+int fimc_is_pipeline_setparams(struct fimc_is_pipeline *pipeline)
+{
+ int ret;
+
+ /* Enabling basic components in pipeline */
+ ret = fimc_is_pipeline_isp_setparams(pipeline, true);
+ ret |= fimc_is_pipeline_drc_setparams(pipeline, false);
+ ret |= fimc_is_pipeline_scc_setparams(pipeline, true);
+ ret |= fimc_is_pipeline_odc_setparams(pipeline, false);
+ ret |= fimc_is_pipeline_dis_setparams(pipeline, false);
+ ret |= fimc_is_pipeline_3dnr_setparams(pipeline, false);
+ ret |= fimc_is_pipeline_scp_setparams(pipeline, true);
+ ret |= fimc_is_pipeline_fd_setparams(pipeline, false);
+ if (ret < 0)
+ is_err("Pipeline setparam failed.\n");
+
+ return ret;
+}
+
+int fimc_is_pipeline_scaler_start(struct fimc_is_pipeline *pipeline,
+ enum fimc_is_scaler_id scaler_id,
+ unsigned int **buf_paddr,
+ unsigned int num_bufs,
+ unsigned int num_planes)
+{
+ struct fimc_is *is = pipeline->is;
+ struct scalerp_param *scp_param =
+ &pipeline->is_region->parameter.scalerp;
+ struct scalerc_param *scc_param =
+ &pipeline->is_region->parameter.scalerc;
+ struct param_dma_output *dma_output;
+ struct fimc_is_fmt *fmt;
+ unsigned int region_index;
+ unsigned long *comp_state;
+ int ret;
+ unsigned int pipe_start_flag = 0;
+ unsigned int i, j, buf_index, buf_mask = 0;
+ unsigned int indexes, lindex, hindex;
+
+ if (!test_bit(PIPELINE_OPEN, &pipeline->state)) {
+ is_err("Pipeline not opened.\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&pipeline->pipe_scl_lock);
+
+ if (test_bit(PIPELINE_START, &pipeline->state)) {
+ /* Pipeline is started.
+ * Stop it now to set params and start again */
+ ret = fimc_is_pipeline_stop(pipeline);
+ if (ret) {
+ is_err("Not able to stop pipeline\n");
+ goto exit;
+ }
+ pipe_start_flag = 1;
+ }
+
+ indexes = lindex = hindex = 0;
+
+ if (scaler_id == SCALER_SCC) {
+ dma_output = &scc_param->dma_output;
+ region_index = FIMC_IS_SCC_REGION_INDEX;
+ comp_state = &pipeline->comp_state[IS_SCC];
+ fmt = pipeline->scaler[SCALER_SCC].fmt;
+ lindex |= LOWBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+ } else {
+ dma_output = &scp_param->dma_output;
+ comp_state = &pipeline->comp_state[IS_SCP];
+ fmt = pipeline->scaler[SCALER_SCC].fmt;
+ region_index = FIMC_IS_SCP_REGION_INDEX;
+ lindex |= LOWBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+ }
+ indexes++;
+
+ for (i = 0; i < num_bufs; i++) {
+ for (j = 0; j < num_planes; j++) {
+ buf_index = i * num_planes + j;
+ pipeline->is_region->shared[region_index + buf_index] =
+ (unsigned int) &buf_paddr[i][j];
+ }
+ buf_mask |= (1 << i);
+ }
+
+ dma_output->cmd = DMA_OUTPUT_COMMAND_ENABLE;
+ dma_output->dma_out_mask = buf_mask;
+ dma_output->buffer_number = num_bufs;
+ dma_output->plane = num_planes;
+ if ((fmt->fourcc == V4L2_PIX_FMT_YUV420M) ||
+ (fmt->fourcc == V4L2_PIX_FMT_NV12M))
+ dma_output->format = DMA_OUTPUT_FORMAT_YUV420;
+ else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
+ dma_output->format = DMA_OUTPUT_FORMAT_YUV422;
+
+ dma_output->buffer_address = pipeline->minfo->shared_paddr +
+ region_index * sizeof(unsigned int);
+
+ ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+ indexes, lindex, hindex);
+ if (ret)
+ pr_err("fimc_is_itf_set_param is fail\n");
+ else
+ set_bit(COMP_START, comp_state);
+
+ if (pipe_start_flag) {
+ ret = fimc_is_pipeline_start(pipeline);
+ if (ret) {
+ is_err("Not able to start pipeline back\n");
+ goto exit;
+ }
+ }
+
+exit:
+ mutex_unlock(&pipeline->pipe_scl_lock);
+ return ret;
+}
+
+int fimc_is_pipeline_scaler_stop(struct fimc_is_pipeline *pipeline,
+ enum fimc_is_scaler_id scaler_id)
+{
+ struct fimc_is *is = pipeline->is;
+ struct scalerp_param *scp_param =
+ &pipeline->is_region->parameter.scalerp;
+ struct scalerc_param *scc_param =
+ &pipeline->is_region->parameter.scalerc;
+ struct param_dma_output *dma_output;
+ unsigned int pipe_start_flag = 0;
+ unsigned int indexes, lindex, hindex;
+ unsigned long *comp_state;
+ int ret;
+
+ if (!test_bit(PIPELINE_OPEN, &pipeline->state))
+ return -EINVAL;
+
+ mutex_lock(&pipeline->pipe_scl_lock);
+
+ if (test_bit(PIPELINE_START, &pipeline->state)) {
+ /* Pipeline is started.
+ * Stop it now to set params and start again */
+ ret = fimc_is_pipeline_stop(pipeline);
+ if (ret) {
+ is_err("Not able to stop pipeline\n");
+ goto exit;
+ }
+ pipe_start_flag = 1;
+ }
+
+ comp_state = (scaler_id == SCALER_SCC) ?
+ &pipeline->comp_state[IS_SCC] : &pipeline->comp_state[IS_SCP];
+
+ if (!test_bit(COMP_START, comp_state)) {
+ is_dbg(1, "Scaler not started\n");
+ ret = 0;
+ goto exit;
+ }
+
+ if (!test_bit(PIPELINE_START, &pipeline->state)) {
+ is_err("Pipeline not started.\n");
+ ret = -EINVAL;
+ goto exit;
+ }
+
+ indexes = lindex = hindex = 0;
+
+ if (scaler_id == SCALER_SCC) {
+ dma_output = &scc_param->dma_output;
+ lindex |= LOWBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+ } else {
+ dma_output = &scp_param->dma_output;
+ lindex |= LOWBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+ hindex |= HIGHBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+ }
+ indexes++;
+ dma_output->cmd = DMA_OUTPUT_COMMAND_DISABLE;
+
+ ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+ indexes, lindex, hindex);
+ if (ret < 0)
+ pr_err("fimc_is_itf_set_param is fail\n");
+ else
+ clear_bit(COMP_START, comp_state);
+
+ if (pipe_start_flag) {
+ ret = fimc_is_pipeline_start(pipeline);
+ if (ret) {
+ is_err("Not able to start pipeline back\n");
+ return -EINVAL;
+ }
+ }
+
+exit:
+ mutex_unlock(&pipeline->pipe_scl_lock);
+ return ret;
+}
+
+void fimc_is_pipeline_config_shot(struct fimc_is_pipeline *pipeline)
+{
+ struct camera2_shot *shot =
+ (struct camera2_shot *)pipeline->shot_vaddr;
+
+ shot->magicnumber = 0x23456789;
+
+ shot->ctl.aa.mode = AA_CONTROL_AUTO;
+ shot->ctl.aa.aemode = AA_AEMODE_ON;
+}
+
+int fimc_is_pipeline_shot(struct fimc_is_pipeline *pipeline)
+{
+ struct fimc_is *is = pipeline->is;
+ int ret;
+ unsigned int rcount;
+ struct camera2_shot *shot =
+ (struct camera2_shot *)pipeline->shot_vaddr;
+ struct fimc_is_buf *scc_buf, *scp_buf, *bayer_buf;
+
+ if (!test_bit(PIPELINE_START, &pipeline->state)) {
+ /* Pipeline not started yet */
+ is_err("\n");
+ return -EINVAL;
+ }
+
+ if (test_bit(PIPELINE_RUN, &pipeline->state)) {
+ /* Pipeline busy. Caller need to wait */
+ is_err("\n");
+ return -EBUSY;
+ }
+
+ fimc_is_pipeline_buf_lock(pipeline);
+
+ if (list_empty(&pipeline->isp.wait_queue)) {
+ /* No more bayer buffers */
+ wake_up(&pipeline->wait_q);
+ fimc_is_pipeline_buf_unlock(pipeline);
+ return 0;
+ }
+
+ /* Set the state as RUN */
+ set_bit(PIPELINE_RUN, &pipeline->state);
+
+ /* Get bayer input buffer */
+ bayer_buf = fimc_is_isp_wait_queue_get(&pipeline->isp);
+ if (!bayer_buf) {
+ fimc_is_pipeline_buf_unlock(pipeline);
+ goto err_exit;
+ }
+ fimc_is_isp_run_queue_add(&pipeline->isp, bayer_buf);
+
+ /* Get SCC buffer */
+ if (test_bit(COMP_START, &pipeline->comp_state[IS_SCC]) &&
+ !list_empty(&pipeline->scaler[SCALER_SCC].wait_queue)) {
+ scc_buf = fimc_is_scaler_wait_queue_get(
+ &pipeline->scaler[SCALER_SCC]);
+ if (scc_buf) {
+ fimc_is_scaler_run_queue_add(
+ &pipeline->scaler[SCALER_SCC],
+ scc_buf);
+ shot->uctl.scalerud.scctargetaddress[0] =
+ scc_buf->paddr[0];
+ shot->uctl.scalerud.scctargetaddress[1] =
+ scc_buf->paddr[1];
+ shot->uctl.scalerud.scctargetaddress[2] =
+ scc_buf->paddr[2];
+ set_bit(COMP_RUN, &pipeline->comp_state[IS_SCC]);
+ }
+ } else {
+ is_dbg(3, "No SCC buffer available\n");
+ shot->uctl.scalerud.scctargetaddress[0] = 0;
+ shot->uctl.scalerud.scctargetaddress[1] = 0;
+ shot->uctl.scalerud.scctargetaddress[2] = 0;
+ }
+
+ /* Get SCP buffer */
+ if (test_bit(COMP_START, &pipeline->comp_state[IS_SCP]) &&
+ !list_empty(&pipeline->scaler[SCALER_SCP].wait_queue)) {
+ scp_buf = fimc_is_scaler_wait_queue_get(
+ &pipeline->scaler[SCALER_SCP]);
+ if (scp_buf) {
+ fimc_is_scaler_run_queue_add(
+ &pipeline->scaler[SCALER_SCP],
+ scp_buf);
+ shot->uctl.scalerud.scptargetaddress[0] =
+ scp_buf->paddr[0];
+ shot->uctl.scalerud.scptargetaddress[1] =
+ scp_buf->paddr[1];
+ shot->uctl.scalerud.scptargetaddress[2] =
+ scp_buf->paddr[2];
+ set_bit(COMP_RUN, &pipeline->comp_state[IS_SCP]);
+ }
+ } else {
+ is_dbg(3, "No SCP buffer available\n");
+ shot->uctl.scalerud.scptargetaddress[0] = 0;
+ shot->uctl.scalerud.scptargetaddress[1] = 0;
+ shot->uctl.scalerud.scptargetaddress[2] = 0;
+ }
+ fimc_is_pipeline_buf_unlock(pipeline);
+
+ /* Send shot command */
+ pipeline->fcount++;
+ rcount = pipeline->fcount;
+ shot->ctl.request.framecount = pipeline->fcount;
+ is_dbg(3, "Shot command fcount : %d, Bayer addr : 0x%08x\n",
+ pipeline->fcount, bayer_buf->paddr[0]);
+ ret = fimc_is_itf_shot_nblk(&is->interface, pipeline->instance,
+ bayer_buf->paddr[0],
+ pipeline->shot_paddr,
+ pipeline->fcount,
+ rcount);
+ if (ret < 0) {
+ is_err("Shot command failed.\n");
+ goto err_exit;
+ }
+ return 0;
+
+err_exit:
+ clear_bit(PIPELINE_RUN, &pipeline->state);
+ clear_bit(COMP_RUN, &pipeline->comp_state[IS_SCC]);
+ clear_bit(COMP_RUN, &pipeline->comp_state[IS_SCP]);
+ return -EINVAL;
+}
+
+int fimc_is_pipeline_start(struct fimc_is_pipeline *pipeline)
+{
+ int ret;
+ struct fimc_is *is = pipeline->is;
+
+ /* Check if open or not */
+ if (!test_bit(PIPELINE_OPEN, &pipeline->state)) {
+ is_err("Pipeline not open.\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&pipeline->pipe_lock);
+
+ /* Check if already started */
+ if (test_bit(PIPELINE_START, &pipeline->state)) {
+ is_dbg(3, "Pipeline already started.\n");
+ mutex_unlock(&pipeline->pipe_lock);
+ return 0;
+ }
+
+ /* Set pipeline component params */
+ ret = fimc_is_pipeline_setparams(pipeline);
+ if (ret < 0) {
+ is_err("Set params failed\n");
+ goto err_exit;
+ }
+
+ /* Send preview still command */
+ ret = fimc_is_itf_preview_still(&is->interface, pipeline->instance);
+ if (ret) {
+ is_err("Preview still command failed\n");
+ goto err_exit;
+ }
+
+ /* Confiture shot memory to A5 */
+ ret = fimc_is_itf_cfg_mem(&is->interface, pipeline->instance,
+ pipeline->shot_paddr, sizeof(struct camera2_shot));
+ if (ret < 0) {
+ is_err("Config A5 mem failed.\n");
+ goto err_exit;
+ }
+
+ /* Set shot params */
+ fimc_is_pipeline_config_shot(pipeline);
+
+ /* Process ON command */
+ ret = fimc_is_itf_process_on(&is->interface, pipeline->instance);
+ if (ret) {
+ is_err("Process on failed\n");
+ goto err_exit;
+ }
+
+ /* Stream ON */
+ ret = fimc_is_itf_stream_on(&is->interface, pipeline->instance);
+ if (ret < 0) {
+ is_err("Stream On failed.\n");
+ goto err_exit;
+ }
+
+ /* Set state to START */
+ set_bit(PIPELINE_START, &pipeline->state);
+
+ mutex_unlock(&pipeline->pipe_lock);
+ return 0;
+
+err_exit:
+ mutex_unlock(&pipeline->pipe_lock);
+ return ret;
+}
+
+int fimc_is_pipeline_stop(struct fimc_is_pipeline *pipeline)
+{
+ int ret;
+ struct fimc_is *is = pipeline->is;
+
+ mutex_lock(&pipeline->pipe_lock);
+
+ /* Check if started */
+ if (!test_bit(PIPELINE_OPEN, &pipeline->state) ||
+ !test_bit(PIPELINE_START, &pipeline->state)) {
+ is_dbg(3, "Pipeline not open/started.\n");
+ ret = -EINVAL;
+ goto err_exit;
+ }
+
+ /* Wait if any operation is in progress */
+ ret = wait_event_timeout(pipeline->wait_q,
+ !test_bit(PIPELINE_RUN, &pipeline->state),
+ FIMC_IS_COMMAND_TIMEOUT);
+ if (!ret) {
+ is_err("Pipeline timeout");
+ ret = -EBUSY;
+ goto err_exit;
+ }
+
+ /* Wait for scaler operations if any to complete */
+ ret = wait_event_timeout(pipeline->scaler[SCALER_SCC].event_q,
+ !test_bit(COMP_RUN, &pipeline->comp_state[IS_SCC]),
+ FIMC_IS_COMMAND_TIMEOUT);
+ if (!ret) {
+ is_err("SCC timeout");
+ ret = -EBUSY;
+ goto err_exit;
+ }
+ ret = wait_event_timeout(pipeline->scaler[SCALER_SCP].event_q,
+ !test_bit(COMP_RUN, &pipeline->comp_state[IS_SCP]),
+ FIMC_IS_COMMAND_TIMEOUT);
+ if (!ret) {
+ is_err("SCP timeout");
+ ret = -EBUSY;
+ goto err_exit;
+ }
+
+
+ /* Process OFF */
+ ret = fimc_is_itf_process_off(&is->interface, pipeline->instance);
+ if (ret) {
+ is_err("Process off failed\n");
+ ret = -EINVAL;
+ goto err_exit;
+ }
+
+ /* Stream OFF */
+ ret = fimc_is_itf_stream_off(&is->interface, pipeline->instance);
+ if (ret < 0) {
+ is_err("Stream Off failed.\n");
+ ret = -EINVAL;
+ goto err_exit;
+ }
+
+ /* Clear state */
+ clear_bit(PIPELINE_START, &pipeline->state);
+
+ mutex_unlock(&pipeline->pipe_lock);
+ return 0;
+
+err_exit:
+ mutex_unlock(&pipeline->pipe_lock);
+ return ret;
+}
+
+int fimc_is_pipeline_open(struct fimc_is_pipeline *pipeline,
+ struct fimc_is_sensor *sensor)
+{
+ struct fimc_is *is = pipeline->is;
+ struct is_region *region;
+ int ret;
+
+ is_dbg(5, "Pipeline open, instance : %d\n", pipeline->instance);
+
+ mutex_lock(&pipeline->pipe_lock);
+
+ /* Check if already open */
+ if (test_bit(PIPELINE_OPEN, &pipeline->state)) {
+ is_err("Pipeline already open.\n");
+ ret = -EINVAL;
+ goto err_exit;
+ }
+
+ /* Init pipeline params */
+ pipeline->fcount = 0;
+ pipeline->sensor = sensor;
+ pipeline->sensor_width = sensor->sensor_info->active_width;
+ pipeline->sensor_height = sensor->sensor_info->active_height;
+
+ /* Init memory */
+ ret = fimc_is_pipeline_initmem(pipeline, is->alloc_ctx);
+ if (ret < 0) {
+ is_err("Pipeline memory init failed.\n");
+ goto err_exit;
+ }
+
+ /* Load firmware */
+ ret = fimc_is_pipeline_load_firmware(pipeline);
+ if (ret < 0) {
+ is_err("Firmware load failed.\n");
+ goto err_fw;
+ }
+
+ /* Power ON */
+ ret = fimc_is_pipeline_power(pipeline, 1);
+ if (ret < 0) {
+ is_err("A5 power on failed.\n");
+ goto err_fw;
+ }
+
+ /* Wait for FW Init to complete */
+ ret = fimc_is_itf_wait_init_state(&is->interface);
+ if (ret < 0) {
+ is_err("FW init failed.\n");
+ goto err_fw;
+ }
+
+ /* Open Sensor */
+ region = pipeline->is_region;
+ memcpy(®ion->shared[0], &sensor->sensor_info->ext,
+ sizeof(struct fimc_is_sensor_ext));
+ ret = fimc_is_itf_open_sensor(&is->interface,
+ pipeline->instance,
+ sensor->sensor_info->sensor_id,
+ sensor->sensor_info->i2c_ch,
+ pipeline->minfo->shared_paddr);
+ if (ret < 0) {
+ is_err("Open sensor failed\n");
+ goto err_exit;
+ }
+
+ is_dbg(3, "Magic Number : %x\n",
+ pipeline->is_region->shared[MAX_SHARED_COUNT-1]);
+
+ /* Copy init params to FW region */
+ memset(®ion->parameter, 0x0, sizeof(struct is_param_region));
+
+ memcpy(®ion->parameter.sensor, &init_sensor_param,
+ sizeof(struct sensor_param));
+ memcpy(®ion->parameter.isp, &init_isp_param,
+ sizeof(struct isp_param));
+ memcpy(®ion->parameter.drc, &init_drc_param,
+ sizeof(struct drc_param));
+ memcpy(®ion->parameter.scalerc, &init_scalerc_param,
+ sizeof(struct scalerc_param));
+ memcpy(®ion->parameter.odc, &init_odc_param,
+ sizeof(struct odc_param));
+ memcpy(®ion->parameter.dis, &init_dis_param,
+ sizeof(struct dis_param));
+ memcpy(®ion->parameter.tdnr, &init_tdnr_param,
+ sizeof(struct tdnr_param));
+ memcpy(®ion->parameter.scalerp, &init_scalerp_param,
+ sizeof(struct scalerp_param));
+ memcpy(®ion->parameter.fd, &init_fd_param,
+ sizeof(struct fd_param));
+
+ /* Load setfile */
+ ret = fimc_is_pipeline_setfile(pipeline);
+ if (ret < 0)
+ goto err_exit;
+
+ /* Stream off */
+ ret = fimc_is_itf_stream_off(&is->interface, pipeline->instance);
+ if (ret < 0)
+ goto err_exit;
+
+ /* Process off */
+ ret = fimc_is_itf_process_off(&is->interface, pipeline->instance);
+ if (ret < 0)
+ goto err_exit;
+
+ /* Set state to OPEN */
+ set_bit(PIPELINE_OPEN, &pipeline->state);
+
+ mutex_unlock(&pipeline->pipe_lock);
+ return 0;
+
+err_fw:
+ fimc_is_pipeline_freemem(pipeline);
+err_exit:
+ mutex_unlock(&pipeline->pipe_lock);
+ return ret;
+}
+
+int fimc_is_pipeline_close(struct fimc_is_pipeline *pipeline)
+{
+ int ret;
+ struct fimc_is *is = pipeline->is;
+
+ mutex_lock(&pipeline->pipe_lock);
+
+ /* Check if opened */
+ if (!test_bit(PIPELINE_OPEN, &pipeline->state)) {
+ is_err("Pipeline not opened\n");
+ ret = -EINVAL;
+ goto err_exit;
+ }
+
+ /* Stop pipeline */
+ if (test_bit(PIPELINE_START, &pipeline->state)) {
+ is_err("Cannot close pipeline when its started\n");
+ ret = -EINVAL;
+ goto err_exit;
+ }
+
+ /* FW power off command */
+ ret = fimc_is_itf_power_down(&is->interface, pipeline->instance);
+ if (ret)
+ is_err("FW power down error\n");
+
+ /* Pipeline power off*/
+ fimc_is_pipeline_power(pipeline, 0);
+
+ /* Free memory */
+ fimc_is_pipeline_freemem(pipeline);
+
+ clear_bit(PIPELINE_OPEN, &pipeline->state);
+ mutex_unlock(&pipeline->pipe_lock);
+ return 0;
+
+err_exit:
+ mutex_unlock(&pipeline->pipe_lock);
+ return ret;
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-pipeline.h b/drivers/media/platform/exynos5-is/fimc-is-pipeline.h
new file mode 100644
index 0000000..0b0682f
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-pipeline.h
@@ -0,0 +1,129 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_PIPELINE_H_
+#define FIMC_IS_PIPELINE_H_
+
+#include "fimc-is-core.h"
+#include "fimc-is-sensor.h"
+#include "fimc-is-isp.h"
+#include "fimc-is-scaler.h"
+
+#define FIMC_IS_A5_MEM_SIZE (0x00A00000)
+#define FIMC_IS_A5_SEN_SIZE (0x00100000)
+#define FIMC_IS_REGION_SIZE (0x5000)
+#define FIMC_IS_SETFILE_SIZE (0xc0d8)
+#define FIMC_IS_TDNR_MEM_SIZE (1920*1080*4)
+#define FIMC_IS_DEBUG_REGION_ADDR (0x00840000)
+#define FIMC_IS_SHARED_REGION_ADDR (0x008C0000)
+
+#define FIMC_IS_SCP_REGION_INDEX 400
+#define FIMC_IS_SCC_REGION_INDEX 447
+
+#define MAX_ODC_INTERNAL_BUF_WIDTH (2560) /* 4808 in HW */
+#define MAX_ODC_INTERNAL_BUF_HEIGHT (1920) /* 3356 in HW */
+#define SIZE_ODC_INTERNAL_BUF \
+ (MAX_ODC_INTERNAL_BUF_WIDTH * MAX_ODC_INTERNAL_BUF_HEIGHT * 3)
+
+#define MAX_DIS_INTERNAL_BUF_WIDTH (2400)
+#define MAX_DIS_INTERNAL_BUF_HEIGHT (1360)
+#define SIZE_DIS_INTERNAL_BUF \
+ (MAX_DIS_INTERNAL_BUF_WIDTH * MAX_DIS_INTERNAL_BUF_HEIGHT * 2)
+
+#define MAX_3DNR_INTERNAL_BUF_WIDTH (1920)
+#define MAX_3DNR_INTERNAL_BUF_HEIGHT (1088)
+#define SIZE_DNR_INTERNAL_BUF \
+ (MAX_3DNR_INTERNAL_BUF_WIDTH * MAX_3DNR_INTERNAL_BUF_HEIGHT * 2)
+
+#define NUM_ODC_INTERNAL_BUF (2)
+#define NUM_DIS_INTERNAL_BUF (5)
+#define NUM_DNR_INTERNAL_BUF (2)
+
+#define FIMC_IS_FW_BASE_MASK ((1 << 26) - 1)
+
+#define FIMC_IS_NUM_COMPS 8
+
+enum pipeline_state {
+ PIPELINE_INIT,
+ PIPELINE_OPEN,
+ PIPELINE_START,
+ PIPELINE_RUN,
+};
+
+enum is_components {
+ IS_ISP,
+ IS_DRC,
+ IS_SCC,
+ IS_ODC,
+ IS_DIS,
+ IS_TDNR,
+ IS_SCP,
+ IS_FD
+};
+
+enum component_state {
+ COMP_ENABLE,
+ COMP_START,
+ COMP_RUN
+};
+
+struct fimc_is_pipeline {
+ unsigned long state;
+ unsigned long comp_state[FIMC_IS_NUM_COMPS];
+ bool force_down;
+ unsigned int instance;
+ spinlock_t slock_buf;
+ unsigned long slock_flags;
+ wait_queue_head_t wait_q;
+ struct mutex pipe_lock;
+ struct mutex pipe_scl_lock;
+
+ struct fimc_is_meminfo *minfo;
+ struct is_region *is_region;
+
+ void *is;
+ struct fimc_is_sensor *sensor;
+ struct fimc_is_isp isp;
+ struct fimc_is_scaler scaler[FIMC_IS_NUM_SCALERS];
+
+ unsigned int fcount;
+ unsigned int sensor_width;
+ unsigned int sensor_height;
+ unsigned int isp_width;
+ unsigned int isp_height;
+ unsigned int scaler_width[FIMC_IS_NUM_SCALERS];
+ unsigned int scaler_height[FIMC_IS_NUM_SCALERS];
+
+ unsigned int shot_paddr;
+ unsigned int shot_vaddr;
+};
+
+void fimc_is_pipeline_buf_lock(struct fimc_is_pipeline *pipeline);
+void fimc_is_pipeline_buf_unlock(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_setparams(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_scaler_start(struct fimc_is_pipeline *pipeline,
+ enum fimc_is_scaler_id scaler_id,
+ unsigned int **buf_paddr,
+ unsigned int num_bufs,
+ unsigned int num_planes);
+int fimc_is_pipeline_scaler_stop(struct fimc_is_pipeline *pipeline,
+ enum fimc_is_scaler_id scaler_id);
+void fimc_is_pipeline_config_shot(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_shot(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_start(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_stop(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_init(struct fimc_is_pipeline *pipeline,
+ unsigned int instance, void *is_ctx);
+int fimc_is_pipeline_destroy(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_open(struct fimc_is_pipeline *pipeline,
+ struct fimc_is_sensor *sensor);
+int fimc_is_pipeline_close(struct fimc_is_pipeline *pipeline);
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* [RFC 10/12] exynos-fimc-is: Adds the hardware interface module
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
` (8 preceding siblings ...)
2013-03-08 14:59 ` [RFC 09/12] exynos-fimc-is: Adds the hardware pipeline control Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-23 19:01 ` Sylwester Nawrocki
2013-03-08 14:59 ` [RFC 11/12] exynos-fimc-is: Adds the Kconfig and Makefile Arun Kumar K
2013-03-08 14:59 ` [RFC 12/12] mipi-csis: Enable all interrupts for fimc-is usage Arun Kumar K
11 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
The hardware interface module finally sends the commands to the
FIMC-IS firmware and runs the interrupt handler for getting the
responses.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
.../media/platform/exynos5-is/fimc-is-interface.c | 1003 ++++++++++++++++++++
.../media/platform/exynos5-is/fimc-is-interface.h | 130 +++
2 files changed, 1133 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.c b/drivers/media/platform/exynos5-is/fimc-is-interface.c
new file mode 100644
index 0000000..2537220
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.c
@@ -0,0 +1,1003 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-regs.h"
+
+#define init_request_barrier(itf) mutex_init(&itf->request_barrier)
+#define enter_request_barrier(itf) mutex_lock(&itf->request_barrier)
+#define exit_request_barrier(itf) mutex_unlock(&itf->request_barrier)
+
+static inline void itf_get_cmd(struct fimc_is_interface *itf,
+ struct fimc_is_msg *msg, unsigned int index)
+{
+ struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+ switch (index) {
+ case INTR_GENERAL:
+ msg->id = 0;
+ msg->command = com_regs->ihcmd;
+ msg->instance = com_regs->ihc_sensorid;
+ msg->parameter1 = com_regs->ihc_param1;
+ msg->parameter2 = com_regs->ihc_param2;
+ msg->parameter3 = com_regs->ihc_param3;
+ msg->parameter4 = com_regs->ihc_param4;
+ break;
+ case INTR_SCC_FDONE:
+ msg->id = 0;
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->scc_sensor_id;
+ msg->parameter1 = com_regs->scc_param1;
+ msg->parameter2 = com_regs->scc_param2;
+ msg->parameter3 = com_regs->scc_param3;
+ msg->parameter4 = 0;
+ break;
+ case INTR_SCP_FDONE:
+ msg->id = 0;
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->scp_sensor_id;
+ msg->parameter1 = com_regs->scp_param1;
+ msg->parameter2 = com_regs->scp_param2;
+ msg->parameter3 = com_regs->scp_param3;
+ msg->parameter4 = 0;
+ break;
+ case INTR_META_DONE:
+ msg->id = 0;
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->meta_sensor_id;
+ msg->parameter1 = com_regs->meta_param1;
+ msg->parameter2 = 0;
+ msg->parameter3 = 0;
+ msg->parameter4 = 0;
+ break;
+ case INTR_SHOT_DONE:
+ msg->id = 0;
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->shot_sensor_id;
+ msg->parameter1 = com_regs->shot_param1;
+ msg->parameter2 = com_regs->shot_param2;
+ msg->parameter3 = 0;
+ msg->parameter4 = 0;
+ break;
+ default:
+ msg->id = 0;
+ msg->command = 0;
+ msg->instance = 0;
+ msg->parameter1 = 0;
+ msg->parameter2 = 0;
+ msg->parameter3 = 0;
+ msg->parameter4 = 0;
+ is_err("unknown command getting\n");
+ break;
+ }
+}
+
+static inline unsigned int itf_get_intr(struct fimc_is_interface *itf)
+{
+ unsigned int status;
+ struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+ status = readl(itf->regs + INTMSR1) | com_regs->ihcmd_iflag |
+ com_regs->scc_iflag |
+ com_regs->scp_iflag |
+ com_regs->meta_iflag |
+ com_regs->shot_iflag;
+
+ return status;
+}
+
+static void itf_set_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&itf->slock_state, flags);
+ set_bit(state, &itf->state);
+ spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static void itf_clr_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&itf->slock_state, flags);
+ clear_bit(state, &itf->state);
+ spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static int itf_get_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&itf->slock_state, flags);
+ ret = test_bit(state, &itf->state);
+ spin_unlock_irqrestore(&itf->slock_state, flags);
+ return ret;
+}
+
+static void itf_init_wakeup(struct fimc_is_interface *itf)
+{
+ itf_set_state(itf, IS_IF_STATE_INIT);
+ wake_up(&itf->irq_queue);
+}
+
+void itf_busy_wakeup(struct fimc_is_interface *itf)
+{
+ itf_clr_state(itf, IS_IF_STATE_BUSY);
+ wake_up(&itf->irq_queue);
+}
+
+static int itf_wait_hw_ready(struct fimc_is_interface *itf)
+{
+ int ret = 0;
+ unsigned int try_count = TRY_RECV_AWARE_COUNT;
+ unsigned int cfg = readl(itf->regs + INTMSR0);
+ unsigned int status = INTMSR0_GET_INTMSD0(cfg);
+
+ while (status) {
+ cfg = readl(itf->regs + INTMSR0);
+ status = INTMSR0_GET_INTMSD0(cfg);
+
+ if (try_count-- == 0) {
+ try_count = TRY_RECV_AWARE_COUNT;
+ is_err("INTMSR0's 0 bit is not cleared.\n");
+ ret = -EINVAL;
+ break;
+ }
+ }
+ return ret;
+}
+
+static int itf_wait_idlestate(struct fimc_is_interface *itf)
+{
+ int ret = 0;
+
+ ret = wait_event_timeout(itf->irq_queue,
+ !itf_get_state(itf, IS_IF_STATE_BUSY),
+ FIMC_IS_COMMAND_TIMEOUT);
+ if (!ret) {
+ is_err("timeout");
+ return -ETIME;
+ }
+ return 0;
+}
+
+int fimc_is_itf_wait_init_state(struct fimc_is_interface *itf)
+{
+ int ret = 0;
+
+ ret = wait_event_timeout(itf->irq_queue,
+ itf_get_state(itf, IS_IF_STATE_INIT),
+ FIMC_IS_STARTUP_TIMEOUT);
+
+ if (!ret) {
+ is_err("timeout\n");
+ return -ETIME;
+ }
+ return 0;
+}
+
+static inline void itf_clr_intr(struct fimc_is_interface *itf,
+ unsigned int index)
+{
+ struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+ switch (index) {
+ case INTR_GENERAL:
+ writel((1<<INTR_GENERAL), itf->regs + INTCR1);
+ com_regs->ihcmd_iflag = 0;
+ break;
+ case INTR_SCC_FDONE:
+ writel((1<<INTR_SCC_FDONE), itf->regs + INTCR1);
+ com_regs->scc_iflag = 0;
+ break;
+ case INTR_SCP_FDONE:
+ writel((1<<INTR_SCP_FDONE), itf->regs + INTCR1);
+ com_regs->scp_iflag = 0;
+ break;
+ case INTR_META_DONE:
+ writel((1<<INTR_META_DONE), itf->regs + INTCR1);
+ com_regs->meta_iflag = 0;
+ break;
+ case INTR_SHOT_DONE:
+ writel((1<<INTR_SHOT_DONE), itf->regs + INTCR1);
+ com_regs->shot_iflag = 0;
+ break;
+ default:
+ is_err("Unknown command clear\n");
+ break;
+ }
+}
+
+/* Send Host to IS command interrupt */
+static void itf_hic_interrupt(struct fimc_is_interface *itf)
+{
+ writel(INTGR0_INTGD0, itf->regs + INTGR0);
+}
+
+int fimc_is_itf_hw_dump(struct fimc_is_interface *itf)
+{
+ struct fimc_is *is = fimc_interface_to_is(itf);
+ int debug_cnt;
+ char *debug;
+ char letter;
+ int count = 0, i;
+
+ debug = (char *)(is->minfo.fw_vaddr + DEBUG_OFFSET);
+ debug_cnt = *((int *)(is->minfo.fw_vaddr + DEBUGCTL_OFFSET))
+ - DEBUG_OFFSET;
+
+ if (itf->debug_cnt > debug_cnt)
+ count = (DEBUG_CNT - itf->debug_cnt) + debug_cnt;
+ else
+ count = debug_cnt - itf->debug_cnt;
+
+ if (count) {
+ pr_info("start(%d %d)\n", debug_cnt, count);
+ for (i = itf->debug_cnt; count > 0; count--) {
+ letter = debug[i];
+ if (letter)
+ pr_cont("%c", letter);
+ i++;
+ if (i > DEBUG_CNT)
+ i = 0;
+ }
+ itf->debug_cnt = debug_cnt;
+ pr_info("end\n");
+ }
+ return count;
+}
+
+static int itf_send_sensor_number(struct fimc_is_interface *itf)
+{
+ struct fimc_is_msg msg;
+ unsigned long flags;
+
+ msg.id = 0;
+ msg.command = ISR_DONE;
+ msg.instance = 0;
+ msg.parameter1 = IHC_GET_SENSOR_NUMBER;
+
+ msg.parameter2 = 1;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ spin_lock_irqsave(&itf->slock, flags);
+ itf->com_regs->hicmd = msg.command;
+ itf->com_regs->hic_sensorid = msg.instance;
+ itf->com_regs->hic_param1 = msg.parameter1;
+ itf->com_regs->hic_param2 = msg.parameter2;
+ itf->com_regs->hic_param3 = msg.parameter3;
+ itf->com_regs->hic_param4 = msg.parameter4;
+ itf_hic_interrupt(itf);
+ spin_unlock_irqrestore(&itf->slock, flags);
+
+ return 0;
+}
+
+static int fimc_is_itf_set_cmd(struct fimc_is_interface *itf,
+ struct fimc_is_msg *msg)
+{
+ int ret = 0;
+ bool block_io, send_cmd;
+ unsigned long flags;
+
+ enter_request_barrier(itf);
+
+ switch (msg->command) {
+ case HIC_STREAM_ON:
+ if (itf->streaming == IS_IF_STREAMING_ON) {
+ send_cmd = false;
+ } else {
+ send_cmd = true;
+ block_io = true;
+ }
+ break;
+ case HIC_STREAM_OFF:
+ if (itf->streaming == IS_IF_STREAMING_OFF) {
+ send_cmd = false;
+ } else {
+ send_cmd = true;
+ block_io = true;
+ }
+ break;
+ case HIC_PROCESS_START:
+ if (itf->processing == IS_IF_PROCESSING_ON) {
+ send_cmd = false;
+ } else {
+ send_cmd = true;
+ block_io = true;
+ }
+ break;
+ case HIC_PROCESS_STOP:
+ if (itf->processing == IS_IF_PROCESSING_OFF) {
+ send_cmd = false;
+ } else {
+ send_cmd = true;
+ block_io = true;
+ }
+ break;
+ case HIC_POWER_DOWN:
+ if (itf->pdown_ready == IS_IF_POWER_DOWN_READY) {
+ send_cmd = false;
+ } else {
+ send_cmd = true;
+ block_io = true;
+ }
+ break;
+ case HIC_OPEN_SENSOR:
+ case HIC_GET_SET_FILE_ADDR:
+ case HIC_SET_PARAMETER:
+ case HIC_PREVIEW_STILL:
+ case HIC_GET_STATIC_METADATA:
+ case HIC_SET_A5_MEM_ACCESS:
+ case HIC_SET_CAM_CONTROL:
+ send_cmd = true;
+ block_io = true;
+ break;
+ case HIC_SHOT:
+ case ISR_DONE:
+ send_cmd = true;
+ block_io = false;
+ break;
+ default:
+ send_cmd = true;
+ block_io = true;
+ break;
+ }
+
+ if (!send_cmd) {
+ is_dbg(3, "skipped\n");
+ goto exit;
+ }
+
+ ret = itf_wait_hw_ready(itf);
+ if (ret) {
+ is_err("waiting for ready is fail");
+ ret = -EBUSY;
+ goto exit;
+ }
+
+ spin_lock_irqsave(&itf->slock, flags);
+ itf_set_state(itf, IS_IF_STATE_BUSY);
+ itf->com_regs->hicmd = msg->command;
+ itf->com_regs->hic_sensorid = msg->instance;
+ itf->com_regs->hic_param1 = msg->parameter1;
+ itf->com_regs->hic_param2 = msg->parameter2;
+ itf->com_regs->hic_param3 = msg->parameter3;
+ itf->com_regs->hic_param4 = msg->parameter4;
+ itf_hic_interrupt(itf);
+ spin_unlock_irqrestore(&itf->slock, flags);
+
+ if (!block_io)
+ goto exit;
+
+ ret = itf_wait_idlestate(itf);
+ if (ret) {
+ is_err("%d command is timeout\n", msg->command);
+ itf_clr_state(itf, IS_IF_STATE_BUSY);
+ ret = -ETIME;
+ goto exit;
+ }
+
+ if (itf->reply.command == ISR_DONE) {
+ switch (msg->command) {
+ case HIC_STREAM_ON:
+ itf->streaming = IS_IF_STREAMING_ON;
+ break;
+ case HIC_STREAM_OFF:
+ itf->streaming = IS_IF_STREAMING_OFF;
+ break;
+ case HIC_PROCESS_START:
+ itf->processing = IS_IF_PROCESSING_ON;
+ break;
+ case HIC_PROCESS_STOP:
+ itf->processing = IS_IF_PROCESSING_OFF;
+ break;
+ case HIC_POWER_DOWN:
+ itf->pdown_ready = IS_IF_POWER_DOWN_READY;
+ break;
+ case HIC_OPEN_SENSOR:
+ if (itf->reply.parameter1 == HIC_POWER_DOWN) {
+ is_err("firmware power down");
+ itf->pdown_ready = IS_IF_POWER_DOWN_READY;
+ ret = -ECANCELED;
+ goto exit;
+ } else
+ itf->pdown_ready = IS_IF_POWER_DOWN_NREADY;
+ break;
+ default:
+ break;
+ }
+ } else {
+ is_err("ISR_NDONE is occured");
+ ret = -EINVAL;
+ }
+
+exit:
+ exit_request_barrier(itf);
+
+ if (ret)
+ fimc_is_itf_hw_dump(itf);
+
+ return ret;
+}
+
+static int fimc_is_itf_set_cmd_shot(struct fimc_is_interface *itf,
+ struct fimc_is_msg *msg)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&itf->slock, flags);
+ itf->com_regs->hicmd = msg->command;
+ itf->com_regs->hic_sensorid = msg->instance;
+ itf->com_regs->hic_param1 = msg->parameter1;
+ itf->com_regs->hic_param2 = msg->parameter2;
+ itf->com_regs->hic_param3 = msg->parameter3;
+ itf->com_regs->hic_param4 = msg->parameter4;
+ itf->com_regs->fcount = msg->parameter3;
+ itf_hic_interrupt(itf);
+ spin_unlock_irqrestore(&itf->slock, flags);
+
+ return ret;
+}
+
+static void itf_handle_general(struct fimc_is_interface *itf,
+ struct fimc_is_msg *msg)
+{
+ switch (msg->command) {
+
+ case IHC_GET_SENSOR_NUMBER:
+ is_dbg(3, "IS version : %d.%d\n",
+ ISDRV_VERSION, msg->parameter1);
+ /* Respond with sensor number */
+ itf_send_sensor_number(itf);
+ itf_init_wakeup(itf);
+ break;
+ case ISR_DONE:
+ switch (msg->parameter1) {
+ case HIC_OPEN_SENSOR:
+ is_dbg(3, "open done\n");
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_GET_SET_FILE_ADDR:
+ is_dbg(3, "saddr(%p) done\n",
+ (void *)msg->parameter2);
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_LOAD_SET_FILE:
+ is_dbg(3, "setfile done\n");
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_SET_A5_MEM_ACCESS:
+ is_dbg(3, "cfgmem done\n");
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_PROCESS_START:
+ is_dbg(3, "process_on done\n");
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_PROCESS_STOP:
+ is_dbg(3, "process_off done\n");
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_STREAM_ON:
+ is_dbg(3, "stream_on done\n");
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_STREAM_OFF:
+ is_dbg(3, "stream_off done\n");
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_SET_PARAMETER:
+ is_dbg(3, "s_param done\n");
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_GET_STATIC_METADATA:
+ is_dbg(3, "g_capability done\n");
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_PREVIEW_STILL:
+ is_dbg(3, "a_param(%dx%d) done\n",
+ msg->parameter2,
+ msg->parameter3);
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ case HIC_POWER_DOWN:
+ is_dbg(3, "powerdown done\n");
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ /*non-blocking command*/
+ case HIC_SHOT:
+ is_err("shot done is not acceptable\n");
+ break;
+ case HIC_SET_CAM_CONTROL:
+ is_err("camctrl is not acceptable\n");
+ break;
+ default:
+ is_err("unknown done is invokded\n");
+ break;
+ }
+ break;
+ case ISR_NDONE:
+ switch (msg->parameter1) {
+ case HIC_SHOT:
+ is_err("shot NOT done is not acceptable\n");
+ break;
+ case HIC_SET_CAM_CONTROL:
+ is_dbg(3, "camctrl NOT done\n");
+ break;
+ case HIC_SET_PARAMETER:
+ is_err("s_param NOT done\n");
+ is_err("param2 : 0x%08X\n", msg->parameter2);
+ is_err("param3 : 0x%08X\n", msg->parameter3);
+ is_err("param4 : 0x%08X\n", msg->parameter4);
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ default:
+ is_err("a command(%d) not done", msg->parameter1);
+ memcpy(&itf->reply, msg,
+ sizeof(struct fimc_is_msg));
+ itf_busy_wakeup(itf);
+ break;
+ }
+ break;
+ case IHC_SET_FACE_MARK:
+ is_err("FACE_MARK(%d,%d,%d) is not acceptable\n",
+ msg->parameter1,
+ msg->parameter2,
+ msg->parameter3);
+ break;
+ case IHC_AA_DONE:
+ is_err("AA_DONE(%d,%d,%d) is not acceptable\n",
+ msg->parameter1,
+ msg->parameter2,
+ msg->parameter3);
+ break;
+ case IHC_FLASH_READY:
+ is_err("IHC_FLASH_READY is not acceptable");
+ break;
+ case IHC_NOT_READY:
+ is_err("IHC_NOT_READY is occured, need reset");
+ break;
+ default:
+ is_err("func_general unknown(0x%08X) end\n", msg->command);
+ break;
+ }
+}
+
+static void itf_handle_scaler_done(struct fimc_is_interface *itf,
+ struct fimc_is_msg *msg)
+{
+ struct fimc_is *is = fimc_interface_to_is(itf);
+ struct fimc_is_pipeline *pipeline = &is->pipeline;
+ struct fimc_is_buf *buf;
+ struct fimc_is_scaler *scl;
+ struct fimc_is_fmt *fmt;
+ struct timeval *tv;
+ struct timespec ts;
+ unsigned int wh, i;
+ unsigned int fcount = msg->parameter1;
+ unsigned long *comp_state;
+
+ if (msg->parameter4 == SCALER_SCC) {
+ scl = &pipeline->scaler[SCALER_SCC];
+ comp_state = &pipeline->comp_state[IS_SCC];
+ } else {
+ scl = &pipeline->scaler[SCALER_SCP];
+ comp_state = &pipeline->comp_state[IS_SCP];
+ }
+
+ fmt = scl->fmt;
+
+ fimc_is_pipeline_buf_lock(pipeline);
+ if (!list_empty(&scl->run_queue)) {
+
+ wh = scl->width * scl->height;
+ buf = fimc_is_scaler_run_queue_get(scl);
+ for (i = 0; i < fmt->num_planes; i++) {
+ vb2_set_plane_payload(buf->vb, i,
+ (wh * fmt->depth[i]) / 8);
+ }
+
+ /* Set timestamp */
+ ktime_get_ts(&ts);
+ tv = &buf->vb->v4l2_buf.timestamp;
+ tv->tv_sec = ts.tv_sec;
+ tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
+ buf->vb->v4l2_buf.sequence = fcount;
+
+ is_dbg(5, "SCP buffer done %d/%d\n",
+ msg->parameter1, msg->parameter3);
+ vb2_buffer_done(buf->vb, VB2_BUF_STATE_DONE);
+ }
+ fimc_is_pipeline_buf_unlock(pipeline);
+ clear_bit(COMP_RUN, comp_state);
+ wake_up(&scl->event_q);
+}
+
+static void itf_handle_shot_done(struct fimc_is_interface *itf,
+ struct fimc_is_msg *msg)
+{
+ struct fimc_is *is = fimc_interface_to_is(itf);
+ struct fimc_is_pipeline *pipeline = &is->pipeline;
+ unsigned int status = msg->parameter2;
+ struct fimc_is_buf *bayer_buf;
+ int ret;
+
+ if (status != ISR_DONE)
+ is_err("Shot done is invalid(0x%08X)\n", status);
+
+ /* DQ the bayer input buffer */
+ fimc_is_pipeline_buf_lock(pipeline);
+ bayer_buf = fimc_is_isp_run_queue_get(&pipeline->isp);
+ if (bayer_buf) {
+ vb2_buffer_done(bayer_buf->vb, VB2_BUF_STATE_DONE);
+ is_dbg(5, "Bayer buffer done.\n");
+ }
+ fimc_is_pipeline_buf_unlock(pipeline);
+
+ /* Clear state & call shot again */
+ clear_bit(PIPELINE_RUN, &pipeline->state);
+
+ ret = fimc_is_pipeline_shot(pipeline);
+ if (ret)
+ is_err("Shot failed\n");
+}
+
+/* Main FIMC-IS interrupt handler */
+static irqreturn_t itf_irq_handler(int irq, void *data)
+{
+ struct fimc_is_interface *itf;
+ struct fimc_is_msg msg;
+ unsigned int status;
+
+ itf = (struct fimc_is_interface *)data;
+ status = itf_get_intr(itf);
+
+ if (status & (1<<INTR_SHOT_DONE)) {
+ itf_get_cmd(itf, &msg, INTR_SHOT_DONE);
+
+ itf_handle_shot_done(itf, &msg);
+
+ status &= ~(1<<INTR_SHOT_DONE);
+ itf_clr_intr(itf, INTR_SHOT_DONE);
+ }
+
+ if (status & (1<<INTR_GENERAL)) {
+ itf_get_cmd(itf, &msg, INTR_GENERAL);
+
+ itf_handle_general(itf, &msg);
+
+ status &= ~(1<<INTR_GENERAL);
+ itf_clr_intr(itf, INTR_GENERAL);
+ }
+
+ if (status & (1<<INTR_SCC_FDONE)) {
+ itf_get_cmd(itf, &msg, INTR_SCC_FDONE);
+
+ msg.parameter4 = SCALER_SCC;
+ itf_handle_scaler_done(itf, &msg);
+
+ status &= ~(1<<INTR_SCC_FDONE);
+ itf_clr_intr(itf, INTR_SCC_FDONE);
+ }
+
+ if (status & (1<<INTR_SCP_FDONE)) {
+ itf_get_cmd(itf, &msg, INTR_SCP_FDONE);
+
+ msg.parameter4 = SCALER_SCP;
+ itf_handle_scaler_done(itf, &msg);
+
+ status &= ~(1<<INTR_SCP_FDONE);
+ itf_clr_intr(itf, INTR_SCP_FDONE);
+ }
+
+ if (status & (1<<INTR_META_DONE)) {
+ status &= ~(1<<INTR_META_DONE);
+ itf_clr_intr(itf, INTR_META_DONE);
+ }
+
+ if (status != 0)
+ is_err("status is NOT all clear(0x%08X)", status);
+
+ return IRQ_HANDLED;
+}
+
+int fimc_is_itf_open_sensor(struct fimc_is_interface *itf,
+ unsigned int instance,
+ unsigned int sensor_id,
+ unsigned int i2c_channel,
+ unsigned int sensor_ext)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_OPEN_SENSOR;
+ msg.instance = instance;
+ msg.parameter1 = sensor_id;
+ msg.parameter2 = i2c_channel;
+ msg.parameter3 = sensor_ext;
+ msg.parameter4 = 0;
+
+ return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_get_setfile_addr(struct fimc_is_interface *itf,
+ unsigned int instance, unsigned int *setfile_addr)
+{
+ int ret;
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_GET_SET_FILE_ADDR;
+ msg.instance = instance;
+ msg.parameter1 = 0;
+ msg.parameter2 = 0;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ ret = fimc_is_itf_set_cmd(itf, &msg);
+ *setfile_addr = itf->reply.parameter2;
+
+ return ret;
+}
+
+int fimc_is_itf_load_setfile(struct fimc_is_interface *itf,
+ unsigned int instance)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_LOAD_SET_FILE;
+ msg.instance = instance;
+ msg.parameter1 = 0;
+ msg.parameter2 = 0;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_stream_on(struct fimc_is_interface *itf,
+ unsigned int instance)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_STREAM_ON;
+ msg.instance = instance;
+ msg.parameter1 = 0;
+ msg.parameter2 = 0;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_stream_off(struct fimc_is_interface *itf,
+ unsigned int instance)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_STREAM_OFF;
+ msg.instance = instance;
+ msg.parameter1 = 0;
+ msg.parameter2 = 0;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_process_on(struct fimc_is_interface *itf,
+ unsigned int instance)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_PROCESS_START;
+ msg.instance = instance;
+ msg.parameter1 = 0;
+ msg.parameter2 = 0;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_process_off(struct fimc_is_interface *itf,
+ unsigned int instance)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_PROCESS_STOP;
+ msg.instance = instance;
+ msg.parameter1 = 0;
+ msg.parameter2 = 0;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_set_param(struct fimc_is_interface *itf,
+ unsigned int instance,
+ unsigned int indexes,
+ unsigned int lindex,
+ unsigned int hindex)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_SET_PARAMETER;
+ msg.instance = instance;
+ msg.parameter1 = ISS_PREVIEW_STILL;
+ msg.parameter2 = indexes;
+ msg.parameter3 = lindex;
+ msg.parameter4 = hindex;
+
+ return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_preview_still(struct fimc_is_interface *itf,
+ unsigned int instance)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_PREVIEW_STILL;
+ msg.instance = instance;
+ msg.parameter1 = 0;
+ msg.parameter2 = 0;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_get_capability(struct fimc_is_interface *itf,
+ unsigned int instance, unsigned int address)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_GET_STATIC_METADATA;
+ msg.instance = instance;
+ msg.parameter1 = address;
+ msg.parameter2 = 0;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_cfg_mem(struct fimc_is_interface *itf,
+ unsigned int instance, unsigned int address,
+ unsigned int size)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_SET_A5_MEM_ACCESS;
+ msg.instance = instance;
+ msg.parameter1 = address;
+ msg.parameter2 = size;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_shot_nblk(struct fimc_is_interface *itf,
+ unsigned int instance, unsigned int bayer,
+ unsigned int shot, unsigned int fcount, unsigned int rcount)
+{
+ struct fimc_is_msg msg;
+
+ msg.id = 0;
+ msg.command = HIC_SHOT;
+ msg.instance = instance;
+ msg.parameter1 = bayer;
+ msg.parameter2 = shot;
+ msg.parameter3 = fcount;
+ msg.parameter4 = rcount;
+
+ return fimc_is_itf_set_cmd_shot(itf, &msg);
+}
+
+int fimc_is_itf_power_down(struct fimc_is_interface *itf,
+ unsigned int instance)
+{
+ struct fimc_is_msg msg;
+ int ret;
+
+ msg.id = 0;
+ msg.command = HIC_POWER_DOWN;
+ msg.instance = instance;
+ msg.parameter1 = 0;
+ msg.parameter2 = 0;
+ msg.parameter3 = 0;
+ msg.parameter4 = 0;
+
+ ret = fimc_is_itf_set_cmd(itf, &msg);
+ itf_clr_state(itf, IS_IF_STATE_INIT);
+
+ return ret;
+}
+
+int fimc_is_interface_init(struct fimc_is_interface *itf,
+ void __iomem *regs, int irq)
+{
+ struct fimc_is *is = fimc_interface_to_is(itf);
+ struct device *dev = &is->pdev->dev;
+ int ret;
+
+ if (!regs || !irq) {
+ is_err("Invalid args\n");
+ return -EINVAL;
+ }
+
+ itf->regs = regs;
+ itf->com_regs = (struct is_common_reg *)(regs + ISSR0);
+
+ init_waitqueue_head(&itf->irq_queue);
+ spin_lock_init(&itf->slock_state);
+ spin_lock_init(&itf->slock);
+
+ /* Register interrupt handler */
+ ret = devm_request_irq(dev, irq, itf_irq_handler,
+ 0, dev_name(dev), itf);
+ if (ret) {
+ dev_err(dev, "Failed to install irq (%d)\n", ret);
+ return -EINVAL;
+ }
+
+ /* Initialize context vars */
+ itf->streaming = IS_IF_STREAMING_INIT;
+ itf->processing = IS_IF_PROCESSING_INIT;
+ itf->pdown_ready = IS_IF_POWER_DOWN_READY;
+ itf->debug_cnt = 0;
+ init_request_barrier(itf);
+
+ return 0;
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.h b/drivers/media/platform/exynos5-is/fimc-is-interface.h
new file mode 100644
index 0000000..54f3aec
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.h
@@ -0,0 +1,130 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_INTERFACE_H_
+#define FIMC_IS_INTERFACE_H_
+
+#include "fimc-is-core.h"
+
+#define TRY_RECV_AWARE_COUNT 100
+
+#define ISDRV_VERSION 111
+
+#define LOWBIT_OF(num) (num >= 32 ? 0 : (unsigned int)1<<num)
+#define HIGHBIT_OF(num) (num >= 32 ? (unsigned int)1<<(num-32) : 0)
+
+enum interrupt_map {
+ INTR_GENERAL = 0,
+ INTR_ISP_FDONE = 1,
+ INTR_SCC_FDONE = 2,
+ INTR_DNR_FDONE = 3,
+ INTR_SCP_FDONE = 4,
+ /* 5 is ISP YUV DONE */
+ INTR_META_DONE = 6,
+ INTR_SHOT_DONE = 7,
+ INTR_MAX_MAP
+};
+
+enum fimc_is_interface_state {
+ IS_IF_STATE_INIT,
+ IS_IF_STATE_OPEN,
+ IS_IF_STATE_START,
+ IS_IF_STATE_BUSY
+};
+
+enum streaming_state {
+ IS_IF_STREAMING_INIT,
+ IS_IF_STREAMING_OFF,
+ IS_IF_STREAMING_ON
+};
+
+enum processing_state {
+ IS_IF_PROCESSING_INIT,
+ IS_IF_PROCESSING_OFF,
+ IS_IF_PROCESSING_ON
+};
+
+enum pdown_ready_state {
+ IS_IF_POWER_DOWN_READY,
+ IS_IF_POWER_DOWN_NREADY
+};
+
+struct fimc_is_msg {
+ unsigned int id;
+ unsigned int command;
+ unsigned int instance;
+ unsigned int parameter1;
+ unsigned int parameter2;
+ unsigned int parameter3;
+ unsigned int parameter4;
+};
+
+struct fimc_is_interface {
+
+ unsigned long state;
+
+ void __iomem *regs;
+ struct is_common_reg __iomem *com_regs;
+ spinlock_t slock;
+ spinlock_t slock_state;
+ wait_queue_head_t irq_queue;
+
+ spinlock_t process_barrier;
+ struct mutex request_barrier;
+
+ enum streaming_state streaming;
+ enum processing_state processing;
+ enum pdown_ready_state pdown_ready;
+
+ struct fimc_is_msg reply;
+
+ int debug_cnt;
+
+};
+
+int fimc_is_interface_init(struct fimc_is_interface *itf,
+ void __iomem *regs, int irq);
+int fimc_is_itf_wait_init_state(struct fimc_is_interface *itf);
+int fimc_is_itf_hw_dump(struct fimc_is_interface *itf);
+int fimc_is_itf_open_sensor(struct fimc_is_interface *itf,
+ unsigned int instance,
+ unsigned int sensor_id,
+ unsigned int i2c_channel,
+ unsigned int sensor_ext);
+int fimc_is_itf_get_setfile_addr(struct fimc_is_interface *this,
+ unsigned int instance, unsigned int *setfile_addr);
+int fimc_is_itf_load_setfile(struct fimc_is_interface *itf,
+ unsigned int instance);
+int fimc_is_itf_stream_on(struct fimc_is_interface *itf,
+ unsigned int instance);
+int fimc_is_itf_stream_off(struct fimc_is_interface *itf,
+ unsigned int instance);
+int fimc_is_itf_process_on(struct fimc_is_interface *itf,
+ unsigned int instance);
+int fimc_is_itf_process_off(struct fimc_is_interface *itf,
+ unsigned int instance);
+int fimc_is_itf_set_param(struct fimc_is_interface *this,
+ unsigned int instance,
+ unsigned int indexes,
+ unsigned int lindex,
+ unsigned int hindex);
+int fimc_is_itf_preview_still(struct fimc_is_interface *itf,
+ unsigned int instance);
+int fimc_is_itf_get_capability(struct fimc_is_interface *itf,
+ unsigned int instance, unsigned int address);
+int fimc_is_itf_cfg_mem(struct fimc_is_interface *itf,
+ unsigned int instance, unsigned int address,
+ unsigned int size);
+int fimc_is_itf_shot_nblk(struct fimc_is_interface *itf,
+ unsigned int instance, unsigned int bayer,
+ unsigned int shot, unsigned int fcount, unsigned int rcount);
+int fimc_is_itf_power_down(struct fimc_is_interface *itf,
+ unsigned int instance);
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [RFC 10/12] exynos-fimc-is: Adds the hardware interface module
2013-03-08 14:59 ` [RFC 10/12] exynos-fimc-is: Adds the hardware interface module Arun Kumar K
@ 2013-03-23 19:01 ` Sylwester Nawrocki
0 siblings, 0 replies; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-23 19:01 UTC (permalink / raw)
To: Arun Kumar K
Cc: linux-media, linux-samsung-soc, devicetree-discuss, s.nawrocki,
kgene.kim, kilyeon.im, arunkk.samsung
On 03/08/2013 03:59 PM, Arun Kumar K wrote:
> The hardware interface module finally sends the commands to the
> FIMC-IS firmware and runs the interrupt handler for getting the
> responses.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
> .../media/platform/exynos5-is/fimc-is-interface.c | 1003 ++++++++++++++++++++
> .../media/platform/exynos5-is/fimc-is-interface.h | 130 +++
> 2 files changed, 1133 insertions(+)
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
> create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h
[...]
> +static void itf_set_state(struct fimc_is_interface *itf,
> + unsigned long state)
> +{
> + unsigned long flags;
> + spin_lock_irqsave(&itf->slock_state, flags);
> + set_bit(state,&itf->state);
If itf->state is always modified with itf->slock_state spinlock
held you could use non-atomic variant, i.e. __set_bit().
> + spin_unlock_irqrestore(&itf->slock_state, flags);
> +}
> +
> +static void itf_clr_state(struct fimc_is_interface *itf,
> + unsigned long state)
> +{
> + unsigned long flags;
> + spin_lock_irqsave(&itf->slock_state, flags);
> + clear_bit(state,&itf->state);
> + spin_unlock_irqrestore(&itf->slock_state, flags);
> +}
> +
> +static int itf_get_state(struct fimc_is_interface *itf,
> + unsigned long state)
> +{
> + int ret = 0;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&itf->slock_state, flags);
> + ret = test_bit(state,&itf->state);
> + spin_unlock_irqrestore(&itf->slock_state, flags);
> + return ret;
> +}
> +int fimc_is_itf_hw_dump(struct fimc_is_interface *itf)
> +{
> + struct fimc_is *is = fimc_interface_to_is(itf);
> + int debug_cnt;
> + char *debug;
> + char letter;
> + int count = 0, i;
> +
> + debug = (char *)(is->minfo.fw_vaddr + DEBUG_OFFSET);
> + debug_cnt = *((int *)(is->minfo.fw_vaddr + DEBUGCTL_OFFSET))
> + - DEBUG_OFFSET;
> +
> + if (itf->debug_cnt> debug_cnt)
> + count = (DEBUG_CNT - itf->debug_cnt) + debug_cnt;
> + else
> + count = debug_cnt - itf->debug_cnt;
> +
> + if (count) {
> + pr_info("start(%d %d)\n", debug_cnt, count);
> + for (i = itf->debug_cnt; count> 0; count--) {
> + letter = debug[i];
> + if (letter)
> + pr_cont("%c", letter);
> + i++;
> + if (i> DEBUG_CNT)
> + i = 0;
> + }
> + itf->debug_cnt = debug_cnt;
> + pr_info("end\n");
> + }
> + return count;
> +}
Why don't you use debugfs for dumping this log buffer ? I found it much
more convenient and the logs appear exactly as written by the firmware.
This is what I have in the Exynos4x12 FIMC-IS driver:
static int fimc_is_log_show(struct seq_file *s, void *data)
{
struct fimc_is *is = s->private;
const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
if (is->memory.vaddr == NULL) {
dev_err(&is->pdev->dev, "Firmware memory is not initialized\n");
return -EIO;
}
seq_printf(s, "%s\n", buf);
return 0;
}
static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
{
return single_open(file, fimc_is_log_show, inode->i_private);
}
static const struct file_operations fimc_is_debugfs_fops = {
.open = fimc_is_debugfs_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static void fimc_is_debugfs_remove(struct fimc_is *is)
{
debugfs_remove(is->debugfs_entry);
is->debugfs_entry = NULL;
}
static int fimc_is_debugfs_create(struct fimc_is *is)
{
struct dentry *dentry;
is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
is, &fimc_is_debugfs_fops);
if (!dentry)
fimc_is_debugfs_remove(is);
return is->debugfs_entry == NULL ? -EIO : 0;
}
^ permalink raw reply [flat|nested] 31+ messages in thread
* [RFC 11/12] exynos-fimc-is: Adds the Kconfig and Makefile
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
` (9 preceding siblings ...)
2013-03-08 14:59 ` [RFC 10/12] exynos-fimc-is: Adds the hardware interface module Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-23 19:02 ` Sylwester Nawrocki
2013-03-08 14:59 ` [RFC 12/12] mipi-csis: Enable all interrupts for fimc-is usage Arun Kumar K
11 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
Modifies the exynos5-is Makefile and Kconfig to include the new
fimc-is driver.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
drivers/media/platform/exynos5-is/Kconfig | 12 ++++++++++++
drivers/media/platform/exynos5-is/Makefile | 3 +++
2 files changed, 15 insertions(+)
diff --git a/drivers/media/platform/exynos5-is/Kconfig b/drivers/media/platform/exynos5-is/Kconfig
index 7aacf3b..588103e 100644
--- a/drivers/media/platform/exynos5-is/Kconfig
+++ b/drivers/media/platform/exynos5-is/Kconfig
@@ -5,3 +5,15 @@ config VIDEO_SAMSUNG_EXYNOS5_MDEV
This is a v4l2 based media controller driver for
Exynos5 SoC.
+if VIDEO_SAMSUNG_EXYNOS5_MDEV
+
+config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS
+ tristate "Samsung Exynos5 SoC FIMC-IS driver"
+ depends on VIDEO_V4L2_SUBDEV_API
+ depends on VIDEO_SAMSUNG_EXYNOS5_MDEV
+ select VIDEOBUF2_DMA_CONTIG
+ help
+ This is a v4l2 driver for Samsung Exynos5 SoC series Imaging
+ subsystem known as FIMC-IS.
+
+endif #VIDEO_SAMSUNG_EXYNOS5_MDEV
diff --git a/drivers/media/platform/exynos5-is/Makefile b/drivers/media/platform/exynos5-is/Makefile
index 472d8e1..e5003d0 100644
--- a/drivers/media/platform/exynos5-is/Makefile
+++ b/drivers/media/platform/exynos5-is/Makefile
@@ -1,4 +1,7 @@
ccflags-y += -Idrivers/media/platform/s5p-fimc
+exynos5-fimc-is-objs := fimc-is-core.o fimc-is-isp.o fimc-is-scaler.o fimc-is-sensor.o
+exynos5-fimc-is-objs += fimc-is-pipeline.o fimc-is-interface.o
exynos-mdevice-objs := exynos5-mdev.o
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_FIMC_IS) += exynos5-fimc-is.o
obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_MDEV) += exynos-mdevice.o
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [RFC 11/12] exynos-fimc-is: Adds the Kconfig and Makefile
2013-03-08 14:59 ` [RFC 11/12] exynos-fimc-is: Adds the Kconfig and Makefile Arun Kumar K
@ 2013-03-23 19:02 ` Sylwester Nawrocki
0 siblings, 0 replies; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-23 19:02 UTC (permalink / raw)
To: Arun Kumar K
Cc: linux-media, linux-samsung-soc, devicetree-discuss, s.nawrocki,
kgene.kim, kilyeon.im, arunkk.samsung
On 03/08/2013 03:59 PM, Arun Kumar K wrote:
> Modifies the exynos5-is Makefile and Kconfig to include the new
> fimc-is driver.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
> drivers/media/platform/exynos5-is/Kconfig | 12 ++++++++++++
> drivers/media/platform/exynos5-is/Makefile | 3 +++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/media/platform/exynos5-is/Kconfig b/drivers/media/platform/exynos5-is/Kconfig
> index 7aacf3b..588103e 100644
> --- a/drivers/media/platform/exynos5-is/Kconfig
> +++ b/drivers/media/platform/exynos5-is/Kconfig
> @@ -5,3 +5,15 @@ config VIDEO_SAMSUNG_EXYNOS5_MDEV
> This is a v4l2 based media controller driver for
> Exynos5 SoC.
>
> +if VIDEO_SAMSUNG_EXYNOS5_MDEV
> +
> +config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS
> + tristate "Samsung Exynos5 SoC FIMC-IS driver"
> + depends on VIDEO_V4L2_SUBDEV_API
> + depends on VIDEO_SAMSUNG_EXYNOS5_MDEV
> + select VIDEOBUF2_DMA_CONTIG
> + help
> + This is a v4l2 driver for Samsung Exynos5 SoC series Imaging
> + subsystem known as FIMC-IS.
nit: Subsystem and V4L2 should be capitalized.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [RFC 12/12] mipi-csis: Enable all interrupts for fimc-is usage
2013-03-08 14:59 [RFC 00/12] Exynos5 FIMC-IS driver Arun Kumar K
` (10 preceding siblings ...)
2013-03-08 14:59 ` [RFC 11/12] exynos-fimc-is: Adds the Kconfig and Makefile Arun Kumar K
@ 2013-03-08 14:59 ` Arun Kumar K
2013-03-12 16:01 ` Sylwester Nawrocki
11 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-08 14:59 UTC (permalink / raw)
To: linux-media, linux-samsung-soc, devicetree-discuss
Cc: s.nawrocki, kgene.kim, kilyeon.im, arunkk.samsung
FIMC-IS firmware needs all the MIPI-CSIS interrupts to be enabled.
This patch enables all those MIPI interrupts.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
drivers/media/platform/s5p-fimc/mipi-csis.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/platform/s5p-fimc/mipi-csis.c b/drivers/media/platform/s5p-fimc/mipi-csis.c
index debda7c..11eef67 100644
--- a/drivers/media/platform/s5p-fimc/mipi-csis.c
+++ b/drivers/media/platform/s5p-fimc/mipi-csis.c
@@ -64,7 +64,7 @@ MODULE_PARM_DESC(debug, "Debug level (0-2)");
/* Interrupt mask */
#define S5PCSIS_INTMSK 0x10
-#define S5PCSIS_INTMSK_EN_ALL 0xf000103f
+#define S5PCSIS_INTMSK_EN_ALL 0xfc00103f
#define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31)
#define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30)
#define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [RFC 12/12] mipi-csis: Enable all interrupts for fimc-is usage
2013-03-08 14:59 ` [RFC 12/12] mipi-csis: Enable all interrupts for fimc-is usage Arun Kumar K
@ 2013-03-12 16:01 ` Sylwester Nawrocki
2013-03-13 4:09 ` Arun Kumar K
0 siblings, 1 reply; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-03-12 16:01 UTC (permalink / raw)
To: Arun Kumar K
Cc: linux-media, linux-samsung-soc, devicetree-discuss, kgene.kim,
kilyeon.im, arunkk.samsung
Hi Arun,
On 03/08/2013 03:59 PM, Arun Kumar K wrote:
> FIMC-IS firmware needs all the MIPI-CSIS interrupts to be enabled.
> This patch enables all those MIPI interrupts.
>
> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
> ---
> drivers/media/platform/s5p-fimc/mipi-csis.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/s5p-fimc/mipi-csis.c b/drivers/media/platform/s5p-fimc/mipi-csis.c
> index debda7c..11eef67 100644
> --- a/drivers/media/platform/s5p-fimc/mipi-csis.c
> +++ b/drivers/media/platform/s5p-fimc/mipi-csis.c
> @@ -64,7 +64,7 @@ MODULE_PARM_DESC(debug, "Debug level (0-2)");
>
> /* Interrupt mask */
> #define S5PCSIS_INTMSK 0x10
> -#define S5PCSIS_INTMSK_EN_ALL 0xf000103f
> +#define S5PCSIS_INTMSK_EN_ALL 0xfc00103f
Do you know what interrupts are assigned to the CSIS_INTMSK
bits 26, 27 ? In the documentation I have they are marked
as reserved. I have tested this patch on Exynos4x12, it seems
OK but you might want to merge it to the patch adding compatible
property for exynos5.
It would be good to know what these bits are for. And how
enabling the interrupts actually help without modifying the
interrupt handler ? Is it enough to just acknowledge those
interrupts ? Or how it works ?
--
Regards,
Sylwester
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [RFC 12/12] mipi-csis: Enable all interrupts for fimc-is usage
2013-03-12 16:01 ` Sylwester Nawrocki
@ 2013-03-13 4:09 ` Arun Kumar K
2013-04-03 12:31 ` Sylwester Nawrocki
0 siblings, 1 reply; 31+ messages in thread
From: Arun Kumar K @ 2013-03-13 4:09 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: Arun Kumar K, LMML, linux-samsung-soc, devicetree-discuss,
kgene.kim, kilyeon.im, shaik.ameer
Hi Sylwester,
>>
>> /* Interrupt mask */
>> #define S5PCSIS_INTMSK 0x10
>> -#define S5PCSIS_INTMSK_EN_ALL 0xf000103f
>> +#define S5PCSIS_INTMSK_EN_ALL 0xfc00103f
>
> Do you know what interrupts are assigned to the CSIS_INTMSK
> bits 26, 27 ? In the documentation I have they are marked
> as reserved. I have tested this patch on Exynos4x12, it seems
> OK but you might want to merge it to the patch adding compatible
> property for exynos5.
The bits 26 and 27 are for Frame start and Frame end interrupts.
Yes this change can be merged with the MIPI-CSIS support for Exynos5.
Shaik will pick it up and merge it along with his patch series in v2.
>
> It would be good to know what these bits are for. And how
> enabling the interrupts actually help without modifying the
> interrupt handler ? Is it enough to just acknowledge those
> interrupts ? Or how it works ?
>
These interrupts are used by the FIMC-IS firmware possibly to check if the
sensor is working. Without enabling these, I get the error from firmware
on Sensor Open command.
Regards
Arun
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [RFC 12/12] mipi-csis: Enable all interrupts for fimc-is usage
2013-03-13 4:09 ` Arun Kumar K
@ 2013-04-03 12:31 ` Sylwester Nawrocki
0 siblings, 0 replies; 31+ messages in thread
From: Sylwester Nawrocki @ 2013-04-03 12:31 UTC (permalink / raw)
To: Arun Kumar K
Cc: Arun Kumar K, LMML, linux-samsung-soc, devicetree-discuss,
kgene.kim, kilyeon.im, shaik.ameer
Hi Arun,
On 03/13/2013 05:09 AM, Arun Kumar K wrote:
> Hi Sylwester,
>
>>>
>>> /* Interrupt mask */
>>> #define S5PCSIS_INTMSK 0x10
>>> -#define S5PCSIS_INTMSK_EN_ALL 0xf000103f
>>> +#define S5PCSIS_INTMSK_EN_ALL 0xfc00103f
>>
>> Do you know what interrupts are assigned to the CSIS_INTMSK
>> bits 26, 27 ? In the documentation I have they are marked
>> as reserved. I have tested this patch on Exynos4x12, it seems
>> OK but you might want to merge it to the patch adding compatible
>> property for exynos5.
>
> The bits 26 and 27 are for Frame start and Frame end interrupts.
> Yes this change can be merged with the MIPI-CSIS support for Exynos5.
> Shaik will pick it up and merge it along with his patch series in v2.
OK, thanks a lot for the clarification. I tested this patch on
Exynos4x12 and I could see twice as many interrupts from MIPI-CSIS as
there was captured frames from the sensor. Certainly we don't want to
see these interrupts when they are not needed. I have been thinking of
some interface that the MIPI-CSIS subdev would provide to the media
driver, so it can enable the interrupts when needed. I suppose a
private subdev ioctl might be good for that. But first I think there
is e.g. a subdev flag needed so a subdev driver can decide that it
doesn't want to have its non-standard ioctls called from user space.
I'll see if I can address those issues.
>> It would be good to know what these bits are for. And how
>> enabling the interrupts actually help without modifying the
>> interrupt handler ? Is it enough to just acknowledge those
>> interrupts ? Or how it works ?
>>
>
> These interrupts are used by the FIMC-IS firmware possibly to check if the
> sensor is working. Without enabling these, I get the error from firmware
> on Sensor Open command.
Hm, interesting... Looks like the MIPI-CSIS interrupts get routed to the
FIMC-IS GIC. I was also wondering how the FIMC-IS receives Embedded Data
from the MIPI CSIS IP, which is sent by an image sensor. Presumably
FIMC-IS can memory map the Embedded Data buffer at the MIPI CSIS internal
memory, and then it reads from there. It's just a guess though.
Regards,
Sylwester
^ permalink raw reply [flat|nested] 31+ messages in thread