[RFC PATCH v3 00/17] ARM: DT cpu bindings updates

[RFC PATCH v3 00/17] ARM: DT cpu bindings updates

[Lorenzo Pieralisi]

This patchset is an update of a previous posting:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/164587.html

v3 changes:

- More dts fixes of in-kernel dts
- Defined ARM v8 behaviour with different cpus node #address-cells
- Added pre ARM11 processors suffixes in the cpu node compatible list
- Reordered series
- Reworded #address-cells definition
- Added ARM v8 - cores running on AArch32 bindings example
- Moved WARN* calls on one line to prevent grepping issues

v2 changes:

- Reworded DT cpu bindings
- Split the set, with per-mach specific dts updates
- Updated cpu node compatible string list
- Defined behaviour of OS running on v8 in AArch32

The introduction of DT cpus/cpu bindings for ARM requires well established
rules to enforce the reg property definition for 32-bit and 64-bit ARM
processors, inclusive of legacy and current uniprocessor/SMP systems.

ARM 64 bit architecture also requires dtb compiled for 64-bit configurations
to be reused for kernels running in 32 bit mode, so the cpus/cpu bindings
specification must be made compliant to cope with this configuration.

Patch #1 of this series is a fix and is included to have a clean patch
series and should get reviewed and merged separately.

Patch #2-17, along with some kernel fixes related to DT parsing function,
update the cpu node bindings and in kernel dts files to cope with legacy,
current and upcoming ARM systems.

In-kernel device tree source files are updated to comply with the latest
specification, so thorough testing is required in order to validate all
changes on all affected ARM systems, in particular systems with exotic
MPIDR configurations that are likely to break with the changes provided.

Code relying on the reg property size to be 4-bytes must be updated so that
dtbs compiled for 64-bit kernels can also be used to boot a 32-bit system.

Lorenzo Pieralisi (17):
  ARM: DT: kernel: move temporary cpu map stack array to static data
  Documentation: devicetree: arm: cpus/cpu nodes bindings updates
  ARM: dts: am33xx: cpus/cpu nodes dts updates
  ARM: dts: armada-370-xp: cpus/cpu node dts updates
  ARM: dts: at91: cpus/cpu node dts updates
  ARM: dts: exynos5440: cpus/cpu nodes dts updates
  ARM: dts: imx: cpus/cpu nodes dts updates
  ARM: dts: lpc32xx: cpus/cpu nodes dts updates
  ARM: dts: omap: cpus/cpu nodes dts updates
  ARM: dts: picoxcell: cpus/cpu nodes dts updates
  ARM: dts: prima2: cpus/cpu node dts updates
  ARM: dts: pxa2xx: cpus/cpu nodes dts updates
  ARM: dts: r8a7740: cpus/cpu nodes dts updates
  ARM: dts: sh7372: cpus/cpu nodes dts updates
  ARM: dts: spear: cpus/cpu nodes dts updates
  ARM: dts: sunxi: cpus/cpu nodes dts updates
  ARM: DT: kernel: DT cpus/cpu node bindings update

 Documentation/devicetree/bindings/arm/cpus.txt | 457 ++++++++++++++++++++++---
 arch/arm/boot/dts/am33xx.dtsi                  |   4 +
 arch/arm/boot/dts/armada-370-xp.dtsi           |   4 +
 arch/arm/boot/dts/at91rm9200.dtsi              |   6 +-
 arch/arm/boot/dts/at91sam9260.dtsi             |   8 +-
 arch/arm/boot/dts/at91sam9263.dtsi             |   8 +-
 arch/arm/boot/dts/at91sam9g45.dtsi             |   8 +-
 arch/arm/boot/dts/at91sam9n12.dtsi             |   8 +-
 arch/arm/boot/dts/at91sam9x5.dtsi              |   8 +-
 arch/arm/boot/dts/exynos5440.dtsi              |  11 +
 arch/arm/boot/dts/imx23.dtsi                   |   8 +-
 arch/arm/boot/dts/imx28.dtsi                   |   8 +-
 arch/arm/boot/dts/imx6dl.dtsi                  |   2 +
 arch/arm/boot/dts/imx6q.dtsi                   |   1 +
 arch/arm/boot/dts/lpc32xx.dtsi                 |   8 +-
 arch/arm/boot/dts/omap2.dtsi                   |   6 +-
 arch/arm/boot/dts/omap3.dtsi                   |   5 +
 arch/arm/boot/dts/omap4.dtsi                   |   7 +
 arch/arm/boot/dts/omap5.dtsi                   |   7 +
 arch/arm/boot/dts/picoxcell-pc3x2.dtsi         |   8 +-
 arch/arm/boot/dts/picoxcell-pc3x3.dtsi         |   8 +-
 arch/arm/boot/dts/prima2.dtsi                  |   2 +
 arch/arm/boot/dts/pxa2xx.dtsi                  |   7 +-
 arch/arm/boot/dts/r8a7740.dtsi                 |   4 +
 arch/arm/boot/dts/sh7372.dtsi                  |   5 +
 arch/arm/boot/dts/spear13xx.dtsi               |   2 +
 arch/arm/boot/dts/spear3xx.dtsi                |   8 +-
 arch/arm/boot/dts/spear600.dtsi                |   8 +-
 arch/arm/boot/dts/sunxi.dtsi                   |   5 +
 arch/arm/kernel/devtree.c                      |  81 +++--
 30 files changed, 602 insertions(+), 110 deletions(-)

-- 
1.7.12

[RFC PATCH v3 01/17] ARM: DT: kernel: move temporary cpu map stack array to static data

[Lorenzo Pieralisi]

As the number of CPUs increase, the temporary array allocated on the
stack in arm_dt_init_cpu_maps() can become too big and trigger stack
issues.
This patch moves the allocated memory to static __initdata so that stack
data is not used anymore to allocate the temporary array.
Memory is marked as __initdata since it need not be persistent after boot.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/kernel/devtree.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 70f1bde..f149217 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -78,11 +78,12 @@ void __init arm_dt_init_cpu_maps(void)
 	 * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
 	 * read as 0.
 	 */
+	static u32 tmp_map[NR_CPUS] __initdata = {
+				[0 ... NR_CPUS-1] = UINT_MAX };
 	struct device_node *cpu, *cpus;
 	u32 i, j, cpuidx = 1;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
-	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
 	bool bootcpu_valid = false;
 	cpus = of_find_node_by_path("/cpus");
 
-- 
1.7.12

[RFC PATCH v3 02/17] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Lorenzo Pieralisi]

In order to extend the current cpu nodes bindings to newer CPUs
inclusive of AArch64 and to update support for older ARM CPUs this
patch updates device tree documentation for the cpu nodes bindings.

Main changes:
    - adds 64-bit bindings
    - define usage of #address-cells
    - define 32/64 dts compatibility settings
    - defines behaviour on pre and post v7 uniprocessor systems
    - adds ARM 11MPcore specific reg property definition

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/cpus.txt | 457 ++++++++++++++++++++++---
 1 file changed, 410 insertions(+), 47 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index f32494d..00badea 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -1,77 +1,440 @@
-* ARM CPUs binding description
+=================
+ARM CPUs bindings
+=================
 
 The device tree allows to describe the layout of CPUs in a system through
 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
 defining properties for every cpu.
 
-Bindings for CPU nodes follow the ePAPR standard, available from:
-
-http://devicetree.org
-
-For the ARM architecture every CPU node must contain the following properties:
-
-- device_type:	must be "cpu"
-- reg:		property matching the CPU MPIDR[23:0] register bits
-		reg[31:24] bits must be set to 0
-- compatible:	should be one of:
-		"arm,arm1020"
-		"arm,arm1020e"
-		"arm,arm1022"
-		"arm,arm1026"
-		"arm,arm720"
-		"arm,arm740"
-		"arm,arm7tdmi"
-		"arm,arm920"
-		"arm,arm922"
-		"arm,arm925"
-		"arm,arm926"
-		"arm,arm940"
-		"arm,arm946"
-		"arm,arm9tdmi"
-		"arm,cortex-a5"
-		"arm,cortex-a7"
-		"arm,cortex-a8"
-		"arm,cortex-a9"
-		"arm,cortex-a15"
-		"arm,arm1136"
-		"arm,arm1156"
-		"arm,arm1176"
-		"arm,arm11mpcore"
-		"faraday,fa526"
-		"intel,sa110"
-		"intel,sa1100"
-		"marvell,feroceon"
-		"marvell,mohawk"
-		"marvell,xsc3"
-		"marvell,xscale"
-
-Example:
+Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
+
+https://www.power.org/documentation/epapr-version-1-1/
+
+with updates for 32-bit and 64-bit ARM systems provided in this document.
+
+================================
+Convention used in this document
+================================
+
+This document follows the conventions described in the ePAPR v1.1, with
+the addition:
+
+- square brackets define bitfields, eg reg[7:0] value of the bitfield in
+  the reg property contained in bits 7 down to 0
+
+=====================================
+cpus and cpu node bindings definition
+=====================================
+
+The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
+nodes to be present and contain the properties described below.
+
+- cpus node
+
+	Description: Container of cpu nodes
+
+	The node name must be "cpus".
+
+	A cpus node must define the following properties:
+
+	- #address-cells
+		Usage: required
+		Value type: <u32>
+
+		Definition depends on ARM architecture version and
+		configuration:
+
+			# On uniprocessor ARM architectures previous to v7
+			  value must be 0.
+			# On 32-bit ARM 11 MPcore, ARM v7 or later systems
+			  value must be 1.
+			# On ARM v8 64-bit systems value must be set to 1
+			  or 2. Refer to the cpu node's reg property
+			  description for allowed configurations.
+
+	- #size-cells
+		Usage: required
+		Value type: <u32>
+		Definition: must be set to 0
+
+- cpu node
+
+	Description: Describes a CPU in an ARM based system
+
+	PROPERTIES
+
+	- device_type
+		Usage: required
+		Value type: <string>
+		Definition: must be "cpu"
+	- reg
+		Usage and definition depend on ARM architecture version and
+		configuration:
+
+			# On uniprocessor ARM architectures previous to v7
+			  this property is optional since they do not define
+			  any register that provides a CPU identifier.
+			  Any value set in the reg property for these CPUs
+			  should be ignored.
+
+			# On ARM 11 MPcore based systems this property is
+			  required and matches the CPUID[11:0] register bits.
+
+			  Bits [11:0] in the reg cell must be set to
+			  bits [11:0] in CPU ID register.
+
+			  All other bits in the reg cell must be set to 0.
+
+			# On 32-bit ARM v7 or later systems this property is
+			  required and matches the CPU MPIDR[23:0] register
+			  bits.
+
+			  Bits [23:0] in the reg cell must be set to
+			  bits [23:0] in MPIDR.
+
+			  All other bits in the reg cell must be set to 0.
+
+			# On ARM v8 64-bit systems, where the reg property
+			  size can be 1 or 2 cells (as defined by cpus node's
+			  #address-cells property), this property is
+			  required and matches:
+
+			  - On systems running the OS in AArch32:
+
+			    * If the cpus node's #address-cells value is 2:
+
+			      The first reg cell must be set to 0.
+
+			      The second reg cell bits [23:0] must be set to
+			      bits [23:0] of MPIDR_EL1.
+
+			      All other bits in the reg cells must be set to 0.
+
+			    * If the cpus node's #address-cells value is 1:
+
+			      Bits [23:0] in the reg cell must be set to
+			      bits [23:0] in MPIDR_EL1.
+
+			      All other bits in the reg cell must be 0.
+
+			  - On systems running the OS in AArch64:
+
+			    * If the cpus node's #address-cells value is 2:
+
+			      The first reg cell bits [7:0] must be set to
+			      bits [39:32] of MPIDR_EL1.
+
+			      The second reg cell bits [23:0] must be set to
+			      bits [23:0] of MPIDR_EL1.
+
+			      All other bits in the reg cells must be set to 0.
+
+			    * If the cpus node's #address-cells value is 1:
+
+			      MPIDR_EL1[63:32] is 0 on all processors in the
+			      system.
+
+			      The reg cell bits [23:0] must be set to
+			      bits [23:0] of MPIDR_EL1.
+
+			      All other bits in the reg cell must be set to 0.
+
+	- compatible:
+		Usage: required
+		Value type: <string>
+		Definition: should be one of:
+			    "arm,arm710t"
+			    "arm,arm720t"
+			    "arm,arm740t"
+			    "arm,arm7ej-s"
+			    "arm,arm7tdmi"
+			    "arm,arm7tdmi-s"
+			    "arm,arm9es"
+			    "arm,arm9ej-s"
+			    "arm,arm920t"
+			    "arm,arm922t"
+			    "arm,arm925"
+			    "arm,arm926e-s"
+			    "arm,arm926ej-s"
+			    "arm,arm940t"
+			    "arm,arm946e-s"
+			    "arm,arm966e-s"
+			    "arm,arm968e-s"
+			    "arm,arm9tdmi"
+			    "arm,arm1020e"
+			    "arm,arm1020t"
+			    "arm,arm1022e"
+			    "arm,arm1026ej-s"
+			    "arm,arm1136j-s"
+			    "arm,arm1136jf-s"
+			    "arm,arm1156t2-s"
+			    "arm,arm1156t2f-s"
+			    "arm,arm1176jzf"
+			    "arm,arm1176jz-s"
+			    "arm,arm1176jzf-s"
+			    "arm,arm11mpcore"
+			    "arm,cortex-a5"
+			    "arm,cortex-a7"
+			    "arm,cortex-a8"
+			    "arm,cortex-a9"
+			    "arm,cortex-a15"
+			    "arm,cortex-a53"
+			    "arm,cortex-a57"
+			    "arm,cortex-m0"
+			    "arm,cortex-m0+"
+			    "arm,cortex-m1"
+			    "arm,cortex-m3"
+			    "arm,cortex-m4"
+			    "arm,cortex-r4"
+			    "arm,cortex-r5"
+			    "arm,cortex-r7"
+			    "faraday,fa526"
+			    "intel,sa110"
+			    "intel,sa1100"
+			    "marvell,feroceon"
+			    "marvell,mohawk"
+			    "marvell,pj4"
+			    "marvell,sheeva-v7"
+			    "marvell,xsc3"
+			    "marvell,xscale"
+			    "qcom,krait"
+			    "qcom,scorpion"
+	- enable-method
+		Value type: <stringlist>
+		Usage and definition depend on ARM architecture version and
+		configuration:
+			# On ARM v8 64-bit systems running the OS in AArch64,
+			  this property is required and must be "spin-table".
+			# On ARM 32-bit systems or ARM v8 systems running
+			  the OS in AArch32 this property is prohibited.
+
+	- cpu-release-addr
+		Usage: required for systems that have an "enable-method"
+		       property value of "spin-table".
+		Value type: <prop-encoded-array>
+		Definition:
+			# On ARM v8 64-bit systems must be a two cell
+			  property identifying a 64-bit zero-initialised
+			  memory location.
+
+Example 1 (dual-cluster big.LITTLE system 32-bit):
 
 	cpus {
 		#size-cells = <0>;
 		#address-cells = <1>;
 
-		CPU0: cpu@0 {
+		cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
 		};
 
-		CPU1: cpu@1 {
+		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x1>;
 		};
 
-		CPU2: cpu@100 {
+		cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 		};
 
-		CPU3: cpu@101 {
+		cpu@101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 		};
 	};
+
+Example 2 (Cortex-A8 uniprocessor 32-bit system):
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a8";
+			reg = <0x0>;
+		};
+	};
+
+Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <0>;
+
+		cpu {
+			device_type = "cpu";
+			compatible = "arm,arm926ej-s";
+		};
+	};
+
+Example 4 (ARM Cortex-A57 64-bit system running OS in AArch64):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <2>;
+
+	cpu@0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x0>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x1>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@10000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10000>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@10001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10001>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@10100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@10101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100000000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x0>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100000001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x1>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100000100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100000101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100010000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10000>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100010001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10001>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100010100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100010101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+};
+
+Example 5 (ARM Cortex-A57 64-bit system running OS in AArch32):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <2>;
+
+	cpu@0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x0>;
+	};
+
+	cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x1>;
+	};
+
+	cpu@100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x100>;
+	};
+
+	cpu@101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x101>;
+	};
+};
-- 
1.7.12

[RFC PATCH v3 03/17] ARM: dts: am33xx: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/am33xx.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 0957645..ab1bcf2 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -24,8 +24,12 @@
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		cpu@0 {
 			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0>;
 
 			/*
 			 * To consider voltage drop between PMIC and SoC,
-- 
1.7.12

[RFC PATCH v3 04/17] ARM: dts: armada-370-xp: cpus/cpu node dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6f1acc7..f13b47a 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -23,8 +23,12 @@
 	compatible = "marvell,armada-370-xp";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		cpu@0 {
 			compatible = "marvell,sheeva-v7";
+			device_type = "cpu";
+			reg = <0>;
 		};
 	};
 
-- 
1.7.12

[RFC PATCH v3 05/17] ARM: dts: at91: cpus/cpu node dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/at91rm9200.dtsi  | 6 +++++-
 arch/arm/boot/dts/at91sam9260.dtsi | 8 ++++++--
 arch/arm/boot/dts/at91sam9263.dtsi | 8 ++++++--
 arch/arm/boot/dts/at91sam9g45.dtsi | 8 ++++++--
 arch/arm/boot/dts/at91sam9n12.dtsi | 8 ++++++--
 arch/arm/boot/dts/at91sam9x5.dtsi  | 8 ++++++--
 6 files changed, 35 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index b0268a5..f16b3d4 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -34,8 +34,12 @@
 		ssc2 = &ssc2;
 	};
 	cpus {
-		cpu@0 {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
 			compatible = "arm,arm920t";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index cb7bcc5..c4eeef7 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -32,8 +32,12 @@
 		ssc0 = &ssc0;
 	};
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 271d4de..f3b5c2a 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -29,8 +29,12 @@
 		ssc1 = &ssc1;
 	};
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 6b1d4ca..6c18bd3 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -35,8 +35,12 @@
 		ssc1 = &ssc1;
 	};
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 7750f98..c3b11af 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -31,8 +31,12 @@
 		ssc0 = &ssc0;
 	};
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index aa98e64..6c39d0f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -33,8 +33,12 @@
 		ssc0 = &ssc0;
 	};
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
-- 
1.7.12

[RFC PATCH v3 06/17] ARM: dts: exynos5440: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/exynos5440.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 5f3562a..fd0966f 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -24,8 +24,13 @@
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "arm,cortex-a15";
+			device_type = "cpu";
+			reg = <0x0>;
 			timer {
 				compatible = "arm,armv7-timer";
 				interrupts = <1 13 0xf08>;
@@ -34,6 +39,8 @@
 		};
 		cpu@1 {
 			compatible = "arm,cortex-a15";
+			device_type = "cpu";
+			reg = <0x1>;
 			timer {
 				compatible = "arm,armv7-timer";
 				interrupts = <1 14 0xf08>;
@@ -42,6 +49,8 @@
 		};
 		cpu@2 {
 			compatible = "arm,cortex-a15";
+			device_type = "cpu";
+			reg = <0x2>;
 			timer {
 				compatible = "arm,armv7-timer";
 				interrupts = <1 14 0xf08>;
@@ -50,6 +59,8 @@
 		};
 		cpu@3 {
 			compatible = "arm,cortex-a15";
+			device_type = "cpu";
+			reg = <0x3>;
 			timer {
 				compatible = "arm,armv7-timer";
 				interrupts = <1 14 0xf08>;
-- 
1.7.12

[RFC PATCH v3 07/17] ARM: dts: imx: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/imx23.dtsi  | 8 ++++++--
 arch/arm/boot/dts/imx28.dtsi  | 8 ++++++--
 arch/arm/boot/dts/imx6dl.dtsi | 2 ++
 arch/arm/boot/dts/imx6q.dtsi  | 1 +
 4 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 56afcf4..0aae18b 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,8 +23,12 @@
 	};
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 7ba4966..07f131fc 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,8 +32,12 @@
 	};
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 63fafe2..b76d85e 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -16,12 +16,14 @@
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
 		};
 
 		cpu@1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
 		};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index cba021e..65c1b62 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -17,6 +17,7 @@
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
 			operating-points = <
-- 
1.7.12

[RFC PATCH v3 08/17] ARM: dts: lpc32xx: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/lpc32xx.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1582f48..3abebb7 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -18,8 +18,12 @@
 	interrupt-parent = <&mic>;
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
-- 
1.7.12

[RFC PATCH v3 09/17] ARM: dts: omap: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/omap2.dtsi | 6 +++++-
 arch/arm/boot/dts/omap3.dtsi | 5 +++++
 arch/arm/boot/dts/omap4.dtsi | 7 +++++++
 arch/arm/boot/dts/omap5.dtsi | 7 +++++++
 4 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 761c4b6..4183027 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -21,8 +21,12 @@
 	};
 
 	cpus {
-		cpu@0 {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
 			compatible = "arm,arm1136jf-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 1acc261..b6f6502 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -21,8 +21,13 @@
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 739bb79..e0f943f 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -28,13 +28,20 @@
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			next-level-cache = <&L2>;
+			reg = <0x0>;
 		};
 		cpu@1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			next-level-cache = <&L2>;
+			reg = <0x1>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 790bb2a..e3cc688 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -31,8 +31,13 @@
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "arm,cortex-a15";
+			device_type = "cpu";
+			reg = <0x0>;
 			timer {
 				compatible = "arm,armv7-timer";
 				/* 14th PPI IRQ, active low level-sensitive */
@@ -42,6 +47,8 @@
 		};
 		cpu@1 {
 			compatible = "arm,cortex-a15";
+			device_type = "cpu";
+			reg = <0x1>;
 			timer {
 				compatible = "arm,armv7-timer";
 				/* 14th PPI IRQ, active low level-sensitive */
-- 
1.7.12

[RFC PATCH v3 10/17] ARM: dts: picoxcell: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 8 ++++----
 arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index f0a8c20..533919e 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -18,13 +18,13 @@
 	#size-cells = <1>;
 
 	cpus {
-		#address-cells = <1>;
+		#address-cells = <0>;
 		#size-cells = <0>;
 
-		cpu@0 {
-			compatible = "arm,1176jz-s";
+		cpu {
+			compatible = "arm,arm1176jz-s";
+			device_type = "cpu";
 			clock-frequency = <400000000>;
-			reg = <0>;
 			d-cache-line-size = <32>;
 			d-cache-size = <32768>;
 			i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index daa962d..ab3e800 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -18,13 +18,13 @@
 	#size-cells = <1>;
 
 	cpus {
-		#address-cells = <1>;
+		#address-cells = <0>;
 		#size-cells = <0>;
 
-		cpu@0 {
-			compatible = "arm,1176jz-s";
+		cpu {
+			compatible = "arm,arm1176jz-s";
+			device_type = "cpu";
 			cpu-clock = <&arm_clk>, "cpu";
-			reg = <0>;
 			d-cache-line-size = <32>;
 			d-cache-size = <32768>;
 			i-cache-line-size = <32>;
-- 
1.7.12

[RFC PATCH v3 11/17] ARM: dts: prima2: cpus/cpu node dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/prima2.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719..02edd89 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -18,6 +18,8 @@
 		#size-cells = <0>;
 
 		cpu@0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0x0>;
 			d-cache-line-size = <32>;
 			i-cache-line-size = <32>;
-- 
1.7.12

[RFC PATCH v3 12/17] ARM: dts: pxa2xx: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/pxa2xx.dtsi | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index f18aad3..a5e90f0 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -23,8 +23,11 @@
 	};
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,xscale";
+		#address-cells = <0>;
+		#size-cells = <0>;
+		cpu {
+			compatible = "marvell,xscale";
+			device_type = "cpu";
 		};
 	};
 
-- 
1.7.12

[RFC PATCH v3 13/17] ARM: dts: r8a7740: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/r8a7740.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 798fa35..8a831e9 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -14,8 +14,12 @@
 	compatible = "renesas,r8a7740";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		cpu@0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 };
-- 
1.7.12

[RFC PATCH v3 14/17] ARM: dts: sh7372: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/sh7372.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc60..7bf020e 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -14,8 +14,13 @@
 	compatible = "renesas,sh7372";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 };
-- 
1.7.12

[RFC PATCH v3 15/17] ARM: dts: spear: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/spear13xx.dtsi | 2 ++
 arch/arm/boot/dts/spear3xx.dtsi  | 8 ++++++--
 arch/arm/boot/dts/spear600.dtsi  | 8 ++++++--
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index b4ca60f..5093d54 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -22,12 +22,14 @@
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
 		};
 
 		cpu@1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
 		};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index c2a852d..f0e3fcf 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -17,8 +17,12 @@
 	interrupt-parent = <&vic>;
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 19f99dc..9f60a7b 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -15,8 +15,12 @@
 	compatible = "st,spear600";
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 
-- 
1.7.12

[RFC PATCH v3 16/17] ARM: dts: sunxi: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/sunxi.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
index 8b36abe..9f45ecf 100644
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -17,8 +17,13 @@
 	interrupt-parent = <&intc>;
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 
-- 
1.7.12

[RFC PATCH v3 17/17] ARM: DT: kernel: DT cpus/cpu node bindings update

[Lorenzo Pieralisi]

DT cpu map parsing code must be made compliant with the latest cpus/cpu
nodes bindings updates, hence this patch updates the arm_dt_init_cpu_maps()
function with checks and additional parsing rules.

Uniprocessor systems predating v7 do not parse the cpus node at all
since the reg property is meaningless on those systems.

Device trees for 64-bit systems can be taken as device tree input also
for 64-bit CPUs running in 32-bit mode. The code checks that the reg entries
are zeroed as required in the respective fields and detects automatically
the cpus node #address-cells value so that device tree written for
64-bit ARM platforms (that can have cpus node #address-cells == 2) can still
be taken as input. The correct device tree entries are to be set up by the
boot loader, kernel code just checks that device tree entries in the cpus
node are as expected for a 32-bit CPU (reg[63:24] == 0).

cpu node entries with invalid reg property or containing duplicates are
ignored and the device tree parsing is not stopped anymore when such
entries are encountered, the device tree cpu node entry is just skipped.

A device tree with cpu nodes missing the boot CPU MPIDR is considered a
hard error and the kernel flags this up as a bug to force firmware updates.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/kernel/devtree.c | 78 +++++++++++++++++++++++++++++------------------
 1 file changed, 48 insertions(+), 30 deletions(-)

diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index f149217..b667217 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -23,6 +23,7 @@
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/smp_plat.h>
+#include <asm/system_info.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -81,48 +82,64 @@ void __init arm_dt_init_cpu_maps(void)
 	static u32 tmp_map[NR_CPUS] __initdata = {
 				[0 ... NR_CPUS-1] = UINT_MAX };
 	struct device_node *cpu, *cpus;
-	u32 i, j, cpuidx = 1;
+	u32 i, j, ac, cpuidx = 1;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
-
+	int len;
 	bool bootcpu_valid = false;
+
 	cpus = of_find_node_by_path("/cpus");
 
-	if (!cpus)
+	if (!cpus || ((cpu_architecture() < CPU_ARCH_ARMv7) && !is_smp()))
 		return;
 
+	if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac)))
+		ac = of_n_addr_cells(cpus);
+
 	for_each_child_of_node(cpus, cpu) {
-		u32 hwid;
+		u64 hwid64;
+		u32 hwid32;
+		const __be32 *prop;
 
 		pr_debug(" * %s...\n", cpu->full_name);
 		/*
-		 * A device tree containing CPU nodes with missing "reg"
-		 * properties is considered invalid to build the
-		 * cpu_logical_map.
+		 * A CPU node with missing or wrong "reg" property is
+		 * considered invalid to build a cpu_logical_map entry.
 		 */
-		if (of_property_read_u32(cpu, "reg", &hwid)) {
-			pr_debug(" * %s missing reg property\n",
-				     cpu->full_name);
-			return;
+		prop = of_get_property(cpu, "reg", &len);
+		if (!prop || len < (ac * sizeof(*prop))) {
+			WARN(1, " * %s node missing/wrong reg property, skipped\n",
+				cpu->full_name);
+				goto next;
 		}
-
 		/*
-		 * 8 MSBs must be set to 0 in the DT since the reg property
-		 * defines the MPIDR[23:0].
+		 * Always read reg as u64 value.
+		 * For dts with #address-cells == 1 hwid64[63:32]
+		 * will be set to 0 by of_read_number.
+		 * Toss away the top 32 bits and store value in hwid32.
+		 */
+		hwid32 = hwid64 = of_read_number(prop, ac);
+		/*
+		 * hwid64[63:24] must be always be 0 since the reg
+		 * property defines the MPIDR[23:0] bits regardless
+		 * of the cpus node #address-cells value.
 		 */
-		if (hwid & ~MPIDR_HWID_BITMASK)
-			return;
+		if (hwid64 & ~MPIDR_HWID_BITMASK) {
+			WARN(1, " * %s node reg[63:24] must be 0 on 32-bit dts, got %#016llx, skipped\n",
+				cpu->full_name, hwid64);
+			goto next;
+		}
 
 		/*
 		 * Duplicate MPIDRs are a recipe for disaster.
 		 * Scan all initialized entries and check for
-		 * duplicates. If any is found just bail out.
+		 * duplicates. If any is found just ignore the CPU.
 		 * temp values were initialized to UINT_MAX
 		 * to avoid matching valid MPIDR[23:0] values.
 		 */
 		for (j = 0; j < cpuidx; j++)
-			if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
-						     "properties in the DT\n"))
-				return;
+			if (WARN(tmp_map[j] == hwid32, " * %s node duplicate cpu reg property, skipped\n",
+						       cpu->full_name))
+				goto next;
 
 		/*
 		 * Build a stashed array of MPIDR values. Numbering scheme
@@ -133,26 +150,27 @@ void __init arm_dt_init_cpu_maps(void)
 		 * logical map built from DT is validated and can be used
 		 * to override the map created in smp_setup_processor_id().
 		 */
-		if (hwid == mpidr) {
+		if (hwid32 == mpidr) {
 			i = 0;
 			bootcpu_valid = true;
 		} else {
 			i = cpuidx++;
 		}
 
-		if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
-					       "max cores %u, capping them\n",
-					       cpuidx, nr_cpu_ids)) {
+		if (WARN_ONCE(cpuidx > nr_cpu_ids, "DT cpu %u nodes greater than max cores %u, capping them\n",
+						    cpuidx, nr_cpu_ids)) {
 			cpuidx = nr_cpu_ids;
-			break;
+			goto next;
 		}
 
-		tmp_map[i] = hwid;
+		tmp_map[i] = hwid32;
+next:	;
 	}
-
-	if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
-				 "fall back to default cpu_logical_map\n"))
-		return;
+	/*
+	 * A DT missing the boot CPU MPIDR is a really bad omen
+	 * Flag it up as such and force firmware/dtb updates
+	 */
+	BUG_ON(!bootcpu_valid);
 
 	/*
 	 * Since the boot CPU node contains proper data, and all nodes have
-- 
1.7.12

Re: [RFC PATCH v3 02/17] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:28 Wed 24 Apr     , Lorenzo Pieralisi wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
> 
> Main changes:
>     - adds 64-bit bindings
>     - define usage of #address-cells
>     - define 32/64 dts compatibility settings
>     - defines behaviour on pre and post v7 uniprocessor systems
>     - adds ARM 11MPcore specific reg property definition
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt | 457 ++++++++++++++++++++++---
>  1 file changed, 410 insertions(+), 47 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index f32494d..00badea 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -1,77 +1,440 @@
> -* ARM CPUs binding description
> +=================
> +ARM CPUs bindings
> +=================
>  
>  The device tree allows to describe the layout of CPUs in a system through
>  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>  defining properties for every cpu.
>  
> -Bindings for CPU nodes follow the ePAPR standard, available from:
> -
> -http://devicetree.org
> -
> -For the ARM architecture every CPU node must contain the following properties:
> -
> -- device_type:	must be "cpu"
> -- reg:		property matching the CPU MPIDR[23:0] register bits
> -		reg[31:24] bits must be set to 0
> -- compatible:	should be one of:
> -		"arm,arm1020"
> -		"arm,arm1020e"
> -		"arm,arm1022"
> -		"arm,arm1026"
> -		"arm,arm720"
> -		"arm,arm740"
> -		"arm,arm7tdmi"
> -		"arm,arm920"
> -		"arm,arm922"
> -		"arm,arm925"
> -		"arm,arm926"
> -		"arm,arm940"
> -		"arm,arm946"
> -		"arm,arm9tdmi"
> -		"arm,cortex-a5"
> -		"arm,cortex-a7"
> -		"arm,cortex-a8"
> -		"arm,cortex-a9"
> -		"arm,cortex-a15"
> -		"arm,arm1136"
> -		"arm,arm1156"
> -		"arm,arm1176"
> -		"arm,arm11mpcore"
> -		"faraday,fa526"
> -		"intel,sa110"
> -		"intel,sa1100"
> -		"marvell,feroceon"
> -		"marvell,mohawk"
> -		"marvell,xsc3"
> -		"marvell,xscale"
> -
> -Example:
> +Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
> +
> +https://www.power.org/documentation/epapr-version-1-1/
> +
> +with updates for 32-bit and 64-bit ARM systems provided in this document.
> +
> +================================
> +Convention used in this document
> +================================
> +
> +This document follows the conventions described in the ePAPR v1.1, with
> +the addition:
> +
> +- square brackets define bitfields, eg reg[7:0] value of the bitfield in
> +  the reg property contained in bits 7 down to 0
> +
> +=====================================
> +cpus and cpu node bindings definition
> +=====================================
> +
> +The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
> +nodes to be present and contain the properties described below.
> +
> +- cpus node
> +
> +	Description: Container of cpu nodes
> +
> +	The node name must be "cpus".
> +
> +	A cpus node must define the following properties:
> +
> +	- #address-cells
> +		Usage: required
> +		Value type: <u32>
> +
> +		Definition depends on ARM architecture version and
> +		configuration:
> +
> +			# On uniprocessor ARM architectures previous to v7
> +			  value must be 0.
> +			# On 32-bit ARM 11 MPcore, ARM v7 or later systems
> +			  value must be 1.
> +			# On ARM v8 64-bit systems value must be set to 1
> +			  or 2. Refer to the cpu node's reg property
> +			  description for allowed configurations.
> +
> +	- #size-cells
> +		Usage: required
> +		Value type: <u32>
> +		Definition: must be set to 0
> +
> +- cpu node
> +
> +	Description: Describes a CPU in an ARM based system
> +
> +	PROPERTIES
> +
> +	- device_type
> +		Usage: required
> +		Value type: <string>
> +		Definition: must be "cpu"
> +	- reg
> +		Usage and definition depend on ARM architecture version and
> +		configuration:
> +
> +			# On uniprocessor ARM architectures previous to v7
> +			  this property is optional since they do not define
> +			  any register that provides a CPU identifier.
> +			  Any value set in the reg property for these CPUs
> +			  should be ignored.
> +
> +			# On ARM 11 MPcore based systems this property is
> +			  required and matches the CPUID[11:0] register bits.
> +
> +			  Bits [11:0] in the reg cell must be set to
> +			  bits [11:0] in CPU ID register.
> +
> +			  All other bits in the reg cell must be set to 0.
> +
> +			# On 32-bit ARM v7 or later systems this property is
> +			  required and matches the CPU MPIDR[23:0] register
> +			  bits.
> +
> +			  Bits [23:0] in the reg cell must be set to
> +			  bits [23:0] in MPIDR.
> +
> +			  All other bits in the reg cell must be set to 0.
> +
> +			# On ARM v8 64-bit systems, where the reg property
> +			  size can be 1 or 2 cells (as defined by cpus node's
> +			  #address-cells property), this property is
> +			  required and matches:
> +
> +			  - On systems running the OS in AArch32:
> +
> +			    * If the cpus node's #address-cells value is 2:
> +
> +			      The first reg cell must be set to 0.
> +
> +			      The second reg cell bits [23:0] must be set to
> +			      bits [23:0] of MPIDR_EL1.
> +
> +			      All other bits in the reg cells must be set to 0.
> +
> +			    * If the cpus node's #address-cells value is 1:
> +
> +			      Bits [23:0] in the reg cell must be set to
> +			      bits [23:0] in MPIDR_EL1.
> +
> +			      All other bits in the reg cell must be 0.
> +
> +			  - On systems running the OS in AArch64:
> +
> +			    * If the cpus node's #address-cells value is 2:
> +
> +			      The first reg cell bits [7:0] must be set to
> +			      bits [39:32] of MPIDR_EL1.
> +
> +			      The second reg cell bits [23:0] must be set to
> +			      bits [23:0] of MPIDR_EL1.
> +
> +			      All other bits in the reg cells must be set to 0.
> +
> +			    * If the cpus node's #address-cells value is 1:
> +
> +			      MPIDR_EL1[63:32] is 0 on all processors in the
> +			      system.
> +
> +			      The reg cell bits [23:0] must be set to
> +			      bits [23:0] of MPIDR_EL1.
> +
> +			      All other bits in the reg cell must be set to 0.
> +
> +	- compatible:
> +		Usage: required
> +		Value type: <string>
> +		Definition: should be one of:
> +			    "arm,arm710t"
> +			    "arm,arm720t"
> +			    "arm,arm740t"
> +			    "arm,arm7ej-s"
> +			    "arm,arm7tdmi"
> +			    "arm,arm7tdmi-s"
> +			    "arm,arm9es"
> +			    "arm,arm9ej-s"
> +			    "arm,arm920t"
> +			    "arm,arm922t"
> +			    "arm,arm925"
> +			    "arm,arm926e-s"
> +			    "arm,arm926ej-s"
> +			    "arm,arm940t"
> +			    "arm,arm946e-s"
> +			    "arm,arm966e-s"
> +			    "arm,arm968e-s"
> +			    "arm,arm9tdmi"
> +			    "arm,arm1020e"
> +			    "arm,arm1020t"
> +			    "arm,arm1022e"
> +			    "arm,arm1026ej-s"
the common name is arm926ejs / arm1026ejs & co

Best Regards,
J.
> +			    "arm,arm1136j-s"
> +			    "arm,arm1136jf-s"
> +			    "arm,arm1156t2-s"
> +			    "arm,arm1156t2f-s"
> +			    "arm,arm1176jzf"
> +			    "arm,arm1176jz-s"
> +			    "arm,arm1176jzf-s"
> +			    "arm,arm11mpcore"
> +			    "arm,cortex-a5"
> +			    "arm,cortex-a7"
> +			    "arm,cortex-a8"
> +			    "arm,cortex-a9"
> +			    "arm,cortex-a15"
> +			    "arm,cortex-a53"
> +			    "arm,cortex-a57"
> +			    "arm,cortex-m0"
> +			    "arm,cortex-m0+"
> +			    "arm,cortex-m1"
> +			    "arm,cortex-m3"
> +			    "arm,cortex-m4"
> +			    "arm,cortex-r4"
> +			    "arm,cortex-r5"
> +			    "arm,cortex-r7"
> +			    "faraday,fa526"
> +			    "intel,sa110"
> +			    "intel,sa1100"
> +			    "marvell,feroceon"
> +			    "marvell,mohawk"
> +			    "marvell,pj4"
> +			    "marvell,sheeva-v7"
> +			    "marvell,xsc3"
> +			    "marvell,xscale"
> +			    "qcom,krait"
> +			    "qcom,scorpion"
> +	- enable-method
> +		Value type: <stringlist>
> +		Usage and definition depend on ARM architecture version and
> +		configuration:
> +			# On ARM v8 64-bit systems running the OS in AArch64,
> +			  this property is required and must be "spin-table".
> +			# On ARM 32-bit systems or ARM v8 systems running
> +			  the OS in AArch32 this property is prohibited.
> +
> +	- cpu-release-addr
> +		Usage: required for systems that have an "enable-method"
> +		       property value of "spin-table".
> +		Value type: <prop-encoded-array>
> +		Definition:
> +			# On ARM v8 64-bit systems must be a two cell
> +			  property identifying a 64-bit zero-initialised
> +			  memory location.
> +
> +Example 1 (dual-cluster big.LITTLE system 32-bit):
>  
>  	cpus {
>  		#size-cells = <0>;
>  		#address-cells = <1>;
>  
> -		CPU0: cpu@0 {
> +		cpu@0 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <0x0>;
>  		};
>  
> -		CPU1: cpu@1 {
> +		cpu@1 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <0x1>;
>  		};
>  
> -		CPU2: cpu@100 {
> +		cpu@100 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a7";
>  			reg = <0x100>;
>  		};
>  
> -		CPU3: cpu@101 {
> +		cpu@101 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a7";
>  			reg = <0x101>;
>  		};
>  	};
> +
> +Example 2 (Cortex-A8 uniprocessor 32-bit system):
> +
> +	cpus {
> +		#size-cells = <0>;
> +		#address-cells = <1>;
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a8";
> +			reg = <0x0>;
> +		};
> +	};
> +
> +Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
> +
> +	cpus {
> +		#size-cells = <0>;
> +		#address-cells = <0>;
> +
> +		cpu {
> +			device_type = "cpu";
> +			compatible = "arm,arm926ej-s";
> +		};
> +	};
> +
> +Example 4 (ARM Cortex-A57 64-bit system running OS in AArch64):
> +
> +cpus {
> +	#size-cells = <0>;
> +	#address-cells = <2>;
> +
> +	cpu@0 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x0>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@1 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x1>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@100 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x100>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@101 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x101>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@10000 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x10000>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@10001 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x10001>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@10100 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x10100>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@10101 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x10101>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@100000000 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x0>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@100000001 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x1>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@100000100 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x100>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@100000101 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x101>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@100010000 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x10000>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@100010001 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x10001>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@100010100 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x10100>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +
> +	cpu@100010101 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x1 0x10101>;
> +		enable-method = "spin-table";
> +		cpu-release-addr = <0 0x20000000>;
> +	};
> +};
> +
> +Example 5 (ARM Cortex-A57 64-bit system running OS in AArch32):
> +
> +cpus {
> +	#size-cells = <0>;
> +	#address-cells = <2>;
> +
> +	cpu@0 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x0>;
> +	};
> +
> +	cpu@1 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x1>;
> +	};
> +
> +	cpu@100 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x100>;
> +	};
> +
> +	cpu@101 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a57";
> +		reg = <0x0 0x101>;
> +	};
> +};
> -- 
> 1.7.12
> 
> 

Re: [RFC PATCH v3 14/17] ARM: dts: sh7372: cpus/cpu nodes dts updates

[Simon Horman]

On Wed, Apr 24, 2013 at 06:28:19PM +0100, Lorenzo Pieralisi wrote:
> This patch updates the in-kernel dts files according to the latest cpus
> and cpu bindings updates for ARM.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>

Acked-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>

> ---
>  arch/arm/boot/dts/sh7372.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
> index 677fc60..7bf020e 100644
> --- a/arch/arm/boot/dts/sh7372.dtsi
> +++ b/arch/arm/boot/dts/sh7372.dtsi
> @@ -14,8 +14,13 @@
>  	compatible = "renesas,sh7372";
>  
>  	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
>  		cpu@0 {
>  			compatible = "arm,cortex-a8";
> +			device_type = "cpu";
> +			reg = <0x0>;
>  		};
>  	};
>  };
> -- 
> 1.7.12
> 
> 

Re: [RFC PATCH v3 13/17] ARM: dts: r8a7740: cpus/cpu nodes dts updates

[Simon Horman]

On Wed, Apr 24, 2013 at 06:28:18PM +0100, Lorenzo Pieralisi wrote:
> This patch updates the in-kernel dts files according to the latest cpus
> and cpu bindings updates for ARM.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>

Acked-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>

> ---
>  arch/arm/boot/dts/r8a7740.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
> index 798fa35..8a831e9 100644
> --- a/arch/arm/boot/dts/r8a7740.dtsi
> +++ b/arch/arm/boot/dts/r8a7740.dtsi
> @@ -14,8 +14,12 @@
>  	compatible = "renesas,r8a7740";
>  
>  	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
>  		cpu@0 {
>  			compatible = "arm,cortex-a9";
> +			device_type = "cpu";
> +			reg = <0x0>;
>  		};
>  	};
>  };
> -- 
> 1.7.12
> 
> 

Re: [RFC PATCH v3 07/17] ARM: dts: imx: cpus/cpu nodes dts updates

[Shawn Guo]

On Wed, Apr 24, 2013 at 06:28:12PM +0100, Lorenzo Pieralisi wrote:
> This patch updates the in-kernel dts files according to the latest cpus
> and cpu bindings updates for ARM.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> ---
>  arch/arm/boot/dts/imx23.dtsi  | 8 ++++++--
>  arch/arm/boot/dts/imx28.dtsi  | 8 ++++++--
>  arch/arm/boot/dts/imx6dl.dtsi | 2 ++
>  arch/arm/boot/dts/imx6q.dtsi  | 1 +
>  4 files changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
> index 56afcf4..0aae18b 100644
> --- a/arch/arm/boot/dts/imx23.dtsi
> +++ b/arch/arm/boot/dts/imx23.dtsi
> @@ -23,8 +23,12 @@
>  	};
>  
>  	cpus {
> -		cpu@0 {
> -			compatible = "arm,arm926ejs";
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
>  		};
>  	};
>  
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index 7ba4966..07f131fc 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -32,8 +32,12 @@
>  	};
>  
>  	cpus {
> -		cpu@0 {
> -			compatible = "arm,arm926ejs";
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
>  		};
>  	};
>  
> diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> index 63fafe2..b76d85e 100644
> --- a/arch/arm/boot/dts/imx6dl.dtsi
> +++ b/arch/arm/boot/dts/imx6dl.dtsi
> @@ -16,12 +16,14 @@
>  
>  		cpu@0 {
>  			compatible = "arm,cortex-a9";
> +			device_type = "cpu";
>  			reg = <0>;
>  			next-level-cache = <&L2>;
>  		};
>  
>  		cpu@1 {
>  			compatible = "arm,cortex-a9";
> +			device_type = "cpu";
>  			reg = <1>;
>  			next-level-cache = <&L2>;
>  		};
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index cba021e..65c1b62 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -17,6 +17,7 @@
>  
>  		cpu@0 {
>  			compatible = "arm,cortex-a9";
> +			device_type = "cpu";

Shouldn't this line be added for cpu@1, cpu@2 and cpu@3 too?  Other than
that,

Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

>  			reg = <0>;
>  			next-level-cache = <&L2>;
>  			operating-points = <
> -- 
> 1.7.12
> 
> 

Re: [RFC PATCH v3 07/17] ARM: dts: imx: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

On Thu, Apr 25, 2013 at 06:44:28AM +0100, Shawn Guo wrote:
> On Wed, Apr 24, 2013 at 06:28:12PM +0100, Lorenzo Pieralisi wrote:
> > This patch updates the in-kernel dts files according to the latest cpus
> > and cpu bindings updates for ARM.
> > 
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > ---
> >  arch/arm/boot/dts/imx23.dtsi  | 8 ++++++--
> >  arch/arm/boot/dts/imx28.dtsi  | 8 ++++++--
> >  arch/arm/boot/dts/imx6dl.dtsi | 2 ++
> >  arch/arm/boot/dts/imx6q.dtsi  | 1 +
> >  4 files changed, 15 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
> > index 56afcf4..0aae18b 100644
> > --- a/arch/arm/boot/dts/imx23.dtsi
> > +++ b/arch/arm/boot/dts/imx23.dtsi
> > @@ -23,8 +23,12 @@
> >  	};
> >  
> >  	cpus {
> > -		cpu@0 {
> > -			compatible = "arm,arm926ejs";
> > +		#address-cells = <0>;
> > +		#size-cells = <0>;
> > +
> > +		cpu {
> > +			compatible = "arm,arm926ej-s";
> > +			device_type = "cpu";
> >  		};
> >  	};
> >  
> > diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> > index 7ba4966..07f131fc 100644
> > --- a/arch/arm/boot/dts/imx28.dtsi
> > +++ b/arch/arm/boot/dts/imx28.dtsi
> > @@ -32,8 +32,12 @@
> >  	};
> >  
> >  	cpus {
> > -		cpu@0 {
> > -			compatible = "arm,arm926ejs";
> > +		#address-cells = <0>;
> > +		#size-cells = <0>;
> > +
> > +		cpu {
> > +			compatible = "arm,arm926ej-s";
> > +			device_type = "cpu";
> >  		};
> >  	};
> >  
> > diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> > index 63fafe2..b76d85e 100644
> > --- a/arch/arm/boot/dts/imx6dl.dtsi
> > +++ b/arch/arm/boot/dts/imx6dl.dtsi
> > @@ -16,12 +16,14 @@
> >  
> >  		cpu@0 {
> >  			compatible = "arm,cortex-a9";
> > +			device_type = "cpu";
> >  			reg = <0>;
> >  			next-level-cache = <&L2>;
> >  		};
> >  
> >  		cpu@1 {
> >  			compatible = "arm,cortex-a9";
> > +			device_type = "cpu";
> >  			reg = <1>;
> >  			next-level-cache = <&L2>;
> >  		};
> > diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> > index cba021e..65c1b62 100644
> > --- a/arch/arm/boot/dts/imx6q.dtsi
> > +++ b/arch/arm/boot/dts/imx6q.dtsi
> > @@ -17,6 +17,7 @@
> >  
> >  		cpu@0 {
> >  			compatible = "arm,cortex-a9";
> > +			device_type = "cpu";
> 
> Shouldn't this line be added for cpu@1, cpu@2 and cpu@3 too?  Other than
> that,

Yes, you are right, fixed. Thanks for reviewing.

Lorenzo

> 
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
> 
> >  			reg = <0>;
> >  			next-level-cache = <&L2>;
> >  			operating-points = <
> > -- 
> > 1.7.12
> > 
> > 
> 
> 

Re: [RFC PATCH v3 02/17] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Lorenzo Pieralisi]

On Wed, Apr 24, 2013 at 08:58:20PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:

[...]

> > +     - compatible:
> > +             Usage: required
> > +             Value type: <string>
> > +             Definition: should be one of:
> > +                         "arm,arm710t"
> > +                         "arm,arm720t"
> > +                         "arm,arm740t"
> > +                         "arm,arm7ej-s"
> > +                         "arm,arm7tdmi"
> > +                         "arm,arm7tdmi-s"
> > +                         "arm,arm9es"
> > +                         "arm,arm9ej-s"
> > +                         "arm,arm920t"
> > +                         "arm,arm922t"
> > +                         "arm,arm925"
> > +                         "arm,arm926e-s"
> > +                         "arm,arm926ej-s"
> > +                         "arm,arm940t"
> > +                         "arm,arm946e-s"
> > +                         "arm,arm966e-s"
> > +                         "arm,arm968e-s"
> > +                         "arm,arm9tdmi"
> > +                         "arm,arm1020e"
> > +                         "arm,arm1020t"
> > +                         "arm,arm1022e"
> > +                         "arm,arm1026ej-s"
> the common name is arm926ejs / arm1026ejs & co

The TRMs names are arm926ej-s/arm1026ej-s/... and other machs are using that
nomenclature already in dts files, time to consolidate.

Lorenzo

Re: [RFC PATCH v3 02/17] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Rob Herring]

On Wed, Apr 24, 2013 at 12:28 PM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
>
> Main changes:
>     - adds 64-bit bindings
>     - define usage of #address-cells
>     - define 32/64 dts compatibility settings
>     - defines behaviour on pre and post v7 uniprocessor systems
>     - adds ARM 11MPcore specific reg property definition
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---

[...]

> +       - enable-method
> +               Value type: <stringlist>
> +               Usage and definition depend on ARM architecture version and
> +               configuration:
> +                       # On ARM v8 64-bit systems running the OS in AArch64,
> +                         this property is required and must be "spin-table".

What about PSCI?

I don't think the ePAPR spin-table definition is sufficient for ARM.
How do you define wake up by SGI or sev instruction.

> +                       # On ARM 32-bit systems or ARM v8 systems running
> +                         the OS in AArch32 this property is prohibited.

Why?

Rob

Re: [RFC PATCH v3 02/17] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Lorenzo Pieralisi]

On Fri, Apr 26, 2013 at 03:51:10AM +0100, Rob Herring wrote:
> On Wed, Apr 24, 2013 at 12:28 PM, Lorenzo Pieralisi
> <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote:
> > In order to extend the current cpu nodes bindings to newer CPUs
> > inclusive of AArch64 and to update support for older ARM CPUs this
> > patch updates device tree documentation for the cpu nodes bindings.
> >
> > Main changes:
> >     - adds 64-bit bindings
> >     - define usage of #address-cells
> >     - define 32/64 dts compatibility settings
> >     - defines behaviour on pre and post v7 uniprocessor systems
> >     - adds ARM 11MPcore specific reg property definition
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> > ---
> 
> [...]
> 
> > +       - enable-method
> > +               Value type: <stringlist>
> > +               Usage and definition depend on ARM architecture version and
> > +               configuration:
> > +                       # On ARM v8 64-bit systems running the OS in AArch64,
> > +                         this property is required and must be "spin-table".
> 
> What about PSCI?

I should add it, at least for ARM v8.

> I don't think the ePAPR spin-table definition is sufficient for ARM.
> How do you define wake up by SGI or sev instruction.

I think Will described the wfe/sev mechanism in:

Documentation/arm64/booting.txt

and the ePAPR does the same in 5.5.2.2/5.5.2.3. Since this is a document
describing cpus/cpu nodes bindings I assume that description does not
belong here. Question is: do we need to specify an ARM implementation
specific enable-method to describe SGI/sev wake-up (ePAPR 5.5.3) ?

> > +                       # On ARM 32-bit systems or ARM v8 systems running
> > +                         the OS in AArch32 this property is prohibited.
> 
> Why?

Because if we define it optional with no possible set of values basically
it can be whatever string. I could define it optional with the same
allowed values as ARM v8 even if it is currently ignored, at least in Linux,
until PSCI implementations get merged.

Thanks,
Lorenzo

Re: [RFC PATCH v3 02/17] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Mark Rutland]

On Fri, Apr 26, 2013 at 11:18:40AM +0100, Lorenzo Pieralisi wrote:
> On Fri, Apr 26, 2013 at 03:51:10AM +0100, Rob Herring wrote:
> > On Wed, Apr 24, 2013 at 12:28 PM, Lorenzo Pieralisi
> > <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote:
> > > In order to extend the current cpu nodes bindings to newer CPUs
> > > inclusive of AArch64 and to update support for older ARM CPUs this
> > > patch updates device tree documentation for the cpu nodes bindings.
> > >
> > > Main changes:
> > >     - adds 64-bit bindings
> > >     - define usage of #address-cells
> > >     - define 32/64 dts compatibility settings
> > >     - defines behaviour on pre and post v7 uniprocessor systems
> > >     - adds ARM 11MPcore specific reg property definition
> > >
> > > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> > > ---
> > 
> > [...]
> > 
> > > +       - enable-method
> > > +               Value type: <stringlist>
> > > +               Usage and definition depend on ARM architecture version and
> > > +               configuration:
> > > +                       # On ARM v8 64-bit systems running the OS in AArch64,
> > > +                         this property is required and must be "spin-table".
> > 
> > What about PSCI?
> 
> I should add it, at least for ARM v8.

It's worth noting KVM uses it on v7 too, so it should be available for CPUs
that are v7+.

> 
> > I don't think the ePAPR spin-table definition is sufficient for ARM.
> > How do you define wake up by SGI or sev instruction.
> 
> I think Will described the wfe/sev mechanism in:
> 
> Documentation/arm64/booting.txt
> 
> and the ePAPR does the same in 5.5.2.2/5.5.2.3. Since this is a document
> describing cpus/cpu nodes bindings I assume that description does not
> belong here. Question is: do we need to specify an ARM implementation
> specific enable-method to describe SGI/sev wake-up (ePAPR 5.5.3) ?
> 
> > > +                       # On ARM 32-bit systems or ARM v8 systems running
> > > +                         the OS in AArch32 this property is prohibited.
> > 
> > Why?
> 
> Because if we define it optional with no possible set of values basically
> it can be whatever string. I could define it optional with the same
> allowed values as ARM v8 even if it is currently ignored, at least in Linux,
> until PSCI implementations get merged.

I believe kvmtool sets the enable-method to "psci" on v7, though I may be
mistaken. Adding Marc to Cc as he knows better.

Cheers,
Mark.

Re: [RFC PATCH v3 02/17] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Marc Zyngier]

On 26/04/13 12:48, Mark Rutland wrote:
> On Fri, Apr 26, 2013 at 11:18:40AM +0100, Lorenzo Pieralisi wrote:
>> On Fri, Apr 26, 2013 at 03:51:10AM +0100, Rob Herring wrote:
>>> On Wed, Apr 24, 2013 at 12:28 PM, Lorenzo Pieralisi
>>> <lorenzo.pieralisi@arm.com> wrote:
>>>> In order to extend the current cpu nodes bindings to newer CPUs
>>>> inclusive of AArch64 and to update support for older ARM CPUs this
>>>> patch updates device tree documentation for the cpu nodes bindings.
>>>>
>>>> Main changes:
>>>>     - adds 64-bit bindings
>>>>     - define usage of #address-cells
>>>>     - define 32/64 dts compatibility settings
>>>>     - defines behaviour on pre and post v7 uniprocessor systems
>>>>     - adds ARM 11MPcore specific reg property definition
>>>>
>>>> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>>>> ---
>>>
>>> [...]
>>>
>>>> +       - enable-method
>>>> +               Value type: <stringlist>
>>>> +               Usage and definition depend on ARM architecture version and
>>>> +               configuration:
>>>> +                       # On ARM v8 64-bit systems running the OS in AArch64,
>>>> +                         this property is required and must be "spin-table".
>>>
>>> What about PSCI?
>>
>> I should add it, at least for ARM v8.
> 
> It's worth noting KVM uses it on v7 too, so it should be available for CPUs
> that are v7+.
> 
>>
>>> I don't think the ePAPR spin-table definition is sufficient for ARM.
>>> How do you define wake up by SGI or sev instruction.
>>
>> I think Will described the wfe/sev mechanism in:
>>
>> Documentation/arm64/booting.txt
>>
>> and the ePAPR does the same in 5.5.2.2/5.5.2.3. Since this is a document
>> describing cpus/cpu nodes bindings I assume that description does not
>> belong here. Question is: do we need to specify an ARM implementation
>> specific enable-method to describe SGI/sev wake-up (ePAPR 5.5.3) ?
>>
>>>> +                       # On ARM 32-bit systems or ARM v8 systems running
>>>> +                         the OS in AArch32 this property is prohibited.
>>>
>>> Why?
>>
>> Because if we define it optional with no possible set of values basically
>> it can be whatever string. I could define it optional with the same
>> allowed values as ARM v8 even if it is currently ignored, at least in Linux,
>> until PSCI implementations get merged.
> 
> I believe kvmtool sets the enable-method to "psci" on v7, though I may be
> mistaken. Adding Marc to Cc as he knows better.

Indeed, kvmtool feeds the exact same DT to an ARMv7 guest:

[...]
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			enable-method = "psci";
			reg = <0x1>;
		};
[...]

The 32bit kernel doesn't check it, though.

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [RFC PATCH v3 05/17] ARM: dts: at91: cpus/cpu node dts updates

[Nicolas Ferre]

On 04/24/2013 07:28 PM, Lorenzo Pieralisi :
> This patch updates the in-kernel dts files according to the latest cpus
> and cpu bindings updates for ARM.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

With changes in compatible string... ok then.

Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

> ---
>  arch/arm/boot/dts/at91rm9200.dtsi  | 6 +++++-
>  arch/arm/boot/dts/at91sam9260.dtsi | 8 ++++++--
>  arch/arm/boot/dts/at91sam9263.dtsi | 8 ++++++--
>  arch/arm/boot/dts/at91sam9g45.dtsi | 8 ++++++--
>  arch/arm/boot/dts/at91sam9n12.dtsi | 8 ++++++--
>  arch/arm/boot/dts/at91sam9x5.dtsi  | 8 ++++++--
>  6 files changed, 35 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
> index b0268a5..f16b3d4 100644
> --- a/arch/arm/boot/dts/at91rm9200.dtsi
> +++ b/arch/arm/boot/dts/at91rm9200.dtsi
> @@ -34,8 +34,12 @@
>  		ssc2 = &ssc2;
>  	};
>  	cpus {
> -		cpu@0 {
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
>  			compatible = "arm,arm920t";
> +			device_type = "cpu";
>  		};
>  	};
>  
> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
> index cb7bcc5..c4eeef7 100644
> --- a/arch/arm/boot/dts/at91sam9260.dtsi
> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
> @@ -32,8 +32,12 @@
>  		ssc0 = &ssc0;
>  	};
>  	cpus {
> -		cpu@0 {
> -			compatible = "arm,arm926ejs";
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
>  		};
>  	};
>  
> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
> index 271d4de..f3b5c2a 100644
> --- a/arch/arm/boot/dts/at91sam9263.dtsi
> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
> @@ -29,8 +29,12 @@
>  		ssc1 = &ssc1;
>  	};
>  	cpus {
> -		cpu@0 {
> -			compatible = "arm,arm926ejs";
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
>  		};
>  	};
>  
> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> index 6b1d4ca..6c18bd3 100644
> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> @@ -35,8 +35,12 @@
>  		ssc1 = &ssc1;
>  	};
>  	cpus {
> -		cpu@0 {
> -			compatible = "arm,arm926ejs";
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
>  		};
>  	};
>  
> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
> index 7750f98..c3b11af 100644
> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
> @@ -31,8 +31,12 @@
>  		ssc0 = &ssc0;
>  	};
>  	cpus {
> -		cpu@0 {
> -			compatible = "arm,arm926ejs";
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
>  		};
>  	};
>  
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index aa98e64..6c39d0f 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -33,8 +33,12 @@
>  		ssc0 = &ssc0;
>  	};
>  	cpus {
> -		cpu@0 {
> -			compatible = "arm,arm926ejs";
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
>  		};
>  	};
>  
> 


-- 
Nicolas Ferre

Re: [RFC PATCH v3 11/17] ARM: dts: prima2: cpus/cpu node dts updates

[Barry Song]

2013/4/25 Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>:
> This patch updates the in-kernel dts files according to the latest cpus
> and cpu bindings updates for ARM.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>

Acked-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>

> ---
>  arch/arm/boot/dts/prima2.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
> index 3329719..02edd89 100644
> --- a/arch/arm/boot/dts/prima2.dtsi
> +++ b/arch/arm/boot/dts/prima2.dtsi
> @@ -18,6 +18,8 @@
>                 #size-cells = <0>;
>
>                 cpu@0 {
> +                       compatible = "arm,cortex-a9";
> +                       device_type = "cpu";
>                         reg = <0x0>;
>                         d-cache-line-size = <32>;
>                         i-cache-line-size = <32>;
> --

Re: [RFC PATCH v3 05/17] ARM: dts: at91: cpus/cpu node dts updates

[Nicolas Ferre]

On 29/04/2013 11:54, Nicolas Ferre :
> On 04/24/2013 07:28 PM, Lorenzo Pieralisi :
>> This patch updates the in-kernel dts files according to the latest cpus
>> and cpu bindings updates for ARM.
>>
>> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
>
> With changes in compatible string... ok then.
>
> Acked-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

Now that our Cortex-A5 is in mainline, can you please update the:

arch/arm/boot/dts/sama5d3.dtsi

as-well?

Thanks, best regards,

>> ---
>>   arch/arm/boot/dts/at91rm9200.dtsi  | 6 +++++-
>>   arch/arm/boot/dts/at91sam9260.dtsi | 8 ++++++--
>>   arch/arm/boot/dts/at91sam9263.dtsi | 8 ++++++--
>>   arch/arm/boot/dts/at91sam9g45.dtsi | 8 ++++++--
>>   arch/arm/boot/dts/at91sam9n12.dtsi | 8 ++++++--
>>   arch/arm/boot/dts/at91sam9x5.dtsi  | 8 ++++++--
>>   6 files changed, 35 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
>> index b0268a5..f16b3d4 100644
>> --- a/arch/arm/boot/dts/at91rm9200.dtsi
>> +++ b/arch/arm/boot/dts/at91rm9200.dtsi
>> @@ -34,8 +34,12 @@
>>   		ssc2 = &ssc2;
>>   	};
>>   	cpus {
>> -		cpu@0 {
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>>   			compatible = "arm,arm920t";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
>> index cb7bcc5..c4eeef7 100644
>> --- a/arch/arm/boot/dts/at91sam9260.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
>> @@ -32,8 +32,12 @@
>>   		ssc0 = &ssc0;
>>   	};
>>   	cpus {
>> -		cpu@0 {
>> -			compatible = "arm,arm926ejs";
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>> +			compatible = "arm,arm926ej-s";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
>> index 271d4de..f3b5c2a 100644
>> --- a/arch/arm/boot/dts/at91sam9263.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
>> @@ -29,8 +29,12 @@
>>   		ssc1 = &ssc1;
>>   	};
>>   	cpus {
>> -		cpu@0 {
>> -			compatible = "arm,arm926ejs";
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>> +			compatible = "arm,arm926ej-s";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
>> index 6b1d4ca..6c18bd3 100644
>> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
>> @@ -35,8 +35,12 @@
>>   		ssc1 = &ssc1;
>>   	};
>>   	cpus {
>> -		cpu@0 {
>> -			compatible = "arm,arm926ejs";
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>> +			compatible = "arm,arm926ej-s";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
>> index 7750f98..c3b11af 100644
>> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
>> @@ -31,8 +31,12 @@
>>   		ssc0 = &ssc0;
>>   	};
>>   	cpus {
>> -		cpu@0 {
>> -			compatible = "arm,arm926ejs";
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>> +			compatible = "arm,arm926ej-s";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
>> index aa98e64..6c39d0f 100644
>> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
>> @@ -33,8 +33,12 @@
>>   		ssc0 = &ssc0;
>>   	};
>>   	cpus {
>> -		cpu@0 {
>> -			compatible = "arm,arm926ejs";
>> +		#address-cells = <0>;
>> +		#size-cells = <0>;
>> +
>> +		cpu {
>> +			compatible = "arm,arm926ej-s";
>> +			device_type = "cpu";
>>   		};
>>   	};
>>
>>
>
>


-- 
Nicolas Ferre

Re: [RFC PATCH v3 05/17] ARM: dts: at91: cpus/cpu node dts updates

[Lorenzo Pieralisi]

On Tue, May 14, 2013 at 10:20:00AM +0100, Nicolas Ferre wrote:
> On 29/04/2013 11:54, Nicolas Ferre :
> > On 04/24/2013 07:28 PM, Lorenzo Pieralisi :
> >> This patch updates the in-kernel dts files according to the latest cpus
> >> and cpu bindings updates for ARM.
> >>
> >> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> >
> > With changes in compatible string... ok then.
> >
> > Acked-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> 
> Now that our Cortex-A5 is in mainline, can you please update the:
> 
> arch/arm/boot/dts/sama5d3.dtsi
> 
> as-well?

I will, no problems.

> Thanks, best regards,

Cheers,
Lorenzo

> 
> >> ---
> >>   arch/arm/boot/dts/at91rm9200.dtsi  | 6 +++++-
> >>   arch/arm/boot/dts/at91sam9260.dtsi | 8 ++++++--
> >>   arch/arm/boot/dts/at91sam9263.dtsi | 8 ++++++--
> >>   arch/arm/boot/dts/at91sam9g45.dtsi | 8 ++++++--
> >>   arch/arm/boot/dts/at91sam9n12.dtsi | 8 ++++++--
> >>   arch/arm/boot/dts/at91sam9x5.dtsi  | 8 ++++++--
> >>   6 files changed, 35 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
> >> index b0268a5..f16b3d4 100644
> >> --- a/arch/arm/boot/dts/at91rm9200.dtsi
> >> +++ b/arch/arm/boot/dts/at91rm9200.dtsi
> >> @@ -34,8 +34,12 @@
> >>   		ssc2 = &ssc2;
> >>   	};
> >>   	cpus {
> >> -		cpu@0 {
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >>   			compatible = "arm,arm920t";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
> >> index cb7bcc5..c4eeef7 100644
> >> --- a/arch/arm/boot/dts/at91sam9260.dtsi
> >> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
> >> @@ -32,8 +32,12 @@
> >>   		ssc0 = &ssc0;
> >>   	};
> >>   	cpus {
> >> -		cpu@0 {
> >> -			compatible = "arm,arm926ejs";
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >> +			compatible = "arm,arm926ej-s";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
> >> index 271d4de..f3b5c2a 100644
> >> --- a/arch/arm/boot/dts/at91sam9263.dtsi
> >> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
> >> @@ -29,8 +29,12 @@
> >>   		ssc1 = &ssc1;
> >>   	};
> >>   	cpus {
> >> -		cpu@0 {
> >> -			compatible = "arm,arm926ejs";
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >> +			compatible = "arm,arm926ej-s";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> >> index 6b1d4ca..6c18bd3 100644
> >> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> >> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> >> @@ -35,8 +35,12 @@
> >>   		ssc1 = &ssc1;
> >>   	};
> >>   	cpus {
> >> -		cpu@0 {
> >> -			compatible = "arm,arm926ejs";
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >> +			compatible = "arm,arm926ej-s";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
> >> index 7750f98..c3b11af 100644
> >> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
> >> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
> >> @@ -31,8 +31,12 @@
> >>   		ssc0 = &ssc0;
> >>   	};
> >>   	cpus {
> >> -		cpu@0 {
> >> -			compatible = "arm,arm926ejs";
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >> +			compatible = "arm,arm926ej-s";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> >> index aa98e64..6c39d0f 100644
> >> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> >> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> >> @@ -33,8 +33,12 @@
> >>   		ssc0 = &ssc0;
> >>   	};
> >>   	cpus {
> >> -		cpu@0 {
> >> -			compatible = "arm,arm926ejs";
> >> +		#address-cells = <0>;
> >> +		#size-cells = <0>;
> >> +
> >> +		cpu {
> >> +			compatible = "arm,arm926ej-s";
> >> +			device_type = "cpu";
> >>   		};
> >>   	};
> >>
> >>
> >
> >
> 
> 
> -- 
> Nicolas Ferre
>