* [PATCH 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR
2013-05-20 8:48 [PATCH 0/6] ARM: imx6q{dl}: add the WEIM driver Huang Shijie
@ 2013-05-20 8:49 ` Huang Shijie
0 siblings, 0 replies; 4+ messages in thread
From: Huang Shijie @ 2013-05-20 8:49 UTC (permalink / raw)
To: grant.likely
Cc: rob.herring, arnd, devicetree-discuss, linux-kernel,
linux-arm-kernel, shawn.guo, Huang Shijie
Add a pinctrl for WEIM nor.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
arch/arm/boot/dts/imx6q.dtsi | 58 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 58 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ed11bcf..e6174c7 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -323,6 +323,64 @@
>;
};
};
+
+ weim {
+ pinctrl_weim_nor_1: weim_norgrp-1 {
+ fsl,pins = <
+ MX6Q_PAD_EIM_OE__EIM_OE_B 0x10
+ MX6Q_PAD_EIM_RW__EIM_RW 0x10
+ MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x10
+ MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x10
+ MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x8000
+ MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x8000
+
+ /* data */
+ MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+ MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+ MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+ MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+ MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+ MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+ MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+ MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+ MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+ MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+ MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+ MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+ MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+ MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+ MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+ MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+
+ /* address */
+ MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+ MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+ MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+ MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+ MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+ MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+ MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+ MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+ MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
+ MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
+ MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
+ MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1
+ MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1
+ MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1
+ MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1
+ MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1
+ MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1
+ MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1
+ MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1
+ MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1
+ MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1
+ MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1
+ MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1
+ MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1
+ >;
+ };
+
+ };
};
};
--
1.7.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* RE: [PATCH 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR
@ 2013-05-21 16:16 Chaiken, Alison
[not found] ` <60BA5429A0E1584BA3633194F6F993B50252C8D8-0dz9ie/QGrnnlEkxMdpx1dQH9K4/4qFeAL8bYrjMMd8@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Chaiken, Alison @ 2013-05-21 16:16 UTC (permalink / raw)
To: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
Cc: b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index ed11bcf..e6174c7 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -323,6 +323,64 @@
> >;
> };
> };
> +
> + weim {
> + pinctrl_weim_nor_1: weim_norgrp-1 {
> + fsl,pins = <
> + MX6Q_PAD_EIM_OE__EIM_OE_B 0x10
> + MX6Q_PAD_EIM_RW__EIM_RW 0x10
> + MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x10
> + MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x10
> + MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x8000
> + MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x8000
The following values are derived using Table 4-1 of "i.MX 6Dual/6Quad Applications Processor Reference Manual Document Number: IMX6DQRM Rev. 1, 04/2013":
MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 0xb0b1
MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 0xb0b1
MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 0xb0b1
MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 0xb060
(I wrote a short C program that parses a human-readable property table for the pins and spits out hex to generate them.) How are 0x10 values calculated? Are settings for MX6Q_PAD_EIM_LBA__EIM_LBA_B and MX6Q_PAD_EIM_BCLK__EIM_BCLK useful? We run NOR without them.
> + MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
> + MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
> + MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
> + MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
> + MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
Are these names correct? "MX6Q_PAD_EIM_A16__EIM_ADDR16" but "MX6Q_PAD_EIM_DA15__EIM_AD15" et cetera?
--
Alison Chaiken
alison_chaiken-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR
[not found] ` <60BA5429A0E1584BA3633194F6F993B50252C8D8-0dz9ie/QGrnnlEkxMdpx1dQH9K4/4qFeAL8bYrjMMd8@public.gmane.org>
@ 2013-05-22 8:12 ` Huang Shijie
2013-05-23 5:43 ` Huang Shijie
1 sibling, 0 replies; 4+ messages in thread
From: Huang Shijie @ 2013-05-22 8:12 UTC (permalink / raw)
To: Chaiken, Alison
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
于 2013年05月22日 00:16, Chaiken, Alison 写道:
>> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
>> index ed11bcf..e6174c7 100644
>> --- a/arch/arm/boot/dts/imx6q.dtsi
>> +++ b/arch/arm/boot/dts/imx6q.dtsi
>> @@ -323,6 +323,64 @@
>> >;
>> };
>> };
>> +
>> + weim {
>> + pinctrl_weim_nor_1: weim_norgrp-1 {
>> + fsl,pins =<
>> + MX6Q_PAD_EIM_OE__EIM_OE_B 0x10
>> + MX6Q_PAD_EIM_RW__EIM_RW 0x10
>> + MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x10
>> + MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x10
>> + MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x8000
>> + MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x8000
> The following values are derived using Table 4-1 of "i.MX 6Dual/6Quad Applications Processor Reference Manual Document Number: IMX6DQRM Rev. 1, 04/2013":
>
> MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 0xb0b1
> MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 0xb0b1
> MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 0xb0b1
> MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 0xb060
>
> (I wrote a short C program that parses a human-readable property table for the pins and spits out hex to generate them.) How are 0x10 values calculated? Are settings
0x10 is from our legacy bsp code.
I think the 0xb0b1 is ok too.
> for MX6Q_PAD_EIM_LBA__EIM_LBA_B and MX6Q_PAD_EIM_BCLK__EIM_BCLK useful? We run NOR without them.
yes. we may remove them.
>> + MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
>> + MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
>> + MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
>> + MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
>> + MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
> Are these names correct? "MX6Q_PAD_EIM_A16__EIM_ADDR16" but "MX6Q_PAD_EIM_DA15__EIM_AD15" et cetera?
>
I think it's correct.
We do not have the MX6Q_PAD_EIM_DA16__EIM_AD16.
thanks
Huang Shijie
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devicetree-discuss mailing list
devicetree-discuss@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR
[not found] ` <60BA5429A0E1584BA3633194F6F993B50252C8D8-0dz9ie/QGrnnlEkxMdpx1dQH9K4/4qFeAL8bYrjMMd8@public.gmane.org>
2013-05-22 8:12 ` Huang Shijie
@ 2013-05-23 5:43 ` Huang Shijie
1 sibling, 0 replies; 4+ messages in thread
From: Huang Shijie @ 2013-05-23 5:43 UTC (permalink / raw)
To: Chaiken, Alison
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
于 2013年05月22日 00:16, Chaiken, Alison 写道:
> MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 0xb0b1
> MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 0xb0b1
> MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 0xb0b1
> MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 0xb0608
I double-checked these pads , I find i copied the wrong value from our
legacy code.
thanks for point this. I really appreciate it.
Huang Shijie
_______________________________________________
devicetree-discuss mailing list
devicetree-discuss@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 4+ messages in thread
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2013-05-21 16:16 [PATCH 4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR Chaiken, Alison
[not found] ` <60BA5429A0E1584BA3633194F6F993B50252C8D8-0dz9ie/QGrnnlEkxMdpx1dQH9K4/4qFeAL8bYrjMMd8@public.gmane.org>
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