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Wed, 09 Oct 2024 00:54:01 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99309aa6afsm610392466b.112.2024.10.09.00.53.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Oct 2024 00:54:00 -0700 (PDT) Message-ID: <519e6de9-7ad2-4c6e-aad4-f7cec6ddaf0a@tuxon.dev> Date: Wed, 9 Oct 2024 10:53:59 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger Content-Language: en-US To: Prabhakar , Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar References: <20241004123658.764557-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20241004123658.764557-4-prabhakar.mahadev-lad.rj@bp.renesas.com> From: claudiu beznea In-Reply-To: <20241004123658.764557-4-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 04.10.2024 15:36, Prabhakar wrote: > From: Lad Prabhakar > > Add support for configuring the multiplexed pins as schmitt-trigger > inputs. > > Signed-off-by: Lad Prabhakar > Reviewed-by: Geert Uytterhoeven Same here: Tested-by: Claudiu Beznea > --- v1->v2 > - Included RB tag > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index 8d576cc74003..13708c71f938 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -140,6 +140,7 @@ > #define PUPD(off) (0x1C00 + (off) * 8) > #define ISEL(off) (0x2C00 + (off) * 8) > #define NOD(off) (0x3000 + (off) * 8) > +#define SMT(off) (0x3400 + (off) * 8) > #define SD_CH(off, ch) ((off) + (ch) * 4) > #define ETH_POC(off, ch) ((off) + (ch) * 4) > #define QSPI (0x3008) > @@ -162,6 +163,7 @@ > #define SR_MASK 0x01 > #define PUPD_MASK 0x03 > #define NOD_MASK 0x01 > +#define SMT_MASK 0x01 > > #define PM_INPUT 0x1 > #define PM_OUTPUT 0x2 > @@ -1351,6 +1353,15 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, > return -EINVAL; > break; > > + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: > + if (!(cfg & PIN_CFG_SMT)) > + return -EINVAL; > + > + arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); > + if (!arg) > + return -EINVAL; > + break; > + > case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: > if (!(cfg & PIN_CFG_IOLH_RZV2H)) > return -EINVAL; > @@ -1489,6 +1500,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, > param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0); > break; > > + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: > + if (!(cfg & PIN_CFG_SMT)) > + return -EINVAL; > + > + rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); > + break; > + > case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: > if (!(cfg & PIN_CFG_IOLH_RZV2H)) > return -EINVAL;