From: Tero Kristo <t-kristo@ti.com>
To: Nishanth Menon <nm@ti.com>
Cc: linux-omap@vger.kernel.org, paul@pwsan.com, khilman@linaro.org,
tony@atomide.com, mturquette@linaro.org, rnayak@ti.com,
linux-arm-kernel@lists.infradead.org,
devicetree-discuss@lists.ozlabs.org
Subject: Re: [PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support
Date: Wed, 31 Jul 2013 18:03:52 +0300 [thread overview]
Message-ID: <51F92758.20405@ti.com> (raw)
In-Reply-To: <51F81D3A.7080007@ti.com>
On 07/30/2013 11:08 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> OMAP3 has slightly different DPLLs from those compared to OMAP4. Modified
>> code for the same.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>> drivers/clk/omap/dpll.c | 96
>> +++++++++++++++++++++++++++++++++++++++++------
>> 1 file changed, 85 insertions(+), 11 deletions(-)
>>
> :) wont repeat the binding crib again..
>
>> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
>> index d8a958a..ecb1fbd 100644
>> --- a/drivers/clk/omap/dpll.c
>> +++ b/drivers/clk/omap/dpll.c
>> @@ -26,6 +26,11 @@
>> #include <linux/of_address.h>
>> #include <linux/clk/omap.h>
>>
>> +enum {
>> + SUBTYPE_OMAP3_DPLL,
>> + SUBTYPE_OMAP4_DPLL,
>> +};
>> +
>> static const struct clk_ops dpll_m4xen_ck_ops = {
>> .enable = &omap3_noncore_dpll_enable,
>> .disable = &omap3_noncore_dpll_disable,
>> @@ -40,6 +45,13 @@ static const struct clk_ops dpll_core_ck_ops = {
>> .get_parent = &omap2_init_dpll_parent,
>> };
>>
>> +static const struct clk_ops omap3_dpll_core_ck_ops = {
>> + .init = &omap2_init_clk_clkdm,
>> + .get_parent = &omap2_init_dpll_parent,
>> + .recalc_rate = &omap3_dpll_recalc,
>> + .round_rate = &omap2_dpll_round_rate,
>> +};
>> +
>> static const struct clk_ops dpll_ck_ops = {
>> .enable = &omap3_noncore_dpll_enable,
>> .disable = &omap3_noncore_dpll_disable,
>> @@ -50,6 +62,26 @@ static const struct clk_ops dpll_ck_ops = {
>> .init = &omap2_init_clk_clkdm,
>> };
>>
>> +static const struct clk_ops omap3_dpll_ck_ops = {
>> + .init = &omap2_init_clk_clkdm,
>> + .enable = &omap3_noncore_dpll_enable,
>> + .disable = &omap3_noncore_dpll_disable,
>> + .get_parent = &omap2_init_dpll_parent,
>> + .recalc_rate = &omap3_dpll_recalc,
>> + .set_rate = &omap3_noncore_dpll_set_rate,
>> + .round_rate = &omap2_dpll_round_rate,
>> +};
>> +
>> +static const struct clk_ops omap3_dpll_per_ck_ops = {
>> + .init = &omap2_init_clk_clkdm,
>> + .enable = &omap3_noncore_dpll_enable,
>> + .disable = &omap3_noncore_dpll_disable,
>> + .get_parent = &omap2_init_dpll_parent,
>> + .recalc_rate = &omap3_dpll_recalc,
>> + .set_rate = &omap3_dpll4_set_rate,
>> + .round_rate = &omap2_dpll_round_rate,
>> +};
>> +
>> static const struct clk_ops dpll_x2_ck_ops = {
>> .recalc_rate = &omap3_clkoutx2_recalc,
>> };
>> @@ -144,7 +176,9 @@ struct clk *omap_clk_register_dpll_x2(struct
>> device *dev, const char *name,
>> * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
>> */
>> static void __init of_omap_dpll_setup(struct device_node *node,
>> - const struct clk_ops *ops)
>> + const struct clk_ops *ops, u32 freqsel,
>> + u32 modes, u8 mul_div_shift,
>> + int subtype)
>> {
>> struct clk *clk;
>> const char *clk_name = node->name;
>> @@ -157,8 +191,8 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>> u32 idlest_mask = 0x1;
>> u32 enable_mask = 0x7;
>> u32 autoidle_mask = 0x7;
>> - u32 mult_mask = 0x7ff << 8;
>> - u32 div1_mask = 0x7f;
>> + u32 mult_mask = 0x7ff << (8 + mul_div_shift);
>> + u32 div1_mask = 0x7f << mul_div_shift;
>> u32 max_multiplier = 2047;
>> u32 max_divider = 128;
>> u32 min_divider = 1;
>> @@ -193,7 +227,7 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>
>> clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>> dd->clk_ref = of_clk_get_from_provider(&clkspec);
>> - if (!dd->clk_ref) {
>> + if (IS_ERR(dd->clk_ref)) {
>
> belongs to original patch.
Agree.
>
>> pr_err("%s: ti,clk-ref for %s not found\n", __func__,
>> clk_name);
>> goto cleanup;
>> @@ -201,7 +235,7 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>
>> clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
>> dd->clk_bypass = of_clk_get_from_provider(&clkspec);
>> - if (!dd->clk_bypass) {
>> + if (IS_ERR(dd->clk_bypass)) {
>
> same
Ditto.
>
>> pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>> clk_name);
>> goto cleanup;
>> @@ -225,14 +259,31 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>> dd->enable_mask = enable_mask;
>> dd->autoidle_mask = autoidle_mask;
>>
>> - dd->modes = 0xa0;
>> + if (!of_property_read_u32(node, "ti,recal-en-bit", &val))
>> + dd->recal_en_bit = val;
>> +
>> + if (!of_property_read_u32(node, "ti,recal-st-bit", &val))
>> + dd->recal_st_bit = val;
>> +
>> + if (!of_property_read_u32(node, "ti,auto-recal-bit", &val))
>> + dd->auto_recal_bit = val;
>
> now I understand what it means.
I am not quite sure you do, as I don't quite get your comment here. :)
You referring to that dd->modes part?
>
>> +
>> + of_property_read_u32(node, "ti,modes", &modes);
> i see we pass in modes, and read ti,modes to &modes. it is a bit sketchy
> without bindings documentation.
ti,modes can be used to override the default modes.
>
>> +
>> + dd->modes = modes;
>
> Should have belonged to original patch.
If I squash this then we are fine.
>
>> +
>> + dd->freqsel_mask = freqsel;
>>
>> if (of_property_read_bool(node, "ti,dpll-j-type")) {
>> dd->sddiv_mask = 0xff000000;
>> - mult_mask = 0xfff << 8;
>> - div1_mask = 0xff;
>> + mult_mask = 0xfff << (8 + mul_div_shift);
>> max_multiplier = 4095;
>> - max_divider = 256;
>> + if (subtype == SUBTYPE_OMAP3_DPLL) {
>> + dd->dco_mask = 0xe00000;
>> + } else {
>> + div1_mask = 0xff << mul_div_shift;
>> + max_divider = 256;
>> + }
>> }
>>
>> if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
>> @@ -281,7 +332,30 @@ static void __init of_omap_dpll_x2_setup(struct
>> device_node *node)
>>
>> __init void of_omap3_dpll_setup(struct device_node *node)
>> {
>> - /* XXX: to be done */
>> + const struct clk_ops *ops;
>> + u32 freqsel = 0xf0;
>> + u32 modes = 0xa0;
>> + u8 mul_div_shift = 0;
>> +
>> + ops = &omap3_dpll_ck_ops;
>> +
>> + if (of_property_read_bool(node, "ti,dpll-core")) {
>> + ops = &omap3_dpll_core_ck_ops;
>> + mul_div_shift = 8;
>> + modes = 0x0;
>> + }
>> +
>> + if (of_property_read_bool(node, "ti,dpll-peripheral")) {
>> + ops = &omap3_dpll_per_ck_ops;
>> + freqsel = 0xf00000;
>> + }
>> +
>> + if (of_property_read_bool(node, "ti,dpll-j-type"))
>> + freqsel = 0x0;
>> +
>> + of_omap_dpll_setup(node, ops, freqsel, modes, mul_div_shift,
>> + SUBTYPE_OMAP3_DPLL);
>> +
>> }
>> EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
>> CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock",
>> of_omap3_dpll_setup);
>> @@ -306,7 +380,7 @@ __init void of_omap4_dpll_setup(struct device_node
>> *node)
>> if (of_property_read_bool(node, "ti,dpll-no-gate"))
>> ops = &dpll_no_gate_ck_ops;
>>
>> - of_omap_dpll_setup(node, ops);
>> + of_omap_dpll_setup(node, ops, 0, 0xa0, 0, SUBTYPE_OMAP4_DPLL);
> what is 0xa0?
Magic modes for DPLL. I'll copy over the macro def as mentioned in one
of the previous patches.
>
>> }
>> EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>> CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>> of_omap4_dpll_setup);
>>
>
> I think this should be squashed and a single dpll.c introduction to be
> done.
Ok.
>
>
next prev parent reply other threads:[~2013-07-31 15:03 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-23 7:19 [PATCHv4 00/33] ARM: OMAP: clock conversion to DT Tero Kristo
2013-07-23 7:19 ` [PATCHv4 01/33] CLK: clkdev: add support for looking up clocks from DT Tero Kristo
2013-07-30 15:04 ` Nishanth Menon
2013-07-31 8:43 ` Tero Kristo
2013-07-23 7:19 ` [PATCHv4 02/33] clk: omap: introduce clock driver Tero Kristo
2013-07-30 15:21 ` Nishanth Menon
2013-07-31 8:59 ` Tero Kristo
2013-08-01 13:44 ` Nishanth Menon
2013-08-01 14:59 ` Tero Kristo
2013-07-23 7:19 ` [PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support Tero Kristo
2013-07-30 16:23 ` Nishanth Menon
2013-07-31 9:46 ` Tero Kristo
2013-08-01 14:00 ` Nishanth Menon
2013-08-01 15:08 ` Tero Kristo
2013-08-01 15:13 ` Nishanth Menon
2013-08-01 8:29 ` Rajendra Nayak
2013-07-23 7:19 ` [PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver Tero Kristo
2013-07-30 18:22 ` Nishanth Menon
2013-07-31 9:59 ` Tero Kristo
2013-07-23 7:20 ` [PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism Tero Kristo
2013-07-30 18:40 ` Nishanth Menon
2013-07-31 10:07 ` Tero Kristo
2013-08-01 14:25 ` Nishanth Menon
2013-08-01 15:18 ` Tero Kristo
2013-08-01 15:24 ` Nishanth Menon
2013-08-01 15:30 ` Tero Kristo
2013-08-02 7:22 ` Tony Lindgren
2013-07-23 7:20 ` [PATCHv4 06/33] CLK: omap: add autoidle support Tero Kristo
2013-07-30 18:56 ` Nishanth Menon
2013-07-31 10:13 ` Tero Kristo
2013-07-23 7:20 ` [PATCHv4 07/33] CLK: omap: add support for OMAP gate clock Tero Kristo
2013-07-30 19:17 ` Nishanth Menon
2013-07-31 14:45 ` Tero Kristo
2013-07-23 7:20 ` [PATCHv4 08/33] ARM: dts: omap4 clock data Tero Kristo
2013-07-30 19:27 ` Nishanth Menon
2013-07-31 14:49 ` Tero Kristo
2013-07-23 7:20 ` [PATCHv4 09/33] CLK: omap: add omap4 clock init file Tero Kristo
2013-07-30 19:33 ` Nishanth Menon
2013-07-31 14:52 ` Tero Kristo
2013-07-23 7:20 ` [PATCHv4 10/33] ARM: OMAP4: remove old clock data and link in new clock init code Tero Kristo
2013-07-30 19:42 ` Nishanth Menon
2013-07-31 14:55 ` Tero Kristo
2013-07-23 7:20 ` [PATCHv4 11/33] ARM: dts: omap5 clock data Tero Kristo
2013-07-23 7:20 ` [PATCHv4 12/33] CLK: omap: add omap5 clock init file Tero Kristo
2013-07-23 7:20 ` [PATCHv4 13/33] ARM: dts: dra7 clock data Tero Kristo
2013-07-23 7:20 ` [PATCHv4 14/33] CLK: omap: add dra7 clock init file Tero Kristo
2013-07-23 7:20 ` [PATCHv4 15/33] CLK: OMAP: DPLL: add support for DT property ti,dpll-no-gate Tero Kristo
2013-07-30 19:18 ` Nishanth Menon
2013-07-31 14:56 ` Tero Kristo
2013-07-23 7:20 ` [PATCHv4 16/33] CLK: OMAP: DPLL: do not of_iomap NULL autoidle register Tero Kristo
2013-07-30 19:49 ` Nishanth Menon
2013-07-31 14:57 ` Tero Kristo
2013-07-23 7:20 ` [PATCHv4 17/33] CLK: DT: add support for set-rate-parent flag Tero Kristo
2013-07-30 19:58 ` Nishanth Menon
2013-07-23 7:20 ` [PATCHv4 18/33] ARM: dts: am33xx clock data Tero Kristo
2013-07-23 7:20 ` [PATCHv4 19/33] CLK: omap: add am33xx clock init file Tero Kristo
2013-07-30 20:00 ` Nishanth Menon
2013-07-31 14:59 ` Tero Kristo
2013-07-23 7:20 ` [PATCHv4 20/33] ARM: AM33xx: remove old clock data and link in new clock init code Tero Kristo
2013-07-23 7:20 ` [PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support Tero Kristo
2013-07-30 20:08 ` Nishanth Menon
2013-07-31 15:03 ` Tero Kristo [this message]
2013-07-23 7:20 ` [PATCHv4 22/33] CLK: OMAP: update gate clock setup for OMAP3 Tero Kristo
2013-07-30 20:13 ` Nishanth Menon
2013-07-31 15:05 ` Tero Kristo
2013-07-23 7:20 ` [PATCHv4 23/33] CLK: OMAP: add interface clock support " Tero Kristo
2013-07-30 20:23 ` Nishanth Menon
2013-07-31 15:09 ` Tero Kristo
2013-08-01 14:50 ` Nishanth Menon
2013-07-23 7:20 ` [PATCHv4 24/33] CLK: OMAP: move some defines from machine to driver header Tero Kristo
2013-07-23 7:20 ` [PATCHv4 25/33] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm Tero Kristo
2013-07-23 7:20 ` [PATCHv4 26/33] CLK: omap: gate: add support for OMAP36xx dpllx_mx_ck:s Tero Kristo
2013-07-23 7:20 ` [PATCHv4 27/33] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name Tero Kristo
2013-07-23 7:20 ` [PATCHv4 28/33] ARM: dts: omap3 clock data Tero Kristo
2013-07-23 7:20 ` [PATCHv4 30/33] clk: OMAP: DRA7: Add APLL support Tero Kristo
2013-07-23 7:20 ` [PATCHv4 31/33] ARM: dts: clk: Add apll related clocks Tero Kristo
2013-07-23 7:20 ` [PATCHv4 32/33] clk: OMAP: DRA7: Change apll_pcie_m2_ck to fixed factor clock Tero Kristo
2013-07-23 7:20 ` [PATCHv4 33/33] clk: DTS: DRA7: Add PCIe related clock nodes Tero Kristo
2013-07-24 14:16 ` [PATCHv4 00/33] ARM: OMAP: clock conversion to DT Roger Quadros
[not found] ` <1374564028-11352-30-git-send-email-t-kristo@ti.com>
2013-07-30 20:19 ` [PATCHv4 29/33] CLK: omap: add omap3 clock init file Nishanth Menon
2013-07-31 6:35 ` Tony Lindgren
2013-07-31 15:10 ` Tero Kristo
2013-08-02 7:24 ` Tony Lindgren
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