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[2003:f6:ef15:2100:2c2b:bcc5:835e:c2dd]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431b437d362sm18232865e9.0.2024.10.29.01.09.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 01:09:22 -0700 (PDT) Message-ID: <51afb385d291d27ea4e5d8b1f5f3389573b119d5.camel@gmail.com> Subject: Re: [PATCH v9 4/8] iio: dac: adi-axi-dac: extend features From: Nuno =?ISO-8859-1?Q?S=E1?= To: Angelo Dureghello , Lars-Peter Clausen , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dlechner@baylibre.com, Mark Brown , Angelo Dureghello Date: Tue, 29 Oct 2024 09:13:42 +0100 In-Reply-To: <20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-4-f6960b4f9719@kernel-space.org> References: <20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-0-f6960b4f9719@kernel-space.org> <20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-4-f6960b4f9719@kernel-space.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2024-10-28 at 22:45 +0100, Angelo Dureghello wrote: > From: Angelo Dureghello >=20 > Extend AXI-DAC backend with new features required to interface > to the ad3552r DAC. Mainly, a new compatible string is added to > support the ad3552r-axi DAC IP, very similar to the generic DAC > IP but with some customizations to work with the ad3552r. >=20 > Then, a series of generic functions has been added to match with > ad3552r needs. Function names has been kept generic as much as > possible, to allow re-utilization from other frontend drivers. >=20 > Signed-off-by: Angelo Dureghello > --- Hi Angelo, Small stuff that Jonathan might be able to change while applying... With th= at: Reviewed-by: Nuno Sa > =C2=A0drivers/iio/dac/adi-axi-dac.c | 256 +++++++++++++++++++++++++++++++= ++++++++-- > - > =C2=A01 file changed, 242 insertions(+), 14 deletions(-) >=20 > diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.= c > index 04193a98616e..155d04ca2315 100644 > --- a/drivers/iio/dac/adi-axi-dac.c > +++ b/drivers/iio/dac/adi-axi-dac.c > @@ -46,9 +46,28 @@ > =C2=A0#define AXI_DAC_CNTRL_1_REG 0x0044 > =C2=A0#define=C2=A0=C2=A0 AXI_DAC_CNTRL_1_SYNC BIT(0) > =C2=A0#define AXI_DAC_CNTRL_2_REG 0x0048 > +#define=C2=A0=C2=A0 AXI_DAC_CNTRL_2_SDR_DDR_N BIT(16) > +#define=C2=A0=C2=A0 AXI_DAC_CNTRL_2_SYMB_8B BIT(14) > =C2=A0#define=C2=A0=C2=A0 ADI_DAC_CNTRL_2_R1_MODE BIT(5) > +#define=C2=A0=C2=A0 AXI_DAC_CNTRL_2_UNSIGNED_DATA BIT(4) > +#define AXI_DAC_STATUS_1_REG 0x0054 > +#define AXI_DAC_STATUS_2_REG 0x0058 > =C2=A0#define AXI_DAC_DRP_STATUS_REG 0x0074 > =C2=A0#define=C2=A0=C2=A0 AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17) > +#define AXI_DAC_CUSTOM_RD_REG 0x0080 > +#define AXI_DAC_CUSTOM_WR_REG 0x0084 > +#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_WR_DATA_8 GENMASK(23, 16) > +#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_WR_DATA_16 GENMASK(23, 8) > +#define AXI_DAC_UI_STATUS_REG 0x0088 > +#define=C2=A0=C2=A0 AXI_DAC_UI_STATUS_IF_BUSY BIT(4) > +#define AXI_DAC_CUSTOM_CTRL_REG 0x008C > +#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_CTRL_ADDRESS GENMASK(31, 24) > +#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_CTRL_SYNCED_TRANSFER BIT(2) > +#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_CTRL_STREAM BIT(1) > +#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA BIT(0) > + > +#define > AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE (AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA | \ > + AXI_DAC_CUSTOM_CTRL_STREAM) > =C2=A0 > =C2=A0/* DAC Channel controls */ > =C2=A0#define AXI_DAC_CHAN_CNTRL_1_REG(c) (0x0400 + (c) * 0x40) > @@ -63,12 +82,21 @@ > =C2=A0#define AXI_DAC_CHAN_CNTRL_7_REG(c) (0x0418 + (c) * 0x40) > =C2=A0#define=C2=A0=C2=A0 AXI_DAC_CHAN_CNTRL_7_DATA_SEL GENMASK(3, 0) > =C2=A0 > +#define AXI_DAC_RD_ADDR(x) (BIT(7) | (x)) > + > =C2=A0/* 360 degrees in rad */ > =C2=A0#define AXI_DAC_2_PI_MEGA 6283190 > =C2=A0 > =C2=A0enum { > =C2=A0 AXI_DAC_DATA_INTERNAL_TONE, > =C2=A0 AXI_DAC_DATA_DMA =3D 2, > + AXI_DAC_DATA_INTERNAL_RAMP_16BIT =3D 11, > +}; > + > +struct axi_dac_info { > + unsigned int version; > + const struct iio_backend_info *backend_info; > + bool has_dac_clk; > =C2=A0}; > =C2=A0 > =C2=A0struct axi_dac_state { > @@ -79,9 +107,11 @@ struct axi_dac_state { > =C2=A0 * data/variables. > =C2=A0 */ > =C2=A0 struct mutex lock; > + const struct axi_dac_info *info; > =C2=A0 u64 dac_clk; > =C2=A0 u32 reg_config; > =C2=A0 bool int_tone; > + int dac_clk_rate; > =C2=A0}; > =C2=A0 > =C2=A0static int axi_dac_enable(struct iio_backend *back) > @@ -471,6 +501,11 @@ static int axi_dac_data_source_set(struct iio_backen= d > *back, unsigned int chan, > =C2=A0 =C2=A0 AXI_DAC_CHAN_CNTRL_7_REG(chan), > =C2=A0 =C2=A0 AXI_DAC_CHAN_CNTRL_7_DATA_SEL, > =C2=A0 =C2=A0 AXI_DAC_DATA_DMA); > + case IIO_BACKEND_INTERNAL_RAMP_16BIT: > + return regmap_update_bits(st->regmap, > + =C2=A0 AXI_DAC_CHAN_CNTRL_7_REG(chan), > + =C2=A0 AXI_DAC_CHAN_CNTRL_7_DATA_SEL, > + =C2=A0 AXI_DAC_DATA_INTERNAL_RAMP_16BIT); > =C2=A0 default: > =C2=A0 return -EINVAL; > =C2=A0 } > @@ -528,6 +563,154 @@ static int axi_dac_reg_access(struct iio_backend *b= ack, > unsigned int reg, > =C2=A0 return regmap_write(st->regmap, reg, writeval); > =C2=A0} > =C2=A0 > +static int axi_dac_ddr_enable(struct iio_backend *back) > +{ > + struct axi_dac_state *st =3D iio_backend_get_priv(back); > + > + return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, > + AXI_DAC_CNTRL_2_SDR_DDR_N); > +} > + > +static int axi_dac_ddr_disable(struct iio_backend *back) > +{ > + struct axi_dac_state *st =3D iio_backend_get_priv(back); > + > + return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 AXI_DAC_CNTRL_2_SDR_DDR_N); > +} > + > +static int axi_dac_data_stream_enable(struct iio_backend *back) > +{ > + struct axi_dac_state *st =3D iio_backend_get_priv(back); > + > + return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 AXI_DAC_CUSTOM_CTRL_STREAM_ENABL= E); > +} > + > +static int axi_dac_data_stream_disable(struct iio_backend *back) > +{ > + struct axi_dac_state *st =3D iio_backend_get_priv(back); > + > + return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, > + AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE); > +} > + > +static int axi_dac_data_transfer_addr(struct iio_backend *back, u32 addr= ess) > +{ > + struct axi_dac_state *st =3D iio_backend_get_priv(back); > + > + if (address > FIELD_MAX(AXI_DAC_CUSTOM_CTRL_ADDRESS)) > + return -EINVAL; > + > + /* > + * Sample register address, when the DAC is configured, or stream > + * start address when the FSM is in stream state. > + */ > + return regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, > + =C2=A0 AXI_DAC_CUSTOM_CTRL_ADDRESS, > + =C2=A0 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS, > + =C2=A0 address)); > +} > + > +static int axi_dac_data_format_set(struct iio_backend *back, unsigned in= t ch, > + =C2=A0=C2=A0 const struct iio_backend_data_fmt *data) > +{ > + struct axi_dac_state *st =3D iio_backend_get_priv(back); > + > + switch (data->type) { > + case IIO_BACKEND_DATA_UNSIGNED: > + return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, > + AXI_DAC_CNTRL_2_UNSIGNED_DATA); > + default: > + return -EINVAL; > + } > +} > + > +static int axi_dac_bus_reg_write_locked(struct iio_backend *back, u32 re= g, > + u32 val, size_t data_size) nit: this is actually unlocked and needs to be locked from the outside. So, unlocked could be a better suffix. But more importantly is the extra call t= o iio_backend_get_priv(). We can just pass *st directly from the outer functi= on. > +{ > + struct axi_dac_state *st =3D iio_backend_get_priv(back); > + int ret; > + u32 ival; > + > + /* > + * Both AXI_DAC_CNTRL_2_REG and AXI_DAC_CUSTOM_WR_REG need to know > + * the data size. So keeping data size control here only, > + * since data size is mandatory for the current transfer. > + * DDR state handled separately by specific backend calls, > + * generally all raw register writes are SDR. > + */ > + if (data_size =3D=3D sizeof(u16)) > + ival =3D FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_16, val); > + else > + ival =3D FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_8, val); > + > + ret =3D regmap_write(st->regmap, AXI_DAC_CUSTOM_WR_REG, ival); > + if (ret) > + return ret; > + > + if (data_size =3D=3D sizeof(u8)) > + ret =3D regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 AXI_DAC_CNTRL_2_SYMB_8B); > + else > + ret =3D regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, > + AXI_DAC_CNTRL_2_SYMB_8B); > + if (ret) > + return ret; > + > + ret =3D regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, > + AXI_DAC_CUSTOM_CTRL_ADDRESS, > + FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS, > reg)); > + if (ret) > + return ret; > + > + ret =3D regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, > + AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA, > + AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA); > + if (ret) > + return ret; > + > + ret =3D regmap_read_poll_timeout(st->regmap, > + AXI_DAC_UI_STATUS_REG, ival, > + FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) =3D=3D > 0, > + 10, 100 * KILO); > + if (ret =3D=3D -ETIMEDOUT) > + dev_err(st->dev, "AXI read timeout\n"); > + > + /* Cleaning always AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA */ > + return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, > + AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA); > +} > + > +static int axi_dac_bus_reg_write(struct iio_backend *back, u32 reg, > + u32 val, size_t data_size) > +{ > + struct axi_dac_state *st =3D iio_backend_get_priv(back); > + > + guard(mutex)(&st->lock); > + return axi_dac_bus_reg_write_locked(back, reg, val, data_size); > +} > + Also just realized that the above read()/write() functions could make more = sense in the patch making the device a "bus controller". But well, not that impor= tant I guess. - Nuno S=C3=A1