From: Stephen Warren <swarren@wwwdotorg.org>
To: Fabian Vogt <fabian@ritter-vogt.de>
Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, devicetree@vger.kernel.org,
linus.walleij@linaro.org, grant.likely@linaro.org,
pawel.moll@arm.com
Subject: Re: [PATCH V3] gpio: New driver for LSI ZEVIO SoCs
Date: Fri, 23 Aug 2013 13:43:47 -0600 [thread overview]
Message-ID: <5217BB73.8050907@wwwdotorg.org> (raw)
In-Reply-To: <1375879989-18606-1-git-send-email-fabian@ritter-vogt.de>
On 08/07/2013 06:53 AM, Fabian Vogt wrote:
> This driver supports the GPIO controller found in LSI ZEVIO SoCs.
> It has been successfully tested on a TI nspire CX calculator.
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
> +Zevio GPIO controller
> +
> +Required properties:
> +- compatible = "lsi,zevio-gpio"
Is there only one zevio chip, or a series? Is "zevio" the full name of
the chip, including any version number?
> +- reg = <BASEADDR SIZE>
> +- #gpio-cells = <2>
> +- gpio-controller;
> +
> +Optional:
> +- #ngpios = <32>: Number of GPIOs. Defaults to 32 if absent
Perhaps one can derive that from the compatible value? The fact this
property exists implies there's more than one zevio chip, so perhaps
each should have an explicit compatible value described above?
Is the GPIO block not also an interrupt source/controller? I see the
following in the patch, and references to some IRQ registers...
> + select GENERIC_IRQ_CHIP
next prev parent reply other threads:[~2013-08-23 19:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-07 12:53 [PATCH V3] gpio: New driver for LSI ZEVIO SoCs Fabian Vogt
2013-08-23 19:43 ` Stephen Warren [this message]
2013-08-25 19:44 ` Fabian Vogt
2013-08-26 16:57 ` Stephen Warren
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