* RE: [PATCH v4 3/5] net: ethernet: cpsw: introduce ti,am3352-cpsw compatible string
[not found] ` <52179AA5.3060408@ti.com>
@ 2013-08-26 5:22 ` Gupta, Pekon
0 siblings, 0 replies; 3+ messages in thread
From: Gupta, Pekon @ 2013-08-26 5:22 UTC (permalink / raw)
To: N, Mugunthan V, Shilimkar, Santosh, bcousson@baylibre.com,
Daniel Mack, Nori, Sekhar
Cc: devicetree@vger.kernel.org, sergei.shtylyov@cogentembedded.com,
Gerlach, Dave, netdev@vger.kernel.org, Bedia, Vaibhav,
ujhelyi.m@gmail.com, linux-omap@vger.kernel.org,
davem@davemloft.net, linux-arm-kernel@lists.infradead.org
>
> On Friday 23 August 2013 10:26 PM, Santosh Shilimkar wrote:
> > On Friday 23 August 2013 12:30 PM, Daniel Mack wrote:
> >> On 23.08.2013 16:23, Santosh Shilimkar wrote:
> >>> On Friday 23 August 2013 10:16 AM, Daniel Mack wrote:
> >>>> +static const struct of_device_id cpsw_of_mtable[] = {
> >>>> + {
> >>>> + .compatible = "ti,am3352-cpsw",
> >>> I didn't notice this earlier, but can't you use the IP version
> >>> as a compatible instead of using a SOC name. Whats really SOC specific
> >>> on this IP ? Sorry i have missed any earlier discussion on this but
> >>> this approach doesn't seem good. Its like adding SOC checks in the
> >>> driver subsystem.
> >> As I already mentioned in the cover letter and in the commit message, I
> >> just don't know which criteria makes most sense here.
> >>
> >> On a general note, I would say that chances that this exactly IP core
> >> with the same version number will appear on some other silicon which
> >> doesn't support the control mode register in an AM33xx fashion, is not
> >> necessarily negligible.
> >>
> >> So what that new compatible string denotes is the cpsw in a version as
> >> found on am3352 SoCs, which is actually exactly what it does.
> >>
> >> I don't have a strong opinion here, but see your point. I just don't
> >> have a better idea on how to treat that.
> >>
> > So just stick the IP version or call it cpsw-v1... cpsw-v2 etc.
> > That way if in future if someone uses those features, they can use
> > this compatible if they don't they use the one which suites that
> > SOC.
> >
> We cannot map control module register with CPSW IP version as both comes
> from different design team and CPSW ip version can be same across SoC
> and gmii sel register definition can be different. Control module
> defines may vary in different SoC as per SoC requirements.
>
> Adding Pekon Gupta who had worked in Silicon team before.
>
[Pekon]: My opinion here..
Uniformity in control module cannot be guaranteed, neither in register
offsets nor their functionality. Uniformity is usually maintained till the
point same person is writing the spec, or it’s a derivative device.
Control-module should not be categorized as IP, instead it’s a group of
miscellaneous logic usually consisting of following:
(a) SoC bug-fixes across silicon revisions.
(b) SoC specific logic like device_type, JTAG-ID.
(c) IP bug fixes which could not be accommodated in IP address-map.
(d) IP logic which depends on SoC configurations.
Due to this un-deterministic composition of control-module, having
a dedicated driver for control module might not work either, as it
has to be updated | re-written for every new device.
So, Following can be used as guideline to determine compatibility
string for DT bindings..
- If binding maps to (a) and (c), .i.e., bug-fixes for SoC or IP,
then its most likely that these would change either in next silicon
revision or in next devices. Hence such bindings should use *not*
use IP compatibility strings, they _may_ use SoC-name based
compatibility string.
- Else if binding maps to (b),.i.e., SoC specific configurations.
then their offsets and functionality should remain same across the
family of devices at-least, so it should use SoC-name based
compatibility string.
- And if binding maps to (d), .i.e., IP feature but depending on SoC
Then it can use IP based compatibility string, along with IP version.
(same approach can be used for CPSW binding used here,
with regards, pekon
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4 3/5] net: ethernet: cpsw: introduce ti,am3352-cpsw compatible string
[not found] ` <5217BDFA.5040904@ti.com>
@ 2013-08-26 5:59 ` Mugunthan V N
2013-08-26 6:45 ` Sekhar Nori
0 siblings, 1 reply; 3+ messages in thread
From: Mugunthan V N @ 2013-08-26 5:59 UTC (permalink / raw)
To: Santosh Shilimkar
Cc: devicetree, sergei.shtylyov, d-gerlach, netdev, Sekhar Nori,
vaibhav.bedia, Daniel Mack, bcousson, ujhelyi.m, linux-omap,
davem, linux-arm-kernel
On Saturday 24 August 2013 01:24 AM, Santosh Shilimkar wrote:
> On Friday 23 August 2013 02:29 PM, Mugunthan V N wrote:
>> On Friday 23 August 2013 11:40 PM, Santosh Shilimkar wrote:
>>> On Friday 23 August 2013 01:39 PM, Sekhar Nori wrote:
>>>> On 8/23/2013 10:58 PM, Santosh Shilimkar wrote:
>>>>> On Friday 23 August 2013 01:24 PM, Daniel Mack wrote:
>>>>>> On 23.08.2013 19:19, Santosh Shilimkar wrote:
>>>>>>> On Friday 23 August 2013 01:09 PM, Sekhar Nori wrote:
>>>>>>>> On 8/23/2013 10:26 PM, Santosh Shilimkar wrote:
>>>>>>>>> So just stick the IP version or call it cpsw-v1... cpsw-v2 etc.
>>>>>>>> If this could be handled using IP version then the right way would be to
>>>>>>>> just read the IP version from hardware and use it. No need of DT property.
>>>>>>>>
>>>>>>> Thats fine as well but I thought the patch needed additional properties like
>>>>>>> CM reg-address come from DT and hence the separate compatible. If you can
>>>>>>> manage without that, thats even better.
>>>>>> We can't, that's the whole point :)
>>>>>>
>>>>> I saw that from the patch :)
>>>>>
>>>>>> Well, theoretically, we could for now, but that's not a clean solution.
>>>>>> Again: the problem here is that the control port is separated from the
>>>>>> cpsw core, and so we have to implement something specific for the AM3352
>>>>>> SoC. I know that's a violation of clean and generic driver ideas, but
>>>>>> there's no way we can assume that every cpsw v2 ip block has a control
>>>>>> port that is compatible to the one found on am335x chips.
>>>>>>
>>>>> But there is a possibility that other SOC will just use the same
>>>>> control module approach. So using a revision IP is just fine. BTW,
>>>> But this is misleading because it makes appear like the same compatible
>>>> can be used on on another SoC like DRA7 which probably has the same
>>>> version of IP but a different control module implementation, when in
>>>> practice it cannot.
>>>>
>>>> The fact is we are doing something SoC specific in the driver and we
>>>> cannot hide that behind IP versions. If really in practice there comes
>>>> another SoC with the same control module definition then it can always
>>>> use ti,am3352-cpsw compatible as well. The compatible name does not
>>>> preclude its usage.
>>>>
>>> My point was the CPSW needs a feature which is implemented using
>>> control module rather than within the IP itself. Its an implementation
>>> detail. As such the additional feature makes sense for that IP. O.w
>>> there was no need to do any monkeying with control module.
>>>
>>> E.g
>>> MMC card detect is a basic functionality, implemented by various types
>>> like control module, PMIC or MMC IP itself. As such the driver need
>>> that support and all the implementation details needs to still handled
>>> to make that part work.
>>>
>>>
>> CPSW core as such understands only GMII/MII signals, there is an
>> additional module which converts GMII/MII signals to RGMII/RMII signals
>> respectively which is called as CPRGMII/CPRMII as specified in the
>> AM335x TRM in Figure 14-1. Ethernet Switch Integration.
>>
>> So to control this sub-module, the control register is used and this has
>> to be configured according to the EVM design like what mode of phy is
>> connected. CPRGMII and CPRMII is no way related to CPSW core.
>>
> Ok then why are you polluting cpsw driver with that code which
> not realted to CPSW as you said above. You are contradicting what
> you said by supporting the SOC usage in the core CPSW driver.
This patch series is not from me and because of the reason I mentioned
about control module driver, so that cpsw driver can make use control
module apis to select phy mode and control module driver takes care of
SoC specific register offsets and definitions, but now it is not
possible as it is not acceptable in mainline. So other way is to keep
these in driver itself as it is done in this patch series with SoC
compatibilities.
Regards
Mugunthan V N
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4 3/5] net: ethernet: cpsw: introduce ti,am3352-cpsw compatible string
2013-08-26 5:59 ` Mugunthan V N
@ 2013-08-26 6:45 ` Sekhar Nori
0 siblings, 0 replies; 3+ messages in thread
From: Sekhar Nori @ 2013-08-26 6:45 UTC (permalink / raw)
To: Mugunthan V N
Cc: Santosh Shilimkar, Daniel Mack, netdev, bcousson, sergei.shtylyov,
davem, ujhelyi.m, vaibhav.bedia, d-gerlach, linux-arm-kernel,
linux-omap, devicetree, Grant Likely, Rob Herring
On Monday 26 August 2013 11:29 AM, Mugunthan V N wrote:
> On Saturday 24 August 2013 01:24 AM, Santosh Shilimkar wrote:
>> On Friday 23 August 2013 02:29 PM, Mugunthan V N wrote:
>>> On Friday 23 August 2013 11:40 PM, Santosh Shilimkar wrote:
>>>> On Friday 23 August 2013 01:39 PM, Sekhar Nori wrote:
>>>>> On 8/23/2013 10:58 PM, Santosh Shilimkar wrote:
>>>>>> On Friday 23 August 2013 01:24 PM, Daniel Mack wrote:
>>>>>>> On 23.08.2013 19:19, Santosh Shilimkar wrote:
>>>>>>>> On Friday 23 August 2013 01:09 PM, Sekhar Nori wrote:
>>>>>>>>> On 8/23/2013 10:26 PM, Santosh Shilimkar wrote:
>>>>>>>>>> So just stick the IP version or call it cpsw-v1... cpsw-v2 etc.
>>>>>>>>> If this could be handled using IP version then the right way would be to
>>>>>>>>> just read the IP version from hardware and use it. No need of DT property.
>>>>>>>>>
>>>>>>>> Thats fine as well but I thought the patch needed additional properties like
>>>>>>>> CM reg-address come from DT and hence the separate compatible. If you can
>>>>>>>> manage without that, thats even better.
>>>>>>> We can't, that's the whole point :)
>>>>>>>
>>>>>> I saw that from the patch :)
>>>>>>
>>>>>>> Well, theoretically, we could for now, but that's not a clean solution.
>>>>>>> Again: the problem here is that the control port is separated from the
>>>>>>> cpsw core, and so we have to implement something specific for the AM3352
>>>>>>> SoC. I know that's a violation of clean and generic driver ideas, but
>>>>>>> there's no way we can assume that every cpsw v2 ip block has a control
>>>>>>> port that is compatible to the one found on am335x chips.
>>>>>>>
>>>>>> But there is a possibility that other SOC will just use the same
>>>>>> control module approach. So using a revision IP is just fine. BTW,
>>>>> But this is misleading because it makes appear like the same compatible
>>>>> can be used on on another SoC like DRA7 which probably has the same
>>>>> version of IP but a different control module implementation, when in
>>>>> practice it cannot.
>>>>>
>>>>> The fact is we are doing something SoC specific in the driver and we
>>>>> cannot hide that behind IP versions. If really in practice there comes
>>>>> another SoC with the same control module definition then it can always
>>>>> use ti,am3352-cpsw compatible as well. The compatible name does not
>>>>> preclude its usage.
>>>>>
>>>> My point was the CPSW needs a feature which is implemented using
>>>> control module rather than within the IP itself. Its an implementation
>>>> detail. As such the additional feature makes sense for that IP. O.w
>>>> there was no need to do any monkeying with control module.
>>>>
>>>> E.g
>>>> MMC card detect is a basic functionality, implemented by various types
>>>> like control module, PMIC or MMC IP itself. As such the driver need
>>>> that support and all the implementation details needs to still handled
>>>> to make that part work.
>>>>
>>>>
>>> CPSW core as such understands only GMII/MII signals, there is an
>>> additional module which converts GMII/MII signals to RGMII/RMII signals
>>> respectively which is called as CPRGMII/CPRMII as specified in the
>>> AM335x TRM in Figure 14-1. Ethernet Switch Integration.
>>>
>>> So to control this sub-module, the control register is used and this has
>>> to be configured according to the EVM design like what mode of phy is
>>> connected. CPRGMII and CPRMII is no way related to CPSW core.
>>>
>> Ok then why are you polluting cpsw driver with that code which
>> not realted to CPSW as you said above. You are contradicting what
>> you said by supporting the SOC usage in the core CPSW driver.
> This patch series is not from me and because of the reason I mentioned
> about control module driver, so that cpsw driver can make use control
> module apis to select phy mode and control module driver takes care of
> SoC specific register offsets and definitions, but now it is not
> possible as it is not acceptable in mainline. So other way is to keep
> these in driver itself as it is done in this patch series with SoC
> compatibilities.
What is done in this patch is _not_ "SoC compatibilities". SoC
compatibility would be what was done in v1 of this patch ie, explicit
check for
of_machine_is_compatible("ti,am33xx")
"ti,am3352-cpsw" says "CPSW as implemented on AM3352". This is not the
same as checking if SoC is AM3352.
The example quoted on ePAPR spec for a compatible string is:
compatible = “fsl,mpc8641-uart”, “ns16550";
MPC8641 is freescale PowerPC based SoC[1]. This shows that it is not
unnatural to use SoC names in compatibles for IPs. That, or the ePAPR
specification needs to be updated to show the right example of how a
compatible could be defined. Until then I see no reason of changing what
is implemented in this patch.
In short, even if there was no control module handling in the driver,
using "ti,am3352-cpsw" would be just fine.
I have also CCed the DT maintainers for their opinion. They should have
been explicitly CCed anyway.
Thanks,
Sekhar
[1] http://www.freescale.com/files/32bit/doc/data_sheet/MPC8641DEC.pdf
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