* [PATCH v9 0/3] DMA: Freescale: Add support for 8-channel DMA engine
@ 2013-08-30 11:26 hongbo.zhang
2013-08-30 11:26 ` [PATCH v9 1/3] DMA: Freescale: revise device tree binding document hongbo.zhang
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: hongbo.zhang @ 2013-08-30 11:26 UTC (permalink / raw)
To: rob.herring, pawel.moll, mark.rutland, swarren, ian.campbell,
vinod.koul, djbw
Cc: Hongbo Zhang, devicetree, linuxppc-dev, linux-kernel
From: Hongbo Zhang <hongbo.zhang@freescale.com>
Hi DMA and DT maintainers, please have a look at these V9 patches.
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch set
adds support this DMA engine.
V8->V9 changes:
- add "Acked-by: Mark Rutland <mark.rutland@arm.com>" into patch [1/3]
- update reg entry <0x100300 0x4 0x100600 0x4> to two seperate ones
<0x100300 0x4>, <0x100600 0x4> in patch [2/3]
- and also use "QorIQ Elo3 DMA" to mention previous "QorIQ DMA" in [2/3]
V7->V8 changes:
- change the word "mapping" to "specifier" for reg and interrupts description
V6->V7 changes:
- only remove unnecessary "CHIP-dma" explanations in [1/3]
V5->V6 changes:
- minor updates of descriptions in binding document and Kconfig
- remove [4/4], that should be another patch in future
V4->V5 changes:
- update description in the dt binding document, to make it more resonable
- add new patch [4/4] to eliminate a compiling warning which already exists
for a long time
V3->V4 changes:
- introduce new patch [1/3] to revise the legacy dma binding document
- and then add new paragraph to describe new dt node binding in [2/3]
- rebase to latest kernel v3.11-rc1
V2->V3 changes:
- edit Documentation/devicetree/bindings/powerpc/fsl/dma.txt
- edit text string in Kconfig and the driver files, using "elo series" to
mention all the current "elo*"
V1->V2 changes:
- removed the codes handling the register dgsr1, since it isn't used currently
- renamed the DMA DT compatible to "fsl,elo3-dma"
- renamed the new dts files to "elo3-dma-<n>.dtsi"
Hongbo Zhang (3):
DMA: Freescale: revise device tree binding document
DMA: Freescale: Add new 8-channel DMA engine device tree nodes
DMA: Freescale: update driver to support 8-channel DMA engine
.../devicetree/bindings/powerpc/fsl/dma.txt | 129 ++++++++++++++------
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 4 +-
arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82 +++++++++++++
arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82 +++++++++++++
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 4 +-
drivers/dma/Kconfig | 9 +-
drivers/dma/fsldma.c | 9 +-
drivers/dma/fsldma.h | 2 +-
8 files changed, 274 insertions(+), 47 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi
--
1.7.9.5
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v9 1/3] DMA: Freescale: revise device tree binding document 2013-08-30 11:26 [PATCH v9 0/3] DMA: Freescale: Add support for 8-channel DMA engine hongbo.zhang @ 2013-08-30 11:26 ` hongbo.zhang 2013-08-30 11:26 ` [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes hongbo.zhang 2013-08-30 11:26 ` [PATCH v9 3/3] DMA: Freescale: update driver to support 8-channel DMA engine hongbo.zhang 2 siblings, 0 replies; 10+ messages in thread From: hongbo.zhang @ 2013-08-30 11:26 UTC (permalink / raw) To: rob.herring, pawel.moll, mark.rutland, swarren, ian.campbell, vinod.koul, djbw Cc: Hongbo Zhang, devicetree, linuxppc-dev, linux-kernel From: Hongbo Zhang <hongbo.zhang@freescale.com> This patch updates the discription of each type of DMA controller and its channels, it is preparation for adding another new DMA controller binding, it also fixes some defects of indent for text alignment at the same time. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Acked-by: Mark Rutland <mark.rutland@arm.com> --- .../devicetree/bindings/powerpc/fsl/dma.txt | 62 +++++++++----------- 1 file changed, 27 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt index 2a4b4bc..ddf17af 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt @@ -1,33 +1,29 @@ -* Freescale 83xx DMA Controller +* Freescale DMA Controllers -Freescale PowerPC 83xx have on chip general purpose DMA controllers. +** Freescale Elo DMA Controller + This is a little-endian DMA controller, used in Freescale mpc83xx series + chips such as mpc8315, mpc8349, mpc8379 etc. Required properties: -- compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-dma", where CHIP is the processor - (mpc8349, mpc8360, etc.) and the second is - "fsl,elo-dma" -- reg : <registers mapping for DMA general status reg> -- ranges : Should be defined as specified in 1) to describe the - DMA controller channels. +- compatible : must include "fsl,elo-dma" +- reg : <registers specifier for DMA general status reg> +- ranges : describes the mapping between the address space of the + DMA channels and the address space of the DMA controller - cell-index : controller index. 0 for controller @ 0x8100 -- interrupts : <interrupt mapping for DMA IRQ> +- interrupts : <interrupt specifier for DMA IRQ> - interrupt-parent : optional, if needed for interrupt mapping - - DMA channel nodes: - - compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-dma-channel", where CHIP is the processor - (mpc8349, mpc8350, etc.) and the second is - "fsl,elo-dma-channel". However, see note below. - - reg : <registers mapping for channel> + - compatible : must include "fsl,elo-dma-channel" + However, see note below. + - reg : <registers specifier for channel> - cell-index : dma channel index starts at 0. Optional properties: - - interrupts : <interrupt mapping for DMA channel IRQ> - (on 83xx this is expected to be identical to - the interrupts property of the parent node) + - interrupts : <interrupt specifier for DMA channel IRQ> + (on 83xx this is expected to be identical to + the interrupts property of the parent node) - interrupt-parent : optional, if needed for interrupt mapping Example: @@ -70,30 +66,26 @@ Example: }; }; -* Freescale 85xx/86xx DMA Controller - -Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers. +** Freescale EloPlus DMA Controller + This is DMA controller with extended addresses and chaining, mainly used in + Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as mpc8540, mpc8641 + p4080, bsc9131 etc. Required properties: -- compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-dma", where CHIP is the processor - (mpc8540, mpc8540, etc.) and the second is - "fsl,eloplus-dma" -- reg : <registers mapping for DMA general status reg> +- compatible : must include "fsl,eloplus-dma" +- reg : <registers specifier for DMA general status reg> - cell-index : controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000 -- ranges : Should be defined as specified in 1) to describe the - DMA controller channels. +- ranges : describes the mapping between the address space of the + DMA channels and the address space of the DMA controller - DMA channel nodes: - - compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-dma-channel", where CHIP is the processor - (mpc8540, mpc8560, etc.) and the second is - "fsl,eloplus-dma-channel". However, see note below. + - compatible : must include "fsl,eloplus-dma-channel" + However, see note below. - cell-index : dma channel index starts at 0. - - reg : <registers mapping for channel> - - interrupts : <interrupt mapping for DMA channel IRQ> + - reg : <registers specifier for channel> + - interrupts : <interrupt specifier for DMA channel IRQ> - interrupt-parent : optional, if needed for interrupt mapping Example: -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes 2013-08-30 11:26 [PATCH v9 0/3] DMA: Freescale: Add support for 8-channel DMA engine hongbo.zhang 2013-08-30 11:26 ` [PATCH v9 1/3] DMA: Freescale: revise device tree binding document hongbo.zhang @ 2013-08-30 11:26 ` hongbo.zhang 2013-09-02 15:58 ` Mark Rutland 2013-08-30 11:26 ` [PATCH v9 3/3] DMA: Freescale: update driver to support 8-channel DMA engine hongbo.zhang 2 siblings, 1 reply; 10+ messages in thread From: hongbo.zhang @ 2013-08-30 11:26 UTC (permalink / raw) To: rob.herring, pawel.moll, mark.rutland, swarren, ian.campbell, vinod.koul, djbw Cc: Hongbo Zhang, devicetree, linuxppc-dev, linux-kernel From: Hongbo Zhang <hongbo.zhang@freescale.com> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds the device tree nodes for them. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> --- .../devicetree/bindings/powerpc/fsl/dma.txt | 67 ++++++++++++++++ arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 4 +- arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82 ++++++++++++++++++++ arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82 ++++++++++++++++++++ arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 4 +- 5 files changed, 235 insertions(+), 4 deletions(-) create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt index ddf17af..332ac77 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt @@ -126,6 +126,73 @@ Example: }; }; +** Freescale Elo3 DMA Controller + This is EloPlus controller with 8 channels, used in Freescale Txxx and Bxxx + series chips, such as t1040, t4240, b4860. + +Required properties: + +- compatible : must include "fsl,elo3-dma" +- reg : <registers specifier for DMA general status reg> +- ranges : describes the mapping between the address space of the + DMA channels and the address space of the DMA controller + +- DMA channel nodes: + - compatible : must include "fsl,eloplus-dma-channel" + - reg : <registers specifier for channel> + - interrupts : <interrupt specifier for DMA channel IRQ> + - interrupt-parent : optional, if needed for interrupt mapping + +Example: +dma@100300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,elo3-dma"; + reg = <0x100300 0x4>, + <0x100600 0x4>; + ranges = <0x0 0x100100 0x500>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + interrupts = <28 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + interrupts = <29 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + interrupts = <30 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + interrupts = <31 2 0 0>; + }; + dma-channel@300 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x300 0x80>; + interrupts = <76 2 0 0>; + }; + dma-channel@380 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x380 0x80>; + interrupts = <77 2 0 0>; + }; + dma-channel@400 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x400 0x80>; + interrupts = <78 2 0 0>; + }; + dma-channel@480 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x480 0x80>; + interrupts = <79 2 0 0>; + }; +}; + Note on DMA channel compatible properties: The compatible property must say "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA driver (fsldma). Any DMA channel used by fsldma cannot be used by another diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi index 7399154..ea53ea1 100644 --- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi @@ -223,13 +223,13 @@ reg = <0xe2000 0x1000>; }; -/include/ "qoriq-dma-0.dtsi" +/include/ "elo3-dma-0.dtsi" dma@100300 { fsl,iommu-parent = <&pamu0>; fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ }; -/include/ "qoriq-dma-1.dtsi" +/include/ "elo3-dma-1.dtsi" dma@101300 { fsl,iommu-parent = <&pamu0>; fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi new file mode 100644 index 0000000..3c210e0 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi @@ -0,0 +1,82 @@ +/* + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ] + * + * Copyright 2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +dma0: dma@100300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,elo3-dma"; + reg = <0x100300 0x4>, + <0x100600 0x4>; + ranges = <0x0 0x100100 0x500>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + interrupts = <28 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + interrupts = <29 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + interrupts = <30 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + interrupts = <31 2 0 0>; + }; + dma-channel@300 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x300 0x80>; + interrupts = <76 2 0 0>; + }; + dma-channel@380 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x380 0x80>; + interrupts = <77 2 0 0>; + }; + dma-channel@400 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x400 0x80>; + interrupts = <78 2 0 0>; + }; + dma-channel@480 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x480 0x80>; + interrupts = <79 2 0 0>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi b/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi new file mode 100644 index 0000000..cccf3bb --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi @@ -0,0 +1,82 @@ +/* + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ] + * + * Copyright 2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +dma1: dma@101300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,elo3-dma"; + reg = <0x101300 0x4>, + <0x101600 0x4>; + ranges = <0x0 0x101100 0x500>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + interrupts = <32 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + interrupts = <33 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + interrupts = <34 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + interrupts = <35 2 0 0>; + }; + dma-channel@300 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x300 0x80>; + interrupts = <80 2 0 0>; + }; + dma-channel@380 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x380 0x80>; + interrupts = <81 2 0 0>; + }; + dma-channel@400 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x400 0x80>; + interrupts = <82 2 0 0>; + }; + dma-channel@480 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x480 0x80>; + interrupts = <83 2 0 0>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi index bd611a9..ec95c60 100644 --- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi @@ -387,8 +387,8 @@ reg = <0xea000 0x4000>; }; -/include/ "qoriq-dma-0.dtsi" -/include/ "qoriq-dma-1.dtsi" +/include/ "elo3-dma-0.dtsi" +/include/ "elo3-dma-1.dtsi" /include/ "qoriq-espi-0.dtsi" spi@110000 { -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes 2013-08-30 11:26 ` [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes hongbo.zhang @ 2013-09-02 15:58 ` Mark Rutland 2013-09-03 9:01 ` Hongbo Zhang 0 siblings, 1 reply; 10+ messages in thread From: Mark Rutland @ 2013-09-02 15:58 UTC (permalink / raw) To: hongbo.zhang@freescale.com Cc: rob.herring@calxeda.com, Pawel Moll, swarren@wwwdotorg.org, ian.campbell@citrix.com, vinod.koul@intel.com, djbw@fb.com, devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Hi, On Fri, Aug 30, 2013 at 12:26:19PM +0100, hongbo.zhang@freescale.com wrote: > From: Hongbo Zhang <hongbo.zhang@freescale.com> > > Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds > the device tree nodes for them. > > Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> > --- > .../devicetree/bindings/powerpc/fsl/dma.txt | 67 ++++++++++++++++ > arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 4 +- > arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82 ++++++++++++++++++++ > arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82 ++++++++++++++++++++ > arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 4 +- > 5 files changed, 235 insertions(+), 4 deletions(-) > create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi > create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi > > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt > index ddf17af..332ac77 100644 > --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt > +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt > @@ -126,6 +126,73 @@ Example: > }; > }; > > +** Freescale Elo3 DMA Controller > + This is EloPlus controller with 8 channels, used in Freescale Txxx and Bxxx I was under the impression EloPlus was the previous revision. Should that say Elo3, or is Elo3 considered to be an EloPlus implementation? > + series chips, such as t1040, t4240, b4860. > + > +Required properties: > + > +- compatible : must include "fsl,elo3-dma" > +- reg : <registers specifier for DMA general status reg> The example has two reg entries. What both are should be specified. From what you described last time, it sounds like each is a status register for four channels. Presumably the first covers the channels at 0x0,0x80,0x100,0x180, and the second covers the channels at 0x300,0x380,0x400,0x480? If the registers have specific names in a datasheet, it would be worth mentioning them. If the specification of the DMA controller allows for more channels, it may be worth describing that case now. > +- ranges : describes the mapping between the address space of the > + DMA channels and the address space of the DMA controller This looks odd as a required property, and I'm slightly confused. Is this used to map the reg values of the DMA channels, or is it used when mapping the DMA address space (for which dma-ranges exists in ePAPR and other bindings). > + > +- DMA channel nodes: > + - compatible : must include "fsl,eloplus-dma-channel" > + - reg : <registers specifier for channel> What does this represent? What are valid values? In the example below it looks like these are offsets of control registers within the dma controller. If the reg property may have any value, how do they get mapped to bits in the status register(s)? May some channels be unusable for some reason, or will all eight channels be wired on any given Elo3 DMA? Cheers, Mark. > + - interrupts : <interrupt specifier for DMA channel IRQ> > + - interrupt-parent : optional, if needed for interrupt mapping > + > +Example: > +dma@100300 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "fsl,elo3-dma"; > + reg = <0x100300 0x4>, > + <0x100600 0x4>; > + ranges = <0x0 0x100100 0x500>; > + dma-channel@0 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x0 0x80>; > + interrupts = <28 2 0 0>; > + }; > + dma-channel@80 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x80 0x80>; > + interrupts = <29 2 0 0>; > + }; > + dma-channel@100 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x100 0x80>; > + interrupts = <30 2 0 0>; > + }; > + dma-channel@180 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x180 0x80>; > + interrupts = <31 2 0 0>; > + }; > + dma-channel@300 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x300 0x80>; > + interrupts = <76 2 0 0>; > + }; > + dma-channel@380 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x380 0x80>; > + interrupts = <77 2 0 0>; > + }; > + dma-channel@400 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x400 0x80>; > + interrupts = <78 2 0 0>; > + }; > + dma-channel@480 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x480 0x80>; > + interrupts = <79 2 0 0>; > + }; > +}; > + > Note on DMA channel compatible properties: The compatible property must say > "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA > driver (fsldma). Any DMA channel used by fsldma cannot be used by another > diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi > index 7399154..ea53ea1 100644 > --- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi > +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi > @@ -223,13 +223,13 @@ > reg = <0xe2000 0x1000>; > }; > > -/include/ "qoriq-dma-0.dtsi" > +/include/ "elo3-dma-0.dtsi" > dma@100300 { > fsl,iommu-parent = <&pamu0>; > fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ > }; > > -/include/ "qoriq-dma-1.dtsi" > +/include/ "elo3-dma-1.dtsi" > dma@101300 { > fsl,iommu-parent = <&pamu0>; > fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ > diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi > new file mode 100644 > index 0000000..3c210e0 > --- /dev/null > +++ b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi > @@ -0,0 +1,82 @@ > +/* > + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ] > + * > + * Copyright 2013 Freescale Semiconductor Inc. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions are met: > + * * Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * * Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * * Neither the name of Freescale Semiconductor nor the > + * names of its contributors may be used to endorse or promote products > + * derived from this software without specific prior written permission. > + * > + * > + * ALTERNATIVELY, this software may be distributed under the terms of the > + * GNU General Public License ("GPL") as published by the Free Software > + * Foundation, either version 2 of that License or (at your option) any > + * later version. > + * > + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY > + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED > + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE > + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY > + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES > + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; > + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND > + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS > + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + */ > + > +dma0: dma@100300 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "fsl,elo3-dma"; > + reg = <0x100300 0x4>, > + <0x100600 0x4>; > + ranges = <0x0 0x100100 0x500>; > + dma-channel@0 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x0 0x80>; > + interrupts = <28 2 0 0>; > + }; > + dma-channel@80 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x80 0x80>; > + interrupts = <29 2 0 0>; > + }; > + dma-channel@100 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x100 0x80>; > + interrupts = <30 2 0 0>; > + }; > + dma-channel@180 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x180 0x80>; > + interrupts = <31 2 0 0>; > + }; > + dma-channel@300 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x300 0x80>; > + interrupts = <76 2 0 0>; > + }; > + dma-channel@380 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x380 0x80>; > + interrupts = <77 2 0 0>; > + }; > + dma-channel@400 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x400 0x80>; > + interrupts = <78 2 0 0>; > + }; > + dma-channel@480 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x480 0x80>; > + interrupts = <79 2 0 0>; > + }; > +}; > diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi b/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi > new file mode 100644 > index 0000000..cccf3bb > --- /dev/null > +++ b/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi > @@ -0,0 +1,82 @@ > +/* > + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ] > + * > + * Copyright 2013 Freescale Semiconductor Inc. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions are met: > + * * Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * * Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * * Neither the name of Freescale Semiconductor nor the > + * names of its contributors may be used to endorse or promote products > + * derived from this software without specific prior written permission. > + * > + * > + * ALTERNATIVELY, this software may be distributed under the terms of the > + * GNU General Public License ("GPL") as published by the Free Software > + * Foundation, either version 2 of that License or (at your option) any > + * later version. > + * > + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY > + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED > + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE > + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY > + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES > + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; > + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND > + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS > + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + */ > + > +dma1: dma@101300 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "fsl,elo3-dma"; > + reg = <0x101300 0x4>, > + <0x101600 0x4>; > + ranges = <0x0 0x101100 0x500>; > + dma-channel@0 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x0 0x80>; > + interrupts = <32 2 0 0>; > + }; > + dma-channel@80 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x80 0x80>; > + interrupts = <33 2 0 0>; > + }; > + dma-channel@100 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x100 0x80>; > + interrupts = <34 2 0 0>; > + }; > + dma-channel@180 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x180 0x80>; > + interrupts = <35 2 0 0>; > + }; > + dma-channel@300 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x300 0x80>; > + interrupts = <80 2 0 0>; > + }; > + dma-channel@380 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x380 0x80>; > + interrupts = <81 2 0 0>; > + }; > + dma-channel@400 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x400 0x80>; > + interrupts = <82 2 0 0>; > + }; > + dma-channel@480 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x480 0x80>; > + interrupts = <83 2 0 0>; > + }; > +}; > diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi > index bd611a9..ec95c60 100644 > --- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi > +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi > @@ -387,8 +387,8 @@ > reg = <0xea000 0x4000>; > }; > > -/include/ "qoriq-dma-0.dtsi" > -/include/ "qoriq-dma-1.dtsi" > +/include/ "elo3-dma-0.dtsi" > +/include/ "elo3-dma-1.dtsi" > > /include/ "qoriq-espi-0.dtsi" > spi@110000 { > -- > 1.7.9.5 > > > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes 2013-09-02 15:58 ` Mark Rutland @ 2013-09-03 9:01 ` Hongbo Zhang 2013-09-10 6:00 ` Hongbo Zhang 2013-09-12 17:15 ` Mark Rutland 0 siblings, 2 replies; 10+ messages in thread From: Hongbo Zhang @ 2013-09-03 9:01 UTC (permalink / raw) To: Mark Rutland Cc: rob.herring@calxeda.com, Pawel Moll, swarren@wwwdotorg.org, ian.campbell@citrix.com, vinod.koul@intel.com, djbw@fb.com, devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org On 09/02/2013 11:58 PM, Mark Rutland wrote: > Hi, > > On Fri, Aug 30, 2013 at 12:26:19PM +0100, hongbo.zhang@freescale.com wrote: >> From: Hongbo Zhang <hongbo.zhang@freescale.com> >> >> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds >> the device tree nodes for them. >> >> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> >> --- >> .../devicetree/bindings/powerpc/fsl/dma.txt | 67 ++++++++++++++++ >> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 4 +- >> arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82 ++++++++++++++++++++ >> arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82 ++++++++++++++++++++ >> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 4 +- >> 5 files changed, 235 insertions(+), 4 deletions(-) >> create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi >> create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi >> >> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt >> index ddf17af..332ac77 100644 >> --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt >> +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt >> @@ -126,6 +126,73 @@ Example: >> }; >> }; >> >> +** Freescale Elo3 DMA Controller >> + This is EloPlus controller with 8 channels, used in Freescale Txxx and Bxxx > I was under the impression EloPlus was the previous revision. Should > that say Elo3, or is Elo3 considered to be an EloPlus implementation? In this patch 1/3 I revise the doc to make it clear we have Elo and EloPlus, and I'm adding another new Elo3. Yes the only difference between Elo3 and EloPlus is channel numbers(8 channels vs 4 channels), so we can call "Elo3 is an 8-channel EloPlus" >> + series chips, such as t1040, t4240, b4860. >> + >> +Required properties: >> + >> +- compatible : must include "fsl,elo3-dma" >> +- reg : <registers specifier for DMA general status reg> > The example has two reg entries. What both are should be specified. From > what you described last time, it sounds like each is a status register > for four channels. > > Presumably the first covers the channels at 0x0,0x80,0x100,0x180, and > the second covers the channels at 0x300,0x380,0x400,0x480? If the > registers have specific names in a datasheet, it would be worth > mentioning them. Yes, each is a status register for four channels, you got it -- this means my statement works. Is it necessary to specify all the register names? I can describe my two registers, but in other cases the reg entryies can cover tens even hundreds of registers, just a summary is OK I think. > If the specification of the DMA controller allows for more channels, it > may be worth describing that case now. This DMA controller doesn't allows for more channels. (Even if it does, it should be another new controller) >> +- ranges : describes the mapping between the address space of the >> + DMA channels and the address space of the DMA controller > This looks odd as a required property, and I'm slightly confused. Is > this used to map the reg values of the DMA channels, or is it used when > mapping the DMA address space (for which dma-ranges exists in ePAPR and > other bindings). It is used to map the reg values of DMA channels. >> + >> +- DMA channel nodes: >> + - compatible : must include "fsl,eloplus-dma-channel" >> + - reg : <registers specifier for channel> > What does this represent? What are valid values? > > In the example below it looks like these are offsets of control > registers within the dma controller. Yes, they are offsets of control registers within dma controller, but the contents in these registers are for dma channels. Physically we have dma controller registers and dma channel registers, they are in one continuous physical address space, we divide all these registers into two controller/channel parts, according to contents in these registers, common status registers for all channels are called dma controller registers, otherwise channel specific registers are called dma channel registers. > If the reg property may have any value, how do they get mapped to bits > in the status register(s)? In fact, each channel has its own status register(and also other registers), the dma controller status register is just aggregation of all channel status register. (that seems duplicated somehow, maybe this is due to hardware compatibility with legacy one, and the device tree just describes the physical hardware without lie) > May some channels be unusable for some reason, or will all eight > channels be wired on any given Elo3 DMA? Sorry, not get your point clearly, maybe you are clear now because of my previous explanations. > Cheers, > Mark. > >> + - interrupts : <interrupt specifier for DMA channel IRQ> >> + - interrupt-parent : optional, if needed for interrupt mapping >> + >> +Example: >> +dma@100300 { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + compatible = "fsl,elo3-dma"; >> + reg = <0x100300 0x4>, >> + <0x100600 0x4>; >> + ranges = <0x0 0x100100 0x500>; >> + dma-channel@0 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x0 0x80>; >> + interrupts = <28 2 0 0>; >> + }; >> + dma-channel@80 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x80 0x80>; >> + interrupts = <29 2 0 0>; >> + }; >> + dma-channel@100 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x100 0x80>; >> + interrupts = <30 2 0 0>; >> + }; >> + dma-channel@180 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x180 0x80>; >> + interrupts = <31 2 0 0>; >> + }; >> + dma-channel@300 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x300 0x80>; >> + interrupts = <76 2 0 0>; >> + }; >> + dma-channel@380 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x380 0x80>; >> + interrupts = <77 2 0 0>; >> + }; >> + dma-channel@400 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x400 0x80>; >> + interrupts = <78 2 0 0>; >> + }; >> + dma-channel@480 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x480 0x80>; >> + interrupts = <79 2 0 0>; >> + }; >> +}; >> + >> Note on DMA channel compatible properties: The compatible property must say >> "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA >> driver (fsldma). Any DMA channel used by fsldma cannot be used by another >> diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi >> index 7399154..ea53ea1 100644 >> --- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi >> +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi >> @@ -223,13 +223,13 @@ >> reg = <0xe2000 0x1000>; >> }; >> >> -/include/ "qoriq-dma-0.dtsi" >> +/include/ "elo3-dma-0.dtsi" >> dma@100300 { >> fsl,iommu-parent = <&pamu0>; >> fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ >> }; >> >> -/include/ "qoriq-dma-1.dtsi" >> +/include/ "elo3-dma-1.dtsi" >> dma@101300 { >> fsl,iommu-parent = <&pamu0>; >> fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ >> diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi >> new file mode 100644 >> index 0000000..3c210e0 >> --- /dev/null >> +++ b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi >> @@ -0,0 +1,82 @@ >> +/* >> + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ] >> + * >> + * Copyright 2013 Freescale Semiconductor Inc. >> + * >> + * Redistribution and use in source and binary forms, with or without >> + * modification, are permitted provided that the following conditions are met: >> + * * Redistributions of source code must retain the above copyright >> + * notice, this list of conditions and the following disclaimer. >> + * * Redistributions in binary form must reproduce the above copyright >> + * notice, this list of conditions and the following disclaimer in the >> + * documentation and/or other materials provided with the distribution. >> + * * Neither the name of Freescale Semiconductor nor the >> + * names of its contributors may be used to endorse or promote products >> + * derived from this software without specific prior written permission. >> + * >> + * >> + * ALTERNATIVELY, this software may be distributed under the terms of the >> + * GNU General Public License ("GPL") as published by the Free Software >> + * Foundation, either version 2 of that License or (at your option) any >> + * later version. >> + * >> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY >> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED >> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE >> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY >> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES >> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; >> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND >> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS >> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> + */ >> + >> +dma0: dma@100300 { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + compatible = "fsl,elo3-dma"; >> + reg = <0x100300 0x4>, >> + <0x100600 0x4>; >> + ranges = <0x0 0x100100 0x500>; >> + dma-channel@0 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x0 0x80>; >> + interrupts = <28 2 0 0>; >> + }; >> + dma-channel@80 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x80 0x80>; >> + interrupts = <29 2 0 0>; >> + }; >> + dma-channel@100 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x100 0x80>; >> + interrupts = <30 2 0 0>; >> + }; >> + dma-channel@180 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x180 0x80>; >> + interrupts = <31 2 0 0>; >> + }; >> + dma-channel@300 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x300 0x80>; >> + interrupts = <76 2 0 0>; >> + }; >> + dma-channel@380 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x380 0x80>; >> + interrupts = <77 2 0 0>; >> + }; >> + dma-channel@400 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x400 0x80>; >> + interrupts = <78 2 0 0>; >> + }; >> + dma-channel@480 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x480 0x80>; >> + interrupts = <79 2 0 0>; >> + }; >> +}; >> diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi b/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi >> new file mode 100644 >> index 0000000..cccf3bb >> --- /dev/null >> +++ b/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi >> @@ -0,0 +1,82 @@ >> +/* >> + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ] >> + * >> + * Copyright 2013 Freescale Semiconductor Inc. >> + * >> + * Redistribution and use in source and binary forms, with or without >> + * modification, are permitted provided that the following conditions are met: >> + * * Redistributions of source code must retain the above copyright >> + * notice, this list of conditions and the following disclaimer. >> + * * Redistributions in binary form must reproduce the above copyright >> + * notice, this list of conditions and the following disclaimer in the >> + * documentation and/or other materials provided with the distribution. >> + * * Neither the name of Freescale Semiconductor nor the >> + * names of its contributors may be used to endorse or promote products >> + * derived from this software without specific prior written permission. >> + * >> + * >> + * ALTERNATIVELY, this software may be distributed under the terms of the >> + * GNU General Public License ("GPL") as published by the Free Software >> + * Foundation, either version 2 of that License or (at your option) any >> + * later version. >> + * >> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY >> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED >> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE >> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY >> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES >> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; >> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND >> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS >> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> + */ >> + >> +dma1: dma@101300 { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + compatible = "fsl,elo3-dma"; >> + reg = <0x101300 0x4>, >> + <0x101600 0x4>; >> + ranges = <0x0 0x101100 0x500>; >> + dma-channel@0 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x0 0x80>; >> + interrupts = <32 2 0 0>; >> + }; >> + dma-channel@80 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x80 0x80>; >> + interrupts = <33 2 0 0>; >> + }; >> + dma-channel@100 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x100 0x80>; >> + interrupts = <34 2 0 0>; >> + }; >> + dma-channel@180 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x180 0x80>; >> + interrupts = <35 2 0 0>; >> + }; >> + dma-channel@300 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x300 0x80>; >> + interrupts = <80 2 0 0>; >> + }; >> + dma-channel@380 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x380 0x80>; >> + interrupts = <81 2 0 0>; >> + }; >> + dma-channel@400 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x400 0x80>; >> + interrupts = <82 2 0 0>; >> + }; >> + dma-channel@480 { >> + compatible = "fsl,eloplus-dma-channel"; >> + reg = <0x480 0x80>; >> + interrupts = <83 2 0 0>; >> + }; >> +}; >> diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi >> index bd611a9..ec95c60 100644 >> --- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi >> +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi >> @@ -387,8 +387,8 @@ >> reg = <0xea000 0x4000>; >> }; >> >> -/include/ "qoriq-dma-0.dtsi" >> -/include/ "qoriq-dma-1.dtsi" >> +/include/ "elo3-dma-0.dtsi" >> +/include/ "elo3-dma-1.dtsi" >> >> /include/ "qoriq-espi-0.dtsi" >> spi@110000 { >> -- >> 1.7.9.5 >> >> >> >> ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes 2013-09-03 9:01 ` Hongbo Zhang @ 2013-09-10 6:00 ` Hongbo Zhang 2013-09-12 17:15 ` Mark Rutland 1 sibling, 0 replies; 10+ messages in thread From: Hongbo Zhang @ 2013-09-10 6:00 UTC (permalink / raw) To: Mark Rutland Cc: rob.herring@calxeda.com, Pawel Moll, swarren@wwwdotorg.org, ian.campbell@citrix.com, vinod.koul@intel.com, djbw@fb.com, devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Mark? ping. On 09/03/2013 05:01 PM, Hongbo Zhang wrote: > On 09/02/2013 11:58 PM, Mark Rutland wrote: >> Hi, >> >> On Fri, Aug 30, 2013 at 12:26:19PM +0100, hongbo.zhang@freescale.com >> wrote: >>> From: Hongbo Zhang <hongbo.zhang@freescale.com> >>> >>> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this >>> patch adds >>> the device tree nodes for them. >>> >>> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> >>> --- >>> .../devicetree/bindings/powerpc/fsl/dma.txt | 67 >>> ++++++++++++++++ >>> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 4 +- >>> arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82 >>> ++++++++++++++++++++ >>> arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82 >>> ++++++++++++++++++++ >>> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 4 +- >>> 5 files changed, 235 insertions(+), 4 deletions(-) >>> create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi >>> create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi >>> >>> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt >>> b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt >>> index ddf17af..332ac77 100644 >>> --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt >>> +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt >>> @@ -126,6 +126,73 @@ Example: >>> }; >>> }; >>> >>> +** Freescale Elo3 DMA Controller >>> + This is EloPlus controller with 8 channels, used in Freescale >>> Txxx and Bxxx >> I was under the impression EloPlus was the previous revision. Should >> that say Elo3, or is Elo3 considered to be an EloPlus implementation? > In this patch 1/3 I revise the doc to make it clear we have Elo and > EloPlus, and I'm adding another new Elo3. Yes the only difference > between Elo3 and EloPlus is channel numbers(8 channels vs 4 channels), > so we can call "Elo3 is an 8-channel EloPlus" >>> + series chips, such as t1040, t4240, b4860. >>> + >>> +Required properties: >>> + >>> +- compatible : must include "fsl,elo3-dma" >>> +- reg : <registers specifier for DMA general status reg> >> The example has two reg entries. What both are should be specified. From >> what you described last time, it sounds like each is a status register >> for four channels. >> >> Presumably the first covers the channels at 0x0,0x80,0x100,0x180, and >> the second covers the channels at 0x300,0x380,0x400,0x480? If the >> registers have specific names in a datasheet, it would be worth >> mentioning them. > Yes, each is a status register for four channels, you got it -- this > means my statement works. > Is it necessary to specify all the register names? > I can describe my two registers, but in other cases the reg entryies > can cover tens even hundreds of registers, just a summary is OK I think. >> If the specification of the DMA controller allows for more channels, it >> may be worth describing that case now. > This DMA controller doesn't allows for more channels. (Even if it > does, it should be another new controller) >>> +- ranges : describes the mapping between the address >>> space of the >>> + DMA channels and the address space of the DMA >>> controller >> This looks odd as a required property, and I'm slightly confused. Is >> this used to map the reg values of the DMA channels, or is it used when >> mapping the DMA address space (for which dma-ranges exists in ePAPR and >> other bindings). > It is used to map the reg values of DMA channels. >>> + >>> +- DMA channel nodes: >>> + - compatible : must include "fsl,eloplus-dma-channel" >>> + - reg : <registers specifier for channel> >> What does this represent? What are valid values? >> >> In the example below it looks like these are offsets of control >> registers within the dma controller. > Yes, they are offsets of control registers within dma controller, but > the contents in these registers are for dma channels. > Physically we have dma controller registers and dma channel registers, > they are in one continuous physical address space, we divide all these > registers into two controller/channel parts, according to contents in > these registers, common status registers for all channels are called > dma controller registers, otherwise channel specific registers are > called dma channel registers. >> If the reg property may have any value, how do they get mapped to bits >> in the status register(s)? > In fact, each channel has its own status register(and also other > registers), the dma controller status register is just aggregation of > all channel status register. (that seems duplicated somehow, maybe > this is due to hardware compatibility with legacy one, and the device > tree just describes the physical hardware without lie) >> May some channels be unusable for some reason, or will all eight >> channels be wired on any given Elo3 DMA? > Sorry, not get your point clearly, maybe you are clear now because of > my previous explanations. >> Cheers, >> Mark. >> >>> + - interrupts : <interrupt specifier for DMA channel >>> IRQ> >>> + - interrupt-parent : optional, if needed for interrupt >>> mapping >>> + >>> +Example: >>> +dma@100300 { >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + compatible = "fsl,elo3-dma"; >>> + reg = <0x100300 0x4>, >>> + <0x100600 0x4>; >>> + ranges = <0x0 0x100100 0x500>; >>> + dma-channel@0 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x0 0x80>; >>> + interrupts = <28 2 0 0>; >>> + }; >>> + dma-channel@80 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x80 0x80>; >>> + interrupts = <29 2 0 0>; >>> + }; >>> + dma-channel@100 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x100 0x80>; >>> + interrupts = <30 2 0 0>; >>> + }; >>> + dma-channel@180 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x180 0x80>; >>> + interrupts = <31 2 0 0>; >>> + }; >>> + dma-channel@300 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x300 0x80>; >>> + interrupts = <76 2 0 0>; >>> + }; >>> + dma-channel@380 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x380 0x80>; >>> + interrupts = <77 2 0 0>; >>> + }; >>> + dma-channel@400 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x400 0x80>; >>> + interrupts = <78 2 0 0>; >>> + }; >>> + dma-channel@480 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x480 0x80>; >>> + interrupts = <79 2 0 0>; >>> + }; >>> +}; >>> + >>> Note on DMA channel compatible properties: The compatible property >>> must say >>> "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by >>> the Elo DMA >>> driver (fsldma). Any DMA channel used by fsldma cannot be used by >>> another >>> diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi >>> b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi >>> index 7399154..ea53ea1 100644 >>> --- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi >>> +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi >>> @@ -223,13 +223,13 @@ >>> reg = <0xe2000 0x1000>; >>> }; >>> >>> -/include/ "qoriq-dma-0.dtsi" >>> +/include/ "elo3-dma-0.dtsi" >>> dma@100300 { >>> fsl,iommu-parent = <&pamu0>; >>> fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ >>> }; >>> >>> -/include/ "qoriq-dma-1.dtsi" >>> +/include/ "elo3-dma-1.dtsi" >>> dma@101300 { >>> fsl,iommu-parent = <&pamu0>; >>> fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ >>> diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi >>> b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi >>> new file mode 100644 >>> index 0000000..3c210e0 >>> --- /dev/null >>> +++ b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi >>> @@ -0,0 +1,82 @@ >>> +/* >>> + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ] >>> + * >>> + * Copyright 2013 Freescale Semiconductor Inc. >>> + * >>> + * Redistribution and use in source and binary forms, with or without >>> + * modification, are permitted provided that the following >>> conditions are met: >>> + * * Redistributions of source code must retain the above >>> copyright >>> + * notice, this list of conditions and the following disclaimer. >>> + * * Redistributions in binary form must reproduce the above >>> copyright >>> + * notice, this list of conditions and the following >>> disclaimer in the >>> + * documentation and/or other materials provided with the >>> distribution. >>> + * * Neither the name of Freescale Semiconductor nor the >>> + * names of its contributors may be used to endorse or >>> promote products >>> + * derived from this software without specific prior written >>> permission. >>> + * >>> + * >>> + * ALTERNATIVELY, this software may be distributed under the terms >>> of the >>> + * GNU General Public License ("GPL") as published by the Free >>> Software >>> + * Foundation, either version 2 of that License or (at your option) >>> any >>> + * later version. >>> + * >>> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' >>> AND ANY >>> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, >>> THE IMPLIED >>> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR >>> PURPOSE ARE >>> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE >>> FOR ANY >>> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR >>> CONSEQUENTIAL DAMAGES >>> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS >>> OR SERVICES; >>> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER >>> CAUSED AND >>> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT >>> LIABILITY, OR TORT >>> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF >>> THE USE OF THIS >>> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >>> + */ >>> + >>> +dma0: dma@100300 { >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + compatible = "fsl,elo3-dma"; >>> + reg = <0x100300 0x4>, >>> + <0x100600 0x4>; >>> + ranges = <0x0 0x100100 0x500>; >>> + dma-channel@0 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x0 0x80>; >>> + interrupts = <28 2 0 0>; >>> + }; >>> + dma-channel@80 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x80 0x80>; >>> + interrupts = <29 2 0 0>; >>> + }; >>> + dma-channel@100 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x100 0x80>; >>> + interrupts = <30 2 0 0>; >>> + }; >>> + dma-channel@180 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x180 0x80>; >>> + interrupts = <31 2 0 0>; >>> + }; >>> + dma-channel@300 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x300 0x80>; >>> + interrupts = <76 2 0 0>; >>> + }; >>> + dma-channel@380 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x380 0x80>; >>> + interrupts = <77 2 0 0>; >>> + }; >>> + dma-channel@400 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x400 0x80>; >>> + interrupts = <78 2 0 0>; >>> + }; >>> + dma-channel@480 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x480 0x80>; >>> + interrupts = <79 2 0 0>; >>> + }; >>> +}; >>> diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi >>> b/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi >>> new file mode 100644 >>> index 0000000..cccf3bb >>> --- /dev/null >>> +++ b/arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi >>> @@ -0,0 +1,82 @@ >>> +/* >>> + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ] >>> + * >>> + * Copyright 2013 Freescale Semiconductor Inc. >>> + * >>> + * Redistribution and use in source and binary forms, with or without >>> + * modification, are permitted provided that the following >>> conditions are met: >>> + * * Redistributions of source code must retain the above >>> copyright >>> + * notice, this list of conditions and the following disclaimer. >>> + * * Redistributions in binary form must reproduce the above >>> copyright >>> + * notice, this list of conditions and the following >>> disclaimer in the >>> + * documentation and/or other materials provided with the >>> distribution. >>> + * * Neither the name of Freescale Semiconductor nor the >>> + * names of its contributors may be used to endorse or >>> promote products >>> + * derived from this software without specific prior written >>> permission. >>> + * >>> + * >>> + * ALTERNATIVELY, this software may be distributed under the terms >>> of the >>> + * GNU General Public License ("GPL") as published by the Free >>> Software >>> + * Foundation, either version 2 of that License or (at your option) >>> any >>> + * later version. >>> + * >>> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' >>> AND ANY >>> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, >>> THE IMPLIED >>> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR >>> PURPOSE ARE >>> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE >>> FOR ANY >>> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR >>> CONSEQUENTIAL DAMAGES >>> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS >>> OR SERVICES; >>> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER >>> CAUSED AND >>> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT >>> LIABILITY, OR TORT >>> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF >>> THE USE OF THIS >>> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >>> + */ >>> + >>> +dma1: dma@101300 { >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + compatible = "fsl,elo3-dma"; >>> + reg = <0x101300 0x4>, >>> + <0x101600 0x4>; >>> + ranges = <0x0 0x101100 0x500>; >>> + dma-channel@0 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x0 0x80>; >>> + interrupts = <32 2 0 0>; >>> + }; >>> + dma-channel@80 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x80 0x80>; >>> + interrupts = <33 2 0 0>; >>> + }; >>> + dma-channel@100 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x100 0x80>; >>> + interrupts = <34 2 0 0>; >>> + }; >>> + dma-channel@180 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x180 0x80>; >>> + interrupts = <35 2 0 0>; >>> + }; >>> + dma-channel@300 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x300 0x80>; >>> + interrupts = <80 2 0 0>; >>> + }; >>> + dma-channel@380 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x380 0x80>; >>> + interrupts = <81 2 0 0>; >>> + }; >>> + dma-channel@400 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x400 0x80>; >>> + interrupts = <82 2 0 0>; >>> + }; >>> + dma-channel@480 { >>> + compatible = "fsl,eloplus-dma-channel"; >>> + reg = <0x480 0x80>; >>> + interrupts = <83 2 0 0>; >>> + }; >>> +}; >>> diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi >>> b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi >>> index bd611a9..ec95c60 100644 >>> --- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi >>> +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi >>> @@ -387,8 +387,8 @@ >>> reg = <0xea000 0x4000>; >>> }; >>> >>> -/include/ "qoriq-dma-0.dtsi" >>> -/include/ "qoriq-dma-1.dtsi" >>> +/include/ "elo3-dma-0.dtsi" >>> +/include/ "elo3-dma-1.dtsi" >>> >>> /include/ "qoriq-espi-0.dtsi" >>> spi@110000 { >>> -- >>> 1.7.9.5 >>> >>> >>> >>> > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes 2013-09-03 9:01 ` Hongbo Zhang 2013-09-10 6:00 ` Hongbo Zhang @ 2013-09-12 17:15 ` Mark Rutland [not found] ` <20130912171541.GH22013-NuALmloUBlrZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org> 1 sibling, 1 reply; 10+ messages in thread From: Mark Rutland @ 2013-09-12 17:15 UTC (permalink / raw) To: Hongbo Zhang Cc: rob.herring@calxeda.com, Pawel Moll, swarren@wwwdotorg.org, ian.campbell@citrix.com, vinod.koul@intel.com, djbw@fb.com, devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote: > On 09/02/2013 11:58 PM, Mark Rutland wrote: > > Hi, > > > > On Fri, Aug 30, 2013 at 12:26:19PM +0100, hongbo.zhang@freescale.com wrote: > >> From: Hongbo Zhang <hongbo.zhang@freescale.com> > >> > >> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds > >> the device tree nodes for them. > >> > >> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> > >> --- > >> .../devicetree/bindings/powerpc/fsl/dma.txt | 67 ++++++++++++++++ > >> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 4 +- > >> arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82 ++++++++++++++++++++ > >> arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82 ++++++++++++++++++++ > >> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 4 +- > >> 5 files changed, 235 insertions(+), 4 deletions(-) > >> create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi > >> create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi > >> > >> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt > >> index ddf17af..332ac77 100644 > >> --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt > >> +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt > >> @@ -126,6 +126,73 @@ Example: > >> }; > >> }; > >> > >> +** Freescale Elo3 DMA Controller > >> + This is EloPlus controller with 8 channels, used in Freescale Txxx and Bxxx > > I was under the impression EloPlus was the previous revision. Should > > that say Elo3, or is Elo3 considered to be an EloPlus implementation? > In this patch 1/3 I revise the doc to make it clear we have Elo and > EloPlus, and I'm adding another new Elo3. Yes the only difference > between Elo3 and EloPlus is channel numbers(8 channels vs 4 channels), > so we can call "Elo3 is an 8-channel EloPlus" Ok. > >> + series chips, such as t1040, t4240, b4860. > >> + > >> +Required properties: > >> + > >> +- compatible : must include "fsl,elo3-dma" > >> +- reg : <registers specifier for DMA general status reg> > > The example has two reg entries. What both are should be specified. From > > what you described last time, it sounds like each is a status register > > for four channels. > > > > Presumably the first covers the channels at 0x0,0x80,0x100,0x180, and > > the second covers the channels at 0x300,0x380,0x400,0x480? If the > > registers have specific names in a datasheet, it would be worth > > mentioning them. > Yes, each is a status register for four channels, you got it -- this > means my statement works. > Is it necessary to specify all the register names? > I can describe my two registers, but in other cases the reg entryies can > cover tens even hundreds of registers, just a summary is OK I think. I think there should at least be a description of which channels each reg entry corresponds to. I see this hasn't been done so far for the older Elo DMAs, but they only had 4 channels max, and one status reg. > > If the specification of the DMA controller allows for more channels, it > > may be worth describing that case now. > This DMA controller doesn't allows for more channels. (Even if it does, > it should be another new controller) Ok. > >> +- ranges : describes the mapping between the address space of the > >> + DMA channels and the address space of the DMA controller > > This looks odd as a required property, and I'm slightly confused. Is > > this used to map the reg values of the DMA channels, or is it used when > > mapping the DMA address space (for which dma-ranges exists in ePAPR and > > other bindings). > It is used to map the reg values of DMA channels. Ok, I guess that makes sense. > >> + > >> +- DMA channel nodes: > >> + - compatible : must include "fsl,eloplus-dma-channel" > >> + - reg : <registers specifier for channel> > > What does this represent? What are valid values? > > > > In the example below it looks like these are offsets of control > > registers within the dma controller. > Yes, they are offsets of control registers within dma controller, but > the contents in these registers are for dma channels. > Physically we have dma controller registers and dma channel registers, > they are in one continuous physical address space, we divide all these > registers into two controller/channel parts, according to contents in > these registers, common status registers for all channels are called dma > controller registers, otherwise channel specific registers are called > dma channel registers. I see, so this reg represents a channels channel specific registers (which are distinct from the shared status registers). I was confused initially as to what address space they were in, but that makes sense with your description of ranges above. > > If the reg property may have any value, how do they get mapped to bits > > in the status register(s)? > In fact, each channel has its own status register(and also other > registers), the dma controller status register is just aggregation of > all channel status register. (that seems duplicated somehow, maybe this > is due to hardware compatibility with legacy one, and the device tree > just describes the physical hardware without lie) My question here was stupid, thanks for the explanation :) > > May some channels be unusable for some reason, or will all eight > > channels be wired on any given Elo3 DMA? > Sorry, not get your point clearly, maybe you are clear now because of my > previous explanations. I assume that on any El03 DMA, there won't be a case where you can't describe the channel at 0x80, for instance. It will always be present (but it might not be wired up to anything any therefore be useful)? This was related to my concerns about the status register description -- if the channels at 0x0,0x80,0x100,0x180 weren't wired, what would get described in the dt? I guess that would never actually happen because all 8 channels must always be present in the Elo3 IP block. Thanks, Mark. ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <20130912171541.GH22013-NuALmloUBlrZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>]
* Re: [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes [not found] ` <20130912171541.GH22013-NuALmloUBlrZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org> @ 2013-09-16 10:25 ` Hongbo Zhang 2013-09-16 22:46 ` Scott Wood 1 sibling, 0 replies; 10+ messages in thread From: Hongbo Zhang @ 2013-09-16 10:25 UTC (permalink / raw) To: Mark Rutland Cc: rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org, Pawel Moll, swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org, ian.campbell-Sxgqhf6Nn4DQT0dZR+AlfA@public.gmane.org, vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, djbw-b10kYP2dOMg@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On 09/13/2013 01:15 AM, Mark Rutland wrote: > On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote: >> On 09/02/2013 11:58 PM, Mark Rutland wrote: >>> Hi, >>> >>> On Fri, Aug 30, 2013 at 12:26:19PM +0100, hongbo.zhang-KZfg59tc24xl57MIdRCFDg@public.gmane.org wrote: >>>> From: Hongbo Zhang <hongbo.zhang-KZfg59tc24xl57MIdRCFDg@public.gmane.org> >>>> >>>> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds >>>> the device tree nodes for them. >>>> >>>> Signed-off-by: Hongbo Zhang <hongbo.zhang-KZfg59tc24xl57MIdRCFDg@public.gmane.org> >>>> --- >>>> .../devicetree/bindings/powerpc/fsl/dma.txt | 67 ++++++++++++++++ >>>> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 4 +- >>>> arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82 ++++++++++++++++++++ >>>> arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82 ++++++++++++++++++++ >>>> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 4 +- >>>> 5 files changed, 235 insertions(+), 4 deletions(-) >>>> create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi >>>> create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi >>>> >>>> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt >>>> index ddf17af..332ac77 100644 >>>> --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt >>>> +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt >>>> @@ -126,6 +126,73 @@ Example: >>>> }; >>>> }; >>>> >>>> +** Freescale Elo3 DMA Controller >>>> + This is EloPlus controller with 8 channels, used in Freescale Txxx and Bxxx >>> I was under the impression EloPlus was the previous revision. Should >>> that say Elo3, or is Elo3 considered to be an EloPlus implementation? >> In this patch 1/3 I revise the doc to make it clear we have Elo and >> EloPlus, and I'm adding another new Elo3. Yes the only difference >> between Elo3 and EloPlus is channel numbers(8 channels vs 4 channels), >> so we can call "Elo3 is an 8-channel EloPlus" > Ok. > >>>> + series chips, such as t1040, t4240, b4860. >>>> + >>>> +Required properties: >>>> + >>>> +- compatible : must include "fsl,elo3-dma" >>>> +- reg : <registers specifier for DMA general status reg> >>> The example has two reg entries. What both are should be specified. From >>> what you described last time, it sounds like each is a status register >>> for four channels. >>> >>> Presumably the first covers the channels at 0x0,0x80,0x100,0x180, and >>> the second covers the channels at 0x300,0x380,0x400,0x480? If the >>> registers have specific names in a datasheet, it would be worth >>> mentioning them. >> Yes, each is a status register for four channels, you got it -- this >> means my statement works. >> Is it necessary to specify all the register names? >> I can describe my two registers, but in other cases the reg entryies can >> cover tens even hundreds of registers, just a summary is OK I think. > I think there should at least be a description of which channels each > reg entry corresponds to. I see this hasn't been done so far for the > older Elo DMAs, but they only had 4 channels max, and one status reg. OK, I will update the reg description to make it more clear. >>> If the specification of the DMA controller allows for more channels, it >>> may be worth describing that case now. >> This DMA controller doesn't allows for more channels. (Even if it does, >> it should be another new controller) > Ok. > >>>> +- ranges : describes the mapping between the address space of the >>>> + DMA channels and the address space of the DMA controller >>> This looks odd as a required property, and I'm slightly confused. Is >>> this used to map the reg values of the DMA channels, or is it used when >>> mapping the DMA address space (for which dma-ranges exists in ePAPR and >>> other bindings). >> It is used to map the reg values of DMA channels. > Ok, I guess that makes sense. > >>>> + >>>> +- DMA channel nodes: >>>> + - compatible : must include "fsl,eloplus-dma-channel" >>>> + - reg : <registers specifier for channel> >>> What does this represent? What are valid values? >>> >>> In the example below it looks like these are offsets of control >>> registers within the dma controller. >> Yes, they are offsets of control registers within dma controller, but >> the contents in these registers are for dma channels. >> Physically we have dma controller registers and dma channel registers, >> they are in one continuous physical address space, we divide all these >> registers into two controller/channel parts, according to contents in >> these registers, common status registers for all channels are called dma >> controller registers, otherwise channel specific registers are called >> dma channel registers. > I see, so this reg represents a channels channel specific registers > (which are distinct from the shared status registers). I was confused > initially as to what address space they were in, but that makes sense > with your description of ranges above. > >>> If the reg property may have any value, how do they get mapped to bits >>> in the status register(s)? >> In fact, each channel has its own status register(and also other >> registers), the dma controller status register is just aggregation of >> all channel status register. (that seems duplicated somehow, maybe this >> is due to hardware compatibility with legacy one, and the device tree >> just describes the physical hardware without lie) > My question here was stupid, thanks for the explanation :) > >>> May some channels be unusable for some reason, or will all eight >>> channels be wired on any given Elo3 DMA? >> Sorry, not get your point clearly, maybe you are clear now because of my >> previous explanations. > I assume that on any El03 DMA, there won't be a case where you can't > describe the channel at 0x80, for instance. It will always be present > (but it might not be wired up to anything any therefore be useful)? > > This was related to my concerns about the status register description -- > if the channels at 0x0,0x80,0x100,0x180 weren't wired, what would get > described in the dt? I guess that would never actually happen because > all 8 channels must always be present in the Elo3 IP block. Yes, for this Elo3 DMA IP block, all the 8 channels are always on. > Thanks, > Mark. > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes [not found] ` <20130912171541.GH22013-NuALmloUBlrZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org> 2013-09-16 10:25 ` Hongbo Zhang @ 2013-09-16 22:46 ` Scott Wood 1 sibling, 0 replies; 10+ messages in thread From: Scott Wood @ 2013-09-16 22:46 UTC (permalink / raw) To: Mark Rutland Cc: Hongbo Zhang, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, ian.campbell-Sxgqhf6Nn4DQT0dZR+AlfA@public.gmane.org, Pawel Moll, swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org, vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org, djbw-b10kYP2dOMg@public.gmane.org, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org On Thu, 2013-09-12 at 18:15 +0100, Mark Rutland wrote: > On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote: > > On 09/02/2013 11:58 PM, Mark Rutland wrote: > > > May some channels be unusable for some reason, or will all eight > > > channels be wired on any given Elo3 DMA? > > Sorry, not get your point clearly, maybe you are clear now because of my > > previous explanations. > > I assume that on any El03 DMA, there won't be a case where you can't > describe the channel at 0x80, for instance. It will always be present > (but it might not be wired up to anything any therefore be useful)? > > This was related to my concerns about the status register description -- > if the channels at 0x0,0x80,0x100,0x180 weren't wired, what would get > described in the dt? I guess that would never actually happen because > all 8 channels must always be present in the Elo3 IP block. If a channel is not usable for whatever reason (other than that "used for a different fixed purpose and thus described with a different compatible" thing that was mentioned earlier in these threads), wouldn't it just have status = "disabled" or similar, or be absent? -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v9 3/3] DMA: Freescale: update driver to support 8-channel DMA engine 2013-08-30 11:26 [PATCH v9 0/3] DMA: Freescale: Add support for 8-channel DMA engine hongbo.zhang 2013-08-30 11:26 ` [PATCH v9 1/3] DMA: Freescale: revise device tree binding document hongbo.zhang 2013-08-30 11:26 ` [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes hongbo.zhang @ 2013-08-30 11:26 ` hongbo.zhang 2 siblings, 0 replies; 10+ messages in thread From: hongbo.zhang @ 2013-08-30 11:26 UTC (permalink / raw) To: rob.herring, pawel.moll, mark.rutland, swarren, ian.campbell, vinod.koul, djbw Cc: devicetree, linuxppc-dev, linux-kernel, Hongbo Zhang From: Hongbo Zhang <hongbo.zhang@freescale.com> This patch adds support to 8-channel DMA engine, thus the driver works for both the new 8-channel and the legacy 4-channel DMA engines. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> --- drivers/dma/Kconfig | 9 +++++---- drivers/dma/fsldma.c | 9 ++++++--- drivers/dma/fsldma.h | 2 +- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 6825957..3979c65 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -89,14 +89,15 @@ config AT_HDMAC Support the Atmel AHB DMA controller. config FSL_DMA - tristate "Freescale Elo and Elo Plus DMA support" + tristate "Freescale Elo series DMA support" depends on FSL_SOC select DMA_ENGINE select ASYNC_TX_ENABLE_CHANNEL_SWITCH ---help--- - Enable support for the Freescale Elo and Elo Plus DMA controllers. - The Elo is the DMA controller on some 82xx and 83xx parts, and the - Elo Plus is the DMA controller on 85xx and 86xx parts. + Enable support for the Freescale Elo series DMA controllers. + The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the + EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on + some Txxx and Bxxx parts. config MPC512X_DMA tristate "Freescale MPC512x built-in DMA engine support" diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 49e8fbd..16a9a48 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -1261,7 +1261,9 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev, WARN_ON(fdev->feature != chan->feature); chan->dev = fdev->dev; - chan->id = ((res.start - 0x100) & 0xfff) >> 7; + chan->id = (res.start & 0xfff) < 0x300 ? + ((res.start - 0x100) & 0xfff) >> 7 : + ((res.start - 0x200) & 0xfff) >> 7; if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { dev_err(fdev->dev, "too many channels for device\n"); err = -EINVAL; @@ -1434,6 +1436,7 @@ static int fsldma_of_remove(struct platform_device *op) } static const struct of_device_id fsldma_of_ids[] = { + { .compatible = "fsl,elo3-dma", }, { .compatible = "fsl,eloplus-dma", }, { .compatible = "fsl,elo-dma", }, {} @@ -1455,7 +1458,7 @@ static struct platform_driver fsldma_of_driver = { static __init int fsldma_init(void) { - pr_info("Freescale Elo / Elo Plus DMA driver\n"); + pr_info("Freescale Elo series DMA driver\n"); return platform_driver_register(&fsldma_of_driver); } @@ -1467,5 +1470,5 @@ static void __exit fsldma_exit(void) subsys_initcall(fsldma_init); module_exit(fsldma_exit); -MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); +MODULE_DESCRIPTION("Freescale Elo series DMA driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index f5c3879..1ffc244 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -112,7 +112,7 @@ struct fsldma_chan_regs { }; struct fsldma_chan; -#define FSL_DMA_MAX_CHANS_PER_DEVICE 4 +#define FSL_DMA_MAX_CHANS_PER_DEVICE 8 struct fsldma_device { void __iomem *regs; /* DGSR register base */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2013-09-16 22:46 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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2013-08-30 11:26 [PATCH v9 0/3] DMA: Freescale: Add support for 8-channel DMA engine hongbo.zhang
2013-08-30 11:26 ` [PATCH v9 1/3] DMA: Freescale: revise device tree binding document hongbo.zhang
2013-08-30 11:26 ` [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes hongbo.zhang
2013-09-02 15:58 ` Mark Rutland
2013-09-03 9:01 ` Hongbo Zhang
2013-09-10 6:00 ` Hongbo Zhang
2013-09-12 17:15 ` Mark Rutland
[not found] ` <20130912171541.GH22013-NuALmloUBlrZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2013-09-16 10:25 ` Hongbo Zhang
2013-09-16 22:46 ` Scott Wood
2013-08-30 11:26 ` [PATCH v9 3/3] DMA: Freescale: update driver to support 8-channel DMA engine hongbo.zhang
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