From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCHv4 2/3] ARM: msm: Add support for APQ8074 Dragonboard Date: Thu, 26 Sep 2013 16:10:02 -0500 Message-ID: <5244A2AA.6050901@gmail.com> References: <1379992406-3541-1-git-send-email-rvaswani@codeaurora.org> <1379992406-3541-2-git-send-email-rvaswani@codeaurora.org> <4E7868D6-56CB-4AF8-8EBF-069966899C23@codeaurora.org> <5243652F.7090408@codeaurora.org> <52447779.3010908@codeaurora.org> <52448852.9050608@codeaurora.org> <50877C70-6066-4E87-9DEA-9F29D098525B@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <50877C70-6066-4E87-9DEA-9F29D098525B-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Kumar Gala Cc: Rohit Vaswani , David Brown , Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Russell King , Daniel Walker , Bryan Huntsman , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 09/26/2013 02:33 PM, Kumar Gala wrote: > > On Sep 26, 2013, at 2:17 PM, Rohit Vaswani wrote: > >> On 9/26/2013 11:05 AM, Rohit Vaswani wrote: >>> On 9/26/2013 9:37 AM, Kumar Gala wrote: >>>> >>> >>>> +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -0,0 >>>> +1,6 @@ +/include/ "qcom-msm8974.dtsi" + +/ { + model = >>>> "Qualcomm APQ8074 Dragonboard"; + compatible = >>>> "qcom,apq8074-dragonboard", "qcom,apq8074"; +}; diff --git >>>> a/arch/arm/boot/dts/qcom-msm8974.dtsi >>>> b/arch/arm/boot/dts/qcom-msm8974.dtsi new file mode 100644 >>>> index 0000000..f04b643 --- /dev/null +++ >>>> b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -0,0 +1,35 @@ >>>> +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + model = >>>> "Qualcomm MSM8974"; + compatible = "qcom,msm8974"; + >>>> interrupt-parent = <&intc>; + + soc: soc { }; >>>>>> We should have a unit address here: >>>>>> >>>>>> soc: soc@FOOBAR { >>>>>> >>>>>> also, split out the curly braces so any future patches do >>>>>> have to muck with that. >>>>>> >>>>>> }; >>>>>> >>>>> Im not sure I understand the reasoning behind the unit >>>>> address for soc ? >>>> Its fairly standard practice and there is a fair amount of >>>> discussion about the lack of a unit address for memory nodes. >>>> >>> That still doesn't really answer anything :) - and I couldn't >>> find any discussions about this either. I don't see anybody in >>> upstream adding an address to soc except sun. What is that >>> address supposed to be for - what does it mean ? The soc is way >>> of encapsulating meaningful blocks for the particular SoC. >> >> I see the mail from Stephen Warren for adding a check stating that >> >> "ePAPR 1.1 section 2.2.1.1 "Node Name Requirements" specifies that >> any node that has a reg property must include a unit address in its >> name with value matching the first entry in its reg property. >> Conversely, if a node does not have a reg property, the node name >> must not include a unit address." >> >> The soc node we have does not have a reg property ? > > Not 100% sure what people will decide on this. There are a number of > examples on the PPC side (arch/powerpc/boot/dts) that are soc@ADDR, > but they don't typically have "reg" properties at the soc level. No, but you may have a ranges property which is related. I've just hit this on highbank in needing to add a second bank of peripherals for midway. So my vote would be to have unit address. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html