[PATCH v2 0/2] ARM DT cpus/cpu and topology bindings

[PATCH v2 0/2] ARM DT cpus/cpu and topology bindings

[Lorenzo Pieralisi]

This is v2 of a previous posting:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-August/192322.html

- v2 changes
	- Removed single core cpu-map example
	- Removed OS dependency from cpus/cpu bindings
	- Updated Marvell compatible strings
	- Clarified behaviour on pre ARM v7 uniprocessor systems and updated
	  examples

This patch resumes DT topology/cpu bindings discussions for ARM that were
started here:

https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/031725.html
https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/032450.html

Comments welcome, thanks,
Lorenzo

Lorenzo Pieralisi (2):
  Documentation: devicetree: arm: cpus/cpu nodes bindings updates
  Documentation: DT: arm: define CPU topology bindings

 Documentation/devicetree/bindings/arm/cpus.txt     | 391 +++++++++++++++--
 Documentation/devicetree/bindings/arm/topology.txt | 474 +++++++++++++++++++++
 2 files changed, 818 insertions(+), 47 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/topology.txt

-- 
1.8.2.2


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[PATCH v2 1/2] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Lorenzo Pieralisi]

In order to extend the current cpu nodes bindings to newer CPUs
inclusive of AArch64 and to update support for older ARM CPUs this
patch updates device tree documentation for the cpu nodes bindings.

Main changes:
    - adds 64-bit bindings
    - define usage of #address-cells
    - defines behaviour on pre and post v7 uniprocessor systems
    - adds ARM 11MPcore specific reg property definition

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/cpus.txt | 391 ++++++++++++++++++++++---
 1 file changed, 344 insertions(+), 47 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index f32494d..e534110 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -1,77 +1,374 @@
-* ARM CPUs binding description
+=================
+ARM CPUs bindings
+=================
 
 The device tree allows to describe the layout of CPUs in a system through
 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
 defining properties for every cpu.
 
-Bindings for CPU nodes follow the ePAPR standard, available from:
-
-http://devicetree.org
-
-For the ARM architecture every CPU node must contain the following properties:
-
-- device_type:	must be "cpu"
-- reg:		property matching the CPU MPIDR[23:0] register bits
-		reg[31:24] bits must be set to 0
-- compatible:	should be one of:
-		"arm,arm1020"
-		"arm,arm1020e"
-		"arm,arm1022"
-		"arm,arm1026"
-		"arm,arm720"
-		"arm,arm740"
-		"arm,arm7tdmi"
-		"arm,arm920"
-		"arm,arm922"
-		"arm,arm925"
-		"arm,arm926"
-		"arm,arm940"
-		"arm,arm946"
-		"arm,arm9tdmi"
-		"arm,cortex-a5"
-		"arm,cortex-a7"
-		"arm,cortex-a8"
-		"arm,cortex-a9"
-		"arm,cortex-a15"
-		"arm,arm1136"
-		"arm,arm1156"
-		"arm,arm1176"
-		"arm,arm11mpcore"
-		"faraday,fa526"
-		"intel,sa110"
-		"intel,sa1100"
-		"marvell,feroceon"
-		"marvell,mohawk"
-		"marvell,xsc3"
-		"marvell,xscale"
-
-Example:
+Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
+
+https://www.power.org/documentation/epapr-version-1-1/
+
+with updates for 32-bit and 64-bit ARM systems provided in this document.
+
+================================
+Convention used in this document
+================================
+
+This document follows the conventions described in the ePAPR v1.1, with
+the addition:
+
+- square brackets define bitfields, eg reg[7:0] value of the bitfield in
+  the reg property contained in bits 7 down to 0
+
+=====================================
+cpus and cpu node bindings definition
+=====================================
+
+The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
+nodes to be present and contain the properties described below.
+
+- cpus node
+
+	Description: Container of cpu nodes
+
+	The node name must be "cpus".
+
+	A cpus node must define the following properties:
+
+	- #address-cells
+		Usage: required
+		Value type: <u32>
+
+		Definition depends on ARM architecture version and
+		configuration:
+
+			# On uniprocessor ARM architectures previous to v7
+			  value must be 1, to enable a simple enumeration
+			  scheme for processors that do not have a HW CPU
+			  identification register.
+			# On 32-bit ARM 11 MPcore, ARM v7 or later systems
+			  value must be 1, that corresponds to CPUID/MPIDR
+			  registers sizes.
+			# On ARM v8 64-bit systems value must be set to 2,
+			  that corresponds to the MPIDR_EL1 register size.
+
+	- #size-cells
+		Usage: required
+		Value type: <u32>
+		Definition: must be set to 0
+
+- cpu node
+
+	Description: Describes a CPU in an ARM based system
+
+	PROPERTIES
+
+	- device_type
+		Usage: required
+		Value type: <string>
+		Definition: must be "cpu"
+	- reg
+		Usage and definition depend on ARM architecture version and
+		configuration:
+
+			# On uniprocessor ARM architectures previous to v7
+			  this property is required and must be set to 0.
+
+			# On ARM 11 MPcore based systems this property is
+			  required and matches the CPUID[11:0] register bits.
+
+			  Bits [11:0] in the reg cell must be set to
+			  bits [11:0] in CPU ID register.
+
+			  All other bits in the reg cell must be set to 0.
+
+			# On 32-bit ARM v7 or later systems this property is
+			  required and matches the CPU MPIDR[23:0] register
+			  bits.
+
+			  Bits [23:0] in the reg cell must be set to
+			  bits [23:0] in MPIDR.
+
+			  All other bits in the reg cell must be set to 0.
+
+			# On ARM v8 64-bit systems this property is required
+			  and matches the MPIDR_EL1 register affinity bits:
+
+			  The first reg cell bits [7:0] must be set to
+			  bits [39:32] of MPIDR_EL1.
+
+			  The second reg cell bits [23:0] must be set to
+			  bits [23:0] of MPIDR_EL1.
+
+			  All other bits in the reg cells must be set to 0.
+
+	- compatible:
+		Usage: required
+		Value type: <string>
+		Definition: should be one of:
+			    "arm,arm710t"
+			    "arm,arm720t"
+			    "arm,arm740t"
+			    "arm,arm7ej-s"
+			    "arm,arm7tdmi"
+			    "arm,arm7tdmi-s"
+			    "arm,arm9es"
+			    "arm,arm9ej-s"
+			    "arm,arm920t"
+			    "arm,arm922t"
+			    "arm,arm925"
+			    "arm,arm926e-s"
+			    "arm,arm926ej-s"
+			    "arm,arm940t"
+			    "arm,arm946e-s"
+			    "arm,arm966e-s"
+			    "arm,arm968e-s"
+			    "arm,arm9tdmi"
+			    "arm,arm1020e"
+			    "arm,arm1020t"
+			    "arm,arm1022e"
+			    "arm,arm1026ej-s"
+			    "arm,arm1136j-s"
+			    "arm,arm1136jf-s"
+			    "arm,arm1156t2-s"
+			    "arm,arm1156t2f-s"
+			    "arm,arm1176jzf"
+			    "arm,arm1176jz-s"
+			    "arm,arm1176jzf-s"
+			    "arm,arm11mpcore"
+			    "arm,cortex-a5"
+			    "arm,cortex-a7"
+			    "arm,cortex-a8"
+			    "arm,cortex-a9"
+			    "arm,cortex-a15"
+			    "arm,cortex-a53"
+			    "arm,cortex-a57"
+			    "arm,cortex-m0"
+			    "arm,cortex-m0+"
+			    "arm,cortex-m1"
+			    "arm,cortex-m3"
+			    "arm,cortex-m4"
+			    "arm,cortex-r4"
+			    "arm,cortex-r5"
+			    "arm,cortex-r7"
+			    "faraday,fa526"
+			    "intel,sa110"
+			    "intel,sa1100"
+			    "marvell,feroceon"
+			    "marvell,mohawk"
+			    "marvell,pj4a"
+			    "marvell,pj4b"
+			    "marvell,sheeva-v5"
+			    "qcom,krait"
+			    "qcom,scorpion"
+	- enable-method
+		Value type: <stringlist>
+		Usage and definition depend on ARM architecture version.
+			# On ARM v8 64-bit this property is required and must
+			  be one of:
+			     "spin-table"
+			     "psci"
+			# On ARM 32-bit systems this property is optional.
+
+	- cpu-release-addr
+		Usage: required for systems that have an "enable-method"
+		       property value of "spin-table".
+		Value type: <prop-encoded-array>
+		Definition:
+			# On ARM v8 64-bit systems must be a two cell
+			  property identifying a 64-bit zero-initialised
+			  memory location.
+
+Example 1 (dual-cluster big.LITTLE system 32-bit):
 
 	cpus {
 		#size-cells = <0>;
 		#address-cells = <1>;
 
-		CPU0: cpu@0 {
+		cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
 		};
 
-		CPU1: cpu@1 {
+		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x1>;
 		};
 
-		CPU2: cpu@100 {
+		cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 		};
 
-		CPU3: cpu@101 {
+		cpu@101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 		};
 	};
+
+Example 2 (Cortex-A8 uniprocessor 32-bit system):
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a8";
+			reg = <0x0>;
+		};
+	};
+
+Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,arm926ej-s";
+			reg = <0x0>;
+		};
+	};
+
+Example 4 (ARM Cortex-A57 64-bit system):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <2>;
+
+	cpu@0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x0>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x1>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@10000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10000>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@10001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10001>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@10100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@10101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100000000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x0>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100000001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x1>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100000100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100000101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100010000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10000>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100010001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10001>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100010100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu@100010101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+};
-- 
1.8.2.2


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Re: [PATCH v2 1/2] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Jason Cooper]

On Mon, Sep 16, 2013 at 12:21:03PM +0100, Lorenzo Pieralisi wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
> 
> Main changes:
>     - adds 64-bit bindings
>     - define usage of #address-cells
>     - defines behaviour on pre and post v7 uniprocessor systems
>     - adds ARM 11MPcore specific reg property definition
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt | 391 ++++++++++++++++++++++---
>  1 file changed, 344 insertions(+), 47 deletions(-)

For the Marvell bits:

Acked-by: Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>

thx,

Jason.
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Re: [PATCH v2 1/2] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Gregory CLEMENT]

On 16/09/2013 13:21, Lorenzo Pieralisi wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
> 
> Main changes:
>     - adds 64-bit bindings
>     - define usage of #address-cells
>     - defines behaviour on pre and post v7 uniprocessor systems
>     - adds ARM 11MPcore specific reg property definition
> 

For the Marvell (EBU) related part

Acked-by:Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

I would like to point that pj4b could be split in two flavors:
pj4b (currently used by Armada 370) and pj4b-mp (currently used
by Armada XP). The motivation for a such split would be for the errata
fix which can be different between pj4b and pj4b_mp. As we can
detect them at runtime, we don't need it from the device tree.
So we can live with a single pj4b binding.

Regards,


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development, consulting, training and support.
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Re: [PATCH v2 1/2] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Mark Rutland]

Hi Lorenzo,

This looks good, but I have a couple comments.

On Mon, Sep 16, 2013 at 12:21:03PM +0100, Lorenzo Pieralisi wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
> 
> Main changes:
>     - adds 64-bit bindings
>     - define usage of #address-cells
>     - defines behaviour on pre and post v7 uniprocessor systems
>     - adds ARM 11MPcore specific reg property definition
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>

[...]

> +=====================================
> +cpus and cpu node bindings definition
> +=====================================
> +
> +The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
> +nodes to be present and contain the properties described below.
> +
> +- cpus node
> +
> +	Description: Container of cpu nodes
> +
> +	The node name must be "cpus".
> +
> +	A cpus node must define the following properties:
> +
> +	- #address-cells
> +		Usage: required
> +		Value type: <u32>
> +
> +		Definition depends on ARM architecture version and
> +		configuration:
> +
> +			# On uniprocessor ARM architectures previous to v7
> +			  value must be 1, to enable a simple enumeration
> +			  scheme for processors that do not have a HW CPU
> +			  identification register.
> +			# On 32-bit ARM 11 MPcore, ARM v7 or later systems
> +			  value must be 1, that corresponds to CPUID/MPIDR
> +			  registers sizes.
> +			# On ARM v8 64-bit systems value must be set to 2,
> +			  that corresponds to the MPIDR_EL1 register size.

Under some situations (where mpidr_el1[63:32] == 0), #address-cells =
<1> needs to be supported for 64-bit hardware, to maintain compatibility
with kvmtool. Will had a commit specifically to allow this (72aea393a2:
"arm64: smp: honour #address-size when parsing CPU reg property"), which
mentions the kvmtool compatibility issue.

I think we need to state that it _should_ be 2. If all the identifiying
bits in the upper half of the register (currently Aff3) are zero, then 1
cell is permitted, and the cell refers to mpidr_el1[31:0].

It's possible that bits which are currently RES0 may become identifying
bits in future, so for the moment we could state that we only allow one
cell when all of mpidr_el1[63:32] is zero, and if mpidr_el1[40:42,23:0]
becomes insufficient to uniquely identify a CPU we need to update the
binding document.

> +
> +	- #size-cells
> +		Usage: required
> +		Value type: <u32>
> +		Definition: must be set to 0
> +
> +- cpu node
> +
> +	Description: Describes a CPU in an ARM based system
> +
> +	PROPERTIES
> +
> +	- device_type
> +		Usage: required
> +		Value type: <string>
> +		Definition: must be "cpu"
> +	- reg
> +		Usage and definition depend on ARM architecture version and
> +		configuration:
> +
> +			# On uniprocessor ARM architectures previous to v7
> +			  this property is required and must be set to 0.
> +
> +			# On ARM 11 MPcore based systems this property is
> +			  required and matches the CPUID[11:0] register bits.
> +
> +			  Bits [11:0] in the reg cell must be set to
> +			  bits [11:0] in CPU ID register.
> +
> +			  All other bits in the reg cell must be set to 0.
> +
> +			# On 32-bit ARM v7 or later systems this property is
> +			  required and matches the CPU MPIDR[23:0] register
> +			  bits.
> +
> +			  Bits [23:0] in the reg cell must be set to
> +			  bits [23:0] in MPIDR.
> +
> +			  All other bits in the reg cell must be set to 0.

These all look fine to me.

> +
> +			# On ARM v8 64-bit systems this property is required
> +			  and matches the MPIDR_EL1 register affinity bits:
> +
> +			  The first reg cell bits [7:0] must be set to
> +			  bits [39:32] of MPIDR_EL1.
> +
> +			  The second reg cell bits [23:0] must be set to
> +			  bits [23:0] of MPIDR_EL1.
> +
> +			  All other bits in the reg cells must be set to 0.

This probably needs to be reworded to cover the #address-cells = <1>
case mentioned above.

[...]

> +	- enable-method
> +		Value type: <stringlist>
> +		Usage and definition depend on ARM architecture version.
> +			# On ARM v8 64-bit this property is required and must
> +			  be one of:
> +			     "spin-table"
> +			     "psci"
> +			# On ARM 32-bit systems this property is optional.
> +
> +	- cpu-release-addr
> +		Usage: required for systems that have an "enable-method"
> +		       property value of "spin-table".
> +		Value type: <prop-encoded-array>
> +		Definition:
> +			# On ARM v8 64-bit systems must be a two cell
> +			  property identifying a 64-bit zero-initialised
> +			  memory location.
> +

Later, we should probably split these into individual bindings docs to
better describe platform requirements. We don't need to do that now.

Otherwise this looks good. Thanks for all the hard work putting this
together, sorry for the last-minute change request.

With the #address-cells = <1> fixups:

Acked-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>

Thanks,
Mark.
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[PATCH v2 2/2] Documentation: DT: arm: define CPU topology bindings

[Lorenzo Pieralisi]

The advent of multi-cluster ARM systems requires a mechanism to describe
how in hierarchical terms CPUs are connected in ARM SoCs so that the kernel
can initialize and map resources like IRQs and memory space to specific
group(s) of CPUs.

The CPU topology is made up of multiple hierarchy levels whose bottom
layers (aka leaf nodes in device tree syntax) contain links to the HW
CPUs in the system.

The topology bindings are generic for both 32-bit and 64-bit systems and
lay the groundwork on top of which affinity schemes can be built.

This patch provides the documentation in the kernel required to define the
device tree bindings describing the CPU topology for ARM 32-bit and 64-bit
systems.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/topology.txt | 474 +++++++++++++++++++++
 1 file changed, 474 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/topology.txt

diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/arm/topology.txt
new file mode 100644
index 0000000..4aa20e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/topology.txt
@@ -0,0 +1,474 @@
+===========================================
+ARM topology binding description
+===========================================
+
+===========================================
+1 - Introduction
+===========================================
+
+In an ARM system, the hierarchy of CPUs is defined through three entities that
+are used to describe the layout of physical CPUs in the system:
+
+- cluster
+- core
+- thread
+
+The cpu nodes (bindings defined in [1]) represent the devices that
+correspond to physical CPUs and are to be mapped to the hierarchy levels.
+
+The bottom hierarchy level sits at core or thread level depending on whether
+symmetric multi-threading (SMT) is supported or not.
+
+For instance in a system where CPUs support SMT, "cpu" nodes represent all
+threads existing in the system and map to the hierarchy level "thread" above.
+In systems where SMT is not supported "cpu" nodes represent all cores present
+in the system and map to the hierarchy level "core" above.
+
+ARM topology bindings allow one to associate cpu nodes with hierarchical groups
+corresponding to the system hierarchy; syntactically they are defined as device
+tree nodes.
+
+The remainder of this document provides the topology bindings for ARM, based
+on the ePAPR standard, available from:
+
+http://www.power.org/documentation/epapr-version-1-1/
+
+If not stated otherwise, whenever a reference to a cpu node phandle is made its
+value must point to a cpu node compliant with the cpu node bindings as
+documented in [1].
+A topology description containing phandles to cpu nodes that are not compliant
+with bindings standardized in [1] is therefore considered invalid.
+
+===========================================
+2 - cpu-map node
+===========================================
+
+The ARM CPU topology is defined within the cpu-map node, which is a direct
+child of the cpus node and provides a container where the actual topology
+nodes are listed.
+
+- cpu-map node
+
+	Usage: Optional - On ARM SMP systems provide CPUs topology to the OS.
+			  ARM uniprocessor systems do not require a topology
+			  description and therefore should not define a
+			  cpu-map node.
+
+	Description: The cpu-map node is just a container node where its
+		     subnodes describe the CPU topology.
+
+	Node name must be "cpu-map".
+
+	The cpu-map node's parent node must be the cpus node.
+
+	The cpu-map node's child nodes can be:
+
+	- one or more cluster nodes
+
+	Any other configuration is considered invalid.
+
+The cpu-map node can only contain three types of child nodes:
+
+- cluster node
+- core node
+- thread node
+
+whose bindings are described in paragraph 3.
+
+The nodes describing the CPU topology (cluster/core/thread) can only be
+defined within the cpu-map node.
+Any other configuration is consider invalid and therefore must be ignored.
+
+===========================================
+2.1 - cpu-map child nodes naming convention
+===========================================
+
+cpu-map child nodes must follow a naming convention where the node name
+must be "clusterN", "coreN", "threadN" depending on the node type (ie
+cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes which
+are siblings within a single common parent node must be given a unique and
+sequential N value, starting from 0).
+cpu-map child nodes which do not share a common parent node can have the same
+name (ie same number N as other cpu-map child nodes at different device tree
+levels) since name uniqueness will be guaranteed by the device tree hierarchy.
+
+===========================================
+3 - cluster/core/thread node bindings
+===========================================
+
+Bindings for cluster/cpu/thread nodes are defined as follows:
+
+- cluster node
+
+	 Description: must be declared within a cpu-map node, one node
+		      per cluster. A system can contain several layers of
+		      clustering and cluster nodes can be contained in parent
+		      cluster nodes.
+
+	The cluster node name must be "clusterN" as described in 2.1 above.
+	A cluster node can not be a leaf node.
+
+	A cluster node's child nodes must be:
+
+	- one or more cluster nodes; or
+	- one or more core nodes
+
+	Any other configuration is considered invalid.
+
+- core node
+
+	Description: must be declared in a cluster node, one node per core in
+		     the cluster. If the system does not support SMT, core
+		     nodes are leaf nodes, otherwise they become containers of
+		     thread nodes.
+
+	The core node name must be "coreN" as described in 2.1 above.
+
+	A core node must be a leaf node if SMT is not supported.
+
+	Properties for core nodes that are leaf nodes:
+
+	- cpu
+		Usage: required
+		Value type: <phandle>
+		Definition: a phandle to the cpu node that corresponds to the
+			    core node.
+
+	If a core node is not a leaf node (CPUs supporting SMT) a core node's
+	child nodes can be:
+
+	- one or more thread nodes
+
+	Any other configuration is considered invalid.
+
+- thread node
+
+	Description: must be declared in a core node, one node per thread
+		     in the core if the system supports SMT. Thread nodes are
+		     always leaf nodes in the device tree.
+
+	The thread node name must be "threadN" as described in 2.1 above.
+
+	A thread node must be a leaf node.
+
+	A thread node must contain the following property:
+
+	- cpu
+		Usage: required
+		Value type: <phandle>
+		Definition: a phandle to the cpu node that corresponds to
+			    the thread node.
+
+===========================================
+4 - Example dts
+===========================================
+
+Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <2>;
+
+	cpu-map {
+		cluster0 {
+			cluster0 {
+				core0 {
+					thread0 {
+						cpu = <&CPU0>;
+					};
+					thread1 {
+						cpu = <&CPU1>;
+					};
+				};
+
+				core1 {
+					thread0 {
+						cpu = <&CPU2>;
+					};
+					thread1 {
+						cpu = <&CPU3>;
+					};
+				};
+			};
+
+			cluster1 {
+				core0 {
+					thread0 {
+						cpu = <&CPU4>;
+					};
+					thread1 {
+						cpu = <&CPU5>;
+					};
+				};
+
+				core1 {
+					thread0 {
+						cpu = <&CPU6>;
+					};
+					thread1 {
+						cpu = <&CPU7>;
+					};
+				};
+			};
+		};
+
+		cluster1 {
+			cluster0 {
+				core0 {
+					thread0 {
+						cpu = <&CPU8>;
+					};
+					thread1 {
+						cpu = <&CPU9>;
+					};
+				};
+				core1 {
+					thread0 {
+						cpu = <&CPU10>;
+					};
+					thread1 {
+						cpu = <&CPU11>;
+					};
+				};
+			};
+
+			cluster1 {
+				core0 {
+					thread0 {
+						cpu = <&CPU12>;
+					};
+					thread1 {
+						cpu = <&CPU13>;
+					};
+				};
+				core1 {
+					thread0 {
+						cpu = <&CPU14>;
+					};
+					thread1 {
+						cpu = <&CPU15>;
+					};
+				};
+			};
+		};
+	};
+
+	CPU0: cpu@0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x0>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU1: cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x1>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU2: cpu@100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU3: cpu@101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU4: cpu@10000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10000>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU5: cpu@10001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10001>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU6: cpu@10100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU7: cpu@10101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU8: cpu@100000000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x0>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU9: cpu@100000001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x1>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU10: cpu@100000100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU11: cpu@100000101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU12: cpu@100010000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10000>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU13: cpu@100010001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10001>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU14: cpu@100010100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	CPU15: cpu@100010101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+};
+
+Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <1>;
+
+	cpu-map {
+		cluster0 {
+			core0 {
+				cpu = <&CPU0>;
+			};
+			core1 {
+				cpu = <&CPU1>;
+			};
+			core2 {
+				cpu = <&CPU2>;
+			};
+			core3 {
+				cpu = <&CPU3>;
+			};
+		};
+
+		cluster1 {
+			core0 {
+				cpu = <&CPU4>;
+			};
+			core1 {
+				cpu = <&CPU5>;
+			};
+			core2 {
+				cpu = <&CPU6>;
+			};
+			core3 {
+				cpu = <&CPU7>;
+			};
+		};
+	};
+
+	CPU0: cpu@0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a15";
+		reg = <0x0>;
+	};
+
+	CPU1: cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a15";
+		reg = <0x1>;
+	};
+
+	CPU2: cpu@2 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a15";
+		reg = <0x2>;
+	};
+
+	CPU3: cpu@3 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a15";
+		reg = <0x3>;
+	};
+
+	CPU4: cpu@100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x100>;
+	};
+
+	CPU5: cpu@101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x101>;
+	};
+
+	CPU6: cpu@102 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x102>;
+	};
+
+	CPU7: cpu@103 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x103>;
+	};
+};
+
+===============================================================================
+[1] ARM Linux kernel documentation
+    Documentation/devicetree/bindings/arm/cpus.txt
-- 
1.8.2.2


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Re: [PATCH v2 0/2] ARM DT cpus/cpu and topology bindings

[Lorenzo Pieralisi]

[replying to self]

Any further comments on this series ? If not, I think bindings are ready to be
queued, but for that I need acks from DT maintainers.

The issue with in kernel dts that (re)-need patching owing to re-introduction
of reg property on pre-v7 UP is still pending.

Please advise, thank you very much,
Lorenzo

On Mon, Sep 16, 2013 at 12:21:02PM +0100, Lorenzo Pieralisi wrote:
> This is v2 of a previous posting:
> 
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-August/192322.html
> 
> - v2 changes
> 	- Removed single core cpu-map example
> 	- Removed OS dependency from cpus/cpu bindings
> 	- Updated Marvell compatible strings
> 	- Clarified behaviour on pre ARM v7 uniprocessor systems and updated
> 	  examples
> 
> This patch resumes DT topology/cpu bindings discussions for ARM that were
> started here:
> 
> https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/031725.html
> https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/032450.html
> 
> Comments welcome, thanks,
> Lorenzo
> 
> Lorenzo Pieralisi (2):
>   Documentation: devicetree: arm: cpus/cpu nodes bindings updates
>   Documentation: DT: arm: define CPU topology bindings
> 
>  Documentation/devicetree/bindings/arm/cpus.txt     | 391 +++++++++++++++--
>  Documentation/devicetree/bindings/arm/topology.txt | 474 +++++++++++++++++++++
>  2 files changed, 818 insertions(+), 47 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/topology.txt
> 
> -- 
> 1.8.2.2
> 

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Re: [PATCH v2 0/2] ARM DT cpus/cpu and topology bindings

[Rob Herring]

On 09/24/2013 11:01 AM, Lorenzo Pieralisi wrote:
> [replying to self]
> 
> Any further comments on this series ? If not, I think bindings are ready to be
> queued, but for that I need acks from DT maintainers.

Who do you plan to take this? Is this dependent on something for 3.13?
If not, I'll apply it.

Rob

> The issue with in kernel dts that (re)-need patching owing to re-introduction
> of reg property on pre-v7 UP is still pending.
> 
> Please advise, thank you very much,
> Lorenzo
> 
> On Mon, Sep 16, 2013 at 12:21:02PM +0100, Lorenzo Pieralisi wrote:
>> This is v2 of a previous posting:
>>
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-August/192322.html
>>
>> - v2 changes
>> 	- Removed single core cpu-map example
>> 	- Removed OS dependency from cpus/cpu bindings
>> 	- Updated Marvell compatible strings
>> 	- Clarified behaviour on pre ARM v7 uniprocessor systems and updated
>> 	  examples
>>
>> This patch resumes DT topology/cpu bindings discussions for ARM that were
>> started here:
>>
>> https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/031725.html
>> https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/032450.html
>>
>> Comments welcome, thanks,
>> Lorenzo
>>
>> Lorenzo Pieralisi (2):
>>   Documentation: devicetree: arm: cpus/cpu nodes bindings updates
>>   Documentation: DT: arm: define CPU topology bindings
>>
>>  Documentation/devicetree/bindings/arm/cpus.txt     | 391 +++++++++++++++--
>>  Documentation/devicetree/bindings/arm/topology.txt | 474 +++++++++++++++++++++
>>  2 files changed, 818 insertions(+), 47 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/arm/topology.txt
>>
>> -- 
>> 1.8.2.2
>>
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

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Re: [PATCH v2 0/2] ARM DT cpus/cpu and topology bindings

[Lorenzo Pieralisi]

On Wed, Sep 25, 2013 at 02:50:38PM +0100, Rob Herring wrote:
> On 09/24/2013 11:01 AM, Lorenzo Pieralisi wrote:
> > [replying to self]
> > 
> > Any further comments on this series ? If not, I think bindings are ready to be
> > queued, but for that I need acks from DT maintainers.
> 
> Who do you plan to take this? Is this dependent on something for 3.13?
> If not, I'll apply it.

v3 on the lists, should be final. No, there are no dependencies on 3.13
to the best of my knowledge. The problem with pre-v7 UP systems with
cpus node #address-cells == 0 is still there and I would like to ask you
please what we/I should do about that, it can trigger a considerable
amount of churn. As soon as these bindings hit the mainline I will
update the DT parsing code, I can easily take all pre-v7 UP dts out
of the picture in the parsing loop (after all, reg property for those
processors is useless), but the dts are _wrong_ regardless when these
patches become the official bindings.

Thanks !
Lorenzo

> 
> Rob
> 
> > The issue with in kernel dts that (re)-need patching owing to re-introduction
> > of reg property on pre-v7 UP is still pending.
> > 
> > Please advise, thank you very much,
> > Lorenzo
> > 
> > On Mon, Sep 16, 2013 at 12:21:02PM +0100, Lorenzo Pieralisi wrote:
> >> This is v2 of a previous posting:
> >>
> >> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-August/192322.html
> >>
> >> - v2 changes
> >> 	- Removed single core cpu-map example
> >> 	- Removed OS dependency from cpus/cpu bindings
> >> 	- Updated Marvell compatible strings
> >> 	- Clarified behaviour on pre ARM v7 uniprocessor systems and updated
> >> 	  examples
> >>
> >> This patch resumes DT topology/cpu bindings discussions for ARM that were
> >> started here:
> >>
> >> https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/031725.html
> >> https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/032450.html
> >>
> >> Comments welcome, thanks,
> >> Lorenzo
> >>
> >> Lorenzo Pieralisi (2):
> >>   Documentation: devicetree: arm: cpus/cpu nodes bindings updates
> >>   Documentation: DT: arm: define CPU topology bindings
> >>
> >>  Documentation/devicetree/bindings/arm/cpus.txt     | 391 +++++++++++++++--
> >>  Documentation/devicetree/bindings/arm/topology.txt | 474 +++++++++++++++++++++
> >>  2 files changed, 818 insertions(+), 47 deletions(-)
> >>  create mode 100644 Documentation/devicetree/bindings/arm/topology.txt
> >>
> >> -- 
> >> 1.8.2.2
> >>
> > 
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 
> 
> 

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Re: [PATCH v2 0/2] ARM DT cpus/cpu and topology bindings

[Rob Herring]

On 09/26/2013 05:02 AM, Lorenzo Pieralisi wrote:
> On Wed, Sep 25, 2013 at 02:50:38PM +0100, Rob Herring wrote:
>> On 09/24/2013 11:01 AM, Lorenzo Pieralisi wrote:
>>> [replying to self]
>>>
>>> Any further comments on this series ? If not, I think bindings are ready to be
>>> queued, but for that I need acks from DT maintainers.
>>
>> Who do you plan to take this? Is this dependent on something for 3.13?
>> If not, I'll apply it.
> 
> v3 on the lists, should be final. No, there are no dependencies on 3.13
> to the best of my knowledge. The problem with pre-v7 UP systems with
> cpus node #address-cells == 0 is still there and I would like to ask you
> please what we/I should do about that, it can trigger a considerable
> amount of churn. As soon as these bindings hit the mainline I will
> update the DT parsing code, I can easily take all pre-v7 UP dts out
> of the picture in the parsing loop (after all, reg property for those
> processors is useless), but the dts are _wrong_ regardless when these
> patches become the official bindings.

Given that this is really a don't care for the kernel, I'm not sure what
kernel change you are thinking. It is not the kernel's job to validate
the dtb, so I think the kernel should not care. We should do this sort
of validation at dtb build time at the latest. As to updating the dts
files, yes we should probably do that.

Rob

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Re: [PATCH v2 0/2] ARM DT cpus/cpu and topology bindings

[Lorenzo Pieralisi]

On Thu, Sep 26, 2013 at 10:42:28PM +0100, Rob Herring wrote:
> On 09/26/2013 05:02 AM, Lorenzo Pieralisi wrote:
> > On Wed, Sep 25, 2013 at 02:50:38PM +0100, Rob Herring wrote:
> >> On 09/24/2013 11:01 AM, Lorenzo Pieralisi wrote:
> >>> [replying to self]
> >>>
> >>> Any further comments on this series ? If not, I think bindings are ready to be
> >>> queued, but for that I need acks from DT maintainers.
> >>
> >> Who do you plan to take this? Is this dependent on something for 3.13?
> >> If not, I'll apply it.
> > 
> > v3 on the lists, should be final. No, there are no dependencies on 3.13
> > to the best of my knowledge. The problem with pre-v7 UP systems with
> > cpus node #address-cells == 0 is still there and I would like to ask you
> > please what we/I should do about that, it can trigger a considerable
> > amount of churn. As soon as these bindings hit the mainline I will
> > update the DT parsing code, I can easily take all pre-v7 UP dts out
> > of the picture in the parsing loop (after all, reg property for those
> > processors is useless), but the dts are _wrong_ regardless when these
> > patches become the official bindings.
> 
> Given that this is really a don't care for the kernel, I'm not sure what
> kernel change you are thinking. It is not the kernel's job to validate
> the dtb, so I think the kernel should not care. We should do this sort
> of validation at dtb build time at the latest. As to updating the dts
> files, yes we should probably do that.

I would like to change the DT parsing loop to improve it (eg now it bails
out as soon as a cpu node does not contain a reg property), not to
change the MPIDR checks related to these new bindings. In short,
kernel changes are not related to these bindings. I will make sure that the
changes will sit in -next for a while to prevent any issues; I understand
your reticence, I will tread more carefully this time.

As to updating the dts files, I am not looking forward to it at all :D,
I would kindly ask platform maintainers to do it, but only when these
bindings get merged in the kernel.

Having said that, if you do not have any objection I would ask you please to
apply v3:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-September/200531.html
or I can send you a pull request for that, as you wish.

Thank you very much,
Lorenzo

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