Re: [PATCH v4 5/8] soc: mediatek: mtk-cmdq: Add mminfra_offset compatibility for DRAM address

AngeloGioacchino Del Regno
2025-03-04T09:37:23Z

Il 18/02/25 06:41, Jason-JH Lin ha scritto:
> Since GCE has been moved to mminfra in MT8196, all transactions from
> mminfra to DRAM will have their addresses adjusted by subtracting a
> mminfra offset.
> This information should be handled inside the CMDQ driver, allowing
> CMDQ users to call CMDQ APIs as usual.
>
> Therefore, CMDQ driver needs to use the mbox API to get the
> mminfra_offset value of the SoC, and then add it to the DRAM address
> when generating instructions to ensure GCE accesses the correct DRAM
> address.
>
> Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 35 ++++++++++++++++++++++++--
> 1 file changed, 33 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index aa9853100d78..f2853a74af01 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -314,10 +314,22 @@ EXPORT_SYMBOL(cmdq_pkt_write_s_mask_value);
>
> int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_addr)
> {
> + struct cmdq_client *cl = (struct cmdq_client *)pkt->cl;
> const u16 high_addr_reg_idx = CMDQ_THR_SPR_IDX0;
> const u16 value_reg_idx = CMDQ_THR_SPR_IDX1;
> int ret;
>
> + if (!cl) {
> + pr_err("%s %d: pkt->cl is NULL!\n", __func__, __LINE__);
> + return -EINVAL;
> + }
> +
> + if (cmdq_addr_need_offset(cl->chan, src_addr))
> + src_addr += cmdq_get_offset_pa(cl->chan);

If the offset is just DRAM IOSTART, you could manage that differently in the cmdq
helper as well as the cmdq mailbox... :-)

> +
> + if (cmdq_addr_need_offset(cl->chan, dst_addr))
> + dst_addr += cmdq_get_offset_pa(cl->chan);
> +
Cheers,
Angelo