From mboxrd@z Thu Jan 1 00:00:00 1970 From: James Hogan Subject: Re: [PATCH] clk: add specified-rate clock Date: Wed, 13 Nov 2013 14:31:25 +0000 Message-ID: <52838D3D.6060007@imgtec.com> References: <1368189862-17119-1-git-send-email-james.hogan@imgtec.com> <20130529173938.6058.96646@quantum> <52838834.4010104@imgtec.com> <5867382.IN2EZ2ivg4@flatron> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <5867382.IN2EZ2ivg4@flatron> Sender: linux-doc-owner@vger.kernel.org To: Tomasz Figa Cc: linux-arm-kernel@lists.infradead.org, Mike Turquette , "devicetree@vger.kernel.org" , Lars-Peter Clausen , Arnd Bergmann , linux-doc@vger.kernel.org, Linus Walleij , Mark Brown , linux-kernel@vger.kernel.org, Rob Herring , Grant Likely , Rob Landley , linux-metag List-Id: devicetree@vger.kernel.org On 13/11/13 14:18, Tomasz Figa wrote: > Hi James, Mike, > > On Wednesday 13 of November 2013 14:09:56 James Hogan wrote: >> On 29/05/13 18:39, Mike Turquette wrote: >>> Quoting James Hogan (2013-05-10 05:44:22) >>>> The frequency of some SoC's external oscillators (for example TZ1090's >>>> XTAL1) are configured by the board using pull-ups/pull-downs of >>>> configuration pins, the logic values of which are automatically latched >>>> on reset and available in an SoC register. Add a generic clock component >>>> and DT bindings to handle this. >>>> >>>> It behaves similar to a fixed rate clock (read-only), except it needs >>>> information about a register field (reg, shift, width), and the >>>> clock-frequency is a mapping from register field values to clock >>>> frequencies. >>>> >>> >>> James, >>> >>> Thanks for sending this! It looks mostly good and is a useful clock >>> type to support. Comments below. >> >> Hi Mike, >> >> Sorry for slight delay getting back to you. I had another think about >> this stuff yesterday... >> > > Just a random idea that came to my mind while reading this thread: > > What about modelling this as a set of fixed rate clocks fed into > a read-only mux? Yes, that had occurred to me too. I suppose the arguments against would be: * it doesn't describe the hardware, there is no mux, just a fixed rate clock with a discoverable frequency. * it would sort of work for my small case of only having 9 possible frequencies (although it would be a bit verbose), but wouldn't scale nicely or be extendible to if the frequency was encoded more continuously in the register value. E.g. if the frequency was 1MHz * (the register value - 1) or something crazy like that. Of course that's conjecture and SoC designers probably aren't going to want to use more pins for bootstrap config than necessary. Cheers James