[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

This series implements a common reset framework driver for Tegra, and
updates all relevant Tegra drivers to use it. It also removes the custom
DMA bindings and replaced them with the standard DMA DT bindings.

Historically, the Tegra clock driver has exported a custom API for module
reset. This series removes that API, and transitions DT and drivers to
the new reset framework.

The custom API used a "struct clk" to identify which module to reset, and
consequently some DT bindings and drivers required clocks to be provided
where they really needed just a reset identifier instead. Due to this
known deficiency, I have always considered most Tegra bindings to be
unstable. This series removes this excuse for instability, although I
still consider some Tegra bindings unstable due to the need to convert to
the common DMA bindings.

Historically, Tegra DMA channels have been represented in DT using a
custom nvidia,dma-request-selector property. Now that standard DMA DT
bindings exist, convert all Tegra bindings, DTs, and drivers to use the
standard instead.

This series makes a DT-ABI-incompatible change to:
- Require reset specifiers in DT where relevant.
- Require standard DMA specifiers.
- Remove clock specifiers from DT where they were only needed for reset.
- Remove legacy DMA specifier properties.

I anticipate merging this whole series into the Tegra and arm-soc trees
as its own branch, due to internal dependencies. This branch will be
stable and can then be merged into any other subsystem trees should any
conflicts arise.

This series depends on Peter's Tegra clock driver rework, available at
git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-tegra124-0
(or whatever version of that gets included in 3.14)

Cc: ac100@lists.launchpad.net
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: alsa-devel@alsa-project.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: devel@driverdev.osuosl.org
Cc: devicetree@vger.kernel.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Dmitry Torokhov <dtor@mail.ru>
Cc: dri-devel@lists.freedesktop.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Julian Andres Klode <jak@jak-linux.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-input@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-serial@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Cc: Marc Dietrich <marvin24@gmx.de>
Cc: Mark Brown <broonie@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: pdeschrijver@nvidia.com
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Terje Bergström <tbergstrom@nvidia.com>
Cc: treding@nvidia.com
Cc: Wolfram Sang <wsa@the-dreams.de>

Stephen Warren (31):
  ARM: tegra: add missing clock documentation to DT bindings
  ARM: tegra: document reset properties in DT bindings
  ARM: tegra: document use of standard DMA DT bindings
  ARM: tegra: update DT files to add reset properties
  ARM: tegra: update DT files to add DMA properties
  ARM: tegra: select the reset framework
  clk: tegra: implement a reset driver
  pci: tegra: use reset framework
  drm/tegra: use reset framework
  ARM: tegra: pass reset to tegra_powergate_sequence_power_up()
  dma: add channel request API that supports deferred probe
  dma: tegra: use reset framework
  dma: tegra: register as an OF DMA controller
  ASoC: dmaengine: support deferred probe for DMA channels
  ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config
  ASoC: tegra: use reset framework
  ASoC: tegra: call pm_runtime APIs around register accesses
  ASoC: tegra: allocate AHUB FIFO during probe() not startup()
  ASoC: tegra: convert to standard DMA DT bindings
  i2c: tegra: use reset framework
  staging: nvec: use reset framework
  spi: tegra: use reset framework
  spi: tegra: convert to standard DMA DT bindings
  serial: tegra: use reset framework
  serial: tegra: convert to standard DMA DT bindings
  Input: tegra-kbc - use reset framework
  USB: EHCI: tegra: use reset framework
  ARM: tegra: remove legacy clock entries from DT
  ARM: tegra: remove legacy DMA entries from DT
  clk: tegra: remove legacy reset APIs
  clk: tegra: remove bogus PCIE_XCLK

 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |   1 +
 .../bindings/clock/nvidia,tegra114-car.txt         |   4 +
 .../bindings/clock/nvidia,tegra124-car.txt         |   4 +
 .../bindings/clock/nvidia,tegra20-car.txt          |   4 +
 .../bindings/clock/nvidia,tegra30-car.txt          |   4 +
 .../devicetree/bindings/dma/tegra20-apbdma.txt     |   9 ++
 .../bindings/gpu/nvidia,tegra20-host1x.txt         | 124 +++++++++++++++
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |  27 +++-
 .../bindings/input/nvidia,tegra20-kbc.txt          |   9 ++
 .../bindings/mmc/nvidia,tegra20-sdhci.txt          |   9 ++
 .../devicetree/bindings/nvec/nvidia,nvec.txt       |  12 ++
 .../bindings/pci/nvidia,tegra20-pcie.txt           |  28 ++--
 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |   9 ++
 .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt |   3 +
 .../bindings/serial/nvidia,tegra20-hsuart.txt      |  19 ++-
 .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |   7 +-
 .../bindings/sound/nvidia,tegra-audio-rt5640.txt   |   7 +-
 .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |   7 +-
 .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |   7 +-
 .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |   7 +-
 .../bindings/sound/nvidia,tegra20-ac97.txt         |  20 ++-
 .../bindings/sound/nvidia,tegra20-i2s.txt          |  19 ++-
 .../bindings/sound/nvidia,tegra30-ahub.txt         |  54 +++++--
 .../bindings/sound/nvidia,tegra30-i2s.txt          |  11 +-
 .../bindings/spi/nvidia,tegra114-spi.txt           |  24 ++-
 .../bindings/spi/nvidia,tegra20-sflash.txt         |  20 ++-
 .../bindings/spi/nvidia,tegra20-slink.txt          |  20 ++-
 .../bindings/timer/nvidia,tegra20-timer.txt        |   3 +
 .../bindings/timer/nvidia,tegra30-timer.txt        |   3 +
 .../bindings/usb/nvidia,tegra20-ehci.txt           |   7 +-
 arch/arm/boot/dts/tegra114.dtsi                    | 142 ++++++++++++++---
 arch/arm/boot/dts/tegra20-paz00.dts                |   2 +
 arch/arm/boot/dts/tegra20.dtsi                     | 132 ++++++++++++++--
 arch/arm/boot/dts/tegra30.dtsi                     | 171 +++++++++++++++++----
 arch/arm/mach-tegra/Kconfig                        |   2 +
 arch/arm/mach-tegra/powergate.c                    |   8 +-
 drivers/clk/tegra/clk-periph-gate.c                |  22 ---
 drivers/clk/tegra/clk-periph.c                     |  40 -----
 drivers/clk/tegra/clk-tegra114.c                   |   3 +-
 drivers/clk/tegra/clk-tegra124.c                   |   2 +-
 drivers/clk/tegra/clk-tegra20.c                    |   9 +-
 drivers/clk/tegra/clk-tegra30.c                    |  10 +-
 drivers/clk/tegra/clk.c                            |  55 ++++++-
 drivers/clk/tegra/clk.h                            |   3 +-
 drivers/dma/acpi-dma.c                             |  12 +-
 drivers/dma/dmaengine.c                            |  44 +++++-
 drivers/dma/of-dma.c                               |  12 +-
 drivers/dma/tegra20-apb-dma.c                      |  49 +++++-
 drivers/gpu/drm/tegra/Kconfig                      |   1 +
 drivers/gpu/drm/tegra/dc.c                         |   9 +-
 drivers/gpu/drm/tegra/drm.h                        |   3 +
 drivers/gpu/drm/tegra/gr3d.c                       |  22 ++-
 drivers/gpu/drm/tegra/hdmi.c                       |  14 +-
 drivers/i2c/busses/i2c-tegra.c                     |  13 +-
 drivers/input/keyboard/tegra-kbc.c                 |  13 +-
 drivers/pci/host/pci-tegra.c                       |  52 +++++--
 drivers/spi/Kconfig                                |   3 +
 drivers/spi/spi-tegra114.c                         |  66 ++++----
 drivers/spi/spi-tegra20-sflash.c                   |  18 ++-
 drivers/spi/spi-tegra20-slink.c                    |  66 ++++----
 drivers/staging/nvec/nvec.c                        |  11 +-
 drivers/staging/nvec/nvec.h                        |   5 +-
 drivers/tty/serial/serial-tegra.c                  |  86 +++++------
 drivers/usb/host/ehci-tegra.c                      |  14 +-
 include/dt-bindings/clock/tegra20-car.h            |   2 +-
 include/dt-bindings/clock/tegra30-car.h            |   2 +-
 include/linux/clk/tegra.h                          |   7 -
 include/linux/dmaengine.h                          |   7 +
 include/linux/of_dma.h                             |   9 +-
 include/linux/tegra-powergate.h                    |   4 +-
 include/sound/dmaengine_pcm.h                      |   6 +
 sound/soc/soc-generic-dmaengine-pcm.c              |  82 +++++++---
 sound/soc/tegra/Kconfig                            |   2 +
 sound/soc/tegra/tegra20_ac97.c                     |  11 --
 sound/soc/tegra/tegra20_i2s.c                      |  20 +--
 sound/soc/tegra/tegra30_ahub.c                     | 125 +++++++++------
 sound/soc/tegra/tegra30_ahub.h                     |  11 +-
 sound/soc/tegra/tegra30_i2s.c                      |  97 ++++++------
 sound/soc/tegra/tegra30_i2s.h                      |   3 +
 sound/soc/tegra/tegra_pcm.c                        |  17 +-
 sound/soc/tegra/tegra_pcm.h                        |   5 +
 81 files changed, 1448 insertions(+), 558 deletions(-)

-- 
1.8.1.5


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[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Many of the Tegra DT binding documents say nothing about the clocks or
clock-names properties, yet those are present and required in DT files.
This patch simply updates the documentation file to match the implicit
definition of the binding, based on real-world DT content.

All Tegra bindings that mention clocks are updated to have consistent
wording and formatting of the clock-related properties.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  1 +
 .../devicetree/bindings/dma/tegra20-apbdma.txt     |  3 ++
 .../bindings/gpu/nvidia,tegra20-host1x.txt         | 61 ++++++++++++++++++++++
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 14 ++---
 .../bindings/input/nvidia,tegra20-kbc.txt          |  3 ++
 .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  3 ++
 .../devicetree/bindings/nvec/nvidia,nvec.txt       |  8 +++
 .../bindings/pci/nvidia,tegra20-pcie.txt           | 16 +++---
 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |  3 ++
 .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt |  3 ++
 .../bindings/serial/nvidia,tegra20-hsuart.txt      |  3 ++
 .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |  7 +--
 .../bindings/sound/nvidia,tegra-audio-rt5640.txt   |  7 +--
 .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |  7 +--
 .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |  7 +--
 .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |  7 +--
 .../bindings/sound/nvidia,tegra20-ac97.txt         |  4 ++
 .../bindings/sound/nvidia,tegra20-i2s.txt          |  3 ++
 .../bindings/sound/nvidia,tegra30-ahub.txt         | 21 ++++++--
 .../bindings/sound/nvidia,tegra30-i2s.txt          |  5 +-
 .../bindings/spi/nvidia,tegra114-spi.txt           |  8 ++-
 .../bindings/spi/nvidia,tegra20-sflash.txt         |  4 +-
 .../bindings/spi/nvidia,tegra20-slink.txt          |  4 +-
 .../bindings/timer/nvidia,tegra20-timer.txt        |  3 ++
 .../bindings/timer/nvidia,tegra30-timer.txt        |  3 ++
 .../bindings/usb/nvidia,tegra20-ehci.txt           |  3 +-
 26 files changed, 172 insertions(+), 39 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index 1608a54e90e1..68ac65f82a1c 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -9,6 +9,7 @@ Required properties:
 - compatible : Should contain "nvidia,tegra<chip>-pmc".
 - reg : Offset and length of the register set for the device
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
   "pclk" (The Tegra clock of that name),
   "clk32k_in" (The 32KHz clock input to Tegra).
diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
index 90fa7da525b8..74bfc54bb184 100644
--- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
+++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
@@ -5,6 +5,8 @@ Required properties:
 - reg: Should contain DMA registers location and length. This shuld include
   all of the per-channel registers.
 - interrupts: Should contain all of the per-channel DMA interrupts.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Examples:
 
@@ -27,4 +29,5 @@ apbdma: dma@6000a000 {
 		       0 149 0x04
 		       0 150 0x04
 		       0 151 0x04 >;
+	clocks = <&tegra_car 34>;
 };
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index b4fa934ae3a2..c9a715a75f60 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -9,6 +9,8 @@ Required properties:
 - #size-cells: The number of cells used to represent the size of an address
   range in the host1x address space. Should be 1.
 - ranges: The mapping of the host1x address space to the CPU address space.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 The host1x top-level node defines a number of children, each representing one
 of the following host1x client modules:
@@ -19,6 +21,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-mpe"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - vi: video input
 
@@ -26,6 +30,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-vi"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - epp: encoder pre-processor
 
@@ -33,6 +39,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-epp"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - isp: image signal processor
 
@@ -40,6 +48,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-isp"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - gr2d: 2D graphics engine
 
@@ -47,12 +57,23 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-gr2d"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - gr3d: 3D graphics engine
 
   Required properties:
   - compatible: "nvidia,tegra<chip>-gr3d"
   - reg: Physical base address and length of the controller's registers.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    (This property may be omitted if the only clock in the list is "3d")
+    - 3d
+      This MUST be the first entry.
+    - 3d2 (Only required on SoCs with two 3D clocks)
 
 - dc: display controller
 
@@ -60,6 +81,12 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-dc"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    - disp1 or disp2 (depending on the controller instance)
+      This MUST be the first entry.
+    - parent
 
   Each display controller node has a child node, named "rgb", that represents
   the RGB output associated with the controller. It can take the following
@@ -76,6 +103,12 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - vdd-supply: regulator for supply voltage
   - pll-supply: regulator for PLL
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    - hdmi
+      This MUST be the first entry.
+    - parent
 
   Optional properties:
   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
@@ -88,12 +121,22 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-tvo"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - dsi: display serial interface
 
   Required properties:
   - compatible: "nvidia,tegra<chip>-dsi"
   - reg: Physical base address and length of the controller's registers.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    - dsi
+      This MUST be the first entry.
+    - parent
 
 Example:
 
@@ -105,6 +148,7 @@ Example:
 		reg = <0x50000000 0x00024000>;
 		interrupts = <0 65 0x04   /* mpcore syncpt */
 			      0 67 0x04>; /* mpcore general */
+		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -115,41 +159,50 @@ Example:
 			compatible = "nvidia,tegra20-mpe";
 			reg = <0x54040000 0x00040000>;
 			interrupts = <0 68 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_MPE>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra20-vi";
 			reg = <0x54080000 0x00040000>;
 			interrupts = <0 69 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_VI>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra20-epp";
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <0 70 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_EPP>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra20-isp";
 			reg = <0x54100000 0x00040000>;
 			interrupts = <0 71 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_ISP>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra20-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <0 72 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
+			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
 		};
 
 		dc@54200000 {
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <0 73 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>;
+			clock-names = "disp1", "parent";
 
 			rgb {
 				status = "disabled";
@@ -160,6 +213,9 @@ Example:
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54240000 0x00040000>;
 			interrupts = <0 74 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>;
+			clock-names = "disp2", "parent";
 
 			rgb {
 				status = "disabled";
@@ -170,6 +226,9 @@ Example:
 			compatible = "nvidia,tegra20-hdmi";
 			reg = <0x54280000 0x00040000>;
 			interrupts = <0 75 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+			clock-names = "hdmi", "parent";
 			status = "disabled";
 		};
 
@@ -177,12 +236,14 @@ Example:
 			compatible = "nvidia,tegra20-tvo";
 			reg = <0x542c0000 0x00040000>;
 			interrupts = <0 76 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_TVO>;
 			status = "disabled";
 		};
 
 		dsi {
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
+			clocks = <&tegra_car TEGRA20_CLK_DSI>;
 			status = "disabled";
 		};
 	};
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index ef77cc7a0e46..96ab40131ae1 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -39,12 +39,14 @@ Required properties:
 - interrupts: Should contain I2C controller interrupts.
 - address-cells: Address cells for I2C device address.
 - size-cells: Size of the I2C device address.
-- clocks: Clock ID as per
-		Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
-	for I2C controller.
-- clock-names: Name of the clock:
-	Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
-	Tegra114 I2C controller: "div-clk".
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  Tegra20/Tegra30:
+  - div-clk
+  - fast-clk
+  Tegra114:
+  - div-clk
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
index 2995fae7ee47..cc28d2194c37 100644
--- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
@@ -13,6 +13,8 @@ Required properties:
   array of pin numbers which is used as column.
 - linux,keymap: The keymap for keys as described in the binding document
   devicetree/bindings/input/matrix-keymap.txt.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Optional properties, in addition to those specified by the shared
 matrix-keyboard bindings:
@@ -31,6 +33,7 @@ keyboard: keyboard {
 	compatible = "nvidia,tegra20-kbc";
 	reg = <0x7000e200 0x100>;
 	interrupts = <0 85 0x04>;
+	clocks = <&tegra_car 36>;
 	nvidia,ghost-filter;
 	nvidia,debounce-delay-ms = <640>;
 	nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index c6d7b11db9eb..f727902a9e8d 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -8,6 +8,8 @@ by mmc.txt and the properties used by the sdhci-tegra driver.
 
 Required properties:
 - compatible : Should be "nvidia,<chip>-sdhci"
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Optional properties:
 - power-gpios : Specify GPIOs for power control
@@ -18,6 +20,7 @@ sdhci@c8000200 {
 	compatible = "nvidia,tegra20-sdhci";
 	reg = <0xc8000200 0x200>;
 	interrupts = <47>;
+	clocks = <&tegra_car 14>;
 	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 	power-gpios = <&gpio 155 0>; /* gpio PT3 */
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
index 5aeee53ff9f4..a97fe575ca29 100644
--- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
+++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
@@ -7,3 +7,11 @@ Required properties:
 - clock-frequency : the frequency of the i2c bus
 - gpios : the gpio used for ec request
 - slave-addr: the i2c address of the slave controller
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  Tegra20/Tegra30:
+  - div-clk
+  - fast-clk
+  Tegra114:
+  - div-clk
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index 6b7510775c50..ad2eb9804afa 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -42,14 +42,14 @@ Required properties:
     - 0xc2000000: prefetchable memory region
   Please refer to the standard PCI bus binding document for a more detailed
   explanation.
-- clocks: List of clock inputs of the controller. Must contain an entry for
-  each entry in the clock-names property.
-- clock-names: Must include the following entries:
-  "pex": The Tegra clock of that name
-  "afi": The Tegra clock of that name
-  "pcie_xclk": The Tegra clock of that name
-  "pll_e": The Tegra clock of that name
-  "cml": The Tegra clock of that name (not required for Tegra20)
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - pex
+  - afi
+  - pcie_xclk
+  - pll_e
+  - cml (not required for Tegra20)
 
 Root ports are defined as subnodes of the PCIe controller node.
 
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index c3fc57af8772..0d608d34fed0 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -7,6 +7,8 @@ Required properties:
 - reg: physical base address and length of the controller's registers
 - #pwm-cells: should be 2. See pwm.txt in this directory for a description of
   the cells format.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -14,4 +16,5 @@ Example:
 		compatible = "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
+		clocks = <&tegra_car 17>;
 	};
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
index 93f45e9dce7c..652d1ff2e8be 100644
--- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
@@ -9,6 +9,8 @@ Required properties:
 - compatible : should be "nvidia,tegra20-rtc".
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A single interrupt specifier.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -16,4 +18,5 @@ timer {
 	compatible = "nvidia,tegra20-rtc";
 	reg = <0x7000e000 0x100>;
 	interrupts = <0 2 0x04>;
+	clocks = <&tegra_car 4>;
 };
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index 392a4493eebd..39148b6236a1 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -6,6 +6,8 @@ Required properties:
 - interrupts: Should contain UART controller interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this UART controller.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Optional properties:
 - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -20,5 +22,6 @@ serial@70006000 {
 	interrupts = <0 36 0x04>;
 	nvidia,dma-request-selector = <&apbdma 8>;
 	nvidia,enable-modem-interrupt;
+	clocks = <&tegra_car 6>;
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
index 8b8903ef0800..57f40f93453e 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-alc5632"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
index dc6224994d69..7788808dcd0b 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex, with RT5640 CODEC
 Required properties:
 - compatible : "nvidia,tegra-audio-rt5640"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
index aab6ce0ad2fc..96f6a57dd6b4 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-wm8753"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
index 4b44dfb6ca0d..b795d282818d 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-wm8903"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
index ad589b163639..436f6cd9d07c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-wm9712"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
index c1454979c1ef..37f4ebf5b184 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -4,12 +4,15 @@ Required properties:
 - compatible : "nvidia,tegra20-ac97"
 - reg : Should contain AC97 controller registers location and length
 - interrupts : Should contain AC97 interrupt
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for the AC97 controller
 - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
   of the GPIO used to reset the external AC97 codec
 - nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
   of the GPIO corresponding with the AC97 DAP _FS line
+
 Example:
 
 ac97@70002000 {
@@ -19,4 +22,5 @@ ac97@70002000 {
 	nvidia,dma-request-selector = <&apbdma 12>;
 	nvidia,codec-reset-gpio = <&gpio 170 0>;
 	nvidia,codec-sync-gpio = <&gpio 120 0>;
+	clocks = <&tegra_car 3>;
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
index 0df2b5c816e3..ba0c9452916d 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
@@ -4,6 +4,8 @@ Required properties:
 - compatible : "nvidia,tegra20-i2s"
 - reg : Should contain I2S registers location and length
 - interrupts : Should contain I2S interrupt
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this I2S controller
 
@@ -14,4 +16,5 @@ i2s@70002800 {
 	reg = <0x70002800 0x200>;
 	interrupts = < 45 >;
 	nvidia,dma-request-selector = < &apbdma 2 >;
+	clocks = <&tegra_car 11>;
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 0e5c12c66523..7299eeadd588 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -12,11 +12,24 @@ Required properties:
   If a single entry is present, the request selectors for the channels are
   assumed to be contiguous, and increment from this value.
   If multiple values are given, one value must be given per channel.
-- clocks : Must contain an entry for each required entry in clock-names.
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0,
-    dam1, dam2, spdif_in.
-  - Tegra114: Additionally requires amx, adx.
+  Tegra30 and later:
+  - d_audio
+  - apbif
+  - i2s0
+  - i2s1
+  - i2s2
+  - i2s3
+  - i2s4
+  - dam0
+  - dam1
+  - dam2
+  - spdif_in
+  Tegra114 and later additionally require:
+  - amx
+  - adx
 - ranges : The bus address mapping for the configlink register bus.
   Can be empty since the mapping is 1:1.
 - #address-cells : For the configlink bus. Should be <1>;
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
index dfa6c037124a..7a3112bc135c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
@@ -3,13 +3,16 @@ NVIDIA Tegra30 I2S controller
 Required properties:
 - compatible : "nvidia,tegra30-i2s"
 - reg : Should contain I2S registers location and length
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback)
   first, tx (capture) second. See nvidia,tegra30-ahub.txt for values.
 
 Example:
 
-i2s@70002800 {
+i2s@70080300 {
 	compatible = "nvidia,tegra30-i2s";
 	reg = <0x70080300 0x100>;
 	nvidia,ahub-cif-ids = <4 4>;
+	clocks = <&tegra_car 11>;
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
index 91ff771c7e77..d4f2d534934b 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
@@ -6,8 +6,10 @@ Required properties:
 - interrupts: Should contain SPI interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this SPI controller.
-- This is also require clock named "spi" as per binding document
-  Documentation/devicetree/bindings/clock/clock-bindings.txt
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -22,5 +24,7 @@ spi@7000d600 {
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clocks = <&tegra_car 44>;
+	clock-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
index 7b53da5cb75b..66e16c7f5939 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -6,6 +6,8 @@ Required properties:
 - interrupts: Should contain SFLASH interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this SFLASH controller.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -21,6 +23,6 @@ spi@7000c380 {
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clocks = <&tegra_car 43>;
 	status = "disabled";
 };
-
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
index eefe15e3d95e..0e6e94eb2b2a 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -6,6 +6,8 @@ Required properties:
 - interrupts: Should contain SLINK interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this SLINK controller.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -21,6 +23,6 @@ spi@7000d600 {
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clocks = <&tegra_car 44>;
 	status = "disabled";
 };
-
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
index e019fdc38773..4a864bd10d3d 100644
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
@@ -8,6 +8,8 @@ Required properties:
 - compatible : should be "nvidia,tegra20-timer".
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A list of 4 interrupts; one per timer channel.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -18,4 +20,5 @@ timer {
 			0 1 0x04
 			0 41 0x04
 			0 42 0x04>;
+	clocks = <&tegra_car 132>;
 };
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
index 906109d4c593..b5082a1cf461 100644
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
@@ -10,6 +10,8 @@ Required properties:
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A list of 6 interrupts; one per each of timer channels 1
     through 5, and one for the shared interrupt for the remaining channels.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 timer {
 	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
@@ -20,4 +22,5 @@ timer {
 		      0 42 0x04
 		      0 121 0x04
 		      0 122 0x04>;
+	clocks = <&tegra_car 214>;
 };
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
index df0933043a5b..b98d0bdfa248 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
@@ -8,7 +8,8 @@ and additions :
 Required properties :
  - compatible : Should be "nvidia,tegra20-ehci".
  - nvidia,phy : phandle of the PHY that the controller is connected to.
- - clocks : Contains a single entry which defines the USB controller's clock.
+ - clocks : Must contain one entry, for the module clock.
+   See ../clocks/clock-bindings.txt for details.
 
 Optional properties:
  - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
-- 
1.8.1.5

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Marc Dietrich]

Hi Stephen,

On Friday 15 November 2013 13:53:56 Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Many of the Tegra DT binding documents say nothing about the clocks or
> clock-names properties, yet those are present and required in DT files.
> This patch simply updates the documentation file to match the implicit
> definition of the binding, based on real-world DT content.
> 
> All Tegra bindings that mention clocks are updated to have consistent
> wording and formatting of the clock-related properties.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  1 +
>  .../devicetree/bindings/dma/tegra20-apbdma.txt     |  3 ++
>  .../bindings/gpu/nvidia,tegra20-host1x.txt         | 61
> ++++++++++++++++++++++ .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |
> 14 ++---
>  .../bindings/input/nvidia,tegra20-kbc.txt          |  3 ++
>  .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  3 ++
>  .../devicetree/bindings/nvec/nvidia,nvec.txt       |  8 +++
>  .../bindings/pci/nvidia,tegra20-pcie.txt           | 16 +++---
>  .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |  3 ++
>  .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt |  3 ++
>  .../bindings/serial/nvidia,tegra20-hsuart.txt      |  3 ++
>  .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-rt5640.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra20-ac97.txt         |  4 ++
>  .../bindings/sound/nvidia,tegra20-i2s.txt          |  3 ++
>  .../bindings/sound/nvidia,tegra30-ahub.txt         | 21 ++++++--
>  .../bindings/sound/nvidia,tegra30-i2s.txt          |  5 +-
>  .../bindings/spi/nvidia,tegra114-spi.txt           |  8 ++-
>  .../bindings/spi/nvidia,tegra20-sflash.txt         |  4 +-
>  .../bindings/spi/nvidia,tegra20-slink.txt          |  4 +-
>  .../bindings/timer/nvidia,tegra20-timer.txt        |  3 ++
>  .../bindings/timer/nvidia,tegra30-timer.txt        |  3 ++
>  .../bindings/usb/nvidia,tegra20-ehci.txt           |  3 +-
>  26 files changed, 172 insertions(+), 39 deletions(-)
> 
> diff --git
> a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index
> 1608a54e90e1..68ac65f82a1c 100644
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> @@ -9,6 +9,7 @@ Required properties:
>  - compatible : Should contain "nvidia,tegra<chip>-pmc".
>  - reg : Offset and length of the register set for the device
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
>    "pclk" (The Tegra clock of that name),
>    "clk32k_in" (The 32KHz clock input to Tegra).
> diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt index
> 90fa7da525b8..74bfc54bb184 100644
> --- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> +++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> @@ -5,6 +5,8 @@ Required properties:
>  - reg: Should contain DMA registers location and length. This shuld include
> all of the per-channel registers.
>  - interrupts: Should contain all of the per-channel DMA interrupts.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Examples:
> 
> @@ -27,4 +29,5 @@ apbdma: dma@6000a000 {
>  		       0 149 0x04
>  		       0 150 0x04
>  		       0 151 0x04 >;
> +	clocks = <&tegra_car 34>;
>  };
> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt index
> b4fa934ae3a2..c9a715a75f60 100644
> --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> @@ -9,6 +9,8 @@ Required properties:
>  - #size-cells: The number of cells used to represent the size of an address
> range in the host1x address space. Should be 1.
>  - ranges: The mapping of the host1x address space to the CPU address space.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  The host1x top-level node defines a number of children, each representing
> one of the following host1x client modules:
> @@ -19,6 +21,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-mpe"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - vi: video input
> 
> @@ -26,6 +30,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-vi"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - epp: encoder pre-processor
> 
> @@ -33,6 +39,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-epp"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - isp: image signal processor
> 
> @@ -40,6 +48,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-isp"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - gr2d: 2D graphics engine
> 
> @@ -47,12 +57,23 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-gr2d"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - gr3d: 3D graphics engine
> 
>    Required properties:
>    - compatible: "nvidia,tegra<chip>-gr3d"
>    - reg: Physical base address and length of the controller's registers.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.

double clocks entry

> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    (This property may be omitted if the only clock in the list is "3d")
> +    - 3d
> +      This MUST be the first entry.

why? isn't the purpose of names that the order is irrelevant?

> +    - 3d2 (Only required on SoCs with two 3D clocks)
> 
>  - dc: display controller
> 
> @@ -60,6 +81,12 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-dc"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - disp1 or disp2 (depending on the controller instance)
> +      This MUST be the first entry.
> +    - parent
> 
>    Each display controller node has a child node, named "rgb", that
> represents the RGB output associated with the controller. It can take the
> following @@ -76,6 +103,12 @@ of the following host1x client modules:
>    - interrupts: The interrupt outputs from the controller.
>    - vdd-supply: regulator for supply voltage
>    - pll-supply: regulator for PLL
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - hdmi
> +      This MUST be the first entry.
> +    - parent
> 
>    Optional properties:
>    - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID
> probing @@ -88,12 +121,22 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-tvo"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - dsi: display serial interface
> 
>    Required properties:
>    - compatible: "nvidia,tegra<chip>-dsi"
>    - reg: Physical base address and length of the controller's registers.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.

double clocks entry

> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - dsi
> +      This MUST be the first entry.
> +    - parent

The clock-names property is marked as "required". So it should also been added 
to the examples below where it is required. Or is it "optional"?

>  Example:
> 
> @@ -105,6 +148,7 @@ Example:
>  		reg = <0x50000000 0x00024000>;
>  		interrupts = <0 65 0x04   /* mpcore syncpt */
>  			      0 67 0x04>; /* mpcore general */
> +		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
> 
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> @@ -115,41 +159,50 @@ Example:
>  			compatible = "nvidia,tegra20-mpe";
>  			reg = <0x54040000 0x00040000>;
>  			interrupts = <0 68 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_MPE>;
>  		};
> 
>  		vi {
>  			compatible = "nvidia,tegra20-vi";
>  			reg = <0x54080000 0x00040000>;
>  			interrupts = <0 69 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_VI>;
>  		};
> 
>  		epp {
>  			compatible = "nvidia,tegra20-epp";
>  			reg = <0x540c0000 0x00040000>;
>  			interrupts = <0 70 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_EPP>;
>  		};
> 
>  		isp {
>  			compatible = "nvidia,tegra20-isp";
>  			reg = <0x54100000 0x00040000>;
>  			interrupts = <0 71 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_ISP>;
>  		};
> 
>  		gr2d {
>  			compatible = "nvidia,tegra20-gr2d";
>  			reg = <0x54140000 0x00040000>;
>  			interrupts = <0 72 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
>  		};
> 
>  		gr3d {
>  			compatible = "nvidia,tegra20-gr3d";
>  			reg = <0x54180000 0x00040000>;
> +			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
>  		};
> 
>  		dc@54200000 {
>  			compatible = "nvidia,tegra20-dc";
>  			reg = <0x54200000 0x00040000>;
>  			interrupts = <0 73 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
> +				 <&tegra_car TEGRA20_CLK_PLL_P>;
> +			clock-names = "disp1", "parent";
> 
>  			rgb {
>  				status = "disabled";
> @@ -160,6 +213,9 @@ Example:
>  			compatible = "nvidia,tegra20-dc";
>  			reg = <0x54240000 0x00040000>;
>  			interrupts = <0 74 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
> +				 <&tegra_car TEGRA20_CLK_PLL_P>;
> +			clock-names = "disp2", "parent";
> 
>  			rgb {
>  				status = "disabled";
> @@ -170,6 +226,9 @@ Example:
>  			compatible = "nvidia,tegra20-hdmi";
>  			reg = <0x54280000 0x00040000>;
>  			interrupts = <0 75 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
> +				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
> +			clock-names = "hdmi", "parent";
>  			status = "disabled";
>  		};
> 
> @@ -177,12 +236,14 @@ Example:
>  			compatible = "nvidia,tegra20-tvo";
>  			reg = <0x542c0000 0x00040000>;
>  			interrupts = <0 76 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_TVO>;
>  			status = "disabled";
>  		};
> 
>  		dsi {
>  			compatible = "nvidia,tegra20-dsi";
>  			reg = <0x54300000 0x00040000>;
> +			clocks = <&tegra_car TEGRA20_CLK_DSI>;
>  			status = "disabled";
>  		};
>  	};
> diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
> b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt index
> ef77cc7a0e46..96ab40131ae1 100644
> --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
> +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
> @@ -39,12 +39,14 @@ Required properties:
>  - interrupts: Should contain I2C controller interrupts.
>  - address-cells: Address cells for I2C device address.
>  - size-cells: Size of the I2C device address.
> -- clocks: Clock ID as per
> -		Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
> -	for I2C controller.
> -- clock-names: Name of the clock:
> -	Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
> -	Tegra114 I2C controller: "div-clk".
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  Tegra20/Tegra30:
> +  - div-clk
> +  - fast-clk
> +  Tegra114:
> +  - div-clk
> 
>  Example:
> 
> diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
> b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt index
> 2995fae7ee47..cc28d2194c37 100644
> --- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
> +++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
> @@ -13,6 +13,8 @@ Required properties:
>    array of pin numbers which is used as column.
>  - linux,keymap: The keymap for keys as described in the binding document
>    devicetree/bindings/input/matrix-keymap.txt.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties, in addition to those specified by the shared
>  matrix-keyboard bindings:
> @@ -31,6 +33,7 @@ keyboard: keyboard {
>  	compatible = "nvidia,tegra20-kbc";
>  	reg = <0x7000e200 0x100>;
>  	interrupts = <0 85 0x04>;
> +	clocks = <&tegra_car 36>;
>  	nvidia,ghost-filter;
>  	nvidia,debounce-delay-ms = <640>;
>  	nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
> diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index
> c6d7b11db9eb..f727902a9e8d 100644
> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> @@ -8,6 +8,8 @@ by mmc.txt and the properties used by the sdhci-tegra
> driver.
> 
>  Required properties:
>  - compatible : Should be "nvidia,<chip>-sdhci"
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties:
>  - power-gpios : Specify GPIOs for power control
> @@ -18,6 +20,7 @@ sdhci@c8000200 {
>  	compatible = "nvidia,tegra20-sdhci";
>  	reg = <0xc8000200 0x200>;
>  	interrupts = <47>;
> +	clocks = <&tegra_car 14>;
>  	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
>  	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
>  	power-gpios = <&gpio 155 0>; /* gpio PT3 */
> diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
> b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt index
> 5aeee53ff9f4..a97fe575ca29 100644
> --- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
> +++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
> @@ -7,3 +7,11 @@ Required properties:
>  - clock-frequency : the frequency of the i2c bus
>  - gpios : the gpio used for ec request
>  - slave-addr: the i2c address of the slave controller
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  Tegra20/Tegra30:
> +  - div-clk
> +  - fast-clk
> +  Tegra114:
> +  - div-clk
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index
> 6b7510775c50..ad2eb9804afa 100644
> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> @@ -42,14 +42,14 @@ Required properties:
>      - 0xc2000000: prefetchable memory region
>    Please refer to the standard PCI bus binding document for a more detailed
> explanation.
> -- clocks: List of clock inputs of the controller. Must contain an entry for
> -  each entry in the clock-names property.
> -- clock-names: Must include the following entries:
> -  "pex": The Tegra clock of that name
> -  "afi": The Tegra clock of that name
> -  "pcie_xclk": The Tegra clock of that name
> -  "pll_e": The Tegra clock of that name
> -  "cml": The Tegra clock of that name (not required for Tegra20)
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - pex
> +  - afi
> +  - pcie_xclk
> +  - pll_e
> +  - cml (not required for Tegra20)
> 
>  Root ports are defined as subnodes of the PCIe controller node.
> 
> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index
> c3fc57af8772..0d608d34fed0 100644
> --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> @@ -7,6 +7,8 @@ Required properties:
>  - reg: physical base address and length of the controller's registers
>  - #pwm-cells: should be 2. See pwm.txt in this directory for a description
> of the cells format.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Example:
> 
> @@ -14,4 +16,5 @@ Example:
>  		compatible = "nvidia,tegra20-pwm";
>  		reg = <0x7000a000 0x100>;
>  		#pwm-cells = <2>;
> +		clocks = <&tegra_car 17>;
>  	};
> diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt index
> 93f45e9dce7c..652d1ff2e8be 100644
> --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> @@ -9,6 +9,8 @@ Required properties:
>  - compatible : should be "nvidia,tegra20-rtc".
>  - reg : Specifies base physical address and size of the registers.
>  - interrupts : A single interrupt specifier.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Example:
> 
> @@ -16,4 +18,5 @@ timer {
>  	compatible = "nvidia,tegra20-rtc";
>  	reg = <0x7000e000 0x100>;
>  	interrupts = <0 2 0x04>;
> +	clocks = <&tegra_car 4>;
>  };
> diff --git
> a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt index
> 392a4493eebd..39148b6236a1 100644
> --- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> @@ -6,6 +6,8 @@ Required properties:
>  - interrupts: Should contain UART controller interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this UART controller.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties:
>  - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
> @@ -20,5 +22,6 @@ serial@70006000 {
>  	interrupts = <0 36 0x04>;
>  	nvidia,dma-request-selector = <&apbdma 8>;
>  	nvidia,enable-modem-interrupt;
> +	clocks = <&tegra_car 6>;
>  	status = "disabled";
>  };
> diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
> index 8b8903ef0800..57f40f93453e 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
> +++
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt @@
> -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-alc5632"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> index dc6224994d69..7788808dcd0b 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex, with RT5640 CODEC
>  Required properties:
>  - compatible : "nvidia,tegra-audio-rt5640"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> index aab6ce0ad2fc..96f6a57dd6b4 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-wm8753"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> index 4b44dfb6ca0d..b795d282818d 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-wm8903"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> index ad589b163639..436f6cd9d07c 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-wm9712"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt index
> c1454979c1ef..37f4ebf5b184 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> @@ -4,12 +4,15 @@ Required properties:
>  - compatible : "nvidia,tegra20-ac97"
>  - reg : Should contain AC97 controller registers location and length
>  - interrupts : Should contain AC97 interrupt
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for the AC97 controller
>  - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the
> number of the GPIO used to reset the external AC97 codec
>  - nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the
> number of the GPIO corresponding with the AC97 DAP _FS line
> +
>  Example:
> 
>  ac97@70002000 {
> @@ -19,4 +22,5 @@ ac97@70002000 {
>  	nvidia,dma-request-selector = <&apbdma 12>;
>  	nvidia,codec-reset-gpio = <&gpio 170 0>;
>  	nvidia,codec-sync-gpio = <&gpio 120 0>;
> +	clocks = <&tegra_car 3>;
>  };
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt index
> 0df2b5c816e3..ba0c9452916d 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> @@ -4,6 +4,8 @@ Required properties:
>  - compatible : "nvidia,tegra20-i2s"
>  - reg : Should contain I2S registers location and length
>  - interrupts : Should contain I2S interrupt
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this I2S controller
> 
> @@ -14,4 +16,5 @@ i2s@70002800 {
>  	reg = <0x70002800 0x200>;
>  	interrupts = < 45 >;
>  	nvidia,dma-request-selector = < &apbdma 2 >;
> +	clocks = <&tegra_car 11>;
>  };
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt index
> 0e5c12c66523..7299eeadd588 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> @@ -12,11 +12,24 @@ Required properties:
>    If a single entry is present, the request selectors for the channels are
>    assumed to be contiguous, and increment from this value.
>    If multiple values are given, one value must be given per channel.
> -- clocks : Must contain an entry for each required entry in clock-names.
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0,
> -    dam1, dam2, spdif_in.
> -  - Tegra114: Additionally requires amx, adx.
> +  Tegra30 and later:
> +  - d_audio
> +  - apbif
> +  - i2s0
> +  - i2s1
> +  - i2s2
> +  - i2s3
> +  - i2s4
> +  - dam0
> +  - dam1
> +  - dam2
> +  - spdif_in
> +  Tegra114 and later additionally require:
> +  - amx
> +  - adx
>  - ranges : The bus address mapping for the configlink register bus.
>    Can be empty since the mapping is 1:1.
>  - #address-cells : For the configlink bus. Should be <1>;
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt index
> dfa6c037124a..7a3112bc135c 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
> @@ -3,13 +3,16 @@ NVIDIA Tegra30 I2S controller
>  Required properties:
>  - compatible : "nvidia,tegra30-i2s"
>  - reg : Should contain I2S registers location and length
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
>  - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx
> (playback) first, tx (capture) second. See nvidia,tegra30-ahub.txt for
> values.
> 
>  Example:
> 
> -i2s@70002800 {
> +i2s@70080300 {
>  	compatible = "nvidia,tegra30-i2s";
>  	reg = <0x70080300 0x100>;
>  	nvidia,ahub-cif-ids = <4 4>;
> +	clocks = <&tegra_car 11>;
>  };
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt index
> 91ff771c7e77..d4f2d534934b 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> @@ -6,8 +6,10 @@ Required properties:
>  - interrupts: Should contain SPI interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SPI controller.
> -- This is also require clock named "spi" as per binding document
> -  Documentation/devicetree/bindings/clock/clock-bindings.txt
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - spi
> 
>  Recommended properties:
>  - spi-max-frequency: Definition as per
> @@ -22,5 +24,7 @@ spi@7000d600 {
>  	spi-max-frequency = <25000000>;
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> +	clocks = <&tegra_car 44>;
> +	clock-names = "spi";
>  	status = "disabled";
>  };
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt index
> 7b53da5cb75b..66e16c7f5939 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> @@ -6,6 +6,8 @@ Required properties:
>  - interrupts: Should contain SFLASH interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SFLASH controller.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Recommended properties:
>  - spi-max-frequency: Definition as per
> @@ -21,6 +23,6 @@ spi@7000c380 {
>  	spi-max-frequency = <25000000>;
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> +	clocks = <&tegra_car 43>;
>  	status = "disabled";
>  };
> -
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt index
> eefe15e3d95e..0e6e94eb2b2a 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
> @@ -6,6 +6,8 @@ Required properties:
>  - interrupts: Should contain SLINK interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SLINK controller.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Recommended properties:
>  - spi-max-frequency: Definition as per
> @@ -21,6 +23,6 @@ spi@7000d600 {
>  	spi-max-frequency = <25000000>;
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> +	clocks = <&tegra_car 44>;
>  	status = "disabled";
>  };
> -
> diff --git
> a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
> b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt index
> e019fdc38773..4a864bd10d3d 100644
> --- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
> @@ -8,6 +8,8 @@ Required properties:
>  - compatible : should be "nvidia,tegra20-timer".
>  - reg : Specifies base physical address and size of the registers.
>  - interrupts : A list of 4 interrupts; one per timer channel.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Example:
> 
> @@ -18,4 +20,5 @@ timer {
>  			0 1 0x04
>  			0 41 0x04
>  			0 42 0x04>;
> +	clocks = <&tegra_car 132>;
>  };
> diff --git
> a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
> b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt index
> 906109d4c593..b5082a1cf461 100644
> --- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
> @@ -10,6 +10,8 @@ Required properties:
>  - reg : Specifies base physical address and size of the registers.
>  - interrupts : A list of 6 interrupts; one per each of timer channels 1
>      through 5, and one for the shared interrupt for the remaining channels.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  timer {
>  	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
> @@ -20,4 +22,5 @@ timer {
>  		      0 42 0x04
>  		      0 121 0x04
>  		      0 122 0x04>;
> +	clocks = <&tegra_car 214>;
>  };
> diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
> b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt index
> df0933043a5b..b98d0bdfa248 100644
> --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
> +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
> @@ -8,7 +8,8 @@ and additions :
>  Required properties :
>   - compatible : Should be "nvidia,tegra20-ehci".
>   - nvidia,phy : phandle of the PHY that the controller is connected to.
> - - clocks : Contains a single entry which defines the USB controller's
> clock. + - clocks : Must contain one entry, for the module clock.
> +   See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties:
>   - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
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Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 11/16/2013 03:00 PM, Marc Dietrich wrote:
> Hi Stephen,
> 
> On Friday 15 November 2013 13:53:56 Stephen Warren wrote:
>> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> Many of the Tegra DT binding documents say nothing about the clocks or
>> clock-names properties, yet those are present and required in DT files.
>> This patch simply updates the documentation file to match the implicit
>> definition of the binding, based on real-world DT content.
>>
>> All Tegra bindings that mention clocks are updated to have consistent
>> wording and formatting of the clock-related properties.

>> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt

(Thanks for pointing out the duplicate entries; I'll fix those.)

>> +  - clocks : Must contain an entry for each entry in clock-names.
>> +    See ../clocks/clock-bindings.txt for details.
>> +  - clock-names : Must include the following entries:
>> +    (This property may be omitted if the only clock in the list is "3d")
>> +    - 3d
>> +      This MUST be the first entry.
> 
> why? isn't the purpose of names that the order is irrelevant?

If we used names from the start, then the order would be irrelevant.

However, this binding didn't use names from the start, and hence the
order of appearance in "clocks" is part of the original binding.
"clock-names" only became part of the binding when the second clock was
introduced.

We can either: (a) document the existing requirements as I have done, or
(b) go through all the bindings and drivers and make potentially
incompatible changes so that all ordering is purely defined by
"clock-names". I was tempted to do (b) for cleanliness, but didn't want
to push my luck on too many ABI-incompatible changes. (b) /might/ also
affect more drivers than this series already does, thus bloating it even
more:-(

P.S. only quoting the parts of the patch you're replying to makes it a
lot easier and quicker to find your replies.

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2855 bytes --]

On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
[...]
> @@ -60,6 +81,12 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-dc"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - disp1 or disp2 (depending on the controller instance)

I'm not sure if this makes sense. The name could be the same independent
of which controller uses it. If it isn't then the driver would need
additional code to find out which instance it is and construct a dynamic
string.

Any objection to just make this entry "disp", or "dc"?

>  - dsi: display serial interface
>  
>    Required properties:
>    - compatible: "nvidia,tegra<chip>-dsi"
>    - reg: Physical base address and length of the controller's registers.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.

There's another duplicate clocks entry here, although perhaps Marc
already caught that.

> +  - clock-names : Must include the following entries:

One other thing I noticed here is that you use a space between the
property name and the :. None of the other properties have that, so it
looks somewhat out of place. The same is true for other bindings, but
there seem to be inconsistencies in some places anyway, so perhaps we
don't care? Well, I do care, don't know about you. =)

> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> index 91ff771c7e77..d4f2d534934b 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> @@ -6,8 +6,10 @@ Required properties:
>  - interrupts: Should contain SPI interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SPI controller.
> -- This is also require clock named "spi" as per binding document
> -  Documentation/devicetree/bindings/clock/clock-bindings.txt
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - spi

This is inconsistent with other bindings that require only a single
clock entry. I suppose that this is required because of the driver
requesting a specifically named clock, in which case that's fine.

Thierry

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Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 11/29/2013 04:49 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote: 
> [...]
>> @@ -60,6 +81,12 @@ of the following host1x client modules: -
>> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base address
>> and length of the controller's registers. - interrupts: The
>> interrupt outputs from the controller. +  - clocks : Must contain
>> an entry for each entry in clock-names. +    See
>> ../clocks/clock-bindings.txt for details. +  - clock-names : Must
>> include the following entries: +    - disp1 or disp2 (depending
>> on the controller instance)
> 
> I'm not sure if this makes sense. The name could be the same
> independent of which controller uses it. If it isn't then the
> driver would need additional code to find out which instance it is
> and construct a dynamic string.
> 
> Any objection to just make this entry "disp", or "dc"?

This patch simply documents the binding that the various drivers
already require and/or whatever is already in the DT files if there
are any clocks the drivers don't currently use. I did consider fixing
up all the current usage to actually be sane, but that would require
even more driver changes (in addition to those required for the reset
framework patches).

>> +  - clock-names : Must include the following entries:
> 
> One other thing I noticed here is that you use a space between the 
> property name and the :. None of the other properties have that, so
> it looks somewhat out of place. The same is true for other
> bindings, but there seem to be inconsistencies in some places
> anyway, so perhaps we don't care? Well, I do care, don't know about
> you. =)

Yes, I simply cut/paste the clock docs from one binding into the other
to make sure the wording was consistent. I guess I need to go through
and adjust the pasted format to match the various bindings. It's a
pity they're plain-text not a schema, so there is no consistency here:-(

>> diff --git
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
>> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
>> index 91ff771c7e77..d4f2d534934b 100644 ---
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
>> +++
>> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
>> @@ -6,8 +6,10 @@ Required properties: - interrupts: Should
>> contain SPI interrupts. - nvidia,dma-request-selector : The Tegra
>> DMA controller's phandle and request selector for this SPI
>> controller. -- This is also require clock named "spi" as per
>> binding document -
>> Documentation/devicetree/bindings/clock/clock-bindings.txt +-
>> clocks : Must contain an entry for each entry in clock-names. +
>> See ../clocks/clock-bindings.txt for details. +- clock-names :
>> Must include the following entries: +  - spi
> 
> This is inconsistent with other bindings that require only a
> single clock entry. I suppose that this is required because of the
> driver requesting a specifically named clock, in which case that's
> fine.

This driver does clk_get(dev, "spi") rather than clk_get(dev, NULL),
so this requires a specific name. Again, I did consider updating all
drivers to use names, but decided I didn't want to do even more driver
changes, but instead just document what was currently required.

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

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On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren wrote:
> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote: 
> > [...]
> >> @@ -60,6 +81,12 @@ of the following host1x client modules: -
> >> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base address
> >> and length of the controller's registers. - interrupts: The
> >> interrupt outputs from the controller. +  - clocks : Must contain
> >> an entry for each entry in clock-names. +    See
> >> ../clocks/clock-bindings.txt for details. +  - clock-names : Must
> >> include the following entries: +    - disp1 or disp2 (depending
> >> on the controller instance)
> > 
> > I'm not sure if this makes sense. The name could be the same
> > independent of which controller uses it. If it isn't then the
> > driver would need additional code to find out which instance it is
> > and construct a dynamic string.
> > 
> > Any objection to just make this entry "disp", or "dc"?
> 
> This patch simply documents the binding that the various drivers
> already require and/or whatever is already in the DT files if there
> are any clocks the drivers don't currently use. I did consider fixing
> up all the current usage to actually be sane, but that would require
> even more driver changes (in addition to those required for the reset
> framework patches).

Okay, I understand. I still think we should change the usage for this
particular use-case subsequently. In retrospect the entry in clock-names
wasn't thought out very well. It seems like the reason for using disp1
and disp2 respectively was so that it would match the system-wide clock
name, rather than the clock's label within the display controller's
context.

Just to clarify what I mean, if we stick to the above, then we'll need
to add code to the driver along the lines of:

	char clock_name[6];

	if (regs->start == 0x54200000)
		index = 1;
	else
		index = 2;

	sprintf(clock_name, "disp%u", index);

	clk = devm_clk_get(&pdev->dev, clock_name);

rather than the much more simple and elegant:

	clk = devm_clk_get(&pdev->dev, "disp");

The whole purpose of the clock consumer ID is to be generic and as such
independent of the specific IP block or instance thereof.

> >> diff --git
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> >> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
> >> index 91ff771c7e77..d4f2d534934b 100644 ---
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
> >> +++
> >> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
> >> @@ -6,8 +6,10 @@ Required properties: - interrupts: Should
> >> contain SPI interrupts. - nvidia,dma-request-selector : The Tegra
> >> DMA controller's phandle and request selector for this SPI
> >> controller. -- This is also require clock named "spi" as per
> >> binding document -
> >> Documentation/devicetree/bindings/clock/clock-bindings.txt +-
> >> clocks : Must contain an entry for each entry in clock-names. +
> >> See ../clocks/clock-bindings.txt for details. +- clock-names :
> >> Must include the following entries: +  - spi
> > 
> > This is inconsistent with other bindings that require only a
> > single clock entry. I suppose that this is required because of the
> > driver requesting a specifically named clock, in which case that's
> > fine.
> 
> This driver does clk_get(dev, "spi") rather than clk_get(dev, NULL),
> so this requires a specific name. Again, I did consider updating all
> drivers to use names, but decided I didn't want to do even more driver
> changes, but instead just document what was currently required.

Yes, I realized that as well. Oh well, I guess that's part of the "pain"
for not doing it right from the start. Although, admittedly, this really
isn't a big issue.

Thierry

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Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 12/02/2013 01:52 AM, Thierry Reding wrote:
> On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren wrote:
>> On 11/29/2013 04:49 AM, Thierry Reding wrote:
>>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
>>>  [...]
>>>> @@ -60,6 +81,12 @@ of the following host1x client modules: - 
>>>> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base
>>>> address and length of the controller's registers. -
>>>> interrupts: The interrupt outputs from the controller. +  -
>>>> clocks : Must contain an entry for each entry in clock-names.
>>>> +    See ../clocks/clock-bindings.txt for details. +  -
>>>> clock-names : Must include the following entries: +    -
>>>> disp1 or disp2 (depending on the controller instance)
>>> 
>>> I'm not sure if this makes sense. The name could be the same 
>>> independent of which controller uses it. If it isn't then the 
>>> driver would need additional code to find out which instance it
>>> is and construct a dynamic string.
>>> 
>>> Any objection to just make this entry "disp", or "dc"?
>> 
>> This patch simply documents the binding that the various drivers 
>> already require and/or whatever is already in the DT files if
>> there are any clocks the drivers don't currently use. I did
>> consider fixing up all the current usage to actually be sane, but
>> that would require even more driver changes (in addition to those
>> required for the reset framework patches).
> 
> Okay, I understand. I still think we should change the usage for
> this particular use-case subsequently. In retrospect the entry in
> clock-names wasn't thought out very well. It seems like the reason
> for using disp1 and disp2 respectively was so that it would match
> the system-wide clock name, rather than the clock's label within
> the display controller's context.
> 
> Just to clarify what I mean, if we stick to the above, then we'll
> need to add code to the driver along the lines of:
> 
> char clock_name[6];
> 
> if (regs->start == 0x54200000) index = 1; else index = 2;
> 
> sprintf(clock_name, "disp%u", index);
> 
> clk = devm_clk_get(&pdev->dev, clock_name);
> 
> rather than the much more simple and elegant:
> 
> clk = devm_clk_get(&pdev->dev, "disp");
> 
> The whole purpose of the clock consumer ID is to be generic and as
> such independent of the specific IP block or instance thereof.

I think if the code needs this clock, I'd be tempted to do the following:

clk = clk_get(dev, "disp1");
if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFERRED)
    clk = clk_get(dev, "disp2");
if (IS_ERR(clk))
    return PTR_ERR(clk);

That avoids having to hard-code IP block base addresses and construct
clock names at run-time.

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

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On Tue, Dec 03, 2013 at 11:31:00AM -0700, Stephen Warren wrote:
> On 12/02/2013 01:52 AM, Thierry Reding wrote:
> > On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren wrote:
> >> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> >>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
> >>>  [...]
> >>>> @@ -60,6 +81,12 @@ of the following host1x client modules: - 
> >>>> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base
> >>>> address and length of the controller's registers. -
> >>>> interrupts: The interrupt outputs from the controller. +  -
> >>>> clocks : Must contain an entry for each entry in clock-names.
> >>>> +    See ../clocks/clock-bindings.txt for details. +  -
> >>>> clock-names : Must include the following entries: +    -
> >>>> disp1 or disp2 (depending on the controller instance)
> >>> 
> >>> I'm not sure if this makes sense. The name could be the same 
> >>> independent of which controller uses it. If it isn't then the 
> >>> driver would need additional code to find out which instance it
> >>> is and construct a dynamic string.
> >>> 
> >>> Any objection to just make this entry "disp", or "dc"?
> >> 
> >> This patch simply documents the binding that the various drivers 
> >> already require and/or whatever is already in the DT files if
> >> there are any clocks the drivers don't currently use. I did
> >> consider fixing up all the current usage to actually be sane, but
> >> that would require even more driver changes (in addition to those
> >> required for the reset framework patches).
> > 
> > Okay, I understand. I still think we should change the usage for
> > this particular use-case subsequently. In retrospect the entry in
> > clock-names wasn't thought out very well. It seems like the reason
> > for using disp1 and disp2 respectively was so that it would match
> > the system-wide clock name, rather than the clock's label within
> > the display controller's context.
> > 
> > Just to clarify what I mean, if we stick to the above, then we'll
> > need to add code to the driver along the lines of:
> > 
> > char clock_name[6];
> > 
> > if (regs->start == 0x54200000) index = 1; else index = 2;
> > 
> > sprintf(clock_name, "disp%u", index);
> > 
> > clk = devm_clk_get(&pdev->dev, clock_name);
> > 
> > rather than the much more simple and elegant:
> > 
> > clk = devm_clk_get(&pdev->dev, "disp");
> > 
> > The whole purpose of the clock consumer ID is to be generic and as
> > such independent of the specific IP block or instance thereof.
> 
> I think if the code needs this clock, I'd be tempted to do the following:
> 
> clk = clk_get(dev, "disp1");
> if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFERRED)
>     clk = clk_get(dev, "disp2");
> if (IS_ERR(clk))
>     return PTR_ERR(clk);
> 
> That avoids having to hard-code IP block base addresses and construct
> clock names at run-time.

I think perhaps we're getting our wires crossed. What I've been trying
to say is that I think the binding should define the first clock to be
named simply "disp".

The reason why I think "disp" is a better choice than "disp1" and
"disp2" is that it merely encodes the purpose of the clock for the
display controller, and doesn't contain knowledge about the particular
instance of the display controller. That's analogous to I2C or SPI nodes
where the clock isn't named "i2c1", "i2c2", ... or "spi1", "spi2", ...
but simply "i2c" or "spi" respectively.

I know that existing DTS files use "disp1" and "disp2", respectively,
but I think that was a wrong choice back at the time and therefore I
suggest that we change it while we still can (DTS files are changing in
3.14 anyway because of the reset and DMA binding updates).

Is that any clearer than what I was saying before?

Thierry

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Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 12/04/2013 01:48 AM, Thierry Reding wrote:
> On Tue, Dec 03, 2013 at 11:31:00AM -0700, Stephen Warren wrote:
>> On 12/02/2013 01:52 AM, Thierry Reding wrote:
>>> On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren 
>>> wrote:
>>>> On 11/29/2013 04:49 AM, Thierry Reding wrote:
>>>>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren 
>>>>> wrote: [...]
>>>>>> @@ -60,6 +81,12 @@ of the following host1x client 
>>>>>> modules: - compatible: "nvidia,tegra<chip>-dc" - reg: 
>>>>>> Physical base address and length of the controller's 
>>>>>> registers. - interrupts: The interrupt outputs from the 
>>>>>> controller. +  - clocks : Must contain an entry for each 
>>>>>> entry in clock-names. +    See 
>>>>>> ../clocks/clock-bindings.txt for details. +  - 
>>>>>> clock-names : Must include the following entries: +    -
>>>>>>  disp1 or disp2 (depending on the controller instance)
>>>>> 
>>>>> I'm not sure if this makes sense. The name could be the 
>>>>> same independent of which controller uses it. If it isn't 
>>>>> then the driver would need additional code to find out 
>>>>> which instance it is and construct a dynamic string.
>>>>> 
>>>>> Any objection to just make this entry "disp", or "dc"?
>>>> 
>>>> This patch simply documents the binding that the various 
>>>> drivers already require and/or whatever is already in the DT 
>>>> files if there are any clocks the drivers don't currently 
>>>> use. I did consider fixing up all the current usage to 
>>>> actually be sane, but that would require even more driver 
>>>> changes (in addition to those required for the reset 
>>>> framework patches).
>>> 
>>> Okay, I understand. I still think we should change the usage 
>>> for this particular use-case subsequently. In retrospect the 
>>> entry in clock-names wasn't thought out very well. It seems 
>>> like the reason for using disp1 and disp2 respectively was so 
>>> that it would match the system-wide clock name, rather than
>>> the clock's label within the display controller's context.
>>> 
>>> Just to clarify what I mean, if we stick to the above, then 
>>> we'll need to add code to the driver along the lines of:
>>> 
>>> char clock_name[6];
>>> 
>>> if (regs->start == 0x54200000) index = 1; else index = 2;
>>> 
>>> sprintf(clock_name, "disp%u", index);
>>> 
>>> clk = devm_clk_get(&pdev->dev, clock_name);
>>> 
>>> rather than the much more simple and elegant:
>>> 
>>> clk = devm_clk_get(&pdev->dev, "disp");
>>> 
>>> The whole purpose of the clock consumer ID is to be generic
>>> and as such independent of the specific IP block or instance 
>>> thereof.
>> 
>> I think if the code needs this clock, I'd be tempted to do the 
>> following:
>> 
>> clk = clk_get(dev, "disp1"); if (IS_ERR(clk) && PTR_ERR(clk) != 
>> -EPROBE_DEFERRED) clk = clk_get(dev, "disp2"); if (IS_ERR(clk)) 
>> return PTR_ERR(clk);
>> 
>> That avoids having to hard-code IP block base addresses and 
>> construct clock names at run-time.
> 
> I think perhaps we're getting our wires crossed. What I've been 
> trying to say is that I think the binding should define the first 
> clock to be named simply "disp".
> 
> The reason why I think "disp" is a better choice than "disp1" and 
> "disp2" is that it merely encodes the purpose of the clock for the
>  display controller, and doesn't contain knowledge about the 
> particular instance of the display controller. That's analogous to 
> I2C or SPI nodes where the clock isn't named "i2c1", "i2c2", ...
> or "spi1", "spi2", ... but simply "i2c" or "spi" respectively.
> 
> I know that existing DTS files use "disp1" and "disp2", 
> respectively, but I think that was a wrong choice back at the time 
> and therefore I suggest that we change it while we still can (DTS 
> files are changing in 3.14 anyway because of the reset and DMA 
> binding updates).
> 
> Is that any clearer than what I was saying before?

No, because I know what you meant before:-)

The thing I was missing is that the existing disp1/disp2 naming is
/only/ something that's in the DT. The driver (and hence the exiting
as-yet-undocumented ABI) looks up this clock as "index 0" not as "name
disp1". Hence, we /can/ change the documented name without affecting
the ABI at all, and not affecting the ABI is something I was trying to
avoid in this patch.

So, how about I fold the following into this patch:

> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> index 42fe3a498e71..ab45c02aa658 100644
> --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> @@ -111,7 +111,7 @@ of the following host1x client modules:
>    - clocks: Must contain an entry for each entry in clock-names.
>      See ../clocks/clock-bindings.txt for details.
>    - clock-names: Must include the following entries:
> -    - disp1 or disp2 (depending on the controller instance)
> +    - dc
>        This MUST be the first entry.
>      - parent
>    - resets: Must contain an entry for each entry in reset-names.
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> index 01c20c7dbb51..648c494e927f 100644
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ b/arch/arm/boot/dts/tegra20.dtsi
> @@ -89,7 +89,7 @@
>                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
>                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> -                       clock-names = "disp1", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 27>;
>                         reset-names = "dc";
>  
> @@ -104,7 +104,7 @@
>                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
>                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> -                       clock-names = "disp2", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 26>;
>                         reset-names = "dc";
>  
> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> index 58a3dca24c49..829eb4b5091d 100644
> --- a/arch/arm/boot/dts/tegra30.dtsi
> +++ b/arch/arm/boot/dts/tegra30.dtsi
> @@ -165,7 +165,7 @@
>                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
>                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> -                       clock-names = "disp1", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 27>;
>                         reset-names = "dc";
>  
> @@ -180,7 +180,7 @@
>                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
>                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> -                       clock-names = "disp2", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 26>;
>                         reset-names = "dc";
>  

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 7925 bytes --]

On Wed, Dec 04, 2013 at 10:34:17AM -0700, Stephen Warren wrote:
> On 12/04/2013 01:48 AM, Thierry Reding wrote:
> > On Tue, Dec 03, 2013 at 11:31:00AM -0700, Stephen Warren wrote:
> >> On 12/02/2013 01:52 AM, Thierry Reding wrote:
> >>> On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren 
> >>> wrote:
> >>>> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> >>>>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren 
> >>>>> wrote: [...]
> >>>>>> @@ -60,6 +81,12 @@ of the following host1x client 
> >>>>>> modules: - compatible: "nvidia,tegra<chip>-dc" - reg: 
> >>>>>> Physical base address and length of the controller's 
> >>>>>> registers. - interrupts: The interrupt outputs from the 
> >>>>>> controller. +  - clocks : Must contain an entry for each 
> >>>>>> entry in clock-names. +    See 
> >>>>>> ../clocks/clock-bindings.txt for details. +  - 
> >>>>>> clock-names : Must include the following entries: +    -
> >>>>>>  disp1 or disp2 (depending on the controller instance)
> >>>>> 
> >>>>> I'm not sure if this makes sense. The name could be the 
> >>>>> same independent of which controller uses it. If it isn't 
> >>>>> then the driver would need additional code to find out 
> >>>>> which instance it is and construct a dynamic string.
> >>>>> 
> >>>>> Any objection to just make this entry "disp", or "dc"?
> >>>> 
> >>>> This patch simply documents the binding that the various 
> >>>> drivers already require and/or whatever is already in the DT 
> >>>> files if there are any clocks the drivers don't currently 
> >>>> use. I did consider fixing up all the current usage to 
> >>>> actually be sane, but that would require even more driver 
> >>>> changes (in addition to those required for the reset 
> >>>> framework patches).
> >>> 
> >>> Okay, I understand. I still think we should change the usage 
> >>> for this particular use-case subsequently. In retrospect the 
> >>> entry in clock-names wasn't thought out very well. It seems 
> >>> like the reason for using disp1 and disp2 respectively was so 
> >>> that it would match the system-wide clock name, rather than
> >>> the clock's label within the display controller's context.
> >>> 
> >>> Just to clarify what I mean, if we stick to the above, then 
> >>> we'll need to add code to the driver along the lines of:
> >>> 
> >>> char clock_name[6];
> >>> 
> >>> if (regs->start == 0x54200000) index = 1; else index = 2;
> >>> 
> >>> sprintf(clock_name, "disp%u", index);
> >>> 
> >>> clk = devm_clk_get(&pdev->dev, clock_name);
> >>> 
> >>> rather than the much more simple and elegant:
> >>> 
> >>> clk = devm_clk_get(&pdev->dev, "disp");
> >>> 
> >>> The whole purpose of the clock consumer ID is to be generic
> >>> and as such independent of the specific IP block or instance 
> >>> thereof.
> >> 
> >> I think if the code needs this clock, I'd be tempted to do the 
> >> following:
> >> 
> >> clk = clk_get(dev, "disp1"); if (IS_ERR(clk) && PTR_ERR(clk) != 
> >> -EPROBE_DEFERRED) clk = clk_get(dev, "disp2"); if (IS_ERR(clk)) 
> >> return PTR_ERR(clk);
> >> 
> >> That avoids having to hard-code IP block base addresses and 
> >> construct clock names at run-time.
> > 
> > I think perhaps we're getting our wires crossed. What I've been 
> > trying to say is that I think the binding should define the first 
> > clock to be named simply "disp".
> > 
> > The reason why I think "disp" is a better choice than "disp1" and 
> > "disp2" is that it merely encodes the purpose of the clock for the
> >  display controller, and doesn't contain knowledge about the 
> > particular instance of the display controller. That's analogous to 
> > I2C or SPI nodes where the clock isn't named "i2c1", "i2c2", ...
> > or "spi1", "spi2", ... but simply "i2c" or "spi" respectively.
> > 
> > I know that existing DTS files use "disp1" and "disp2", 
> > respectively, but I think that was a wrong choice back at the time 
> > and therefore I suggest that we change it while we still can (DTS 
> > files are changing in 3.14 anyway because of the reset and DMA 
> > binding updates).
> > 
> > Is that any clearer than what I was saying before?
> 
> No, because I know what you meant before:-)
> 
> The thing I was missing is that the existing disp1/disp2 naming is
> /only/ something that's in the DT. The driver (and hence the exiting
> as-yet-undocumented ABI) looks up this clock as "index 0" not as "name
> disp1". Hence, we /can/ change the documented name without affecting
> the ABI at all, and not affecting the ABI is something I was trying to
> avoid in this patch.

Excellent. Glad we're finally on the same page.

> So, how about I fold the following into this patch:
> 
> > diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> > index 42fe3a498e71..ab45c02aa658 100644
> > --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> > +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> > @@ -111,7 +111,7 @@ of the following host1x client modules:
> >    - clocks: Must contain an entry for each entry in clock-names.
> >      See ../clocks/clock-bindings.txt for details.
> >    - clock-names: Must include the following entries:
> > -    - disp1 or disp2 (depending on the controller instance)
> > +    - dc
> >        This MUST be the first entry.
> >      - parent
> >    - resets: Must contain an entry for each entry in reset-names.
> > diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> > index 01c20c7dbb51..648c494e927f 100644
> > --- a/arch/arm/boot/dts/tegra20.dtsi
> > +++ b/arch/arm/boot/dts/tegra20.dtsi
> > @@ -89,7 +89,7 @@
> >                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
> >                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> > -                       clock-names = "disp1", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 27>;
> >                         reset-names = "dc";
> >  
> > @@ -104,7 +104,7 @@
> >                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
> >                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> > -                       clock-names = "disp2", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 26>;
> >                         reset-names = "dc";
> >  
> > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> > index 58a3dca24c49..829eb4b5091d 100644
> > --- a/arch/arm/boot/dts/tegra30.dtsi
> > +++ b/arch/arm/boot/dts/tegra30.dtsi
> > @@ -165,7 +165,7 @@
> >                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
> >                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> > -                       clock-names = "disp1", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 27>;
> >                         reset-names = "dc";
> >  
> > @@ -180,7 +180,7 @@
> >                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
> >                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> > -                       clock-names = "disp2", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 26>;
> >                         reset-names = "dc";
> >  

That looks perfect. Thanks!

Thierry

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Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 11/29/2013 04:49 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
...
>> +  - clock-names : Must include the following entries:
> 
> One other thing I noticed here is that you use a space between the 
> property name and the :. None of the other properties have that, so
> it looks somewhat out of place. The same is true for other
> bindings, but there seem to be inconsistencies in some places
> anyway, so perhaps we don't care? Well, I do care, don't know about
> you. =)

I've fixed those up locally. I assume you don't want a repost for such
a trivial change? I'll double-check the "resets" patch for the same issue.

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 962 bytes --]

On Tue, Dec 03, 2013 at 11:36:19AM -0700, Stephen Warren wrote:
> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
> ...
> >> +  - clock-names : Must include the following entries:
> > 
> > One other thing I noticed here is that you use a space between the 
> > property name and the :. None of the other properties have that, so
> > it looks somewhat out of place. The same is true for other
> > bindings, but there seem to be inconsistencies in some places
> > anyway, so perhaps we don't care? Well, I do care, don't know about
> > you. =)
> 
> I've fixed those up locally. I assume you don't want a repost for such
> a trivial change? I'll double-check the "resets" patch for the same issue.

No need for a repost. I'll trust you on that one. But I'll urge you to
consider what I said about the "disp" clock entry for the display
controllers before merging this.

Thierry

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[PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Update all the Tegra DT bindings to require resets/reset-names properties
where the HW module has reset inputs. Remove any entries from clocks or
clock-names that were only required to identify reset inputs, rather than
referring to real clocks.

This is a DT-ABI-incompatible change. It is the first of two changes
required for me to consider the Tegra DT bindings as stable, the other
being conversion to the common DMA DT bindings.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/clock/nvidia,tegra114-car.txt         |  4 ++
 .../bindings/clock/nvidia,tegra124-car.txt         |  4 ++
 .../bindings/clock/nvidia,tegra20-car.txt          |  4 ++
 .../bindings/clock/nvidia,tegra30-car.txt          |  4 ++
 .../devicetree/bindings/dma/tegra20-apbdma.txt     |  6 +++
 .../bindings/gpu/nvidia,tegra20-host1x.txt         | 63 ++++++++++++++++++++++
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |  6 +++
 .../bindings/input/nvidia,tegra20-kbc.txt          |  6 +++
 .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  6 +++
 .../devicetree/bindings/nvec/nvidia,nvec.txt       |  4 ++
 .../bindings/pci/nvidia,tegra20-pcie.txt           | 14 +++--
 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |  6 +++
 .../bindings/serial/nvidia,tegra20-hsuart.txt      |  6 +++
 .../bindings/sound/nvidia,tegra20-ac97.txt         |  6 +++
 .../bindings/sound/nvidia,tegra20-i2s.txt          |  6 +++
 .../bindings/sound/nvidia,tegra30-ahub.txt         | 17 ++++--
 .../bindings/sound/nvidia,tegra30-i2s.txt          |  6 +++
 .../bindings/spi/nvidia,tegra114-spi.txt           |  6 +++
 .../bindings/spi/nvidia,tegra20-sflash.txt         |  6 +++
 .../bindings/spi/nvidia,tegra20-slink.txt          |  6 +++
 .../bindings/usb/nvidia,tegra20-ehci.txt           |  4 ++
 21 files changed, 181 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
index 0c80c2677104..9acea9d93160 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra114-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra114-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
index 1a91ec60dee5..ded5d6212c84 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra124-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra124-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index fcfed5bf73fb..6c5901b503d0 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra20-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra20-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index 0f714081e986..63618cde12df 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra30-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra30-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
index 74bfc54bb184..0b1e577ab9d3 100644
--- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
+++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
@@ -7,6 +7,10 @@ Required properties:
 - interrupts: Should contain all of the per-channel DMA interrupts.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - dma
 
 Examples:
 
@@ -30,4 +34,6 @@ apbdma: dma@6000a000 {
 		       0 150 0x04
 		       0 151 0x04 >;
 	clocks = <&tegra_car 34>;
+	resets = <&tegra_car 34>;
+	reset-names = "dma";
 };
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index c9a715a75f60..8e22d234dc4c 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -11,6 +11,10 @@ Required properties:
 - ranges: The mapping of the host1x address space to the CPU address space.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - host1x
 
 The host1x top-level node defines a number of children, each representing one
 of the following host1x client modules:
@@ -23,6 +27,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - mpe
 
 - vi: video input
 
@@ -32,6 +40,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - vi
 
 - epp: encoder pre-processor
 
@@ -41,6 +53,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - epp
 
 - isp: image signal processor
 
@@ -50,6 +66,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - isp
 
 - gr2d: 2D graphics engine
 
@@ -59,6 +79,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - 2d
 
 - gr3d: 3D graphics engine
 
@@ -74,6 +98,11 @@ of the following host1x client modules:
     - 3d
       This MUST be the first entry.
     - 3d2 (Only required on SoCs with two 3D clocks)
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - 3d
+    - 3d2 (Only required on SoCs with two 3D clocks)
 
 - dc: display controller
 
@@ -87,6 +116,10 @@ of the following host1x client modules:
     - disp1 or disp2 (depending on the controller instance)
       This MUST be the first entry.
     - parent
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - dc
 
   Each display controller node has a child node, named "rgb", that represents
   the RGB output associated with the controller. It can take the following
@@ -109,6 +142,10 @@ of the following host1x client modules:
     - hdmi
       This MUST be the first entry.
     - parent
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - hdmi
 
   Optional properties:
   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
@@ -137,6 +174,10 @@ of the following host1x client modules:
     - dsi
       This MUST be the first entry.
     - parent
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - dsi
 
 Example:
 
@@ -149,6 +190,8 @@ Example:
 		interrupts = <0 65 0x04   /* mpcore syncpt */
 			      0 67 0x04>; /* mpcore general */
 		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -160,6 +203,8 @@ Example:
 			reg = <0x54040000 0x00040000>;
 			interrupts = <0 68 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_MPE>;
+			resets = <&tegra_car 60>;
+			reset-names = "mpe";
 		};
 
 		vi {
@@ -167,6 +212,8 @@ Example:
 			reg = <0x54080000 0x00040000>;
 			interrupts = <0 69 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_VI>;
+			resets = <&tegra_car 100>;
+			reset-names = "vi";
 		};
 
 		epp {
@@ -174,6 +221,8 @@ Example:
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <0 70 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_EPP>;
+			resets = <&tegra_car 19>;
+			reset-names = "epp";
 		};
 
 		isp {
@@ -181,6 +230,8 @@ Example:
 			reg = <0x54100000 0x00040000>;
 			interrupts = <0 71 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_ISP>;
+			resets = <&tegra_car 23>;
+			reset-names = "isp";
 		};
 
 		gr2d {
@@ -188,12 +239,16 @@ Example:
 			reg = <0x54140000 0x00040000>;
 			interrupts = <0 72 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+			resets = <&tegra_car 21>;
+			reset-names = "2d";
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+			resets = <&tegra_car 24>;
+			reset-names = "3d";
 		};
 
 		dc@54200000 {
@@ -203,6 +258,8 @@ Example:
 			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -216,6 +273,8 @@ Example:
 			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -229,6 +288,8 @@ Example:
 			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 			clock-names = "hdmi", "parent";
+			resets = <&tegra_car 51>;
+			reset-names = "hdmi";
 			status = "disabled";
 		};
 
@@ -244,6 +305,8 @@ Example:
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_DSI>;
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
 			status = "disabled";
 		};
 	};
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index 96ab40131ae1..2b3af72dfb9c 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -47,6 +47,10 @@ Required properties:
   - fast-clk
   Tegra114:
   - div-clk
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2c
 
 Example:
 
@@ -58,5 +62,7 @@ Example:
 		#size-cells = <0>;
 		clocks = <&tegra_car 12>, <&tegra_car 124>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
index cc28d2194c37..83b14b6389fc 100644
--- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
@@ -15,6 +15,10 @@ Required properties:
   devicetree/bindings/input/matrix-keymap.txt.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - kbc
 
 Optional properties, in addition to those specified by the shared
 matrix-keyboard bindings:
@@ -34,6 +38,8 @@ keyboard: keyboard {
 	reg = <0x7000e200 0x100>;
 	interrupts = <0 85 0x04>;
 	clocks = <&tegra_car 36>;
+	resets = <&tegra_car 36>;
+	reset-names = "kbc";
 	nvidia,ghost-filter;
 	nvidia,debounce-delay-ms = <640>;
 	nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index f727902a9e8d..f357c16ea815 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -10,6 +10,10 @@ Required properties:
 - compatible : Should be "nvidia,<chip>-sdhci"
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - sdhci
 
 Optional properties:
 - power-gpios : Specify GPIOs for power control
@@ -21,6 +25,8 @@ sdhci@c8000200 {
 	reg = <0xc8000200 0x200>;
 	interrupts = <47>;
 	clocks = <&tegra_car 14>;
+	resets = <&tegra_car 14>;
+	reset-names = "sdhci";
 	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 	power-gpios = <&gpio 155 0>; /* gpio PT3 */
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
index a97fe575ca29..5ae601e7f51f 100644
--- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
+++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
@@ -15,3 +15,7 @@ Required properties:
   - fast-clk
   Tegra114:
   - div-clk
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2c
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index ad2eb9804afa..6d91016100b3 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -47,9 +47,14 @@ Required properties:
 - clock-names : Must include the following entries:
   - pex
   - afi
-  - pcie_xclk
   - pll_e
   - cml (not required for Tegra20)
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - pex
+  - afi
+  - pcie_x
 
 Root ports are defined as subnodes of the PCIe controller node.
 
@@ -91,9 +96,10 @@ SoC DTSI:
 			  0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */
 			  0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
 
-		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
-			 <&tegra_car 118>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
+		clock-names = "pex", "afi", "pll_e";
+		resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
 		pci@1,0 {
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index 0d608d34fed0..a65d4c3be231 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -9,6 +9,10 @@ Required properties:
   the cells format.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - pwm
 
 Example:
 
@@ -17,4 +21,6 @@ Example:
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car 17>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 	};
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index 39148b6236a1..69ccdbe3760e 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -8,6 +8,10 @@ Required properties:
   request selector for this UART controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - serial
 
 Optional properties:
 - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -23,5 +27,7 @@ serial@70006000 {
 	nvidia,dma-request-selector = <&apbdma 8>;
 	nvidia,enable-modem-interrupt;
 	clocks = <&tegra_car 6>;
+	resets = <&tegra_car 6>;
+	reset-names = "serial";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
index 37f4ebf5b184..2b6817f6e40e 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -6,6 +6,10 @@ Required properties:
 - interrupts : Should contain AC97 interrupt
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - ac97
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for the AC97 controller
 - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
@@ -23,4 +27,6 @@ ac97@70002000 {
 	nvidia,codec-reset-gpio = <&gpio 170 0>;
 	nvidia,codec-sync-gpio = <&gpio 120 0>;
 	clocks = <&tegra_car 3>;
+	resets = <&tegra_car 3>;
+	reset-names = "ac97";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
index ba0c9452916d..8b070aeca3db 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
@@ -6,6 +6,10 @@ Required properties:
 - interrupts : Should contain I2S interrupt
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2s
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this I2S controller
 
@@ -17,4 +21,6 @@ i2s@70002800 {
 	interrupts = < 45 >;
 	nvidia,dma-request-selector = < &apbdma 2 >;
 	clocks = <&tegra_car 11>;
+	resets = <&tegra_car 11>;
+	reset-names = "i2s";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 7299eeadd588..60d59a54ca07 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -15,6 +15,11 @@ Required properties:
 - clocks : Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
+  - d_audio
+  - apbif
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
   Tegra30 and later:
   - d_audio
   - apbif
@@ -26,7 +31,7 @@ Required properties:
   - dam0
   - dam1
   - dam2
-  - spdif_in
+  - spdif
   Tegra114 and later additionally require:
   - amx
   - adx
@@ -48,13 +53,15 @@ ahub@70080000 {
 	reg = <0x70080000 0x200 0x70080200 0x100>;
 	interrupts = < 0 103 0x04 >;
 	nvidia,dma-request-selector = <&apbdma 1>;
-	clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
+	clocks = <&tegra_car 106>, <&tegra_car 107>;
+	clock-names = "d_audio", "apbif";
+	resets = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
 		<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
 		<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
-		<&tegra_car 110>, <&tegra_car 162>;
-	clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+		<&tegra_car 110>, <&tegra_car 10>;
+	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 		"i2s3", "i2s4", "dam0", "dam1", "dam2",
-		"spdif_in";
+		"spdif";
 	ranges;
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
index 7a3112bc135c..0c113ffe3814 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
@@ -5,6 +5,10 @@ Required properties:
 - reg : Should contain I2S registers location and length
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2s
 - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback)
   first, tx (capture) second. See nvidia,tegra30-ahub.txt for values.
 
@@ -15,4 +19,6 @@ i2s@70080300 {
 	reg = <0x70080300 0x100>;
 	nvidia,ahub-cif-ids = <4 4>;
 	clocks = <&tegra_car 11>;
+	resets = <&tegra_car 11>;
+	reset-names = "i2s";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
index d4f2d534934b..fcd9f67999de 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
@@ -10,6 +10,10 @@ Required properties:
   See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
   - spi
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -26,5 +30,7 @@ spi@7000d600 {
 	#size-cells = <0>;
 	clocks = <&tegra_car 44>;
 	clock-names = "spi";
+	resets = <&tegra_car 44>;
+	reset-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
index 66e16c7f5939..e144f144717f 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -8,6 +8,10 @@ Required properties:
   request selector for this SFLASH controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -24,5 +28,7 @@ spi@7000c380 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 43>;
+	resets = <&tegra_car 43>;
+	reset-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
index 0e6e94eb2b2a..9393e28f444b 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -8,6 +8,10 @@ Required properties:
   request selector for this SLINK controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -24,5 +28,7 @@ spi@7000d600 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 44>;
+	resets = <&tegra_car 44>;
+	reset-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
index b98d0bdfa248..3dc9140e3dfb 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
@@ -10,6 +10,10 @@ Required properties :
  - nvidia,phy : phandle of the PHY that the controller is connected to.
  - clocks : Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
+ - resets : Must contain an entry for each entry in reset-names.
+   See ../reset/reset.txt for details.
+ - reset-names : Must include the following entries:
+   - usb
 
 Optional properties:
  - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
-- 
1.8.1.5

Re: [PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Thierry Reding]

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On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote:
[...]
> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
[...]
> +  - resets : Must contain an entry for each entry in reset-names.
> +    See ../reset/reset.txt for details.
> +  - reset-names : Must include the following entries:
> +    - dc

For consistency with this, the clock-names entry for the first clock in
this node should then be "dc" as well.

> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
[...]
> -  - spdif_in
> +  - spdif

Why is this renamed?

Thierry

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Re: [PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Stephen Warren]

On 11/29/2013 05:23 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote: 
> [...]
>> diff --git
>> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>
>> 
[...]
>> +  - resets : Must contain an entry for each entry in
>> reset-names. +    See ../reset/reset.txt for details. +  -
>> reset-names : Must include the following entries: +    - dc
> 
> For consistency with this, the clock-names entry for the first
> clock in this node should then be "dc" as well.

The dc driver gets the clock by name, so this isn't a requirement.

>> diff --git
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
>> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
>
>> 
[...]
>> -  - spdif_in +  - spdif
> 
> Why is this renamed?

There are two separate clocks for the SPDIF input and output modules,
but just a single reset.

Re: [PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1508 bytes --]

On Sun, Dec 01, 2013 at 12:06:49PM -0700, Stephen Warren wrote:
> On 11/29/2013 05:23 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote: 
> > [...]
> >> diff --git
> >> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >
> >> 
> [...]
> >> +  - resets : Must contain an entry for each entry in
> >> reset-names. +    See ../reset/reset.txt for details. +  -
> >> reset-names : Must include the following entries: +    - dc
> > 
> > For consistency with this, the clock-names entry for the first
> > clock in this node should then be "dc" as well.
> 
> The dc driver gets the clock by name, so this isn't a requirement.

Right, but like I've said in another reply, I'd very much like for this
to be fixed up so we don't have to mess around with per-instance names
for clocks. So instead of naming the first clock in the display
controller node "disp", we could rename it to "dc" for consistency with
the reset bindings.

> >> diff --git
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> >> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> >
> >> 
> [...]
> >> -  - spdif_in +  - spdif
> > 
> > Why is this renamed?
> 
> There are two separate clocks for the SPDIF input and output modules,
> but just a single reset.

I also realized that when reviewing one of the subsequent patches.

Thierry

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Re: [PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Stephen Warren]

On 12/02/2013 02:08 AM, Thierry Reding wrote:
> On Sun, Dec 01, 2013 at 12:06:49PM -0700, Stephen Warren wrote:
>> On 11/29/2013 05:23 AM, Thierry Reding wrote:
>>> On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote:
>>>  [...]
>>>> diff --git 
>>>> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>>>>
>>>> 
b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>>> 
>>>> 
>> [...]
>>>> +  - resets : Must contain an entry for each entry in 
>>>> reset-names. +    See ../reset/reset.txt for details. +  - 
>>>> reset-names : Must include the following entries: +    - dc
>>> 
>>> For consistency with this, the clock-names entry for the first 
>>> clock in this node should then be "dc" as well.
>> 
>> The dc driver gets the clock by name, so this isn't a
>> requirement.
> 
> Right, but like I've said in another reply, I'd very much like for
> this to be fixed up so we don't have to mess around with
> per-instance names for clocks. So instead of naming the first clock
> in the display controller node "disp", we could rename it to "dc"
> for consistency with the reset bindings.

I assume you're now OK with not changing the clock names, given my
explanation?

Re: [PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2606 bytes --]

On Tue, Dec 03, 2013 at 11:48:33AM -0700, Stephen Warren wrote:
> On 12/02/2013 02:08 AM, Thierry Reding wrote:
> > On Sun, Dec 01, 2013 at 12:06:49PM -0700, Stephen Warren wrote:
> >> On 11/29/2013 05:23 AM, Thierry Reding wrote:
> >>> On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote:
> >>>  [...]
> >>>> diff --git 
> >>>> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >>>>
> >>>> 
> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >>> 
> >>>> 
> >> [...]
> >>>> +  - resets : Must contain an entry for each entry in 
> >>>> reset-names. +    See ../reset/reset.txt for details. +  - 
> >>>> reset-names : Must include the following entries: +    - dc
> >>> 
> >>> For consistency with this, the clock-names entry for the first 
> >>> clock in this node should then be "dc" as well.
> >> 
> >> The dc driver gets the clock by name, so this isn't a
> >> requirement.
> > 
> > Right, but like I've said in another reply, I'd very much like for
> > this to be fixed up so we don't have to mess around with
> > per-instance names for clocks. So instead of naming the first clock
> > in the display controller node "disp", we could rename it to "dc"
> > for consistency with the reset bindings.
> 
> I assume you're now OK with not changing the clock names, given my
> explanation?

No. Rather I hope that I was able to clarify what I was aiming for. To
illustrate with another example: if we were to mirror the naming of the
clocks for the resets, the nodes would look like this:

	dc@54200000 {
		...
		clock-names = "disp1", "parent";
		...
		reset-names = "dc1";
	};

	dc@54240000 {
		...
		clock-names = "disp2", "parent";
		...
		reset-names = "dc2";
	};

Rather than what I proposed, which would be either:

	dc@54200000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "dc";
	};

	dc@54240000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "dc";
	};

Or this:

	dc@54200000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "disp";
	};

	dc@54240000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "disp";
	};

Or even this:

	dc@54200000 {
		...
		clock-names = "dc", "parent";
		...
		reset-names = "dc";
	};

	dc@54240000 {
		...
		clock-names = "dc", "parent";
		...
		reset-names = "dc";
	};

The display controller driver doesn't request the first clock by name,
so it doesn't really matter what it's called, but "disp1" and "disp2"
are just wrong in my opinion.

Thierry

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Update all the Tegra DT bindings to require the standard dmas/dma-names
properties rather than non-standard nvidia,dma-request-selector property.

This is a DT-ABI-incompatible change. It is the second of two changes
required for me to consider the Tegra DT bindings as stable, the other
being the previous conversion to the common reset bindings.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt     |  7 +++++++
 .../bindings/serial/nvidia,tegra20-hsuart.txt          | 10 +++++++---
 .../devicetree/bindings/sound/nvidia,tegra20-ac97.txt  | 14 +++++++++-----
 .../devicetree/bindings/sound/nvidia,tegra20-i2s.txt   | 14 +++++++++-----
 .../devicetree/bindings/sound/nvidia,tegra30-ahub.txt  | 18 +++++++++++++-----
 .../devicetree/bindings/spi/nvidia,tegra114-spi.txt    | 14 +++++++++-----
 .../devicetree/bindings/spi/nvidia,tegra20-sflash.txt  | 10 +++++++---
 .../devicetree/bindings/spi/nvidia,tegra20-slink.txt   | 10 +++++++---
 8 files changed, 68 insertions(+), 29 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index 2b3af72dfb9c..13a7f9dc1681 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -51,6 +51,11 @@ Required properties:
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - i2c
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Example:
 
@@ -64,5 +69,7 @@ Example:
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index 69ccdbe3760e..e2b18972a674 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 - reg: Should contain UART controller registers location and length.
 - interrupts: Should contain UART controller interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this UART controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - serial
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Optional properties:
 - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -24,10 +27,11 @@ serial@70006000 {
 	reg = <0x70006000 0x40>;
 	reg-shift = <2>;
 	interrupts = <0 36 0x04>;
-	nvidia,dma-request-selector = <&apbdma 8>;
 	nvidia,enable-modem-interrupt;
 	clocks = <&tegra_car 6>;
 	resets = <&tegra_car 6>;
 	reset-names = "serial";
+	dmas = <&apbdma 8>, <&apbdma 8>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
index 2b6817f6e40e..eaf00102d92c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : "nvidia,tegra20-ac97"
 - reg : Should contain AC97 controller registers location and length
 - interrupts : Should contain AC97 interrupt
-- clocks : Must contain one entry, for the module clock.
-  See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - ac97
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for the AC97 controller
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
   of the GPIO used to reset the external AC97 codec
 - nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
@@ -23,10 +26,11 @@ ac97@70002000 {
 	compatible = "nvidia,tegra20-ac97";
 	reg = <0x70002000 0x200>;
 	interrupts = <0 81 0x04>;
-	nvidia,dma-request-selector = <&apbdma 12>;
 	nvidia,codec-reset-gpio = <&gpio 170 0>;
 	nvidia,codec-sync-gpio = <&gpio 120 0>;
 	clocks = <&tegra_car 3>;
 	resets = <&tegra_car 3>;
 	reset-names = "ac97";
+	dmas = <&apbdma 12>, <&apbdma 12>;
+	dma-names = "rx", "tx";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
index 8b070aeca3db..dc30c6bfbe95 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : "nvidia,tegra20-i2s"
 - reg : Should contain I2S registers location and length
 - interrupts : Should contain I2S interrupt
-- clocks : Must contain one entry, for the module clock.
-  See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - i2s
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this I2S controller
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -19,8 +22,9 @@ i2s@70002800 {
 	compatible = "nvidia,tegra20-i2s";
 	reg = <0x70002800 0x200>;
 	interrupts = < 45 >;
-	nvidia,dma-request-selector = < &apbdma 2 >;
 	clocks = <&tegra_car 11>;
 	resets = <&tegra_car 11>;
 	reset-names = "i2s";
+	dmas = <&apbdma 21>, <&apbdma 21>;
+	dma-names = "rx", "tx";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 60d59a54ca07..3376ba42a209 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -7,11 +7,6 @@ Required properties:
   - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
   - Tegra114 requires an additional entry, for the APBIF2 register block.
 - interrupts : Should contain AHUB interrupt
-- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each
-  entry contains the Tegra DMA controller's phandle and request selector.
-  If a single entry is present, the request selectors for the channels are
-  assumed to be contiguous, and increment from this value.
-  If multiple values are given, one value must be given per channel.
 - clocks : Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
@@ -36,6 +31,14 @@ Required properties:
   - amx
   - adx
 - ranges : The bus address mapping for the configlink register bus.
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx0 .. rx<n>
+  - tx0 .. tx<n>
+  ... where n is:
+  Tegra30: 3
+  Tegra114, Tegra124: 9
   Can be empty since the mapping is 1:1.
 - #address-cells : For the configlink bus. Should be <1>;
 - #size-cells : For the configlink bus. Should be <1>.
@@ -62,6 +65,11 @@ ahub@70080000 {
 	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 		"i2s3", "i2s4", "dam0", "dam1", "dam2",
 		"spdif";
+	dmas = <&apbdma 1>, <&apbdma 1>;
+	       <&apbdma 2>, <&apbdma 2>;
+	       <&apbdma 3>, <&apbdma 3>;
+	       <&apbdma 4>, <&apbdma 4>;
+	dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3";
 	ranges;
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
index fcd9f67999de..7ea701e07dc2 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
@@ -4,16 +4,19 @@ Required properties:
 - compatible : should be "nvidia,tegra114-spi".
 - reg: Should contain SPI registers location and length.
 - interrupts: Should contain SPI interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SPI controller.
-- clocks : Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
   - spi
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - spi
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -24,7 +27,6 @@ spi@7000d600 {
 	compatible = "nvidia,tegra114-spi";
 	reg = <0x7000d600 0x200>;
 	interrupts = <0 82 0x04>;
-	nvidia,dma-request-selector = <&apbdma 16>;
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -32,5 +34,7 @@ spi@7000d600 {
 	clock-names = "spi";
 	resets = <&tegra_car 44>;
 	reset-names = "spi";
+	dmas = <&apbdma 16>, <&apbdma 16>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
index e144f144717f..bdf08e6dec9b 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : should be "nvidia,tegra20-sflash".
 - reg: Should contain SFLASH registers location and length.
 - interrupts: Should contain SFLASH interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SFLASH controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - spi
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -23,12 +26,13 @@ spi@7000c380 {
 	compatible = "nvidia,tegra20-sflash";
 	reg = <0x7000c380 0x80>;
 	interrupts = <0 39 0x04>;
-	nvidia,dma-request-selector = <&apbdma 16>;
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 43>;
 	resets = <&tegra_car 43>;
 	reset-names = "spi";
+	dmas = <&apbdma 11>, <&apbdma 11>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
index 9393e28f444b..5db9144a33c8 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".
 - reg: Should contain SLINK registers location and length.
 - interrupts: Should contain SLINK interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SLINK controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - spi
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -23,12 +26,13 @@ spi@7000d600 {
 	compatible = "nvidia,tegra20-slink";
 	reg = <0x7000d600 0x200>;
 	interrupts = <0 82 0x04>;
-	nvidia,dma-request-selector = <&apbdma 16>;
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 44>;
 	resets = <&tegra_car 44>;
 	reset-names = "spi";
+	dmas = <&apbdma 16>, <&apbdma 16>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
-- 
1.8.1.5

Re: [PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 6402 bytes --]

On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote:
[...]
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> index 2b6817f6e40e..eaf00102d92c 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> @@ -4,14 +4,17 @@ Required properties:
>  - compatible : "nvidia,tegra20-ac97"
>  - reg : Should contain AC97 controller registers location and length
>  - interrupts : Should contain AC97 interrupt
> -- clocks : Must contain one entry, for the module clock.
> -  See ../clocks/clock-bindings.txt for details.
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - ac97
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for the AC97 controller
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx
> +  - tx
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.

Was this unintentionally moved?

> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> index 8b070aeca3db..dc30c6bfbe95 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> @@ -4,14 +4,17 @@ Required properties:
>  - compatible : "nvidia,tegra20-i2s"
>  - reg : Should contain I2S registers location and length
>  - interrupts : Should contain I2S interrupt
> -- clocks : Must contain one entry, for the module clock.
> -  See ../clocks/clock-bindings.txt for details.
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - i2s
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for this I2S controller
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx
> +  - tx
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.

This too?

> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> index 60d59a54ca07..3376ba42a209 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> @@ -7,11 +7,6 @@ Required properties:
>    - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
>    - Tegra114 requires an additional entry, for the APBIF2 register block.
>  - interrupts : Should contain AHUB interrupt
> -- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each
> -  entry contains the Tegra DMA controller's phandle and request selector.
> -  If a single entry is present, the request selectors for the channels are
> -  assumed to be contiguous, and increment from this value.
> -  If multiple values are given, one value must be given per channel.
>  - clocks : Must contain an entry for each entry in clock-names.
>    See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> @@ -36,6 +31,14 @@ Required properties:
>    - amx
>    - adx
>  - ranges : The bus address mapping for the configlink register bus.
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx0 .. rx<n>
> +  - tx0 .. tx<n>
> +  ... where n is:
> +  Tegra30: 3
> +  Tegra114, Tegra124: 9
>    Can be empty since the mapping is 1:1.

I think this line belongs to the description of the "ranges" property.

> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> index fcd9f67999de..7ea701e07dc2 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> @@ -4,16 +4,19 @@ Required properties:
>  - compatible : should be "nvidia,tegra114-spi".
>  - reg: Should contain SPI registers location and length.
>  - interrupts: Should contain SPI interrupts.
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for this SPI controller.
> -- clocks : Must contain an entry for each entry in clock-names.
> -  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
>    - spi
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - spi
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx
> +  - tx
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.

Another accidental move? I beginning to think there might be a pattern
to this, but I haven't figured it out yet.

> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> index e144f144717f..bdf08e6dec9b 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> @@ -4,14 +4,17 @@ Required properties:
>  - compatible : should be "nvidia,tegra20-sflash".
>  - reg: Should contain SFLASH registers location and length.
>  - interrupts: Should contain SFLASH interrupts.
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for this SFLASH controller.
>  - clocks : Must contain one entry, for the module clock.

But then this doesn't move it... perhaps it really is accidental in
other places. =)

Thierry

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Re: [PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Stephen Warren]

On 11/29/2013 05:29 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote: 
> [...]
>> diff --git
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>>
>> 
index 2b6817f6e40e..eaf00102d92c 100644
>> ---
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>>
>> 
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>> @@ -4,14 +4,17 @@ Required properties: - compatible :
>> "nvidia,tegra20-ac97" - reg : Should contain AC97 controller
>> registers location and length - interrupts : Should contain AC97
>> interrupt -- clocks : Must contain one entry, for the module
>> clock. -  See ../clocks/clock-bindings.txt for details. - resets
>> : Must contain an entry for each entry in reset-names. See
>> ../reset/reset.txt for details. - reset-names : Must include the
>> following entries: - ac97 -- nvidia,dma-request-selector : The
>> Tegra DMA controller's phandle and -  request selector for the
>> AC97 controller +- dmas : Must contain an entry for each entry in
>> clock-names. +  See ../dma/dma.txt for details. +- dma-names :
>> Must include the following entries: +  - rx +  - tx +- clocks :
>> Must contain one entry, for the module clock. +  See
>> ../clocks/clock-bindings.txt for details.
> 
> Was this unintentionally moved?

IIRC, at the end of the series, each binding describes reg,
interrupts, clocks, reset, dmas in that order, for consistency.

>> diff --git
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>>
>> 
index e144f144717f..bdf08e6dec9b 100644
>> ---
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>>
>> 
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>> @@ -4,14 +4,17 @@ Required properties: - compatible : should be
>> "nvidia,tegra20-sflash". - reg: Should contain SFLASH registers
>> location and length. - interrupts: Should contain SFLASH
>> interrupts. -- nvidia,dma-request-selector : The Tegra DMA
>> controller's phandle and -  request selector for this SFLASH
>> controller. - clocks : Must contain one entry, for the module
>> clock.
> 
> But then this doesn't move it... perhaps it really is accidental
> in other places. =)

The patch to that file does move the docs for the dmas property...

Re: [PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2973 bytes --]

On Sun, Dec 01, 2013 at 12:09:51PM -0700, Stephen Warren wrote:
> On 11/29/2013 05:29 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote: 
> > [...]
> >> diff --git
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >>
> >> 
> index 2b6817f6e40e..eaf00102d92c 100644
> >> ---
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >>
> >> 
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >> @@ -4,14 +4,17 @@ Required properties: - compatible :
> >> "nvidia,tegra20-ac97" - reg : Should contain AC97 controller
> >> registers location and length - interrupts : Should contain AC97
> >> interrupt -- clocks : Must contain one entry, for the module
> >> clock. -  See ../clocks/clock-bindings.txt for details. - resets
> >> : Must contain an entry for each entry in reset-names. See
> >> ../reset/reset.txt for details. - reset-names : Must include the
> >> following entries: - ac97 -- nvidia,dma-request-selector : The
> >> Tegra DMA controller's phandle and -  request selector for the
> >> AC97 controller +- dmas : Must contain an entry for each entry in
> >> clock-names. +  See ../dma/dma.txt for details. +- dma-names :
> >> Must include the following entries: +  - rx +  - tx +- clocks :
> >> Must contain one entry, for the module clock. +  See
> >> ../clocks/clock-bindings.txt for details.
> > 
> > Was this unintentionally moved?
> 
> IIRC, at the end of the series, each binding describes reg,
> interrupts, clocks, reset, dmas in that order, for consistency.

Okay, that's fine then. I was just making sure this hadn't slipped
through the cracks.

> >> diff --git
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >>
> >> 
> index e144f144717f..bdf08e6dec9b 100644
> >> ---
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >>
> >> 
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >> @@ -4,14 +4,17 @@ Required properties: - compatible : should be
> >> "nvidia,tegra20-sflash". - reg: Should contain SFLASH registers
> >> location and length. - interrupts: Should contain SFLASH
> >> interrupts. -- nvidia,dma-request-selector : The Tegra DMA
> >> controller's phandle and -  request selector for this SFLASH
> >> controller. - clocks : Must contain one entry, for the module
> >> clock.
> > 
> > But then this doesn't move it... perhaps it really is accidental
> > in other places. =)
> 
> The patch to that file does move the docs for the dmas property...

My point was that the clocks and clock-names properties didn't move like
they did for other hunks. But if all those changes end up making the
bindings documentation more consistent, then I'm all for it.

Thierry

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Re: [PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Stephen Warren]

On 11/29/2013 05:29 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote:

>> diff --git
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
>> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt

>>
>> 
- ranges : The bus address mapping for the configlink register bus.
>> +- dmas : Must contain an entry for each entry in clock-names. +
>> See ../dma/dma.txt for details. +- dma-names : Must include the
>> following entries: +  - rx0 .. rx<n> +  - tx0 .. tx<n> +  ...
>> where n is: +  Tegra30: 3 +  Tegra114, Tegra124: 9 Can be empty
>> since the mapping is 1:1.
> 
> I think this line belongs to the description of the "ranges"
> property.

Yes, I've fixed that up locally simply by moving the inserted lines 1
line lower. I assume you don't want a repost for that?

Re: [PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1005 bytes --]

On Tue, Dec 03, 2013 at 11:52:23AM -0700, Stephen Warren wrote:
> On 11/29/2013 05:29 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote:
> 
> >> diff --git
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> >> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> 
> >>
> >> 
> - ranges : The bus address mapping for the configlink register bus.
> >> +- dmas : Must contain an entry for each entry in clock-names. +
> >> See ../dma/dma.txt for details. +- dma-names : Must include the
> >> following entries: +  - rx0 .. rx<n> +  - tx0 .. tx<n> +  ...
> >> where n is: +  Tegra30: 3 +  Tegra114, Tegra124: 9 Can be empty
> >> since the mapping is 1:1.
> > 
> > I think this line belongs to the description of the "ranges"
> > property.
> 
> Yes, I've fixed that up locally simply by moving the inserted lines 1
> line lower. I assume you don't want a repost for that?

No need for a repost.

Thierry

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[PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

An earlier patch updated the Tegra DT bindings to require resets and
reset-names properties to be filled in. This patch updates the DT files
to include those properties.

Note that any legacy clocks and clock-names entries that are replaced by
reset properties are not yet removed; the drivers must be updated to use
the new resets and reset-names properties first.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/tegra114.dtsi     |  83 ++++++++++++++++++++++++++--
 arch/arm/boot/dts/tegra20-paz00.dts |   2 +
 arch/arm/boot/dts/tegra20.dtsi      |  81 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra30.dtsi      | 104 ++++++++++++++++++++++++++++++++++++
 4 files changed, 266 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 8d42787c8ff1..c40dbdcb3741 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -43,6 +43,7 @@
 		compatible = "nvidia,tegra114-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	apbdma: dma {
@@ -81,6 +82,8 @@
 			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
 	};
 
 	ahb: ahb {
@@ -125,8 +128,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	uartb: serial@70006040 {
@@ -135,8 +140,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	uartc: serial@70006200 {
@@ -145,8 +152,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	uartd: serial@70006300 {
@@ -155,8 +164,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	pwm: pwm {
@@ -164,6 +175,8 @@
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA114_CLK_PWM>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 		status = "disabled";
 	};
 
@@ -175,6 +188,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -186,6 +201,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -197,6 +214,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -208,6 +227,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 103>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -219,6 +240,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -231,6 +254,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 		clock-names = "spi";
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -243,6 +268,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 		clock-names = "spi";
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -255,6 +282,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 		clock-names = "spi";
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -267,6 +296,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 		clock-names = "spi";
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -279,6 +310,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 		clock-names = "spi";
+		resets = <&tegra_car 104>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -291,6 +324,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 		clock-names = "spi";
+		resets = <&tegra_car 105>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -306,6 +341,8 @@
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_KBC>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
 		status = "disabled";
 	};
 
@@ -353,6 +390,22 @@
 		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif_in", "amx", "adx";
+		resets = <&tegra_car 106>, /* d_audio */
+			 <&tegra_car 107>, /* apbif */
+			 <&tegra_car 30>,  /* i2s0 */
+			 <&tegra_car 11>,  /* i2s1 */
+			 <&tegra_car 18>,  /* i2s2 */
+			 <&tegra_car 101>, /* i2s3 */
+			 <&tegra_car 102>, /* i2s4 */
+			 <&tegra_car 108>, /* dam0 */
+			 <&tegra_car 109>, /* dam1 */
+			 <&tegra_car 110>, /* dam2 */
+			 <&tegra_car 10>,  /* spdif */
+			 <&tegra_car 153>, /* amx */
+			 <&tegra_car 154>; /* adx */
+		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
+			      "spdif", "amx", "adx";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -362,6 +415,8 @@
 			reg = <0x70080300 0x100>;
 			nvidia,ahub-cif-ids = <4 4>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S0>;
+			resets = <&tegra_car 30>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -370,6 +425,8 @@
 			reg = <0x70080400 0x100>;
 			nvidia,ahub-cif-ids = <5 5>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S1>;
+			resets = <&tegra_car 11>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -378,6 +435,8 @@
 			reg = <0x70080500 0x100>;
 			nvidia,ahub-cif-ids = <6 6>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S2>;
+			resets = <&tegra_car 18>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -386,6 +445,8 @@
 			reg = <0x70080600 0x100>;
 			nvidia,ahub-cif-ids = <7 7>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S3>;
+			resets = <&tegra_car 101>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -394,6 +455,8 @@
 			reg = <0x70080700 0x100>;
 			nvidia,ahub-cif-ids = <8 8>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S4>;
+			resets = <&tegra_car 102>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 	};
@@ -403,6 +466,8 @@
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -411,6 +476,8 @@
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -419,6 +486,8 @@
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -427,6 +496,8 @@
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -436,6 +507,8 @@
 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA114_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
 		nvidia,phy = <&phy1>;
 		status = "disabled";
 	};
@@ -467,6 +540,8 @@
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA114_CLK_USB3>;
+		resets = <&tegra_car 59>;
+		reset-names = "usb";
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 8d71fc9d8a2f..e57fb3aefc2a 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -280,6 +280,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 		       	 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 	};
 
 	i2c@7000d000 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index df40b54fd8bc..159facbce524 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -22,6 +22,8 @@
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -33,6 +35,8 @@
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_MPE>;
+			resets = <&tegra_car 60>;
+			reset-names = "mpe";
 		};
 
 		vi {
@@ -40,6 +44,8 @@
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_VI>;
+			resets = <&tegra_car 100>;
+			reset-names = "vi";
 		};
 
 		epp {
@@ -47,6 +53,8 @@
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_EPP>;
+			resets = <&tegra_car 19>;
+			reset-names = "epp";
 		};
 
 		isp {
@@ -54,6 +62,8 @@
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_ISP>;
+			resets = <&tegra_car 23>;
+			reset-names = "isp";
 		};
 
 		gr2d {
@@ -61,12 +71,16 @@
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+			resets = <&tegra_car 21>;
+			reset-names = "2d";
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+			resets = <&tegra_car 24>;
+			reset-names = "3d";
 		};
 
 		dc@54200000 {
@@ -76,6 +90,8 @@
 			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -89,6 +105,8 @@
 			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -102,6 +120,8 @@
 			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 			clock-names = "hdmi", "parent";
+			resets = <&tegra_car 51>;
+			reset-names = "hdmi";
 			status = "disabled";
 		};
 
@@ -117,6 +137,8 @@
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_DSI>;
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
 			status = "disabled";
 		};
 	};
@@ -160,6 +182,7 @@
 		compatible = "nvidia,tegra20-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	apbdma: dma {
@@ -182,6 +205,8 @@
 			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
 	};
 
 	ahb {
@@ -224,6 +249,8 @@
 		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 12>;
 		clocks = <&tegra_car TEGRA20_CLK_AC97>;
+		resets = <&tegra_car 3>;
+		reset-names = "ac97";
 		status = "disabled";
 	};
 
@@ -233,6 +260,8 @@
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 2>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
+		resets = <&tegra_car 11>;
+		reset-names = "i2s";
 		status = "disabled";
 	};
 
@@ -242,6 +271,8 @@
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
+		resets = <&tegra_car 18>;
+		reset-names = "i2s";
 		status = "disabled";
 	};
 
@@ -259,6 +290,8 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -269,6 +302,8 @@
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -279,6 +314,8 @@
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -289,6 +326,8 @@
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -299,6 +338,8 @@
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
+		resets = <&tegra_car 66>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -307,6 +348,8 @@
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA20_CLK_PWM>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 		status = "disabled";
 	};
 
@@ -326,6 +369,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -337,6 +382,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SPI>;
+		resets = <&tegra_car 43>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -349,6 +396,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -361,6 +410,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -373,6 +424,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_DVC>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -384,6 +437,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -395,6 +450,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -406,6 +463,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -417,6 +476,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -425,6 +486,8 @@
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_KBC>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
 		status = "disabled";
 	};
 
@@ -481,6 +544,10 @@
 			 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
 			 <&tegra_car TEGRA20_CLK_PLL_E>;
 		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		resets = <&tegra_car 70>,
+		         <&tegra_car 72>,
+		         <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
 		pci@1,0 {
@@ -517,6 +584,8 @@
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
 		clocks = <&tegra_car TEGRA20_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
 		nvidia,needs-double-reset;
 		nvidia,phy = <&phy1>;
 		status = "disabled";
@@ -548,6 +617,8 @@
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
 		clocks = <&tegra_car TEGRA20_CLK_USB2>;
+		resets = <&tegra_car 58>;
+		reset-names = "usb";
 		nvidia,phy = <&phy2>;
 		status = "disabled";
 	};
@@ -569,6 +640,8 @@
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA20_CLK_USB3>;
+		resets = <&tegra_car 59>;
+		reset-names = "usb";
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
@@ -597,6 +670,8 @@
 		reg = <0xc8000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -605,6 +680,8 @@
 		reg = <0xc8000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -613,6 +690,8 @@
 		reg = <0xc8000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -621,6 +700,8 @@
 		reg = <0xc8000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 2bd55cfd88ad..95635e54bd34 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -44,6 +44,10 @@
 			 <&tegra_car TEGRA30_CLK_PLL_E>,
 			 <&tegra_car TEGRA30_CLK_CML0>;
 		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+		resets = <&tegra_car 70>,
+		         <&tegra_car 72>,
+		         <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
 		pci@1,0 {
@@ -92,6 +96,8 @@
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 		clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -103,6 +109,8 @@
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_MPE>;
+			resets = <&tegra_car 60>;
+			reset-names = "mpe";
 		};
 
 		vi {
@@ -110,6 +118,8 @@
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_VI>;
+			resets = <&tegra_car 164>;
+			reset-names = "vi";
 		};
 
 		epp {
@@ -117,6 +127,8 @@
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_EPP>;
+			resets = <&tegra_car 19>;
+			reset-names = "epp";
 		};
 
 		isp {
@@ -124,12 +136,16 @@
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_ISP>;
+			resets = <&tegra_car 23>;
+			reset-names = "isp";
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra30-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&tegra_car 21>;
+			reset-names = "2d";
 			clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 		};
 
@@ -139,6 +155,9 @@
 			clocks = <&tegra_car TEGRA30_CLK_GR3D
 				  &tegra_car TEGRA30_CLK_GR3D2>;
 			clock-names = "3d", "3d2";
+			resets = <&tegra_car 24>,
+			         <&tegra_car 98>;
+			reset-names = "3d", "3d2";
 		};
 
 		dc@54200000 {
@@ -148,6 +167,8 @@
 			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 				 <&tegra_car TEGRA30_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -161,6 +182,8 @@
 			clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 				 <&tegra_car TEGRA30_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -174,6 +197,8 @@
 			clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 				 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 			clock-names = "hdmi", "parent";
+			resets = <&tegra_car 51>;
+			reset-names = "hdmi";
 			status = "disabled";
 		};
 
@@ -189,6 +214,8 @@
 			compatible = "nvidia,tegra30-dsi";
 			reg = <0x54300000 0x00040000>;
 			clocks = <&tegra_car TEGRA30_CLK_DSIA>;
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
 			status = "disabled";
 		};
 	};
@@ -234,6 +261,7 @@
 		compatible = "nvidia,tegra30-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	apbdma: dma {
@@ -272,6 +300,8 @@
 			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
 	};
 
 	ahb: ahb {
@@ -317,6 +347,8 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -327,6 +359,8 @@
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -337,6 +371,8 @@
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -347,6 +383,8 @@
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -357,6 +395,8 @@
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
+		resets = <&tegra_car 66>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -365,6 +405,8 @@
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA30_CLK_PWM>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 		status = "disabled";
 	};
 
@@ -384,6 +426,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -396,6 +440,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -408,6 +454,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -419,6 +467,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
+		resets = <&tegra_car 103>;
+		reset-names = "i2c";
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -432,6 +482,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -443,6 +495,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -454,6 +508,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -465,6 +521,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -476,6 +534,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -487,6 +547,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
+		resets = <&tegra_car 104>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -498,6 +560,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
+		resets = <&tegra_car 106>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -506,6 +570,8 @@
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_KBC>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
 		status = "disabled";
 	};
 
@@ -555,6 +621,20 @@
 		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif_in";
+		resets = <&tegra_car 106>, /* d_audio */
+			 <&tegra_car 107>, /* apbif */
+			 <&tegra_car 30>,  /* i2s0 */
+			 <&tegra_car 11>,  /* i2s1 */
+			 <&tegra_car 18>,  /* i2s2 */
+			 <&tegra_car 101>, /* i2s3 */
+			 <&tegra_car 102>, /* i2s4 */
+			 <&tegra_car 108>, /* dam0 */
+			 <&tegra_car 109>, /* dam1 */
+			 <&tegra_car 110>, /* dam2 */
+			 <&tegra_car 10>;  /* spdif */
+		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
+			      "spdif";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -564,6 +644,8 @@
 			reg = <0x70080300 0x100>;
 			nvidia,ahub-cif-ids = <4 4>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S0>;
+			resets = <&tegra_car 30>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -572,6 +654,8 @@
 			reg = <0x70080400 0x100>;
 			nvidia,ahub-cif-ids = <5 5>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S1>;
+			resets = <&tegra_car 11>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -580,6 +664,8 @@
 			reg = <0x70080500 0x100>;
 			nvidia,ahub-cif-ids = <6 6>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S2>;
+			resets = <&tegra_car 18>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -588,6 +674,8 @@
 			reg = <0x70080600 0x100>;
 			nvidia,ahub-cif-ids = <7 7>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S3>;
+			resets = <&tegra_car 101>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -596,6 +684,8 @@
 			reg = <0x70080700 0x100>;
 			nvidia,ahub-cif-ids = <8 8>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S4>;
+			resets = <&tegra_car 102>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 	};
@@ -605,6 +695,8 @@
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -613,6 +705,8 @@
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -621,6 +715,8 @@
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -629,6 +725,8 @@
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -638,6 +736,8 @@
 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA30_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
 		nvidia,needs-double-reset;
 		nvidia,phy = <&phy1>;
 		status = "disabled";
@@ -671,6 +771,8 @@
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
 		clocks = <&tegra_car TEGRA30_CLK_USB2>;
+		resets = <&tegra_car 58>;
+		reset-names = "usb";
 		nvidia,phy = <&phy2>;
 		status = "disabled";
 	};
@@ -692,6 +794,8 @@
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA30_CLK_USB3>;
+		resets = <&tegra_car 59>;
+		reset-names = "usb";
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
-- 
1.8.1.5

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Re: [PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1758 bytes --]

On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote:
[...]
> @@ -135,8 +140,10 @@
>  		reg-shift = <2>;
>  		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
>  		nvidia,dma-request-selector = <&apbdma 9>;
> -		status = "disabled";
>  		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
> +		resets = <&tegra_car 7>;

This is confusing. For some reason that escapes me the tegra114-car.h
file defines TEGRA114_CLK_UARTB as 192. Other reset entries match the
numerical value of the TEGRA114_CLK_* define, which makes it easy to
double-check this.

But UARTB is indeed at bit 7, so this looks good.

Oh, I think perhaps it's caused by bit 7 being shared by both the UARTB
and the VFIR controllers for reset, but not for the clocks.

>  			reg = <0x70080300 0x100>;
>  			nvidia,ahub-cif-ids = <4 4>;
>  			clocks = <&tegra_car TEGRA114_CLK_I2S0>;

The clocks for these i2s devices are already listed in the ahub node. Is
that on purpose?

> @@ -110,6 +118,8 @@
>  			reg = <0x54080000 0x00040000>;
>  			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&tegra_car TEGRA30_CLK_VI>;
> +			resets = <&tegra_car 164>;

I think this needs to be 20.

> @@ -139,6 +155,9 @@
>  			clocks = <&tegra_car TEGRA30_CLK_GR3D
>  				  &tegra_car TEGRA30_CLK_GR3D2>;
>  			clock-names = "3d", "3d2";
> +			resets = <&tegra_car 24>,

For some reason bit 24 is missing from the register definition. Given
that this has worked before I suppose either the documentation is stale
or it's not necessary to take this module out of reset.

> +			 <&tegra_car 30>,  /* i2s0 */
> +			 <&tegra_car 11>,  /* i2s1 */
> +			 <&tegra_car 18>,  /* i2s2 */
> +			 <&tegra_car 101>, /* i2s3 */
> +			 <&tegra_car 102>, /* i2s4 */

Some comment for these as for Tegra20.

Thierry

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Re: [PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Stephen Warren]

On 11/29/2013 06:00 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote: 
> [...]
>> @@ -135,8 +140,10 @@ reg-shift = <2>; interrupts = <GIC_SPI 37
>> IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 9>; 
>> -		status = "disabled"; clocks = <&tegra_car
>> TEGRA114_CLK_UARTB>; +		resets = <&tegra_car 7>;
> 
> This is confusing. For some reason that escapes me the
> tegra114-car.h file defines TEGRA114_CLK_UARTB as 192. Other reset
> entries match the numerical value of the TEGRA114_CLK_* define,
> which makes it easy to double-check this.
> 
> But UARTB is indeed at bit 7, so this looks good.
> 
> Oh, I think perhaps it's caused by bit 7 being shared by both the
> UARTB and the VFIR controllers for reset, but not for the clocks.

Yes, there's a single reset bit that affects 2 HW modules, yet each HW
module has its own clock. So the reset and clock IDs don't exactly
align. That's the main reason I wanted to switch the drivers to the
reset framework rather than piggy-backing on the clock framework to do
resets, so the difference in name-spaces is explicit.

>> reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks =
>> <&tegra_car TEGRA114_CLK_I2S0>;
> 
> The clocks for these i2s devices are already listed in the ahub
> node. Is that on purpose?

Yes.

The AHUB driver needs to remove reset from the HW modules, so that the
configlink bus works. Reset removal used to require a custom Tegra API
that took a clock as a parameter. Hence, the AHUB node needed the
clock reference. After this series, the AHUB only needs a reset handle
to use the standard reset API. However, the clock references are left
in the AHUB node until after the AHUB driver is converted, so the
series is bisectable. After the series, only the I2S driver needs to
clock references.

>> @@ -110,6 +118,8 @@ reg = <0x54080000 0x00040000>; interrupts =
>> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car
>> TEGRA30_CLK_VI>; +			resets = <&tegra_car 164>;
> 
> I think this needs to be 20.

OK, I'll check that when I get back...

>> +			 <&tegra_car 30>,  /* i2s0 */ +			 <&tegra_car 11>,  /* i2s1
>> */ +			 <&tegra_car 18>,  /* i2s2 */ +			 <&tegra_car 101>, /*
>> i2s3 */ +			 <&tegra_car 102>, /* i2s4 */
> 
> Some comment for these as for Tegra20.

I'm not sure which other comment was "for Tegra20", since none of the
filenames were quoted, but I'll try to check when I get back.

Re: [PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1586 bytes --]

On Sun, Dec 01, 2013 at 12:15:07PM -0700, Stephen Warren wrote:
> On 11/29/2013 06:00 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote: 
[...]
> >> reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks =
> >> <&tegra_car TEGRA114_CLK_I2S0>;
> > 
> > The clocks for these i2s devices are already listed in the ahub
> > node. Is that on purpose?
> 
> Yes.
> 
> The AHUB driver needs to remove reset from the HW modules, so that the
> configlink bus works. Reset removal used to require a custom Tegra API
> that took a clock as a parameter. Hence, the AHUB node needed the
> clock reference. After this series, the AHUB only needs a reset handle
> to use the standard reset API. However, the clock references are left
> in the AHUB node until after the AHUB driver is converted, so the
> series is bisectable. After the series, only the I2S driver needs to
> clock references.
[...]
> >> +			 <&tegra_car 30>,  /* i2s0 */ +			 <&tegra_car 11>,  /* i2s1
> >> */ +			 <&tegra_car 18>,  /* i2s2 */ +			 <&tegra_car 101>, /*
> >> i2s3 */ +			 <&tegra_car 102>, /* i2s4 */
> > 
> > Some comment for these as for Tegra20.
> 
> I'm not sure which other comment was "for Tegra20", since none of the
> filenames were quoted, but I'll try to check when I get back.

Indeed. I didn't quote the filenames. =( And I typoed Tegra114 as
Tegra20. I was referring to the "I2S clocks are listed in both the AHUB
and I2S nodes" comment above for Tegra114. From your earlier reply,
though this looks good then.

Thierry

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Re: [PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Stephen Warren]

On 11/29/2013 06:00 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote:
...
>> @@ -110,6 +118,8 @@ reg = <0x54080000 0x00040000>; interrupts =
>> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car
>> TEGRA30_CLK_VI>; +			resets = <&tegra_car 164>;
> 
> I think this needs to be 20.

Yes, I've fixed that to be 20 in both tegra20.dtsi and tegra30.dtsi in
this patch.

[PATCH 05/31] ARM: tegra: update DT files to add DMA properties

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

This patch switches the Tegra DT files to use the standard DMA DT bindings
rather than custom properties. Note that the legacy properties are not yet
removed; the drivers must be updated to use the new properties first.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/tegra114.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra20.dtsi  | 35 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra30.dtsi  | 39 +++++++++++++++++++++++++++++++++++
 3 files changed, 119 insertions(+)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index c40dbdcb3741..b4f2e62909a7 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -84,6 +84,7 @@
 		clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 		resets = <&tegra_car 34>;
 		reset-names = "dma";
+		#dma-cells = <1>;
 	};
 
 	ahb: ahb {
@@ -131,6 +132,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -143,6 +146,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -155,6 +160,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -167,6 +174,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -190,6 +199,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -203,6 +214,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 54>;
 		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -216,6 +229,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -229,6 +244,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 103>;
 		reset-names = "i2c";
+		dmas = <&apbdma 26>, <&apbdma 26>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -242,6 +259,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 47>;
 		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -256,6 +275,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 41>;
 		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -270,6 +291,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 44>;
 		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -284,6 +307,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 46>;
 		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -298,6 +323,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 68>;
 		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -312,6 +339,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 104>;
 		reset-names = "spi";
+		dmas = <&apbdma 27>, <&apbdma 27>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -326,6 +355,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 105>;
 		reset-names = "spi";
+		dmas = <&apbdma 28>, <&apbdma 28>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -406,6 +437,20 @@
 		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif", "amx", "adx";
+		dmas = <&apbdma 1>, <&apbdma 1>,
+		       <&apbdma 2>, <&apbdma 2>,
+		       <&apbdma 3>, <&apbdma 3>,
+		       <&apbdma 4>, <&apbdma 4>,
+		       <&apbdma 6>, <&apbdma 6>,
+		       <&apbdma 7>, <&apbdma 7>,
+		       <&apbdma 12>, <&apbdma 12>,
+		       <&apbdma 13>, <&apbdma 13>,
+		       <&apbdma 14>, <&apbdma 14>,
+		       <&apbdma 29>, <&apbdma 29>;
+		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+			    "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
+			    "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
+			    "rx9", "tx9";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 159facbce524..c53e02e08310 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -207,6 +207,7 @@
 		clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 		resets = <&tegra_car 34>;
 		reset-names = "dma";
+		#dma-cells = <1>;
 	};
 
 	ahb {
@@ -251,6 +252,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_AC97>;
 		resets = <&tegra_car 3>;
 		reset-names = "ac97";
+		dmas = <&apbdma 12>, <&apbdma 12>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -262,6 +265,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 		resets = <&tegra_car 11>;
 		reset-names = "i2s";
+		dmas = <&apbdma 2>, <&apbdma 2>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -273,6 +278,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 		resets = <&tegra_car 18>;
 		reset-names = "i2s";
+		dmas = <&apbdma 1>, <&apbdma 1>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -292,6 +299,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -304,6 +313,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -316,6 +327,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -328,6 +341,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -340,6 +355,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
+		dmas = <&apbdma 20>, <&apbdma 20>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -371,6 +388,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -384,6 +403,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SPI>;
 		resets = <&tegra_car 43>;
 		reset-names = "spi";
+		dmas = <&apbdma 11>, <&apbdma 11>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -398,6 +419,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 54>;
 		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -412,6 +435,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -426,6 +451,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 47>;
 		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -439,6 +466,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 		resets = <&tegra_car 41>;
 		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -452,6 +481,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 		resets = <&tegra_car 44>;
 		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -465,6 +496,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 		resets = <&tegra_car 46>;
 		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -478,6 +511,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 		resets = <&tegra_car 68>;
 		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 95635e54bd34..0e69dd9f33e6 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -302,6 +302,7 @@
 		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 		resets = <&tegra_car 34>;
 		reset-names = "dma";
+		#dma-cells = <1>;
 	};
 
 	ahb: ahb {
@@ -349,6 +350,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -361,6 +364,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -373,6 +378,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -385,6 +392,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -397,6 +406,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
+		dmas = <&apbdma 20>, <&apbdma 20>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -428,6 +439,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -442,6 +455,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 54>;
 		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -456,6 +471,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -470,6 +487,8 @@
 		resets = <&tegra_car 103>;
 		reset-names = "i2c";
 		clock-names = "div-clk", "fast-clk";
+		dmas = <&apbdma 26>, <&apbdma 26>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -484,6 +503,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 47>;
 		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -497,6 +518,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 		resets = <&tegra_car 41>;
 		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -510,6 +533,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 		resets = <&tegra_car 44>;
 		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -523,6 +548,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 		resets = <&tegra_car 46>;
 		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -536,6 +563,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 		resets = <&tegra_car 68>;
 		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -549,6 +578,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 		resets = <&tegra_car 104>;
 		reset-names = "spi";
+		dmas = <&apbdma 27>, <&apbdma 27>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -562,6 +593,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 		resets = <&tegra_car 106>;
 		reset-names = "spi";
+		dmas = <&apbdma 28>, <&apbdma 28>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -635,6 +668,12 @@
 		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif";
+		dmas = <&apbdma 1>, <&apbdma 1>,
+		       <&apbdma 2>, <&apbdma 2>,
+		       <&apbdma 3>, <&apbdma 3>,
+		       <&apbdma 4>, <&apbdma 4>;
+		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+			    "rx3", "tx3";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
1.8.1.5

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Re: [PATCH 05/31] ARM: tegra: update DT files to add DMA properties

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1400 bytes --]

On Fri, Nov 15, 2013 at 01:54:00PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> This patch switches the Tegra DT files to use the standard DMA DT bindings
> rather than custom properties. Note that the legacy properties are not yet
> removed; the drivers must be updated to use the new properties first.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm/boot/dts/tegra114.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/tegra20.dtsi  | 35 ++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/tegra30.dtsi  | 39 +++++++++++++++++++++++++++++++++++
>  3 files changed, 119 insertions(+)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[PATCH 28/31] ARM: tegra: remove legacy clock entries from DT

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Now that all Tegra drivers have been converted to use the common reset
framework, we can remove all the legacy DT clocks/clock-names entries for
"clocks" that were only used with the old custom Tegra module reset API.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/tegra20.dtsi |  3 +--
 arch/arm/boot/dts/tegra30.dtsi | 18 +++---------------
 2 files changed, 4 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c53e02e08310..61d2f3868f4f 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -576,9 +576,8 @@
 
 		clocks = <&tegra_car TEGRA20_CLK_PEX>,
 			 <&tegra_car TEGRA20_CLK_AFI>,
-			 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
 			 <&tegra_car TEGRA20_CLK_PLL_E>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		clock-names = "pex", "afi", "pll_e";
 		resets = <&tegra_car 70>,
 		         <&tegra_car 72>,
 		         <&tegra_car 74>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 0e69dd9f33e6..348b0f07f675 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -40,10 +40,9 @@
 
 		clocks = <&tegra_car TEGRA30_CLK_PCIE>,
 			 <&tegra_car TEGRA30_CLK_AFI>,
-			 <&tegra_car TEGRA30_CLK_PCIEX>,
 			 <&tegra_car TEGRA30_CLK_PLL_E>,
 			 <&tegra_car TEGRA30_CLK_CML0>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+		clock-names = "pex", "afi", "pll_e", "cml";
 		resets = <&tegra_car 70>,
 		         <&tegra_car 72>,
 		         <&tegra_car 74>;
@@ -641,19 +640,8 @@
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
-			 <&tegra_car TEGRA30_CLK_APBIF>,
-			 <&tegra_car TEGRA30_CLK_I2S0>,
-			 <&tegra_car TEGRA30_CLK_I2S1>,
-			 <&tegra_car TEGRA30_CLK_I2S2>,
-			 <&tegra_car TEGRA30_CLK_I2S3>,
-			 <&tegra_car TEGRA30_CLK_I2S4>,
-			 <&tegra_car TEGRA30_CLK_DAM0>,
-			 <&tegra_car TEGRA30_CLK_DAM1>,
-			 <&tegra_car TEGRA30_CLK_DAM2>,
-			 <&tegra_car TEGRA30_CLK_SPDIF_IN>;
-		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
-			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
-			      "spdif_in";
+			 <&tegra_car TEGRA30_CLK_APBIF>;
+		clock-names = "d_audio", "apbif";
 		resets = <&tegra_car 106>, /* d_audio */
 			 <&tegra_car 107>, /* apbif */
 			 <&tegra_car 30>,  /* i2s0 */
-- 
1.8.1.5

Re: [PATCH 28/31] ARM: tegra: remove legacy clock entries from DT

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1282 bytes --]

On Fri, Nov 15, 2013 at 01:54:23PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Now that all Tegra drivers have been converted to use the common reset
> framework, we can remove all the legacy DT clocks/clock-names entries for
> "clocks" that were only used with the old custom Tegra module reset API.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm/boot/dts/tegra20.dtsi |  3 +--
>  arch/arm/boot/dts/tegra30.dtsi | 18 +++---------------
>  2 files changed, 4 insertions(+), 17 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[PATCH 29/31] ARM: tegra: remove legacy DMA entries from DT

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Now that all Tegra drivers have been converted to use DMA APIs which
retrieve DMA channel information from standard DMA DT properties, we can
remove all the legacy DT DMA-related properties.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/tegra114.dtsi | 14 --------------
 arch/arm/boot/dts/tegra20.dtsi  | 13 -------------
 arch/arm/boot/dts/tegra30.dtsi  | 12 ------------
 3 files changed, 39 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index b4f2e62909a7..6d4858b2c701 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -128,7 +128,6 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
@@ -142,7 +141,6 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
@@ -156,7 +154,6 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
@@ -170,7 +167,6 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
@@ -268,7 +264,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d400 0x200>;
 		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC1>;
@@ -284,7 +279,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d600 0x200>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC2>;
@@ -300,7 +294,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d800 0x200>;
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC3>;
@@ -316,7 +309,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000da00 0x200>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC4>;
@@ -332,7 +324,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000dc00 0x200>;
 		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC5>;
@@ -348,7 +339,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000de00 0x200>;
 		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC6>;
@@ -401,10 +391,6 @@
 		      <0x70080200 0x100>,
 		      <0x70081000 0x200>;
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
-			<&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
-			<&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
-			<&apbdma 29>;
 		clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
 			 <&tegra_car TEGRA114_CLK_APBIF>,
 			 <&tegra_car TEGRA114_CLK_I2S0>,
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 61d2f3868f4f..f780f7bed7bf 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -248,7 +248,6 @@
 		compatible = "nvidia,tegra20-ac97";
 		reg = <0x70002000 0x200>;
 		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 12>;
 		clocks = <&tegra_car TEGRA20_CLK_AC97>;
 		resets = <&tegra_car 3>;
 		reset-names = "ac97";
@@ -261,7 +260,6 @@
 		compatible = "nvidia,tegra20-i2s";
 		reg = <0x70002800 0x200>;
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 2>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 		resets = <&tegra_car 11>;
 		reset-names = "i2s";
@@ -274,7 +272,6 @@
 		compatible = "nvidia,tegra20-i2s";
 		reg = <0x70002a00 0x200>;
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 		resets = <&tegra_car 18>;
 		reset-names = "i2s";
@@ -295,7 +292,6 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
@@ -309,7 +305,6 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
@@ -323,7 +318,6 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
@@ -337,7 +331,6 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
@@ -351,7 +344,6 @@
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
@@ -397,7 +389,6 @@
 		compatible = "nvidia,tegra20-sflash";
 		reg = <0x7000c380 0x80>;
 		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 11>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SPI>;
@@ -460,7 +451,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d400 0x200>;
 		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
@@ -475,7 +465,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d600 0x200>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
@@ -490,7 +479,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d800 0x200>;
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
@@ -505,7 +493,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000da00 0x200>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 348b0f07f675..03ec194e832f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -345,7 +345,6 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
@@ -359,7 +358,6 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
@@ -373,7 +371,6 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
@@ -387,7 +384,6 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
@@ -401,7 +397,6 @@
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
@@ -511,7 +506,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d400 0x200>;
 		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
@@ -526,7 +520,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d600 0x200>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
@@ -541,7 +534,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d800 0x200>;
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
@@ -556,7 +548,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000da00 0x200>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
@@ -571,7 +562,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000dc00 0x200>;
 		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
@@ -586,7 +576,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000de00 0x200>;
 		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
@@ -638,7 +627,6 @@
 		reg = <0x70080000 0x200
 		       0x70080200 0x100>;
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 			 <&tegra_car TEGRA30_CLK_APBIF>;
 		clock-names = "d_audio", "apbif";
-- 
1.8.1.5

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Re: [PATCH 29/31] ARM: tegra: remove legacy DMA entries from DT

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1240 bytes --]

On Fri, Nov 15, 2013 at 01:54:24PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Now that all Tegra drivers have been converted to use DMA APIs which
> retrieve DMA channel information from standard DMA DT properties, we can
> remove all the legacy DT DMA-related properties.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm/boot/dts/tegra114.dtsi | 14 --------------
>  arch/arm/boot/dts/tegra20.dtsi  | 13 -------------
>  arch/arm/boot/dts/tegra30.dtsi  | 12 ------------
>  3 files changed, 39 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Terje Bergström]

On 15.11.2013 22:53, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> This series implements a common reset framework driver for Tegra, and
> updates all relevant Tegra drivers to use it. It also removes the custom
> DMA bindings and replaced them with the standard DMA DT bindings.
> 
> Historically, the Tegra clock driver has exported a custom API for module
> reset. This series removes that API, and transitions DT and drivers to
> the new reset framework.
> 
> The custom API used a "struct clk" to identify which module to reset, and
> consequently some DT bindings and drivers required clocks to be provided
> where they really needed just a reset identifier instead. Due to this
> known deficiency, I have always considered most Tegra bindings to be
> unstable. This series removes this excuse for instability, although I
> still consider some Tegra bindings unstable due to the need to convert to
> the common DMA bindings.
> 
> Historically, Tegra DMA channels have been represented in DT using a
> custom nvidia,dma-request-selector property. Now that standard DMA DT
> bindings exist, convert all Tegra bindings, DTs, and drivers to use the
> standard instead.
> 
> This series makes a DT-ABI-incompatible change to:
> - Require reset specifiers in DT where relevant.
> - Require standard DMA specifiers.
> - Remove clock specifiers from DT where they were only needed for reset.
> - Remove legacy DMA specifier properties.
> 
> I anticipate merging this whole series into the Tegra and arm-soc trees
> as its own branch, due to internal dependencies. This branch will be
> stable and can then be merged into any other subsystem trees should any
> conflicts arise.
> 
> This series depends on Peter's Tegra clock driver rework, available at
> git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-tegra124-0
> (or whatever version of that gets included in 3.14)

Overall, a good change. For host1x part:

Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>

This patch does not change the behavior, but we have in original code
the problem that we don't flush the MC queue when resetting an engine.
This can cause some memory writes to not hit memory. There was an
earlier discussion on that, but we seem to have lost track of the issue.

Terje

Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Arnd Bergmann]

On Friday 15 November 2013, Stephen Warren wrote:
> This series implements a common reset framework driver for Tegra, and
> updates all relevant Tegra drivers to use it. It also removes the custom
> DMA bindings and replaced them with the standard DMA DT bindings.

The series is rather long, so I may have missed it, but I think you need one
more patch to the apbdma binding to document the use of #dma-cells, what
value it has, and what the format of the dma specifiers in slave drivers
needs to be.

	Arnd

Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

On 11/20/2013 08:37 AM, Arnd Bergmann wrote:
> On Friday 15 November 2013, Stephen Warren wrote:
>> This series implements a common reset framework driver for Tegra, and
>> updates all relevant Tegra drivers to use it. It also removes the custom
>> DMA bindings and replaced them with the standard DMA DT bindings.
> 
> The series is rather long, so I may have missed it, but I think you need one
> more patch to the apbdma binding to document the use of #dma-cells, what
> value it has, and what the format of the dma specifiers in slave drivers
> needs to be.

Yes, you're right. I will fold the following into "ARM: tegra: document
use of standard DMA DT bindings":

> diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> index 0b1e577ab9d3..0b0f9498e265 100644
> --- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> +++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> @@ -11,6 +11,10 @@ Required properties:
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - dma
> +- #iommu-cells : Must be <1>. This dictates the length of DMA specifiers in
> +  client nodes' dmas properties. The specifier represents the DMA request
> +  select value for the peripheral. For more details, consult the Tegra TRM's
> +  documentation of the APB DMA channel control register REQ_SEL field.
>  
>  Examples:
>  
> @@ -36,4 +40,5 @@ apbdma: dma@6000a000 {
>  	clocks = <&tegra_car 34>;
>  	resets = <&tegra_car 34>;
>  	reset-names = "dma";
> +	#iommu-cells = <1>;
>  };

Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Arnd Bergmann]

On Wednesday 20 November 2013, Stephen Warren wrote:
> > +- #iommu-cells : Must be <1>. This dictates the length of DMA specifiers in
> > +  client nodes' dmas properties. The specifier represents the DMA request
> > +  select value for the peripheral. For more details, consult the Tegra TRM's
> > +  documentation of the APB DMA channel control register REQ_SEL field.
> >  
> >  Examples:
> >  
> > @@ -36,4 +40,5 @@ apbdma: dma@6000a000 {
> >       clocks = <&tegra_car 34>;
> >       resets = <&tegra_car 34>;
> >       reset-names = "dma";
> > +     #iommu-cells = <1>;


s/iommu/dma/

Otherwise looks good. The dts files are correct, so I guess it's just
a typo here.

	Arnd

Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

On 11/20/2013 10:03 AM, Arnd Bergmann wrote:
> On Wednesday 20 November 2013, Stephen Warren wrote:
>>> +- #iommu-cells : Must be <1>. This dictates the length of DMA specifiers in
>>> +  client nodes' dmas properties. The specifier represents the DMA request
>>> +  select value for the peripheral. For more details, consult the Tegra TRM's
>>> +  documentation of the APB DMA channel control register REQ_SEL field.
>>>  
>>>  Examples:
>>>  
>>> @@ -36,4 +40,5 @@ apbdma: dma@6000a000 {
>>>       clocks = <&tegra_car 34>;
>>>       resets = <&tegra_car 34>;
>>>       reset-names = "dma";
>>> +     #iommu-cells = <1>;
> 
> 
> s/iommu/dma/
> 
> Otherwise looks good. The dts files are correct, so I guess it's just
> a typo here.

Thanks, fixed locally.

Re: [Ac100] [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Martino Brandolini]

[-- Attachment #1.1: Type: text/plain, Size: 2260 bytes --]

Dear all,
My ac100 screen is flickering so much. I realized I'm not using it anymore.
So if anyone wants to have it for free would be for me a huge pleasure to
give it away. I'm based in milan and I'll be in London for the next week.
Maybe someone needs it.

Martino


2013/11/20 Stephen Warren <swarren@wwwdotorg.org>

> On 11/20/2013 08:37 AM, Arnd Bergmann wrote:
> > On Friday 15 November 2013, Stephen Warren wrote:
> >> This series implements a common reset framework driver for Tegra, and
> >> updates all relevant Tegra drivers to use it. It also removes the custom
> >> DMA bindings and replaced them with the standard DMA DT bindings.
> >
> > The series is rather long, so I may have missed it, but I think you need
> one
> > more patch to the apbdma binding to document the use of #dma-cells, what
> > value it has, and what the format of the dma specifiers in slave drivers
> > needs to be.
>
> Yes, you're right. I will fold the following into "ARM: tegra: document
> use of standard DMA DT bindings":
>
> > diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> > index 0b1e577ab9d3..0b0f9498e265 100644
> > --- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> > +++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> > @@ -11,6 +11,10 @@ Required properties:
> >    See ../reset/reset.txt for details.
> >  - reset-names : Must include the following entries:
> >    - dma
> > +- #iommu-cells : Must be <1>. This dictates the length of DMA
> specifiers in
> > +  client nodes' dmas properties. The specifier represents the DMA
> request
> > +  select value for the peripheral. For more details, consult the Tegra
> TRM's
> > +  documentation of the APB DMA channel control register REQ_SEL field.
> >
> >  Examples:
> >
> > @@ -36,4 +40,5 @@ apbdma: dma@6000a000 {
> >       clocks = <&tegra_car 34>;
> >       resets = <&tegra_car 34>;
> >       reset-names = "dma";
> > +     #iommu-cells = <1>;
> >  };
>
>
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Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

On 11/15/2013 01:53 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> This series implements a common reset framework driver for Tegra, and
> updates all relevant Tegra drivers to use it. It also removes the custom
> DMA bindings and replaced them with the standard DMA DT bindings.
> 
> Historically, the Tegra clock driver has exported a custom API for module
> reset. This series removes that API, and transitions DT and drivers to
> the new reset framework.
> 
> The custom API used a "struct clk" to identify which module to reset, and
> consequently some DT bindings and drivers required clocks to be provided
> where they really needed just a reset identifier instead. Due to this
> known deficiency, I have always considered most Tegra bindings to be
> unstable. This series removes this excuse for instability, although I
> still consider some Tegra bindings unstable due to the need to convert to
> the common DMA bindings.
> 
> Historically, Tegra DMA channels have been represented in DT using a
> custom nvidia,dma-request-selector property. Now that standard DMA DT
> bindings exist, convert all Tegra bindings, DTs, and drivers to use the
> standard instead.
> 
> This series makes a DT-ABI-incompatible change to:
> - Require reset specifiers in DT where relevant.
> - Require standard DMA specifiers.
> - Remove clock specifiers from DT where they were only needed for reset.
> - Remove legacy DMA specifier properties.
> 
> I anticipate merging this whole series into the Tegra and arm-soc trees
> as its own branch, due to internal dependencies. This branch will be
> stable and can then be merged into any other subsystem trees should any
> conflicts arise.
> 
> This series depends on Peter's Tegra clock driver rework, available at
> git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-tegra124-0
> (or whatever version of that gets included in 3.14)

I've applied this series (and pulled in the DMA/ASoC/clk dependencies
required) to Tegra's for-3.14/dmas-resets-rework branch.