* [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants
@ 2013-12-02 13:55 Laxman Dewangan
2013-12-02 13:55 ` [PATCH 2/2] ARM: tegra: convert device tree file of Dalmore to use pinctrl defines Laxman Dewangan
[not found] ` <1385992502-12771-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
0 siblings, 2 replies; 11+ messages in thread
From: Laxman Dewangan @ 2013-12-02 13:55 UTC (permalink / raw)
To: rob.herring, swarren
Cc: pawel.moll, mark.rutland, ijc+devicetree, linux, thierry.reding,
devicetree, linux-arm-kernel, linux-tegra, linux-kernel,
Laxman Dewangan
Defines pincontrol constants to use from Tegra's DTS file
for tegra pincontrol properties option.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
include/dt-bindings/pinctrl/pinctrl-tegra.h | 65 +++++++++++++++++++++++++++
1 files changed, 65 insertions(+), 0 deletions(-)
create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
new file mode 100644
index 0000000..c2bfa3f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h
@@ -0,0 +1,65 @@
+/*
+ * This header provides constants for TEGRA pinctrl bindings.
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
+#define _DT_BINDINGS_PINCTRL_TEGRA_H
+
+/* Input/output */
+#define TEGRA_PIN_OUTPUT 0
+#define TEGRA_PIN_INPUT 1
+
+/* Pull up/down/normal */
+#define TEGRA_PIN_PUPD_NORMAL 0
+#define TEGRA_PIN_PUPD_PULL_DOWN 1
+#define TEGRA_PIN_PUPD_PULL_UP 2
+
+/* Tristate/normal */
+#define TEGRA_PIN_NORMAL 0
+#define TEGRA_PIN_TRISTATE 1
+
+/* Rcv Sel enable/disable */
+#define TEGRA_PIN_RCV_SEL_DISABLE 0
+#define TEGRA_PIN_RCV_SEL_ENABLE 1
+
+/* Lock enable/disable */
+#define TEGRA_PIN_LOCK_DISABLE 0
+#define TEGRA_PIN_LOCK_ENABLE 1
+
+/* Open drain enable/disable */
+#define TEGRA_PIN_OPEN_DRAIN_DISABLE 0
+#define TEGRA_PIN_OPEN_DRAIN_ENABLE 1
+
+/* High speed mode */
+#define TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_DISABLE 0
+#define TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE 1
+
+/* Schmitt enable/disable */
+#define TEGRA_PIN_DRIVE_SCHMITT_DISABLE 0
+#define TEGRA_PIN_DRIVE_SCHMITT_ENABLE 1
+
+/* Low power mode */
+#define TEGRA_PIN_LP_DRIVE_DIV_8 0
+#define TEGRA_PIN_LP_DRIVE_DIV_4 1
+#define TEGRA_PIN_LP_DRIVE_DIV_2 2
+#define TEGRA_PIN_LP_DRIVE_DIV_1 3
+
+#define TEGRA_PIN_SLEW_RATE_FASTEST 0
+#define TEGRA_PIN_SLEW_RATE_FAST 1
+#define TEGRA_PIN_SLEW_RATE_SLOW 2
+#define TEGRA_PIN_SLEW_RATE_SLOWEST 3
+
+#endif
--
1.7.1.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2] ARM: tegra: convert device tree file of Dalmore to use pinctrl defines
2013-12-02 13:55 [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants Laxman Dewangan
@ 2013-12-02 13:55 ` Laxman Dewangan
[not found] ` <1385992502-12771-2-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[not found] ` <1385992502-12771-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
1 sibling, 1 reply; 11+ messages in thread
From: Laxman Dewangan @ 2013-12-02 13:55 UTC (permalink / raw)
To: rob.herring, swarren
Cc: pawel.moll, mark.rutland, ijc+devicetree, linux, thierry.reding,
devicetree, linux-arm-kernel, linux-tegra, linux-kernel,
Laxman Dewangan
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
arch/arm/boot/dts/tegra114-dalmore.dts | 549 ++++++++++++++++----------------
1 files changed, 275 insertions(+), 274 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb5ec23..ea0eb31 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,6 +1,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include "tegra114.dtsi"
/ {
@@ -19,41 +20,41 @@
clk1_out_pw4 {
nvidia,pins = "clk1_out_pw4";
nvidia,function = "extperiph1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
dap1_din_pn1 {
nvidia,pins = "dap1_din_pn1";
nvidia,function = "i2s0";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
dap1_dout_pn2 {
nvidia,pins = "dap1_dout_pn2",
"dap1_fs_pn0",
"dap1_sclk_pn3";
nvidia,function = "i2s0";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
dap2_din_pa4 {
nvidia,pins = "dap2_din_pa4";
nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
dap2_dout_pa5 {
nvidia,pins = "dap2_dout_pa5",
"dap2_fs_pa2",
"dap2_sclk_pa3";
nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
dap4_din_pp5 {
nvidia,pins = "dap4_din_pp5",
@@ -61,17 +62,17 @@
"dap4_fs_pp4",
"dap4_sclk_pp7";
nvidia,function = "i2s3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
dvfs_pwm_px0 {
nvidia,pins = "dvfs_pwm_px0",
"dvfs_clk_px2";
nvidia,function = "cldvfs";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
ulpi_clk_py0 {
nvidia,pins = "ulpi_clk_py0",
@@ -84,128 +85,128 @@
"ulpi_data6_po7",
"ulpi_data7_po0";
nvidia,function = "ulpi";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
ulpi_dir_py1 {
nvidia,pins = "ulpi_dir_py1",
"ulpi_nxt_py2";
nvidia,function = "ulpi";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
ulpi_stp_py3 {
nvidia,pins = "ulpi_stp_py3";
nvidia,function = "ulpi";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1",
"cam_i2c_sda_pbb2";
nvidia,function = "i2c3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
- nvidia,lock = <0>;
- nvidia,open-drain = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
+ nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_DISABLE>;
};
cam_mclk_pcc0 {
nvidia,pins = "cam_mclk_pcc0",
"pbb0";
nvidia,function = "vi_alt3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
- nvidia,lock = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+ nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
};
gen2_i2c_scl_pt5 {
nvidia,pins = "gen2_i2c_scl_pt5",
"gen2_i2c_sda_pt6";
nvidia,function = "i2c2";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
- nvidia,lock = <0>;
- nvidia,open-drain = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
+ nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_DISABLE>;
};
gmi_a16_pj7 {
nvidia,pins = "gmi_a16_pj7";
nvidia,function = "uartd";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
gmi_a17_pb0 {
nvidia,pins = "gmi_a17_pb0",
"gmi_a18_pb1";
nvidia,function = "uartd";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gmi_a19_pk7 {
nvidia,pins = "gmi_a19_pk7";
nvidia,function = "uartd";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
gmi_ad5_pg5 {
nvidia,pins = "gmi_ad5_pg5",
"gmi_cs6_n_pi3",
"gmi_wr_n_pi0";
nvidia,function = "spi4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gmi_ad6_pg6 {
nvidia,pins = "gmi_ad6_pg6",
"gmi_ad7_pg7";
nvidia,function = "spi4";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gmi_ad12_ph4 {
nvidia,pins = "gmi_ad12_ph4";
nvidia,function = "rsvd4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
gmi_ad9_ph1 {
nvidia,pins = "gmi_ad9_ph1";
nvidia,function = "pwm1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
gmi_cs1_n_pj2 {
nvidia,pins = "gmi_cs1_n_pj2",
"gmi_oe_n_pi1";
nvidia,function = "soc";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
clk2_out_pw5 {
nvidia,pins = "clk2_out_pw5";
nvidia,function = "extperiph2";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
sdmmc1_clk_pz0 {
nvidia,pins = "sdmmc1_clk_pz0";
nvidia,function = "sdmmc1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
sdmmc1_cmd_pz1 {
nvidia,pins = "sdmmc1_cmd_pz1",
@@ -214,23 +215,23 @@
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,function = "sdmmc1";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
sdmmc1_wp_n_pv3 {
nvidia,pins = "sdmmc1_wp_n_pv3";
nvidia,function = "spi4";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
sdmmc3_cmd_pa7 {
nvidia,pins = "sdmmc3_cmd_pa7",
@@ -242,16 +243,16 @@
"sdmmc3_clk_lb_out_pee4",
"sdmmc3_clk_lb_in_pee5";
nvidia,function = "sdmmc3";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4";
nvidia,function = "sdmmc4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
sdmmc4_cmd_pt7 {
nvidia,pins = "sdmmc4_cmd_pt7",
@@ -264,16 +265,16 @@
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
clk_32k_out_pa0 {
nvidia,pins = "clk_32k_out_pa0";
nvidia,function = "blink";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
kb_col0_pq0 {
nvidia,pins = "kb_col0_pq0",
@@ -283,265 +284,265 @@
"kb_row1_pr1",
"kb_row2_pr2";
nvidia,function = "kbc";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
dap3_din_pp1 {
nvidia,pins = "dap3_din_pp1",
"dap3_sclk_pp3";
nvidia,function = "displayb";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
pv0 {
nvidia,pins = "pv0";
nvidia,function = "rsvd4";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
kb_row7_pr7 {
nvidia,pins = "kb_row7_pr7";
nvidia,function = "rsvd2";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
kb_row10_ps2 {
nvidia,pins = "kb_row10_ps2";
nvidia,function = "uarta";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
kb_row9_ps1 {
nvidia,pins = "kb_row9_ps1";
nvidia,function = "uarta";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
pwr_i2c_scl_pz6 {
nvidia,pins = "pwr_i2c_scl_pz6",
"pwr_i2c_sda_pz7";
nvidia,function = "i2cpwr";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
- nvidia,lock = <0>;
- nvidia,open-drain = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
+ nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_DISABLE>;
};
sys_clk_req_pz5 {
nvidia,pins = "sys_clk_req_pz5";
nvidia,function = "sysclk";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
core_pwr_req {
nvidia,pins = "core_pwr_req";
nvidia,function = "pwron";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
cpu_pwr_req {
nvidia,pins = "cpu_pwr_req";
nvidia,function = "cpu";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
pwr_int_n {
nvidia,pins = "pwr_int_n";
nvidia,function = "pmi";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
reset_out_n {
nvidia,pins = "reset_out_n";
nvidia,function = "reset_out_n";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
clk3_out_pee0 {
nvidia,pins = "clk3_out_pee0";
nvidia,function = "extperiph3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
gen1_i2c_scl_pc4 {
nvidia,pins = "gen1_i2c_scl_pc4",
"gen1_i2c_sda_pc5";
nvidia,function = "i2c1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
- nvidia,lock = <0>;
- nvidia,open-drain = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
+ nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_DISABLE>;
};
uart2_cts_n_pj5 {
nvidia,pins = "uart2_cts_n_pj5";
nvidia,function = "uartb";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
uart2_rts_n_pj6 {
nvidia,pins = "uart2_rts_n_pj6";
nvidia,function = "uartb";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
uart2_rxd_pc3 {
nvidia,pins = "uart2_rxd_pc3";
nvidia,function = "irda";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
uart2_txd_pc2 {
nvidia,pins = "uart2_txd_pc2";
nvidia,function = "irda";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
uart3_cts_n_pa1 {
nvidia,pins = "uart3_cts_n_pa1",
"uart3_rxd_pw7";
nvidia,function = "uartc";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
uart3_rts_n_pc0 {
nvidia,pins = "uart3_rts_n_pc0",
"uart3_txd_pw6";
nvidia,function = "uartc";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
owr {
nvidia,pins = "owr";
nvidia,function = "owr";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
hdmi_cec_pee3 {
nvidia,pins = "hdmi_cec_pee3";
nvidia,function = "cec";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
- nvidia,lock = <0>;
- nvidia,open-drain = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
+ nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_DISABLE>;
};
ddc_scl_pv4 {
nvidia,pins = "ddc_scl_pv4",
"ddc_sda_pv5";
nvidia,function = "i2c4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
- nvidia,lock = <0>;
- nvidia,rcv-sel = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
+ nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_RCV_SEL_ENABLE>;
};
spdif_in_pk6 {
nvidia,pins = "spdif_in_pk6";
nvidia,function = "usb";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
- nvidia,lock = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
+ nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
};
usb_vbus_en0_pn4 {
nvidia,pins = "usb_vbus_en0_pn4";
nvidia,function = "usb";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
- nvidia,lock = <0>;
- nvidia,open-drain = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
+ nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_ENABLE>;
};
gpio_x6_aud_px6 {
nvidia,pins = "gpio_x6_aud_px6";
nvidia,function = "spi6";
- nvidia,pull = <2>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gpio_x4_aud_px4 {
nvidia,pins = "gpio_x4_aud_px4",
"gpio_x7_aud_px7";
nvidia,function = "rsvd1";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
gpio_x5_aud_px5 {
nvidia,pins = "gpio_x5_aud_px5";
nvidia,function = "rsvd1";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gpio_w2_aud_pw2 {
nvidia,pins = "gpio_w2_aud_pw2";
nvidia,function = "rsvd2";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gpio_w3_aud_pw3 {
nvidia,pins = "gpio_w3_aud_pw3";
nvidia,function = "spi6";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gpio_x1_aud_px1 {
nvidia,pins = "gpio_x1_aud_px1";
nvidia,function = "rsvd4";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gpio_x3_aud_px3 {
nvidia,pins = "gpio_x3_aud_px3";
nvidia,function = "rsvd4";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
dap3_fs_pp0 {
nvidia,pins = "dap3_fs_pp0";
nvidia,function = "i2s2";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
dap3_dout_pp2 {
nvidia,pins = "dap3_dout_pp2";
nvidia,function = "i2s2";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
pv1 {
nvidia,pins = "pv1";
nvidia,function = "rsvd1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
pbb3 {
nvidia,pins = "pbb3",
@@ -549,25 +550,25 @@
"pbb6",
"pbb7";
nvidia,function = "rsvd4";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
pcc1 {
nvidia,pins = "pcc1",
"pcc2";
nvidia,function = "rsvd4";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gmi_ad0_pg0 {
nvidia,pins = "gmi_ad0_pg0",
"gmi_ad1_pg1";
nvidia,function = "gmi";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
gmi_ad10_ph2 {
nvidia,pins = "gmi_ad10_ph2",
@@ -576,17 +577,17 @@
"gmi_ad8_ph0",
"gmi_clk_pk1";
nvidia,function = "gmi";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
gmi_ad2_pg2 {
nvidia,pins = "gmi_ad2_pg2",
"gmi_ad3_pg3";
nvidia,function = "gmi";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gmi_adv_n_pk0 {
nvidia,pins = "gmi_adv_n_pk0",
@@ -598,39 +599,39 @@
"gmi_iordy_pi5",
"gmi_wp_n_pc7";
nvidia,function = "gmi";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
gmi_cs3_n_pk4 {
nvidia,pins = "gmi_cs3_n_pk4";
nvidia,function = "gmi";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
clk2_req_pcc5 {
nvidia,pins = "clk2_req_pcc5";
nvidia,function = "rsvd4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
kb_col3_pq3 {
nvidia,pins = "kb_col3_pq3",
"kb_col6_pq6",
"kb_col7_pq7";
nvidia,function = "kbc";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
kb_col5_pq5 {
nvidia,pins = "kb_col5_pq5";
nvidia,function = "kbc";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
kb_row3_pr3 {
nvidia,pins = "kb_row3_pr3",
@@ -638,77 +639,77 @@
"kb_row6_pr6",
"kb_row8_ps0";
nvidia,function = "kbc";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
clk3_req_pee1 {
nvidia,pins = "clk3_req_pee1";
nvidia,function = "rsvd4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
pu4 {
nvidia,pins = "pu4";
nvidia,function = "displayb";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
pu5 {
nvidia,pins = "pu5",
"pu6";
nvidia,function = "displayb";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
hdmi_int_pn7 {
nvidia,pins = "hdmi_int_pn7";
nvidia,function = "rsvd1";
- nvidia,pull = <1>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_NORMAL>;
+ nvidia,enable-input = <TEGRA_PIN_INPUT>;
};
clk1_req_pee2 {
nvidia,pins = "clk1_req_pee2",
"usb_vbus_en1_pn5";
nvidia,function = "rsvd4";
- nvidia,pull = <1>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <0>;
+ nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+ nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
};
drive_sdio1 {
nvidia,pins = "drive_sdio1";
- nvidia,high-speed-mode = <1>;
- nvidia,schmitt = <0>;
- nvidia,low-power-mode = <3>;
+ nvidia,high-speed-mode = <TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DRIVE_SCHMITT_DISABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
nvidia,pull-down-strength = <36>;
nvidia,pull-up-strength = <20>;
- nvidia,slew-rate-rising = <2>;
- nvidia,slew-rate-falling = <2>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
};
drive_sdio3 {
nvidia,pins = "drive_sdio3";
- nvidia,high-speed-mode = <1>;
- nvidia,schmitt = <0>;
- nvidia,low-power-mode = <3>;
+ nvidia,high-speed-mode = <TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DRIVE_SCHMITT_DISABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
nvidia,pull-down-strength = <22>;
nvidia,pull-up-strength = <36>;
- nvidia,slew-rate-rising = <0>;
- nvidia,slew-rate-falling = <0>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
};
drive_gma {
nvidia,pins = "drive_gma";
- nvidia,high-speed-mode = <1>;
- nvidia,schmitt = <0>;
- nvidia,low-power-mode = <3>;
+ nvidia,high-speed-mode = <TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DRIVE_SCHMITT_DISABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
nvidia,pull-down-strength = <2>;
nvidia,pull-up-strength = <1>;
- nvidia,slew-rate-rising = <0>;
- nvidia,slew-rate-falling = <0>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
nvidia,drive-type = <1>;
};
};
--
1.7.1.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants
[not found] ` <1385992502-12771-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
@ 2013-12-02 14:25 ` Thierry Reding
[not found] ` <20131202142522.GA17566-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2013-12-03 20:05 ` Stephen Warren
2013-12-03 20:06 ` Stephen Warren
2 siblings, 1 reply; 11+ messages in thread
From: Thierry Reding @ 2013-12-02 14:25 UTC (permalink / raw)
To: Laxman Dewangan
Cc: rob.herring-bsGFqQB8/DxBDgjK7y7TUQ,
swarren-3lzwWm7+Weoh9ZMKESR00Q, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-lFZ/pmaqli7XmaaqVzeoHQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 2175 bytes --]
On Mon, Dec 02, 2013 at 07:25:01PM +0530, Laxman Dewangan wrote:
I think the canonical subject prefix for Tegra is:
ARM: tegra:
Perhaps also mention that you "Add" the header file? Like so:
ARM: tegra: Add header file for pinctrl constants
> Defines pincontrol constants to use from Tegra's DTS file
Perhaps: "This new header file defines..."? "DTS files"
> for tegra pincontrol properties option.
"Tegra"
>
> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> include/dt-bindings/pinctrl/pinctrl-tegra.h | 65 +++++++++++++++++++++++++++
> 1 files changed, 65 insertions(+), 0 deletions(-)
> create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h
>
> diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
[...]
> +/* Pull up/down/normal */
> +#define TEGRA_PIN_PUPD_NORMAL 0
> +#define TEGRA_PIN_PUPD_PULL_DOWN 1
> +#define TEGRA_PIN_PUPD_PULL_UP 2
Perhaps these would be easier to use as:
#define TEGRA_PIN_PULL_NONE 0
#define TEGRA_PIN_PULL_DOWN 1
#define TEGRA_PIN_PULL_UP 2
?
> +/* Tristate/normal */
> +#define TEGRA_PIN_NORMAL 0
> +#define TEGRA_PIN_TRISTATE 1
> +
> +/* Rcv Sel enable/disable */
> +#define TEGRA_PIN_RCV_SEL_DISABLE 0
> +#define TEGRA_PIN_RCV_SEL_ENABLE 1
> +
> +/* Lock enable/disable */
> +#define TEGRA_PIN_LOCK_DISABLE 0
> +#define TEGRA_PIN_LOCK_ENABLE 1
> +
> +/* Open drain enable/disable */
> +#define TEGRA_PIN_OPEN_DRAIN_DISABLE 0
> +#define TEGRA_PIN_OPEN_DRAIN_ENABLE 1
> +
> +/* High speed mode */
> +#define TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_DISABLE 0
> +#define TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE 1
> +
> +/* Schmitt enable/disable */
> +#define TEGRA_PIN_DRIVE_SCHMITT_DISABLE 0
> +#define TEGRA_PIN_DRIVE_SCHMITT_ENABLE 1
These are all boolean, so I wonder if perhaps we should be simply
defining a single pair and reuse that in different contexts:
#define TEGRA_PIN_DISABLE 0
#define TEGRA_PIN_ENABLE 1
The property names should provide enough context for them to be used
unambiguously.
Thierry
[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants
[not found] ` <20131202142522.GA17566-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
@ 2013-12-03 6:04 ` Laxman Dewangan
[not found] ` <529D745D.2070503-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
0 siblings, 1 reply; 11+ messages in thread
From: Laxman Dewangan @ 2013-12-03 6:04 UTC (permalink / raw)
To: Thierry Reding
Cc: rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org,
swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
On Monday 02 December 2013 07:55 PM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Dec 02, 2013 at 07:25:01PM +0530, Laxman Dewangan wrote:
>
> +
> +/* Schmitt enable/disable */
> +#define TEGRA_PIN_DRIVE_SCHMITT_DISABLE 0
> +#define TEGRA_PIN_DRIVE_SCHMITT_ENABLE 1
> These are all boolean, so I wonder if perhaps we should be simply
> defining a single pair and reuse that in different contexts:
>
> #define TEGRA_PIN_DISABLE 0
> #define TEGRA_PIN_ENABLE 1
>
> The property names should provide enough context for them to be used
> unambiguously.
>
>
I can make generic ENABLE/DISABLE macro as you suggested but datasheet
says as 0=NORMAL, 1 = TRISTATE. and that's why I kept name very near to
the datasheet.
Thanks,
Laxman
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants
[not found] ` <1385992502-12771-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-12-02 14:25 ` [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants Thierry Reding
@ 2013-12-03 20:05 ` Stephen Warren
2013-12-03 20:06 ` Stephen Warren
2 siblings, 0 replies; 11+ messages in thread
From: Stephen Warren @ 2013-12-03 20:05 UTC (permalink / raw)
To: Laxman Dewangan, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ
Cc: pawel.moll-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-lFZ/pmaqli7XmaaqVzeoHQ,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 12/02/2013 06:55 AM, Laxman Dewangan wrote:
> Defines pincontrol constants to use from Tegra's DTS file
> for tegra pincontrol properties option.
> diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
> +/* Tristate/normal */
> +#define TEGRA_PIN_NORMAL 0
> +#define TEGRA_PIN_TRISTATE 1
"NORMAL" is a bit generic. "DRIVEN" might work better.
> +/* High speed mode */
> +#define TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_DISABLE 0
> +#define TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE 1
> +
> +/* Schmitt enable/disable */
> +#define TEGRA_PIN_DRIVE_SCHMITT_DISABLE 0
> +#define TEGRA_PIN_DRIVE_SCHMITT_ENABLE 1
I expect you can remove "DRIVE_" from all those names to make things
shorter.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants
[not found] ` <1385992502-12771-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-12-02 14:25 ` [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants Thierry Reding
2013-12-03 20:05 ` Stephen Warren
@ 2013-12-03 20:06 ` Stephen Warren
2 siblings, 0 replies; 11+ messages in thread
From: Stephen Warren @ 2013-12-03 20:06 UTC (permalink / raw)
To: Laxman Dewangan, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ
Cc: pawel.moll-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-lFZ/pmaqli7XmaaqVzeoHQ,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 12/02/2013 06:55 AM, Laxman Dewangan wrote:
> Defines pincontrol constants to use from Tegra's DTS file
> for tegra pincontrol properties option.
> diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
> +/* Pull up/down/normal */
> +#define TEGRA_PIN_PUPD_NORMAL 0
> +#define TEGRA_PIN_PUPD_PULL_DOWN 1
> +#define TEGRA_PIN_PUPD_PULL_UP 2
... and s/NORMAL/NONE/ here too, I think. Some people might consider
some other value e.g. pull-up as normal:-)
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants
[not found] ` <529D745D.2070503-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
@ 2013-12-03 20:08 ` Stephen Warren
[not found] ` <529E3A34.4030206-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
0 siblings, 1 reply; 11+ messages in thread
From: Stephen Warren @ 2013-12-03 20:08 UTC (permalink / raw)
To: Laxman Dewangan, Thierry Reding
Cc: rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
On 12/02/2013 11:04 PM, Laxman Dewangan wrote:
> On Monday 02 December 2013 07:55 PM, Thierry Reding wrote:
>> * PGP Signed by an unknown key
>>
>> On Mon, Dec 02, 2013 at 07:25:01PM +0530, Laxman Dewangan wrote:
>>
>
>> +
>> +/* Schmitt enable/disable */
>> +#define TEGRA_PIN_DRIVE_SCHMITT_DISABLE 0
>> +#define TEGRA_PIN_DRIVE_SCHMITT_ENABLE 1
>> These are all boolean, so I wonder if perhaps we should be simply
>> defining a single pair and reuse that in different contexts:
>>
>> #define TEGRA_PIN_DISABLE 0
>> #define TEGRA_PIN_ENABLE 1
>>
>> The property names should provide enough context for them to be used
>> unambiguously.
>>
>>
>
> I can make generic ENABLE/DISABLE macro as you suggested but datasheet
> says as 0=NORMAL, 1 = TRISTATE. and that's why I kept name very near to
> the datasheet.
That documentation is relative to a specific field, whereas the
namespace for #defines is global. Hence, we may have to name #defines
using stricter rules than the TRM's field values, in order to make them
unambiguous.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: tegra: convert device tree file of Dalmore to use pinctrl defines
[not found] ` <1385992502-12771-2-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
@ 2013-12-03 20:09 ` Stephen Warren
[not found] ` <529E3A6E.1050003-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
0 siblings, 1 reply; 11+ messages in thread
From: Stephen Warren @ 2013-12-03 20:09 UTC (permalink / raw)
To: Laxman Dewangan, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ
Cc: pawel.moll-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-lFZ/pmaqli7XmaaqVzeoHQ,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 12/02/2013 06:55 AM, Laxman Dewangan wrote:
> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Patch description?
BTW, did you compile all the Tegra DT files before and after this
change, and make sure that there's zero difference between them (i.e.
they're identical byte-for-byte when compiled)? I don't feel like
manually double-checking this entire patch...
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants
[not found] ` <529E3A34.4030206-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
@ 2013-12-04 5:49 ` Laxman Dewangan
0 siblings, 0 replies; 11+ messages in thread
From: Laxman Dewangan @ 2013-12-04 5:49 UTC (permalink / raw)
To: Stephen Warren
Cc: Thierry Reding,
rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
On Wednesday 04 December 2013 01:38 AM, Stephen Warren wrote:
> On 12/02/2013 11:04 PM, Laxman Dewangan wrote:
>> On Monday 02 December 2013 07:55 PM, Thierry Reding wrote:
>>> * PGP Signed by an unknown key
>>>
>>> On Mon, Dec 02, 2013 at 07:25:01PM +0530, Laxman Dewangan wrote:
>>>
>>> +
>>> +/* Schmitt enable/disable */
>>> +#define TEGRA_PIN_DRIVE_SCHMITT_DISABLE 0
>>> +#define TEGRA_PIN_DRIVE_SCHMITT_ENABLE 1
>>> These are all boolean, so I wonder if perhaps we should be simply
>>> defining a single pair and reuse that in different contexts:
>>>
>>> #define TEGRA_PIN_DISABLE 0
>>> #define TEGRA_PIN_ENABLE 1
>>>
>>> The property names should provide enough context for them to be used
>>> unambiguously.
>>>
>>>
>> I can make generic ENABLE/DISABLE macro as you suggested but datasheet
>> says as 0=NORMAL, 1 = TRISTATE. and that's why I kept name very near to
>> the datasheet.
> That documentation is relative to a specific field, whereas the
> namespace for #defines is global. Hence, we may have to name #defines
> using stricter rules than the TRM's field values, in order to make them
> unambiguous.
I send the V2 patches on which I have taken care of this.
Request you to please review.
Thanks,
Laxman
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: tegra: convert device tree file of Dalmore to use pinctrl defines
[not found] ` <529E3A6E.1050003-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
@ 2013-12-04 5:51 ` Laxman Dewangan
2013-12-04 16:59 ` Stephen Warren
0 siblings, 1 reply; 11+ messages in thread
From: Laxman Dewangan @ 2013-12-04 5:51 UTC (permalink / raw)
To: Stephen Warren
Cc: rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
On Wednesday 04 December 2013 01:39 AM, Stephen Warren wrote:
> On 12/02/2013 06:55 AM, Laxman Dewangan wrote:
>> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Patch description?
>
> BTW, did you compile all the Tegra DT files before and after this
> change, and make sure that there's zero difference between them (i.e.
> they're identical byte-for-byte when compiled)? I don't feel like
> manually double-checking this entire patch...
I just made changes for the Dalmore only. Not touched Tegra30 and
Tegra20_ platform dts.
For Dalmore, I compare the binary before and after this change as well
dts generated back from dtb using dtc.
It is same.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: tegra: convert device tree file of Dalmore to use pinctrl defines
2013-12-04 5:51 ` Laxman Dewangan
@ 2013-12-04 16:59 ` Stephen Warren
0 siblings, 0 replies; 11+ messages in thread
From: Stephen Warren @ 2013-12-04 16:59 UTC (permalink / raw)
To: Laxman Dewangan
Cc: rob.herring@calxeda.com, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, linux@arm.linux.org.uk,
thierry.reding@gmail.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
On 12/03/2013 10:51 PM, Laxman Dewangan wrote:
> On Wednesday 04 December 2013 01:39 AM, Stephen Warren wrote:
>> On 12/02/2013 06:55 AM, Laxman Dewangan wrote:
>>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>> Patch description?
>>
>> BTW, did you compile all the Tegra DT files before and after this
>> change, and make sure that there's zero difference between them (i.e.
>> they're identical byte-for-byte when compiled)? I don't feel like
>> manually double-checking this entire patch...
>
> I just made changes for the Dalmore only. Not touched Tegra30 and
> Tegra20_ platform dts.
OK. Why not convert all the DTs at once?
> For Dalmore, I compare the binary before and after this change as well
> dts generated back from dtb using dtc.
> It is same.
Great.
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2013-12-04 16:59 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-12-02 13:55 [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants Laxman Dewangan
2013-12-02 13:55 ` [PATCH 2/2] ARM: tegra: convert device tree file of Dalmore to use pinctrl defines Laxman Dewangan
[not found] ` <1385992502-12771-2-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-12-03 20:09 ` Stephen Warren
[not found] ` <529E3A6E.1050003-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-12-04 5:51 ` Laxman Dewangan
2013-12-04 16:59 ` Stephen Warren
[not found] ` <1385992502-12771-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-12-02 14:25 ` [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants Thierry Reding
[not found] ` <20131202142522.GA17566-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2013-12-03 6:04 ` Laxman Dewangan
[not found] ` <529D745D.2070503-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-12-03 20:08 ` Stephen Warren
[not found] ` <529E3A34.4030206-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-12-04 5:49 ` Laxman Dewangan
2013-12-03 20:05 ` Stephen Warren
2013-12-03 20:06 ` Stephen Warren
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