* [PATCH 0/4] Add Broadcom Capri pinctrl driver
@ 2013-10-04 0:23 Sherman Yin
2013-10-04 0:23 ` [PATCH 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin
` (3 more replies)
0 siblings, 4 replies; 85+ messages in thread
From: Sherman Yin @ 2013-10-04 0:23 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Christian Daudt, Russell King,
Linus Walleij, Grant Likely, Matt Porter
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sherman Yin
The following patches adds a pinctrl driver for Broadcom Capri (BCM281xx) SoCs.
The first patch, adding the void * to pinctrl_pin_desc, has been previously
discussed with LinusW. See this thread:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/165880.html
Sherman Yin (4):
pinctrl: Add void * to pinctrl_pin_desc
pinctrl: Add pinctrl binding for Broadcom Capri SoCs
ARM: pinctrl: Add Broadcom Capri pinctrl driver
pinctrl: Enable pinctrl for Broadcom Capri SoCs
.../bindings/pinctrl/brcm,capri-pinctrl.txt | 419 +++++
arch/arm/boot/dts/bcm11351.dtsi | 4 +
arch/arm/mach-bcm/Kconfig | 2 +
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-capri.c | 1727 ++++++++++++++++++++
include/linux/pinctrl/pinctrl.h | 2 +
7 files changed, 2165 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-capri.c
--
1.7.9.5
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^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH 1/4] pinctrl: Add void * to pinctrl_pin_desc 2013-10-04 0:23 [PATCH 0/4] Add Broadcom Capri pinctrl driver Sherman Yin @ 2013-10-04 0:23 ` Sherman Yin [not found] ` <1380846199-12829-2-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> [not found] ` <1380846199-12829-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> ` (2 subsequent siblings) 3 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-10-04 0:23 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin drv_data is added to the pinctrl_pin_desc for drivers to define additional driver-specific per-pin data. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- Change-Id: I78b2c44b93d88b04897fd0af80ffce213e338d6b --- include/linux/pinctrl/pinctrl.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 5979147..c8e42c4 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -32,10 +32,12 @@ struct device_node; * pins, pads or other muxable units in this struct * @number: unique pin number from the global pin number space * @name: a name for this pin + * @drv_data: driver-defined per-pin data. pinctrl core does not touch this */ struct pinctrl_pin_desc { unsigned number; const char *name; + void *drv_data; }; /* Convenience macro to define a single named or anonymous pin descriptor */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
[parent not found: <1380846199-12829-2-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH 1/4] pinctrl: Add void * to pinctrl_pin_desc [not found] ` <1380846199-12829-2-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2013-10-09 8:55 ` Linus Walleij 2013-10-09 22:57 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-10-09 8:55 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Fri, Oct 4, 2013 at 2:23 AM, Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote: > drv_data is added to the pinctrl_pin_desc for drivers to define additional > driver-specific per-pin data. > > Signed-off-by: Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> > Reviewed-by: Christian Daudt <bcm-xK7y4jjYLqYh9ZMKESR00Q@public.gmane.org> > Reviewed-by: Matt Porter <matt.porter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > Change-Id: I78b2c44b93d88b04897fd0af80ffce213e338d6b Why are you giving me this funky Gerrit stuff along with the patch? It's not like I have any use for it, and anything below the three dashes will be deleted when applying. The patch is OK but won't be applied until some driver is using it (i.e. this BRCM one...) Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 85+ messages in thread
* RE: [PATCH 1/4] pinctrl: Add void * to pinctrl_pin_desc 2013-10-09 8:55 ` Linus Walleij @ 2013-10-09 22:57 ` Sherman Yin 0 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-10-09 22:57 UTC (permalink / raw) To: Linus Walleij Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org >> --- >> Change-Id: I78b2c44b93d88b04897fd0af80ffce213e338d6b > >Why are you giving me this funky Gerrit stuff along with the patch? >It's not like I have any use for it, and anything below the three >dashes will be deleted when applying. > >The patch is OK but won't be applied until some driver is >using it (i.e. this BRCM one...) Sorry, I didn't remove it since it's after the 3 dashes and will be discarded anyway. Will remove Change-Id: from future patches. Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <1380846199-12829-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>]
* [PATCH 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs [not found] ` <1380846199-12829-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2013-10-04 0:23 ` Sherman Yin 2013-10-04 12:51 ` Matt Porter [not found] ` <1380846199-12829-3-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> 2013-10-04 0:23 ` [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin 1 sibling, 2 replies; 85+ messages in thread From: Sherman Yin @ 2013-10-04 0:23 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-doc-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sherman Yin Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> Reviewed-by: Christian Daudt <bcm-xK7y4jjYLqYh9ZMKESR00Q@public.gmane.org> Reviewed-by: Matt Porter <matt.porter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- .../bindings/pinctrl/brcm,capri-pinctrl.txt | 419 ++++++++++++++++++++ 1 file changed, 419 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt new file mode 100644 index 0000000..79e0e5a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt @@ -0,0 +1,419 @@ +Broadcom Capri Pin Controller + +This is a pin controller for the Broadcom BCM281xx SoC family, which includes +BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs. + +=== Pin Controller Node === + +Required Properties: + +- compatible: Must be "brcm,capri-pinctrl". +- reg: Base address of the PAD Controller register block and the size + of the block. + +For example, the following is the bare minimum node: + + pinctrl@35004800 { + compatible = "brcm,capri-pinctrl"; + reg = <0x35004800 0x430>; + }; + +As a Pin Controller Device, in addition to the required properties, this node +should also contain the pin configuration nodes that client devices reference, +if any. + +=== Pin Configuration Node === + +Each pin configuration node is a sub-node of the pin controller node and is a +container of an arbitrary number of subnodes, called group nodes. + +Please refer to the pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the definition of a +"pin configuration node". + +=== Group Node === + +A group node specifies the desired pin mux and/or pin configuration for an +arbitrary number of pins. The group node only affect the properties specified +in the node, and has no effect on any properties that are omitted. + +The names of the group nodes are optional and not used. The group nodes have +the following properties: + +Required Properties: + +- brcm,pins: Multiple strings. Specifies the name(s) of one or more pins to + be configured by this node. + +Optional Properties: + +- brcm,function: Multiple strings. Specifies the pin mux selection. Values are: + "alt1", "alt2", "alt3", "alt4" +- brcm,hysteresis: Multiple integers, applicable to standard pins only. Turns + on hysteresis of input. + 0: TTL input, 1: Schmitt Trigger input +- brcm,pull: Multiple integers, applicable to standard pins only. Specifies + pull-up or pull-down. + 0: neither, 1: pull-up, 2: pull-down, 3: both +- brcm,input_dis: Multiple integers, applicable to all pins. Input disable + control. + 0: off, 1: input disabled +- brcm,slew: Multiple integers. Slew rate of output. + 0: fast output, 1: normal output (most pins) + 0: normal output, 1: fast output (IC_DM and IC_DP) + 0: Fast mode, 1: High speed mode (I2C) +- brcm,drive_str: Multiple integers. Drive strength. + 0: 2 mA + 1: 4 mA + 2: 6 mA + 3: 8 mA + 4: 10 mA + 5: 12 mA + 6: 14 mA + 7: 16 mA +- brcm,pull_up_str: Multiple integers. Pull Up strength. + 0: No pull-up + 1: 1.2 kOhm + 2: 1.8 kOhm + 3: 720 Ohm + 4: 2.7 kOhm + 5: 831 Ohm + 6: 1.08 kOhm + 7: 568 Ohm +- brcm,mode: Multiple integers. Mode select. + 0: Fast mode, 1: High Speed mode (I2C) + +Any optional property must have 1 or n values, where n is the number of pins +specified in the brcm,pins property: +- If 1 value is specified for a property, this value is applied to all pins + listed in the brcm,pins property. +- If n values are specified, the i th value is applied to the i th pin, where + i is the index in the array of values and pins, and (0 <= i < n). This + provides an easy way to set different values for different pins in the same + group. + +Example: + + // pin configuration node + dev_a_active { + //group node + grp_1 { + brcm,pins = "pin1", "pin2", "pin3"; + brcm,function = "alt1"; + brcm,drive_str = <2 4 6>; + brcm,slew = <1>; + }; + + grp_2 { + ... + }; + + ... + }; + +In the example above, "dev_a_active" is a pin configuration node and has a +number of sub-nodes. In the group node "grp_1", 3 pins are defined in the +"brcm,pins" property. Thus, any optional properties must have either 1 or 3 +values. The "brcm,function" property has only one value, "alt1", therefore the +pin mux selection for all 3 pins is "alt1". Similarly, "brcm,slew" has only one +value, <1>, so all 3 pins are configured with a slew rate setting of <1>. +"brcm,drive_str" has 3 values, and they are applied in the same order of the pins +listed in "brcm,pins": the drive strength of "pin1" is set to <2>, <4> for +"pin2", and <6> for "pin3". Finally, no other parameters are sepcified, +implying no changes to any other parameters for these pins. + +=== Pin Names and Type === + +There are 3 types of pins in the BCM281xx SoC family, each type can be +configured by different properties in a group node. The following is a list of +node properties applicable to different pin types. + +Standard pins: +- brcm,function +- brcm,hysteresis +- brcm,pull +- brcm,input_dis +- brcm,slew +- brcm,drive_str + +I2C pins: +- brcm,function +- brcm,input_dis +- brcm,slew +- brcm,pull_up_str + +HDMI pins: +- brcm,function +- brcm,input_dis +- brcm,mode + +The following are valid pin names and their pin types: + + "adcsync", std + "bat_rm", std + "bsc1_scl", i2c + "bsc1_sda", i2c + "bsc2_scl", i2c + "bsc2_sda", i2c + "classgpwr", std + "clk_cx8", std + "clkout_0", std + "clkout_1", std + "clkout_2", std + "clkout_3", std + "clkreq_in_0", std + "clkreq_in_1", std + "cws_sys_req1", std + "cws_sys_req2", std + "cws_sys_req3", std + "digmic1_clk", std + "digmic1_dq", std + "digmic2_clk", std + "digmic2_dq", std + "gpen13", std + "gpen14", std + "gpen15", std + "gpio00", std + "gpio01", std + "gpio02", std + "gpio03", std + "gpio04", std + "gpio05", std + "gpio06", std + "gpio07", std + "gpio08", std + "gpio09", std + "gpio10", std + "gpio11", std + "gpio12", std + "gpio13", std + "gpio14", std + "gps_pablank", std + "gps_tmark", std + "hdmi_scl", hdmi + "hdmi_sda", hdmi + "ic_dm", std + "ic_dp", std + "kp_col_ip_0", std + "kp_col_ip_1", std + "kp_col_ip_2", std + "kp_col_ip_3", std + "kp_row_op_0", std + "kp_row_op_1", std + "kp_row_op_2", std + "kp_row_op_3", std + "lcd_b_0", std + "lcd_b_1", std + "lcd_b_2", std + "lcd_b_3", std + "lcd_b_4", std + "lcd_b_5", std + "lcd_b_6", std + "lcd_b_7", std + "lcd_g_0", std + "lcd_g_1", std + "lcd_g_2", std + "lcd_g_3", std + "lcd_g_4", std + "lcd_g_5", std + "lcd_g_6", std + "lcd_g_7", std + "lcd_hsync", std + "lcd_oe", std + "lcd_pclk", std + "lcd_r_0", std + "lcd_r_1", std + "lcd_r_2", std + "lcd_r_3", std + "lcd_r_4", std + "lcd_r_5", std + "lcd_r_6", std + "lcd_r_7", std + "lcd_vsync", std + "mdmgpio0", std + "mdmgpio1", std + "mdmgpio2", std + "mdmgpio3", std + "mdmgpio4", std + "mdmgpio5", std + "mdmgpio6", std + "mdmgpio7", std + "mdmgpio8", std + "mphi_data_0", std + "mphi_data_1", std + "mphi_data_2", std + "mphi_data_3", std + "mphi_data_4", std + "mphi_data_5", std + "mphi_data_6", std + "mphi_data_7", std + "mphi_data_8", std + "mphi_data_9", std + "mphi_data_10", std + "mphi_data_11", std + "mphi_data_12", std + "mphi_data_13", std + "mphi_data_14", std + "mphi_data_15", std + "mphi_ha0", std + "mphi_hat0", std + "mphi_hat1", std + "mphi_hce0_n", std + "mphi_hce1_n", std + "mphi_hrd_n", std + "mphi_hwr_n", std + "mphi_run0", std + "mphi_run1", std + "mtx_scan_clk", std + "mtx_scan_data", std + "nand_ad_0", std + "nand_ad_1", std + "nand_ad_2", std + "nand_ad_3", std + "nand_ad_4", std + "nand_ad_5", std + "nand_ad_6", std + "nand_ad_7", std + "nand_ale", std + "nand_cen_0", std + "nand_cen_1", std + "nand_cle", std + "nand_oen", std + "nand_rdy_0", std + "nand_rdy_1", std + "nand_wen", std + "nand_wp", std + "pc1", std + "pc2", std + "pmu_int", std + "pmu_scl", i2c + "pmu_sda", i2c + "rfst2g_mtsloten3g", std + "rgmii_0_rx_ctl", std + "rgmii_0_rxc", std + "rgmii_0_rxd_0", std + "rgmii_0_rxd_1", std + "rgmii_0_rxd_2", std + "rgmii_0_rxd_3", std + "rgmii_0_tx_ctl", std + "rgmii_0_txc", std + "rgmii_0_txd_0", std + "rgmii_0_txd_1", std + "rgmii_0_txd_2", std + "rgmii_0_txd_3", std + "rgmii_1_rx_ctl", std + "rgmii_1_rxc", std + "rgmii_1_rxd_0", std + "rgmii_1_rxd_1", std + "rgmii_1_rxd_2", std + "rgmii_1_rxd_3", std + "rgmii_1_tx_ctl", std + "rgmii_1_txc", std + "rgmii_1_txd_0", std + "rgmii_1_txd_1", std + "rgmii_1_txd_2", std + "rgmii_1_txd_3", std + "rgmii_gpio_0", std + "rgmii_gpio_1", std + "rgmii_gpio_2", std + "rgmii_gpio_3", std + "rtxdata2g_txdata3g1", std + "rtxen2g_txdata3g2", std + "rxdata3g0", std + "rxdata3g1", std + "rxdata3g2", std + "sdio1_clk", std + "sdio1_cmd", std + "sdio1_data_0", std + "sdio1_data_1", std + "sdio1_data_2", std + "sdio1_data_3", std + "sdio4_clk", std + "sdio4_cmd", std + "sdio4_data_0", std + "sdio4_data_1", std + "sdio4_data_2", std + "sdio4_data_3", std + "sim_clk", std + "sim_data", std + "sim_det", std + "sim_resetn", std + "sim2_clk", std + "sim2_data", std + "sim2_det", std + "sim2_resetn", std + "sri_c", std + "sri_d", std + "sri_e", std + "ssp_extclk", std + "ssp0_clk", std + "ssp0_fs", std + "ssp0_rxd", std + "ssp0_txd", std + "ssp2_clk", std + "ssp2_fs_0", std + "ssp2_fs_1", std + "ssp2_fs_2", std + "ssp2_fs_3", std + "ssp2_rxd_0", std + "ssp2_rxd_1", std + "ssp2_txd_0", std + "ssp2_txd_1", std + "ssp3_clk", std + "ssp3_fs", std + "ssp3_rxd", std + "ssp3_txd", std + "ssp4_clk", std + "ssp4_fs", std + "ssp4_rxd", std + "ssp4_txd", std + "ssp5_clk", std + "ssp5_fs", std + "ssp5_rxd", std + "ssp5_txd", std + "ssp6_clk", std + "ssp6_fs", std + "ssp6_rxd", std + "ssp6_txd", std + "stat_1", std + "stat_2", std + "sysclken", std + "traceclk", std + "tracedt00", std + "tracedt01", std + "tracedt02", std + "tracedt03", std + "tracedt04", std + "tracedt05", std + "tracedt06", std + "tracedt07", std + "tracedt08", std + "tracedt09", std + "tracedt10", std + "tracedt11", std + "tracedt12", std + "tracedt13", std + "tracedt14", std + "tracedt15", std + "txdata3g0", std + "txpwrind", std + "uartb1_ucts", std + "uartb1_urts", std + "uartb1_urxd", std + "uartb1_utxd", std + "uartb2_urxd", std + "uartb2_utxd", std + "uartb3_ucts", std + "uartb3_urts", std + "uartb3_urxd", std + "uartb3_utxd", std + "uartb4_ucts", std + "uartb4_urts", std + "uartb4_urxd", std + "uartb4_utxd", std + "vc_cam1_scl", i2c + "vc_cam1_sda", i2c + "vc_cam2_scl", i2c + "vc_cam2_sda", i2c + "vc_cam3_scl", i2c + "vc_cam3_sda", i2c -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2013-10-04 0:23 ` [PATCH 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin @ 2013-10-04 12:51 ` Matt Porter [not found] ` <1380846199-12829-3-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> 1 sibling, 0 replies; 85+ messages in thread From: Matt Porter @ 2013-10-04 12:51 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel On 10/03/2013 08:23 PM, Sherman Yin wrote: > Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > Reviewed-by: Christian Daudt <bcm@fixthebug.org> > Reviewed-by: Matt Porter <matt.porter@linaro.org> > --- > .../bindings/pinctrl/brcm,capri-pinctrl.txt | 419 ++++++++++++++++++++ > 1 file changed, 419 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt > > diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt > new file mode 100644 > index 0000000..79e0e5a > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt > @@ -0,0 +1,419 @@ > +Broadcom Capri Pin Controller > + > +This is a pin controller for the Broadcom BCM281xx SoC family, which includes > +BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs. > + > +=== Pin Controller Node === > + > +Required Properties: > + > +- compatible: Must be "brcm,capri-pinctrl". > +- reg: Base address of the PAD Controller register block and the size > + of the block. > + > +For example, the following is the bare minimum node: > + > + pinctrl@35004800 { > + compatible = "brcm,capri-pinctrl"; > + reg = <0x35004800 0x430>; > + }; > + > +As a Pin Controller Device, in addition to the required properties, this node > +should also contain the pin configuration nodes that client devices reference, > +if any. > + > +=== Pin Configuration Node === > + > +Each pin configuration node is a sub-node of the pin controller node and is a > +container of an arbitrary number of subnodes, called group nodes. > + > +Please refer to the pinctrl-bindings.txt in this directory for details of the > +common pinctrl bindings used by client devices, including the definition of a > +"pin configuration node". > + > +=== Group Node === > + > +A group node specifies the desired pin mux and/or pin configuration for an > +arbitrary number of pins. The group node only affect the properties specified > +in the node, and has no effect on any properties that are omitted. > + > +The names of the group nodes are optional and not used. The group nodes have > +the following properties: > + > +Required Properties: > + > +- brcm,pins: Multiple strings. Specifies the name(s) of one or more pins to > + be configured by this node. > + > +Optional Properties: > + > +- brcm,function: Multiple strings. Specifies the pin mux selection. Values are: > + "alt1", "alt2", "alt3", "alt4" > +- brcm,hysteresis: Multiple integers, applicable to standard pins only. Turns > + on hysteresis of input. > + 0: TTL input, 1: Schmitt Trigger input > +- brcm,pull: Multiple integers, applicable to standard pins only. Specifies > + pull-up or pull-down. > + 0: neither, 1: pull-up, 2: pull-down, 3: both > +- brcm,input_dis: Multiple integers, applicable to all pins. Input disable I missed this before. Hyphens are preferred over underscores in property names. > + control. > + 0: off, 1: input disabled > +- brcm,slew: Multiple integers. Slew rate of output. > + 0: fast output, 1: normal output (most pins) > + 0: normal output, 1: fast output (IC_DM and IC_DP) > + 0: Fast mode, 1: High speed mode (I2C) > +- brcm,drive_str: Multiple integers. Drive strength. > + 0: 2 mA > + 1: 4 mA > + 2: 6 mA > + 3: 8 mA > + 4: 10 mA > + 5: 12 mA > + 6: 14 mA > + 7: 16 mA > +- brcm,pull_up_str: Multiple integers. Pull Up strength. > + 0: No pull-up > + 1: 1.2 kOhm > + 2: 1.8 kOhm > + 3: 720 Ohm > + 4: 2.7 kOhm > + 5: 831 Ohm > + 6: 1.08 kOhm > + 7: 568 Ohm > +- brcm,mode: Multiple integers. Mode select. > + 0: Fast mode, 1: High Speed mode (I2C) ^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <1380846199-12829-3-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs [not found] ` <1380846199-12829-3-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2013-10-09 8:53 ` Linus Walleij 2013-10-10 17:57 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-10-09 8:53 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Fri, Oct 4, 2013 at 2:23 AM, Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote: > +- brcm,hysteresis: Multiple integers, applicable to standard pins only. Turns > + on hysteresis of input. > + 0: TTL input, 1: Schmitt Trigger input > +- brcm,pull: Multiple integers, applicable to standard pins only. Specifies > + pull-up or pull-down. > + 0: neither, 1: pull-up, 2: pull-down, 3: both > +- brcm,input_dis: Multiple integers, applicable to all pins. Input disable > + control. > + 0: off, 1: input disabled > +- brcm,slew: Multiple integers. Slew rate of output. > + 0: fast output, 1: normal output (most pins) > + 0: normal output, 1: fast output (IC_DM and IC_DP) > + 0: Fast mode, 1: High speed mode (I2C) 0,0,0? I don't get this. > +- brcm,drive_str: Multiple integers. Drive strength. > + 0: 2 mA > + 1: 4 mA > + 2: 6 mA > + 3: 8 mA > + 4: 10 mA > + 5: 12 mA > + 6: 14 mA > + 7: 16 mA > +- brcm,pull_up_str: Multiple integers. Pull Up strength. > + 0: No pull-up > + 1: 1.2 kOhm > + 2: 1.8 kOhm > + 3: 720 Ohm > + 4: 2.7 kOhm > + 5: 831 Ohm > + 6: 1.08 kOhm > + 7: 568 Ohm > +- brcm,mode: Multiple integers. Mode select. > + 0: Fast mode, 1: High Speed mode (I2C) This should *all* be using generic pin config. For the devicetree side of this, read: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt Your driver should also be selecting GENERIC_PINCONF in drivers/pinctrl/Kconfig so you use the generic pinconf library. Read include/linux/pinctrl/pinconf-generic.h for definitions of the generic config options. Your driver should be calling pinconf_generic_parse_dt_config() and pinconf_generic_dt_subnode_to_map() to get the config out of the device tree nodes. I don't understand the brcm,mode. Can this be selected on all pins or just for I2C? I would suspect it be related to things like disabling the schmitt-trigger, but elaborate on this so we understand what this is. It may need to be added to the generic options if it turns out to be unique enough. New options can be added but first we need to exactly understand those to see that their definitions does not overlap with already existing generic pin config terminology. > +The following are valid pin names and their pin types: > + > + "adcsync", std std? std what? Sorry I don't get anything from this list... you need to be way more specific in defining what is happening here. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 85+ messages in thread
* RE: [PATCH 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2013-10-09 8:53 ` Linus Walleij @ 2013-10-10 17:57 ` Sherman Yin 0 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-10-10 17:57 UTC (permalink / raw) To: Linus Walleij Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org >This should *all* be using generic pin config. > >For the devicetree side of this, read: >Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt > >Your driver should also be selecting GENERIC_PINCONF in >drivers/pinctrl/Kconfig so you use the generic pinconf >library. > >Read >include/linux/pinctrl/pinconf-generic.h >for definitions of the generic config options. > >Your driver should be calling >pinconf_generic_parse_dt_config() and >pinconf_generic_dt_subnode_to_map() to get the config >out of the device tree nodes. > >I don't understand the brcm,mode. Can this be selected on >all pins or just for I2C? I would suspect it be related to >things like disabling the schmitt-trigger, but elaborate on this >so we understand what this is. It may need to be added to the >generic options if it turns out to be unique enough. > >New options can be added but first we need to exactly understand >those to see that their definitions does not overlap with already >existing generic pin config terminology. > >> +The following are valid pin names and their pin types: >> + >> + "adcsync", std > >std? std what? > >Sorry I don't get anything from this list... you need to be way >more specific in defining what is happening here. Ok, I think some new APIs have been added since I first wrote this driver early this year. I'll take a look at the generic pin code and rework this driver. Thanks, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver [not found] ` <1380846199-12829-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> 2013-10-04 0:23 ` [PATCH 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin @ 2013-10-04 0:23 ` Sherman Yin 2013-10-09 9:10 ` Linus Walleij 2013-10-17 6:03 ` Christian Daudt 1 sibling, 2 replies; 85+ messages in thread From: Sherman Yin @ 2013-10-04 0:23 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-doc-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sherman Yin Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> Reviewed-by: Christian Daudt <bcm-xK7y4jjYLqYh9ZMKESR00Q@public.gmane.org> Reviewed-by: Matt Porter <matt.porter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- arch/arm/mach-bcm/Kconfig | 2 + drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-capri.c | 1727 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 1740 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-capri.c diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 69d67f7..2546365 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -10,6 +10,8 @@ config ARCH_BCM select GENERIC_CLOCKEVENTS select GENERIC_TIME select GPIO_BCM + select PINCTRL + select PINCTRL_CAPRI select SPARSE_IRQ select TICK_ONESHOT select CACHE_L2X0 diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b6e864e..f97eb11 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -75,6 +75,16 @@ config PINCTRL_BCM2835 select PINMUX select PINCONF +config PINCTRL_CAPRI + bool "Broadcom Capri pinctrl driver" + select PINMUX + select PINCONF + help + Say Y here to support Broadcom Capri pinctrl driver, which is used for + the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, + BCM28145, and BCM28155 SoCs. This driver requires the pinctrl + framework. GPIO is provided by a separate GPIO driver. + config PINCTRL_IMX bool select PINMUX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 496d9bf..5e1a68e 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o +obj-$(CONFIG_PINCTRL_CAPRI) += pinctrl-capri.o obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o diff --git a/drivers/pinctrl/pinctrl-capri.c b/drivers/pinctrl/pinctrl-capri.c new file mode 100644 index 0000000..2a4dcf1 --- /dev/null +++ b/drivers/pinctrl/pinctrl-capri.c @@ -0,0 +1,1727 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/slab.h> +#include "core.h" + +#define CAPRI_PINCONF_PACK(val, mask) (((val) << 16) | ((mask) & 0xffff)) +#define CAPRI_PINCONF_UNPACK_VAL(conf) ((conf) >> 16) +#define CAPRI_PINCONF_UNPACK_MASK(conf) ((conf) & 0xffff) + +enum capri_pinconf_param { + CAPRI_PINCONF_PARAM_NONE = 0, + CAPRI_PINCONF_PARAM_HYST, + CAPRI_PINCONF_PARAM_PULL, + CAPRI_PINCONF_PARAM_SLEW, + CAPRI_PINCONF_PARAM_INPUT_DIS, + CAPRI_PINCONF_PARAM_DRV_STR, + CAPRI_PINCONF_PARAM_PULL_UP_STR, + CAPRI_PINCONF_PARAM_MODE, +}; + +struct capri_cfg_param { + const char *property; + enum capri_pinconf_param id; +}; + +static const struct capri_cfg_param capri_pinconf_params[] = { + {"brcm,hysteresis", CAPRI_PINCONF_PARAM_HYST}, + {"brcm,pull", CAPRI_PINCONF_PARAM_PULL}, + {"brcm,slew", CAPRI_PINCONF_PARAM_SLEW}, + {"brcm,input_dis", CAPRI_PINCONF_PARAM_INPUT_DIS}, + {"brcm,drive_str", CAPRI_PINCONF_PARAM_DRV_STR}, + {"brcm,pull_up_str", CAPRI_PINCONF_PARAM_PULL_UP_STR}, + {"brcm,mode", CAPRI_PINCONF_PARAM_MODE}, +}; + +/* Capri Pin Control Registers Definitions */ + +/* Functionn Select bits are the same for all pin control registers */ +#define CAPRI_PIN_REG_F_SEL_MASK 0x0700 +#define CAPRI_PIN_REG_F_SEL_SHIFT 8 + +/* Standard pin register */ +#define CAPRI_STD_PIN_REG_DRV_STR_MASK 0x0007 +#define CAPRI_STD_PIN_REG_DRV_STR_SHIFT 0 +#define CAPRI_STD_PIN_REG_INPUT_DIS_MASK 0x0008 +#define CAPRI_STD_PIN_REG_INPUT_DIS_SHIFT 3 +#define CAPRI_STD_PIN_REG_SLEW_MASK 0x0010 +#define CAPRI_STD_PIN_REG_SLEW_SHIFT 4 +#define CAPRI_STD_PIN_REG_PULL_MASK 0x0060 +#define CAPRI_STD_PIN_REG_PULL_SHIFT 5 +#define CAPRI_STD_PIN_REG_HYST_MASK 0x0080 +#define CAPRI_STD_PIN_REG_HYST_SHIFT 7 + +/* I2C pin register */ +#define CAPRI_I2C_PIN_REG_INPUT_DIS_MASK 0x0004 +#define CAPRI_I2C_PIN_REG_INPUT_DIS_SHIFT 2 +#define CAPRI_I2C_PIN_REG_SLEW_MASK 0x0008 +#define CAPRI_I2C_PIN_REG_SLEW_SHIFT 3 +#define CAPRI_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070 +#define CAPRI_I2C_PIN_REG_PULL_UP_STR_SHIFT 4 + +/* HDMI pin register */ +#define CAPRI_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008 +#define CAPRI_HDMI_PIN_REG_INPUT_DIS_SHIFT 3 +#define CAPRI_HDMI_PIN_REG_MODE_MASK 0x0010 +#define CAPRI_HDMI_PIN_REG_MODE_SHIFT 4 + +/* Macro to update reg with new pin config param */ +#define CAPRI_PIN_REG_SET(reg, type, param, val) \ + (((reg) & ~CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK) \ + | (((val) << CAPRI_ ## type ## _PIN_REG_ ## param ## _SHIFT) \ + & CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK)) + +/** + * capri_pin_type - types of pin register + */ +enum capri_pin_type { + CAPRI_PIN_TYPE_UNKNOWN = 0, + CAPRI_PIN_TYPE_STD, + CAPRI_PIN_TYPE_I2C, + CAPRI_PIN_TYPE_HDMI, +}; + +static enum capri_pin_type std_pin = CAPRI_PIN_TYPE_STD; +static enum capri_pin_type i2c_pin = CAPRI_PIN_TYPE_I2C; +static enum capri_pin_type hdmi_pin = CAPRI_PIN_TYPE_HDMI; + +/** + * capri_pin_function- define pin function + */ +struct capri_pin_function { + const char *name; + const char * const *groups; + const unsigned ngroups; +}; + +/** + * capri_pinctrl_data - Broadcom-specific pinctrl data + * @reg_base - base of pinctrl registers + */ +struct capri_pinctrl_data { + void __iomem *reg_base; + + /* List of all pins */ + const struct pinctrl_pin_desc *pins; + const unsigned npins; + + const struct capri_pin_function *functions; + const unsigned nfunctions; +}; + +#define _PIN(offset) (offset) + +/* + * Pin number definition. The order here must be the same as defined in the + * PADCTRLREG block in the RDB. + */ +#define CAPRI_PIN_ADCSYNC _PIN(0) +#define CAPRI_PIN_BAT_RM _PIN(1) +#define CAPRI_PIN_BSC1_SCL _PIN(2) +#define CAPRI_PIN_BSC1_SDA _PIN(3) +#define CAPRI_PIN_BSC2_SCL _PIN(4) +#define CAPRI_PIN_BSC2_SDA _PIN(5) +#define CAPRI_PIN_CLASSGPWR _PIN(6) +#define CAPRI_PIN_CLK_CX8 _PIN(7) +#define CAPRI_PIN_CLKOUT_0 _PIN(8) +#define CAPRI_PIN_CLKOUT_1 _PIN(9) +#define CAPRI_PIN_CLKOUT_2 _PIN(10) +#define CAPRI_PIN_CLKOUT_3 _PIN(11) +#define CAPRI_PIN_CLKREQ_IN_0 _PIN(12) +#define CAPRI_PIN_CLKREQ_IN_1 _PIN(13) +#define CAPRI_PIN_CWS_SYS_REQ1 _PIN(14) +#define CAPRI_PIN_CWS_SYS_REQ2 _PIN(15) +#define CAPRI_PIN_CWS_SYS_REQ3 _PIN(16) +#define CAPRI_PIN_DIGMIC1_CLK _PIN(17) +#define CAPRI_PIN_DIGMIC1_DQ _PIN(18) +#define CAPRI_PIN_DIGMIC2_CLK _PIN(19) +#define CAPRI_PIN_DIGMIC2_DQ _PIN(20) +#define CAPRI_PIN_GPEN13 _PIN(21) +#define CAPRI_PIN_GPEN14 _PIN(22) +#define CAPRI_PIN_GPEN15 _PIN(23) +#define CAPRI_PIN_GPIO00 _PIN(24) +#define CAPRI_PIN_GPIO01 _PIN(25) +#define CAPRI_PIN_GPIO02 _PIN(26) +#define CAPRI_PIN_GPIO03 _PIN(27) +#define CAPRI_PIN_GPIO04 _PIN(28) +#define CAPRI_PIN_GPIO05 _PIN(29) +#define CAPRI_PIN_GPIO06 _PIN(30) +#define CAPRI_PIN_GPIO07 _PIN(31) +#define CAPRI_PIN_GPIO08 _PIN(32) +#define CAPRI_PIN_GPIO09 _PIN(33) +#define CAPRI_PIN_GPIO10 _PIN(34) +#define CAPRI_PIN_GPIO11 _PIN(35) +#define CAPRI_PIN_GPIO12 _PIN(36) +#define CAPRI_PIN_GPIO13 _PIN(37) +#define CAPRI_PIN_GPIO14 _PIN(38) +#define CAPRI_PIN_GPS_PABLANK _PIN(39) +#define CAPRI_PIN_GPS_TMARK _PIN(40) +#define CAPRI_PIN_HDMI_SCL _PIN(41) +#define CAPRI_PIN_HDMI_SDA _PIN(42) +#define CAPRI_PIN_IC_DM _PIN(43) +#define CAPRI_PIN_IC_DP _PIN(44) +#define CAPRI_PIN_KP_COL_IP_0 _PIN(45) +#define CAPRI_PIN_KP_COL_IP_1 _PIN(46) +#define CAPRI_PIN_KP_COL_IP_2 _PIN(47) +#define CAPRI_PIN_KP_COL_IP_3 _PIN(48) +#define CAPRI_PIN_KP_ROW_OP_0 _PIN(49) +#define CAPRI_PIN_KP_ROW_OP_1 _PIN(50) +#define CAPRI_PIN_KP_ROW_OP_2 _PIN(51) +#define CAPRI_PIN_KP_ROW_OP_3 _PIN(52) +#define CAPRI_PIN_LCD_B_0 _PIN(53) +#define CAPRI_PIN_LCD_B_1 _PIN(54) +#define CAPRI_PIN_LCD_B_2 _PIN(55) +#define CAPRI_PIN_LCD_B_3 _PIN(56) +#define CAPRI_PIN_LCD_B_4 _PIN(57) +#define CAPRI_PIN_LCD_B_5 _PIN(58) +#define CAPRI_PIN_LCD_B_6 _PIN(59) +#define CAPRI_PIN_LCD_B_7 _PIN(60) +#define CAPRI_PIN_LCD_G_0 _PIN(61) +#define CAPRI_PIN_LCD_G_1 _PIN(62) +#define CAPRI_PIN_LCD_G_2 _PIN(63) +#define CAPRI_PIN_LCD_G_3 _PIN(64) +#define CAPRI_PIN_LCD_G_4 _PIN(65) +#define CAPRI_PIN_LCD_G_5 _PIN(66) +#define CAPRI_PIN_LCD_G_6 _PIN(67) +#define CAPRI_PIN_LCD_G_7 _PIN(68) +#define CAPRI_PIN_LCD_HSYNC _PIN(69) +#define CAPRI_PIN_LCD_OE _PIN(70) +#define CAPRI_PIN_LCD_PCLK _PIN(71) +#define CAPRI_PIN_LCD_R_0 _PIN(72) +#define CAPRI_PIN_LCD_R_1 _PIN(73) +#define CAPRI_PIN_LCD_R_2 _PIN(74) +#define CAPRI_PIN_LCD_R_3 _PIN(75) +#define CAPRI_PIN_LCD_R_4 _PIN(76) +#define CAPRI_PIN_LCD_R_5 _PIN(77) +#define CAPRI_PIN_LCD_R_6 _PIN(78) +#define CAPRI_PIN_LCD_R_7 _PIN(79) +#define CAPRI_PIN_LCD_VSYNC _PIN(80) +#define CAPRI_PIN_MDMGPIO0 _PIN(81) +#define CAPRI_PIN_MDMGPIO1 _PIN(82) +#define CAPRI_PIN_MDMGPIO2 _PIN(83) +#define CAPRI_PIN_MDMGPIO3 _PIN(84) +#define CAPRI_PIN_MDMGPIO4 _PIN(85) +#define CAPRI_PIN_MDMGPIO5 _PIN(86) +#define CAPRI_PIN_MDMGPIO6 _PIN(87) +#define CAPRI_PIN_MDMGPIO7 _PIN(88) +#define CAPRI_PIN_MDMGPIO8 _PIN(89) +#define CAPRI_PIN_MPHI_DATA_0 _PIN(90) +#define CAPRI_PIN_MPHI_DATA_1 _PIN(91) +#define CAPRI_PIN_MPHI_DATA_2 _PIN(92) +#define CAPRI_PIN_MPHI_DATA_3 _PIN(93) +#define CAPRI_PIN_MPHI_DATA_4 _PIN(94) +#define CAPRI_PIN_MPHI_DATA_5 _PIN(95) +#define CAPRI_PIN_MPHI_DATA_6 _PIN(96) +#define CAPRI_PIN_MPHI_DATA_7 _PIN(97) +#define CAPRI_PIN_MPHI_DATA_8 _PIN(98) +#define CAPRI_PIN_MPHI_DATA_9 _PIN(99) +#define CAPRI_PIN_MPHI_DATA_10 _PIN(100) +#define CAPRI_PIN_MPHI_DATA_11 _PIN(101) +#define CAPRI_PIN_MPHI_DATA_12 _PIN(102) +#define CAPRI_PIN_MPHI_DATA_13 _PIN(103) +#define CAPRI_PIN_MPHI_DATA_14 _PIN(104) +#define CAPRI_PIN_MPHI_DATA_15 _PIN(105) +#define CAPRI_PIN_MPHI_HA0 _PIN(106) +#define CAPRI_PIN_MPHI_HAT0 _PIN(107) +#define CAPRI_PIN_MPHI_HAT1 _PIN(108) +#define CAPRI_PIN_MPHI_HCE0_N _PIN(109) +#define CAPRI_PIN_MPHI_HCE1_N _PIN(110) +#define CAPRI_PIN_MPHI_HRD_N _PIN(111) +#define CAPRI_PIN_MPHI_HWR_N _PIN(112) +#define CAPRI_PIN_MPHI_RUN0 _PIN(113) +#define CAPRI_PIN_MPHI_RUN1 _PIN(114) +#define CAPRI_PIN_MTX_SCAN_CLK _PIN(115) +#define CAPRI_PIN_MTX_SCAN_DATA _PIN(116) +#define CAPRI_PIN_NAND_AD_0 _PIN(117) +#define CAPRI_PIN_NAND_AD_1 _PIN(118) +#define CAPRI_PIN_NAND_AD_2 _PIN(119) +#define CAPRI_PIN_NAND_AD_3 _PIN(120) +#define CAPRI_PIN_NAND_AD_4 _PIN(121) +#define CAPRI_PIN_NAND_AD_5 _PIN(122) +#define CAPRI_PIN_NAND_AD_6 _PIN(123) +#define CAPRI_PIN_NAND_AD_7 _PIN(124) +#define CAPRI_PIN_NAND_ALE _PIN(125) +#define CAPRI_PIN_NAND_CEN_0 _PIN(126) +#define CAPRI_PIN_NAND_CEN_1 _PIN(127) +#define CAPRI_PIN_NAND_CLE _PIN(128) +#define CAPRI_PIN_NAND_OEN _PIN(129) +#define CAPRI_PIN_NAND_RDY_0 _PIN(130) +#define CAPRI_PIN_NAND_RDY_1 _PIN(131) +#define CAPRI_PIN_NAND_WEN _PIN(132) +#define CAPRI_PIN_NAND_WP _PIN(133) +#define CAPRI_PIN_PC1 _PIN(134) +#define CAPRI_PIN_PC2 _PIN(135) +#define CAPRI_PIN_PMU_INT _PIN(136) +#define CAPRI_PIN_PMU_SCL _PIN(137) +#define CAPRI_PIN_PMU_SDA _PIN(138) +#define CAPRI_PIN_RFST2G_MTSLOTEN3G _PIN(139) +#define CAPRI_PIN_RGMII_0_RX_CTL _PIN(140) +#define CAPRI_PIN_RGMII_0_RXC _PIN(141) +#define CAPRI_PIN_RGMII_0_RXD_0 _PIN(142) +#define CAPRI_PIN_RGMII_0_RXD_1 _PIN(143) +#define CAPRI_PIN_RGMII_0_RXD_2 _PIN(144) +#define CAPRI_PIN_RGMII_0_RXD_3 _PIN(145) +#define CAPRI_PIN_RGMII_0_TX_CTL _PIN(146) +#define CAPRI_PIN_RGMII_0_TXC _PIN(147) +#define CAPRI_PIN_RGMII_0_TXD_0 _PIN(148) +#define CAPRI_PIN_RGMII_0_TXD_1 _PIN(149) +#define CAPRI_PIN_RGMII_0_TXD_2 _PIN(150) +#define CAPRI_PIN_RGMII_0_TXD_3 _PIN(151) +#define CAPRI_PIN_RGMII_1_RX_CTL _PIN(152) +#define CAPRI_PIN_RGMII_1_RXC _PIN(153) +#define CAPRI_PIN_RGMII_1_RXD_0 _PIN(154) +#define CAPRI_PIN_RGMII_1_RXD_1 _PIN(155) +#define CAPRI_PIN_RGMII_1_RXD_2 _PIN(156) +#define CAPRI_PIN_RGMII_1_RXD_3 _PIN(157) +#define CAPRI_PIN_RGMII_1_TX_CTL _PIN(158) +#define CAPRI_PIN_RGMII_1_TXC _PIN(159) +#define CAPRI_PIN_RGMII_1_TXD_0 _PIN(160) +#define CAPRI_PIN_RGMII_1_TXD_1 _PIN(161) +#define CAPRI_PIN_RGMII_1_TXD_2 _PIN(162) +#define CAPRI_PIN_RGMII_1_TXD_3 _PIN(163) +#define CAPRI_PIN_RGMII_GPIO_0 _PIN(164) +#define CAPRI_PIN_RGMII_GPIO_1 _PIN(165) +#define CAPRI_PIN_RGMII_GPIO_2 _PIN(166) +#define CAPRI_PIN_RGMII_GPIO_3 _PIN(167) +#define CAPRI_PIN_RTXDATA2G_TXDATA3G1 _PIN(168) +#define CAPRI_PIN_RTXEN2G_TXDATA3G2 _PIN(169) +#define CAPRI_PIN_RXDATA3G0 _PIN(170) +#define CAPRI_PIN_RXDATA3G1 _PIN(171) +#define CAPRI_PIN_RXDATA3G2 _PIN(172) +#define CAPRI_PIN_SDIO1_CLK _PIN(173) +#define CAPRI_PIN_SDIO1_CMD _PIN(174) +#define CAPRI_PIN_SDIO1_DATA_0 _PIN(175) +#define CAPRI_PIN_SDIO1_DATA_1 _PIN(176) +#define CAPRI_PIN_SDIO1_DATA_2 _PIN(177) +#define CAPRI_PIN_SDIO1_DATA_3 _PIN(178) +#define CAPRI_PIN_SDIO4_CLK _PIN(179) +#define CAPRI_PIN_SDIO4_CMD _PIN(180) +#define CAPRI_PIN_SDIO4_DATA_0 _PIN(181) +#define CAPRI_PIN_SDIO4_DATA_1 _PIN(182) +#define CAPRI_PIN_SDIO4_DATA_2 _PIN(183) +#define CAPRI_PIN_SDIO4_DATA_3 _PIN(184) +#define CAPRI_PIN_SIM_CLK _PIN(185) +#define CAPRI_PIN_SIM_DATA _PIN(186) +#define CAPRI_PIN_SIM_DET _PIN(187) +#define CAPRI_PIN_SIM_RESETN _PIN(188) +#define CAPRI_PIN_SIM2_CLK _PIN(189) +#define CAPRI_PIN_SIM2_DATA _PIN(190) +#define CAPRI_PIN_SIM2_DET _PIN(191) +#define CAPRI_PIN_SIM2_RESETN _PIN(192) +#define CAPRI_PIN_SRI_C _PIN(193) +#define CAPRI_PIN_SRI_D _PIN(194) +#define CAPRI_PIN_SRI_E _PIN(195) +#define CAPRI_PIN_SSP_EXTCLK _PIN(196) +#define CAPRI_PIN_SSP0_CLK _PIN(197) +#define CAPRI_PIN_SSP0_FS _PIN(198) +#define CAPRI_PIN_SSP0_RXD _PIN(199) +#define CAPRI_PIN_SSP0_TXD _PIN(200) +#define CAPRI_PIN_SSP2_CLK _PIN(201) +#define CAPRI_PIN_SSP2_FS_0 _PIN(202) +#define CAPRI_PIN_SSP2_FS_1 _PIN(203) +#define CAPRI_PIN_SSP2_FS_2 _PIN(204) +#define CAPRI_PIN_SSP2_FS_3 _PIN(205) +#define CAPRI_PIN_SSP2_RXD_0 _PIN(206) +#define CAPRI_PIN_SSP2_RXD_1 _PIN(207) +#define CAPRI_PIN_SSP2_TXD_0 _PIN(208) +#define CAPRI_PIN_SSP2_TXD_1 _PIN(209) +#define CAPRI_PIN_SSP3_CLK _PIN(210) +#define CAPRI_PIN_SSP3_FS _PIN(211) +#define CAPRI_PIN_SSP3_RXD _PIN(212) +#define CAPRI_PIN_SSP3_TXD _PIN(213) +#define CAPRI_PIN_SSP4_CLK _PIN(214) +#define CAPRI_PIN_SSP4_FS _PIN(215) +#define CAPRI_PIN_SSP4_RXD _PIN(216) +#define CAPRI_PIN_SSP4_TXD _PIN(217) +#define CAPRI_PIN_SSP5_CLK _PIN(218) +#define CAPRI_PIN_SSP5_FS _PIN(219) +#define CAPRI_PIN_SSP5_RXD _PIN(220) +#define CAPRI_PIN_SSP5_TXD _PIN(221) +#define CAPRI_PIN_SSP6_CLK _PIN(222) +#define CAPRI_PIN_SSP6_FS _PIN(223) +#define CAPRI_PIN_SSP6_RXD _PIN(224) +#define CAPRI_PIN_SSP6_TXD _PIN(225) +#define CAPRI_PIN_STAT_1 _PIN(226) +#define CAPRI_PIN_STAT_2 _PIN(227) +#define CAPRI_PIN_SYSCLKEN _PIN(228) +#define CAPRI_PIN_TRACECLK _PIN(229) +#define CAPRI_PIN_TRACEDT00 _PIN(230) +#define CAPRI_PIN_TRACEDT01 _PIN(231) +#define CAPRI_PIN_TRACEDT02 _PIN(232) +#define CAPRI_PIN_TRACEDT03 _PIN(233) +#define CAPRI_PIN_TRACEDT04 _PIN(234) +#define CAPRI_PIN_TRACEDT05 _PIN(235) +#define CAPRI_PIN_TRACEDT06 _PIN(236) +#define CAPRI_PIN_TRACEDT07 _PIN(237) +#define CAPRI_PIN_TRACEDT08 _PIN(238) +#define CAPRI_PIN_TRACEDT09 _PIN(239) +#define CAPRI_PIN_TRACEDT10 _PIN(240) +#define CAPRI_PIN_TRACEDT11 _PIN(241) +#define CAPRI_PIN_TRACEDT12 _PIN(242) +#define CAPRI_PIN_TRACEDT13 _PIN(243) +#define CAPRI_PIN_TRACEDT14 _PIN(244) +#define CAPRI_PIN_TRACEDT15 _PIN(245) +#define CAPRI_PIN_TXDATA3G0 _PIN(246) +#define CAPRI_PIN_TXPWRIND _PIN(247) +#define CAPRI_PIN_UARTB1_UCTS _PIN(248) +#define CAPRI_PIN_UARTB1_URTS _PIN(249) +#define CAPRI_PIN_UARTB1_URXD _PIN(250) +#define CAPRI_PIN_UARTB1_UTXD _PIN(251) +#define CAPRI_PIN_UARTB2_URXD _PIN(252) +#define CAPRI_PIN_UARTB2_UTXD _PIN(253) +#define CAPRI_PIN_UARTB3_UCTS _PIN(254) +#define CAPRI_PIN_UARTB3_URTS _PIN(255) +#define CAPRI_PIN_UARTB3_URXD _PIN(256) +#define CAPRI_PIN_UARTB3_UTXD _PIN(257) +#define CAPRI_PIN_UARTB4_UCTS _PIN(258) +#define CAPRI_PIN_UARTB4_URTS _PIN(259) +#define CAPRI_PIN_UARTB4_URXD _PIN(260) +#define CAPRI_PIN_UARTB4_UTXD _PIN(261) +#define CAPRI_PIN_VC_CAM1_SCL _PIN(262) +#define CAPRI_PIN_VC_CAM1_SDA _PIN(263) +#define CAPRI_PIN_VC_CAM2_SCL _PIN(264) +#define CAPRI_PIN_VC_CAM2_SDA _PIN(265) +#define CAPRI_PIN_VC_CAM3_SCL _PIN(266) +#define CAPRI_PIN_VC_CAM3_SDA _PIN(267) + +#define CAPRI_PIN_DESC(a, b, c) \ + { .number = a, .name = b, .drv_data = &c##_pin } + +/* + * Pin description definition. The order here must be the same as defined in + * the PADCTRLREG block in the RDB, since the pin number is used as an index + * into this array. + */ +static const struct pinctrl_pin_desc capri_pinctrl_pins[] = { + CAPRI_PIN_DESC(CAPRI_PIN_ADCSYNC, "adcsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_BAT_RM, "bat_rm", std), + CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SCL, "bsc1_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SDA, "bsc1_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SCL, "bsc2_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SDA, "bsc2_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_CLASSGPWR, "classgpwr", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLK_CX8, "clk_cx8", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_0, "clkout_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_1, "clkout_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_2, "clkout_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_3, "clkout_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_0, "clkreq_in_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_1, "clkreq_in_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ1, "cws_sys_req1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ2, "cws_sys_req2", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ3, "cws_sys_req3", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_CLK, "digmic1_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_DQ, "digmic1_dq", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_CLK, "digmic2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_DQ, "digmic2_dq", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN13, "gpen13", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN14, "gpen14", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN15, "gpen15", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO00, "gpio00", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO01, "gpio01", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO02, "gpio02", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO03, "gpio03", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO04, "gpio04", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO05, "gpio05", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO06, "gpio06", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO07, "gpio07", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO08, "gpio08", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO09, "gpio09", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO10, "gpio10", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO11, "gpio11", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO12, "gpio12", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO13, "gpio13", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO14, "gpio14", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPS_PABLANK, "gps_pablank", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPS_TMARK, "gps_tmark", std), + CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SCL, "hdmi_scl", hdmi), + CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SDA, "hdmi_sda", hdmi), + CAPRI_PIN_DESC(CAPRI_PIN_IC_DM, "ic_dm", std), + CAPRI_PIN_DESC(CAPRI_PIN_IC_DP, "ic_dp", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_0, "kp_col_ip_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_1, "kp_col_ip_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_2, "kp_col_ip_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_3, "kp_col_ip_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_0, "kp_row_op_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_1, "kp_row_op_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_2, "kp_row_op_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_3, "kp_row_op_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_0, "lcd_b_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_1, "lcd_b_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_2, "lcd_b_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_3, "lcd_b_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_4, "lcd_b_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_5, "lcd_b_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_6, "lcd_b_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_7, "lcd_b_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_0, "lcd_g_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_1, "lcd_g_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_2, "lcd_g_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_3, "lcd_g_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_4, "lcd_g_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_5, "lcd_g_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_6, "lcd_g_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_7, "lcd_g_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_HSYNC, "lcd_hsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_OE, "lcd_oe", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_PCLK, "lcd_pclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_0, "lcd_r_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_1, "lcd_r_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_2, "lcd_r_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_3, "lcd_r_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_4, "lcd_r_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_5, "lcd_r_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_6, "lcd_r_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_7, "lcd_r_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_VSYNC, "lcd_vsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO0, "mdmgpio0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO1, "mdmgpio1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO2, "mdmgpio2", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO3, "mdmgpio3", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO4, "mdmgpio4", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO5, "mdmgpio5", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO6, "mdmgpio6", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO7, "mdmgpio7", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO8, "mdmgpio8", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_0, "mphi_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_1, "mphi_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_2, "mphi_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_3, "mphi_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_4, "mphi_data_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_5, "mphi_data_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_6, "mphi_data_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_7, "mphi_data_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_8, "mphi_data_8", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_9, "mphi_data_9", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_10, "mphi_data_10", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_11, "mphi_data_11", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_12, "mphi_data_12", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_13, "mphi_data_13", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_14, "mphi_data_14", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_15, "mphi_data_15", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HA0, "mphi_ha0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT0, "mphi_hat0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT1, "mphi_hat1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE0_N, "mphi_hce0_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE1_N, "mphi_hce1_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HRD_N, "mphi_hrd_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HWR_N, "mphi_hwr_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN0, "mphi_run0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN1, "mphi_run1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_DATA, "mtx_scan_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_0, "nand_ad_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_1, "nand_ad_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_2, "nand_ad_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_3, "nand_ad_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_4, "nand_ad_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_5, "nand_ad_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_6, "nand_ad_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_7, "nand_ad_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_ALE, "nand_ale", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_0, "nand_cen_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_1, "nand_cen_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CLE, "nand_cle", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_OEN, "nand_oen", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_0, "nand_rdy_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_1, "nand_rdy_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_WEN, "nand_wen", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_WP, "nand_wp", std), + CAPRI_PIN_DESC(CAPRI_PIN_PC1, "pc1", std), + CAPRI_PIN_DESC(CAPRI_PIN_PC2, "pc2", std), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_INT, "pmu_int", std), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_SCL, "pmu_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_SDA, "pmu_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXC, "rgmii_0_rxc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXC, "rgmii_0_txc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXC, "rgmii_1_rxc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXC, "rgmii_1_txc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RTXDATA2G_TXDATA3G1, "rtxdata2g_txdata3g1", + std), + CAPRI_PIN_DESC(CAPRI_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G0, "rxdata3g0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G1, "rxdata3g1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G2, "rxdata3g2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CLK, "sdio1_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CMD, "sdio1_cmd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_0, "sdio1_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_1, "sdio1_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_2, "sdio1_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_3, "sdio1_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CLK, "sdio4_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CMD, "sdio4_cmd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_0, "sdio4_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_1, "sdio4_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_2, "sdio4_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_3, "sdio4_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_CLK, "sim_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_DATA, "sim_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_DET, "sim_det", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_RESETN, "sim_resetn", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_CLK, "sim2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DATA, "sim2_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DET, "sim2_det", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_RESETN, "sim2_resetn", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_C, "sri_c", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_D, "sri_d", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_E, "sri_e", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP_EXTCLK, "ssp_extclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_CLK, "ssp0_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_FS, "ssp0_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_RXD, "ssp0_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_TXD, "ssp0_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_CLK, "ssp2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_0, "ssp2_fs_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_1, "ssp2_fs_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_2, "ssp2_fs_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_3, "ssp2_fs_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_0, "ssp2_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_1, "ssp2_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_0, "ssp2_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_1, "ssp2_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_CLK, "ssp3_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_FS, "ssp3_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_RXD, "ssp3_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_TXD, "ssp3_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_CLK, "ssp4_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_FS, "ssp4_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_RXD, "ssp4_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_TXD, "ssp4_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_CLK, "ssp5_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_FS, "ssp5_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_RXD, "ssp5_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_TXD, "ssp5_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_CLK, "ssp6_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_FS, "ssp6_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_RXD, "ssp6_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_TXD, "ssp6_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_STAT_1, "stat_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_STAT_2, "stat_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SYSCLKEN, "sysclken", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACECLK, "traceclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT00, "tracedt00", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT01, "tracedt01", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT02, "tracedt02", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT03, "tracedt03", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT04, "tracedt04", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT05, "tracedt05", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT06, "tracedt06", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT07, "tracedt07", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT08, "tracedt08", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT09, "tracedt09", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT10, "tracedt10", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT11, "tracedt11", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT12, "tracedt12", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT13, "tracedt13", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT14, "tracedt14", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT15, "tracedt15", std), + CAPRI_PIN_DESC(CAPRI_PIN_TXDATA3G0, "txdata3g0", std), + CAPRI_PIN_DESC(CAPRI_PIN_TXPWRIND, "txpwrind", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UCTS, "uartb1_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URTS, "uartb1_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URXD, "uartb1_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UTXD, "uartb1_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_URXD, "uartb2_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_UTXD, "uartb2_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UCTS, "uartb3_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URTS, "uartb3_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URXD, "uartb3_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UTXD, "uartb3_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UCTS, "uartb4_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URTS, "uartb4_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URXD, "uartb4_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UTXD, "uartb4_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c), +}; + +static const char * const capri_alt_groups[] = { + "adcsync", + "bat_rm", + "bsc1_scl", + "bsc1_sda", + "bsc2_scl", + "bsc2_sda", + "classgpwr", + "clk_cx8", + "clkout_0", + "clkout_1", + "clkout_2", + "clkout_3", + "clkreq_in_0", + "clkreq_in_1", + "cws_sys_req1", + "cws_sys_req2", + "cws_sys_req3", + "digmic1_clk", + "digmic1_dq", + "digmic2_clk", + "digmic2_dq", + "gpen13", + "gpen14", + "gpen15", + "gpio00", + "gpio01", + "gpio02", + "gpio03", + "gpio04", + "gpio05", + "gpio06", + "gpio07", + "gpio08", + "gpio09", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gps_pablank", + "gps_tmark", + "hdmi_scl", + "hdmi_sda", + "ic_dm", + "ic_dp", + "kp_col_ip_0", + "kp_col_ip_1", + "kp_col_ip_2", + "kp_col_ip_3", + "kp_row_op_0", + "kp_row_op_1", + "kp_row_op_2", + "kp_row_op_3", + "lcd_b_0", + "lcd_b_1", + "lcd_b_2", + "lcd_b_3", + "lcd_b_4", + "lcd_b_5", + "lcd_b_6", + "lcd_b_7", + "lcd_g_0", + "lcd_g_1", + "lcd_g_2", + "lcd_g_3", + "lcd_g_4", + "lcd_g_5", + "lcd_g_6", + "lcd_g_7", + "lcd_hsync", + "lcd_oe", + "lcd_pclk", + "lcd_r_0", + "lcd_r_1", + "lcd_r_2", + "lcd_r_3", + "lcd_r_4", + "lcd_r_5", + "lcd_r_6", + "lcd_r_7", + "lcd_vsync", + "mdmgpio0", + "mdmgpio1", + "mdmgpio2", + "mdmgpio3", + "mdmgpio4", + "mdmgpio5", + "mdmgpio6", + "mdmgpio7", + "mdmgpio8", + "mphi_data_0", + "mphi_data_1", + "mphi_data_2", + "mphi_data_3", + "mphi_data_4", + "mphi_data_5", + "mphi_data_6", + "mphi_data_7", + "mphi_data_8", + "mphi_data_9", + "mphi_data_10", + "mphi_data_11", + "mphi_data_12", + "mphi_data_13", + "mphi_data_14", + "mphi_data_15", + "mphi_ha0", + "mphi_hat0", + "mphi_hat1", + "mphi_hce0_n", + "mphi_hce1_n", + "mphi_hrd_n", + "mphi_hwr_n", + "mphi_run0", + "mphi_run1", + "mtx_scan_clk", + "mtx_scan_data", + "nand_ad_0", + "nand_ad_1", + "nand_ad_2", + "nand_ad_3", + "nand_ad_4", + "nand_ad_5", + "nand_ad_6", + "nand_ad_7", + "nand_ale", + "nand_cen_0", + "nand_cen_1", + "nand_cle", + "nand_oen", + "nand_rdy_0", + "nand_rdy_1", + "nand_wen", + "nand_wp", + "pc1", + "pc2", + "pmu_int", + "pmu_scl", + "pmu_sda", + "rfst2g_mtsloten3g", + "rgmii_0_rx_ctl", + "rgmii_0_rxc", + "rgmii_0_rxd_0", + "rgmii_0_rxd_1", + "rgmii_0_rxd_2", + "rgmii_0_rxd_3", + "rgmii_0_tx_ctl", + "rgmii_0_txc", + "rgmii_0_txd_0", + "rgmii_0_txd_1", + "rgmii_0_txd_2", + "rgmii_0_txd_3", + "rgmii_1_rx_ctl", + "rgmii_1_rxc", + "rgmii_1_rxd_0", + "rgmii_1_rxd_1", + "rgmii_1_rxd_2", + "rgmii_1_rxd_3", + "rgmii_1_tx_ctl", + "rgmii_1_txc", + "rgmii_1_txd_0", + "rgmii_1_txd_1", + "rgmii_1_txd_2", + "rgmii_1_txd_3", + "rgmii_gpio_0", + "rgmii_gpio_1", + "rgmii_gpio_2", + "rgmii_gpio_3", + "rtxdata2g_txdata3g1", + "rtxen2g_txdata3g2", + "rxdata3g0", + "rxdata3g1", + "rxdata3g2", + "sdio1_clk", + "sdio1_cmd", + "sdio1_data_0", + "sdio1_data_1", + "sdio1_data_2", + "sdio1_data_3", + "sdio4_clk", + "sdio4_cmd", + "sdio4_data_0", + "sdio4_data_1", + "sdio4_data_2", + "sdio4_data_3", + "sim_clk", + "sim_data", + "sim_det", + "sim_resetn", + "sim2_clk", + "sim2_data", + "sim2_det", + "sim2_resetn", + "sri_c", + "sri_d", + "sri_e", + "ssp_extclk", + "ssp0_clk", + "ssp0_fs", + "ssp0_rxd", + "ssp0_txd", + "ssp2_clk", + "ssp2_fs_0", + "ssp2_fs_1", + "ssp2_fs_2", + "ssp2_fs_3", + "ssp2_rxd_0", + "ssp2_rxd_1", + "ssp2_txd_0", + "ssp2_txd_1", + "ssp3_clk", + "ssp3_fs", + "ssp3_rxd", + "ssp3_txd", + "ssp4_clk", + "ssp4_fs", + "ssp4_rxd", + "ssp4_txd", + "ssp5_clk", + "ssp5_fs", + "ssp5_rxd", + "ssp5_txd", + "ssp6_clk", + "ssp6_fs", + "ssp6_rxd", + "ssp6_txd", + "stat_1", + "stat_2", + "sysclken", + "traceclk", + "tracedt00", + "tracedt01", + "tracedt02", + "tracedt03", + "tracedt04", + "tracedt05", + "tracedt06", + "tracedt07", + "tracedt08", + "tracedt09", + "tracedt10", + "tracedt11", + "tracedt12", + "tracedt13", + "tracedt14", + "tracedt15", + "txdata3g0", + "txpwrind", + "uartb1_ucts", + "uartb1_urts", + "uartb1_urxd", + "uartb1_utxd", + "uartb2_urxd", + "uartb2_utxd", + "uartb3_ucts", + "uartb3_urts", + "uartb3_urxd", + "uartb3_utxd", + "uartb4_ucts", + "uartb4_urts", + "uartb4_urxd", + "uartb4_utxd", + "vc_cam1_scl", + "vc_cam1_sda", + "vc_cam2_scl", + "vc_cam2_sda", + "vc_cam3_scl", + "vc_cam3_sda", +}; + +/* Every pin can implement all ALT1-ALT4 functions */ +#define CAPRI_PIN_FUNCTION(fcn_name) \ +{ \ + .name = #fcn_name, \ + .groups = capri_alt_groups, \ + .ngroups = ARRAY_SIZE(capri_alt_groups), \ +} + +static const struct capri_pin_function capri_functions[] = { + CAPRI_PIN_FUNCTION(alt1), + CAPRI_PIN_FUNCTION(alt2), + CAPRI_PIN_FUNCTION(alt3), + CAPRI_PIN_FUNCTION(alt4), +}; + +static struct capri_pinctrl_data capri_pinctrl = { + .pins = capri_pinctrl_pins, + .npins = ARRAY_SIZE(capri_pinctrl_pins), + .functions = capri_functions, + .nfunctions = ARRAY_SIZE(capri_functions), +}; + +static int capri_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->npins; +} + +static const char *capri_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->pins[group].name; +} + +static int capri_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pdata->pins[group].number; + *num_pins = 1; + + return 0; +} + +static void capri_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} + +static void capri_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned num_maps) +{ + int i; + + /* + * First free all the per-pin config arrays since they are dynamically + * allocated. + */ + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + + kfree(map); +} + +/** + * capri_resize_map - krealloc for pinctrl_map + * @pctldev: ptr to pinctrl_dev, for logging purposes + * @map: ptr to pinctrl_map array + * @nmaps: in - current size of pinctrl_map, out - new size of pinctrl_map + * @change: number of elements to expand/shrink pinctrl_map array by + * + * Shrinks or expands the existing pinctrl_map <maps> by <change> elements by + * memory reallocation. Sets the new elements to zero before returning. + * the new array is <nmaps + change> elements long. + */ +static int capri_resize_map(struct pinctrl_dev *pctldev, + struct pinctrl_map **map, + unsigned *nmaps, + int change) +{ + int old_num = *nmaps; + int new_num = old_num + change; + struct pinctrl_map *new_map; + + /* If no change, just return */ + if (!change) + goto resize_exit; + + /* New size should never be < 0 */ + if (new_num < 0) { + dev_warn(pctldev->dev, + "Negative size requested for pinctrl_map\n"); + new_num = 0; + } + + /* Shrink or expand map */ + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) { + dev_err(pctldev->dev, "No memory for new pinctrl mappings.\n"); + return -ENOMEM; + } + + /* Clear new maps */ + if (change > 0) + memset(new_map + old_num, 0, change * sizeof(*new_map)); + + *map = new_map; + *nmaps = new_num; + +resize_exit: + dev_dbg(pctldev->dev, "%s(): pinctrl_map size %d->%d\n", + __func__, old_num, new_num); + + return 0; +} + +/* Add a pinmux mapping for one pin */ +static int capri_dt_pinmux_to_map(struct pinctrl_dev *pctldev, + struct device_node *pnode, + struct pinctrl_map **map, + int *map_index, + int pin_count, + int pin_index, + const char *pin_name) +{ + int mux_count, index, ret; + const char *function = NULL; + + mux_count = of_property_count_strings(pnode, "brcm,function"); + + dev_dbg(pctldev->dev, "%s(): mux_count = %d\n", __func__, mux_count); + + if (mux_count <= 0) + /* Nothing to do, just return */ + return 0; + else if ((mux_count != 1) && (mux_count != pin_count)) { + dev_err(pctldev->dev, + "%s(): Invalid # of functions in DT node %s.\n", + __func__, pnode->name); + return -EINVAL; + } + + index = (mux_count == 1 ? 0 : pin_index); + + ret = of_property_read_string_index(pnode, + "brcm,function", + index, + &function); + if (ret < 0) { + dev_err(pctldev->dev, + "%s(): Error reading pinmux in node %s\n", + __func__, pnode->name); + return -EINVAL; + } + + /* + * dt_remember_or_free_map() will set the following members of + * struct pinctrl_map later: dev_name, name, ctrl_dev_name + */ + (*map)[*map_index].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*map_index].data.mux.group = pin_name; + (*map)[*map_index].data.mux.function = function; + + (*map_index)++; + + dev_dbg(pctldev->dev, "%s(): New pinmux mapping: %s->%s\n", + __func__, pin_name, function); + + return 0; +} + +/* Return the pin type for a given pin name */ +static enum capri_pin_type pin_type_get(struct pinctrl_dev *pctldev, + const char *pin_name) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + struct pinctrl_pin_desc const *desc; + int i; + + for (i = 0; i < pdata->npins; i++) { + desc = &pdata->pins[i]; + if (desc->name && !strcmp(pin_name, desc->name)) { + dev_dbg(pctldev->dev, + "%s(): Pin %s is pin number %d, type %d\n", + __func__, pin_name, desc->number, + *(enum capri_pin_type *)desc->drv_data); + + return *(enum capri_pin_type *)desc->drv_data; + } + } + + dev_warn(pctldev->dev, + "%s(): Cannot find pin named %s\n", + __func__, pin_name); + + return CAPRI_PIN_TYPE_UNKNOWN; +} + +static int capri_std_pin_update(struct pinctrl_dev *pctldev, + enum capri_pinconf_param param, + unsigned val, + u32 *reg_val, + u32 *reg_mask) +{ + switch (param) { + case CAPRI_PINCONF_PARAM_HYST: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Hysteresis.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, STD, HYST, val); + *reg_mask |= CAPRI_STD_PIN_REG_HYST_MASK; + break; + + case CAPRI_PINCONF_PARAM_PULL: + if (val > 3) { + dev_err(pctldev->dev, + "Invalid pin config for Pull up/down.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, STD, PULL, val); + *reg_mask |= CAPRI_STD_PIN_REG_PULL_MASK; + break; + + case CAPRI_PINCONF_PARAM_SLEW: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Slew Rate.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, STD, SLEW, val); + *reg_mask |= CAPRI_STD_PIN_REG_SLEW_MASK; + break; + + case CAPRI_PINCONF_PARAM_INPUT_DIS: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Input Disable.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, STD, INPUT_DIS, val); + *reg_mask |= CAPRI_STD_PIN_REG_INPUT_DIS_MASK; + break; + + case CAPRI_PINCONF_PARAM_DRV_STR: + /* Valid range is 2-16 mA, even numbers only */ + if ((val < 2) || (val > 16) || (val % 2)) { + dev_err(pctldev->dev, + "Invalid pin config for Drive Strength.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, STD, DRV_STR, (val/2)-1); + *reg_mask |= CAPRI_STD_PIN_REG_DRV_STR_MASK; + break; + + default: + dev_err(pctldev->dev, "Unrecognized pin config.\n"); + return -EINVAL; + + } /* switch config */ + + return 0; +} + +static int capri_i2c_pin_update(struct pinctrl_dev *pctldev, + enum capri_pinconf_param param, + unsigned val, + u32 *reg_val, + u32 *reg_mask) +{ + switch (param) { + case CAPRI_PINCONF_PARAM_PULL_UP_STR: + if (val > 7) { + dev_err(pctldev->dev, + "Invalid pin config for Pull Up Strength.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, I2C, PULL_UP_STR, val); + *reg_mask |= CAPRI_I2C_PIN_REG_PULL_UP_STR_MASK; + break; + + case CAPRI_PINCONF_PARAM_SLEW: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Slew Rate.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, I2C, SLEW, val); + *reg_mask |= CAPRI_I2C_PIN_REG_SLEW_MASK; + break; + + case CAPRI_PINCONF_PARAM_INPUT_DIS: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Input Disable.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, I2C, INPUT_DIS, val); + *reg_mask |= CAPRI_I2C_PIN_REG_INPUT_DIS_MASK; + break; + + default: + dev_err(pctldev->dev, "Unrecognized pin config.\n"); + return -EINVAL; + + } /* switch config */ + + return 0; +} + +static int capri_hdmi_pin_update(struct pinctrl_dev *pctldev, + enum capri_pinconf_param param, + unsigned val, + u32 *reg_val, + u32 *reg_mask) +{ + switch (param) { + case CAPRI_PINCONF_PARAM_MODE: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Mode.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, HDMI, MODE, val); + *reg_mask |= CAPRI_HDMI_PIN_REG_MODE_MASK; + break; + + case CAPRI_PINCONF_PARAM_INPUT_DIS: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Input Disable.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, HDMI, INPUT_DIS, val); + *reg_mask |= CAPRI_HDMI_PIN_REG_INPUT_DIS_MASK; + break; + + default: + dev_err(pctldev->dev, "Unrecognized pin config.\n"); + return -EINVAL; + + } /* switch config */ + + return 0; +} + +/** + * capri_dt_pincfg_to_map - Add a pincfg mapping for one pin + * @map_index - the index into the map array to write next + */ +static int capri_dt_pincfg_to_map(struct pinctrl_dev *pctldev, + struct device_node *pnode, + struct pinctrl_map **map, + int *map_index, + int pin_count, + int pin_index, + const char *pin_name) +{ + int val_count, prop_index, i, rc; + enum capri_pin_type pin_type; + unsigned long prop_val = 0; + u32 cfg_val, cfg_mask; + unsigned long *cfgs; + const struct capri_cfg_param *param; + struct property *prop; + + cfg_val = 0; + cfg_mask = 0; + + pin_type = pin_type_get(pctldev, pin_name); + if (pin_type == CAPRI_PIN_TYPE_UNKNOWN) + return -EINVAL; + + /* + * Loop through each of the defined pin config properties, and build + * cfg_val and cfg_mask as we go. cfg_val will be written straight to + * the pin config register when this pin config is applied. + */ + for (i = 0; i < ARRAY_SIZE(capri_pinconf_params); i++) { + param = &capri_pinconf_params[i]; + + /* TODO: replace with of_property_count_u32() */ + prop = of_find_property(pnode, param->property, NULL); + + if (!prop) + continue; + + val_count = prop->length / sizeof(u32); + + dev_dbg(pctldev->dev, "%s(): %d values for %s.\n", + __func__, val_count, param->property); + + if ((val_count != 1) && (val_count != pin_count)) { + dev_err(pctldev->dev, + "%s(): Invalid # of values for %s " + "in DT node %s\n", + __func__, param->property, pnode->name); + return -EINVAL; + } + + prop_index = (val_count == 1 ? 0 : pin_index); + + /* TODO: replace with of_property_read_u32_index() */ + prop_val = be32_to_cpup((u32 *)prop->value + prop_index); + + /* Different pins have different configuration options */ + switch (pin_type) { + case CAPRI_PIN_TYPE_STD: + rc = capri_std_pin_update(pctldev, + param->id, + prop_val, + &cfg_val, + &cfg_mask); + break; + + case CAPRI_PIN_TYPE_I2C: + rc = capri_i2c_pin_update(pctldev, + param->id, + prop_val, + &cfg_val, + &cfg_mask); + break; + + case CAPRI_PIN_TYPE_HDMI: + rc = capri_hdmi_pin_update(pctldev, + param->id, + prop_val, + &cfg_val, + &cfg_mask); + break; + + default: + dev_err(pctldev->dev, "Unknown pin type.\n"); + return -EINVAL; + + } /* switch pin type */ + + if (rc) { + dev_err(pctldev->dev, "Error setting pin config\n"); + return rc; + } + + dev_dbg(pctldev->dev, + "%s(): cfg_val=0x%x, cfg_mask=0x%x for pin %s\n", + __func__, cfg_val, cfg_mask, pin_name); + } /* for each defined pin config parameter */ + + /* + * In Capri, the top 16 bits of the pin control register are reserved, + * so we only need to set the lower 16 bits. Since the pinctrl core + * stores pin configs as an array of u32, we will pack the register + * value in the upper 16 bits and the mask in the lower 16 bits. + */ + cfgs = kmalloc(sizeof(unsigned long), GFP_KERNEL); + if (!cfgs) + return -ENOMEM; + + *cfgs = CAPRI_PINCONF_PACK(cfg_val, cfg_mask); + + /* + * dt_remember_or_free_map() will set the following members of + * struct pinctrl_map later: dev_name, name, ctrl_dev_name + */ + + dev_dbg(pctldev->dev, + "%s(): Add new pin conf map: config = 0x%lx for pin %s\n", + __func__, *cfgs, pin_name); + + (*map)[*map_index].type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)[*map_index].data.configs.group_or_pin = pin_name; + (*map)[*map_index].data.configs.configs = cfgs; + (*map)[*map_index].data.configs.num_configs = 1; + + (*map_index)++; + + return 0; +} + +/* Process the pin configuration node */ +static int capri_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *pnode, + struct pinctrl_map **map, + unsigned *nmaps) +{ + struct device_node *pchild; + int pin_count, pin_index, ret, map_index; + const char *pin_name; + struct property *prop; + + *map = NULL; + *nmaps = 0; + + /* Index of next spot to write in pinctrl_map array */ + map_index = 0; + + /* For each pin group */ + for_each_child_of_node(pnode, pchild) { + /* Requires at least 1 pin per group. */ + pin_count = of_property_count_strings(pchild, "brcm,pins"); + + dev_dbg(pctldev->dev, "%s(): Node %s configures %d pins.\n", + __func__, pchild->name, pin_count); + + if (pin_count <= 0) { + dev_err(pctldev->dev, + "%s(): No pins specified in DT node %s.\n", + __func__, pchild->name); + return -EINVAL; + } + + /* Pre-alloc a pinctrl_map array of size pin_count*2 */ + ret = capri_resize_map(pctldev, map, nmaps, pin_count * 2); + if (ret) + return ret; + + pin_index = 0; + + /* Create pin maps for each pin */ + of_property_for_each_string(pchild, + "brcm,pins", + prop, + pin_name) { + ret = capri_dt_pinmux_to_map(pctldev, + pchild, + map, + &map_index, + pin_count, + pin_index, + pin_name); + if (ret) + return ret; + + ret = capri_dt_pincfg_to_map(pctldev, + pchild, + map, + &map_index, + pin_count, + pin_index, + pin_name); + if (ret) + return ret; + dev_dbg(pctldev->dev, + "%s(): Done pin %s in, next map is %d\n", + __func__, pin_name, map_index); + pin_index++; + } /* for each pin */ + } /* for each group */ + + /* + * Clean up any over-allocated elements for the pinctrl_map array. This + * could be moved to the end of for each group loop, but it's probably + * more efficient here. + */ + if (map_index < *nmaps) { + ret = capri_resize_map(pctldev, map, nmaps, *nmaps-map_index); + if (ret) + return ret; + } + + return 0; +} + +static struct pinctrl_ops capri_pinctrl_ops = { + .get_groups_count = capri_pinctrl_get_groups_count, + .get_group_name = capri_pinctrl_get_group_name, + .get_group_pins = capri_pinctrl_get_group_pins, + .pin_dbg_show = capri_pinctrl_pin_dbg_show, + .dt_node_to_map = capri_pinctrl_dt_node_to_map, + .dt_free_map = capri_pinctrl_dt_free_map, +}; + +static int capri_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->nfunctions; +} + +static const char *capri_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->functions[function].name; +} + +static int capri_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *groups = pdata->functions[function].groups; + *num_groups = pdata->functions[function].ngroups; + + return 0; +} + +static int capri_pinmux_enable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + const struct capri_pin_function *f = &pdata->functions[function]; + void __iomem *reg = pdata->reg_base + (4 * pdata->pins[group].number); + u32 old_reg_val; + u32 new_reg_val; + + dev_dbg(pctldev->dev, + "%s(): Enable function %s (%d) of pin %s (%d) @reg 0x%p.\n", + __func__, f->name, function, pdata->pins[group].name, + pdata->pins[group].number, reg); + + old_reg_val = readl(reg); + new_reg_val = (old_reg_val & ~CAPRI_PIN_REG_F_SEL_MASK) + | ((function << CAPRI_PIN_REG_F_SEL_SHIFT) + & CAPRI_PIN_REG_F_SEL_MASK); + + if (new_reg_val != old_reg_val) { + dev_dbg(pctldev->dev, + "Reg 0x%p change from 0x%x to 0x%x\n", + reg, old_reg_val, new_reg_val); + writel(new_reg_val, reg); + } else + dev_dbg(pctldev->dev, + "Reg 0x%p=0x%x (no change)\n", + reg, old_reg_val); + + return 0; +} + +static struct pinmux_ops capri_pinctrl_pinmux_ops = { + .get_functions_count = capri_pinctrl_get_fcns_count, + .get_function_name = capri_pinctrl_get_fcn_name, + .get_function_groups = capri_pinctrl_get_fcn_groups, + .enable = capri_pinmux_enable, +}; + +static int capri_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + return -ENOTSUPP; +} + +static int capri_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + void __iomem *reg = pdata->reg_base + (4 * pin); + u32 old_reg_val; + u32 new_reg_val; + unsigned cfg_val, cfg_mask; + + /* + * This driver packs the pin config register value and mask into one + * 32 bit value, so it only expects 1 config. + */ + if ((num_configs != 1) || (!configs)) { + dev_err(pctldev->dev, + "Unable to set config pin %s - incorrect parameters", + pdata->pins[pin].name); + return -EPERM; + } + + cfg_val = CAPRI_PINCONF_UNPACK_VAL(*configs); + cfg_mask = CAPRI_PINCONF_UNPACK_MASK(*configs); + + dev_dbg(pctldev->dev, + "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n", + __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask); + + old_reg_val = readl(reg); + new_reg_val = (old_reg_val & ~cfg_mask) | cfg_val; + + if (new_reg_val != old_reg_val) { + dev_dbg(pctldev->dev, + "Reg 0x%p change from 0x%x to 0x%x\n", + reg, old_reg_val, new_reg_val); + writel(new_reg_val, reg); + } else + dev_dbg(pctldev->dev, + "Reg 0x%p=0x%x (no change)\n", + reg, old_reg_val); + + + return 0; +} + +static struct pinconf_ops capri_pinctrl_pinconf_ops = { + .pin_config_get = capri_pinctrl_pin_config_get, + .pin_config_set = capri_pinctrl_pin_config_set, +}; + +static struct pinctrl_desc capri_pinctrl_desc = { + /* name, pins, npins members initialized in probe function */ + .pctlops = &capri_pinctrl_ops, + .pmxops = &capri_pinctrl_pinmux_ops, + .confops = &capri_pinctrl_pinconf_ops, + .owner = THIS_MODULE, +}; + +int __init capri_pinctrl_probe(struct platform_device *pdev) +{ + struct capri_pinctrl_data *pdata = &capri_pinctrl; + struct resource *res; + struct pinctrl_dev *pctl; + + /* So far We can assume there is only 1 bank of registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Missing MEM resource\n"); + return -ENODEV; + } + + pdata->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pdata->reg_base)) { + dev_err(&pdev->dev, "Failed to ioremap MEM resource\n"); + return -ENODEV; + } + + /* Initialize the dynamic part of pinctrl_desc */ + capri_pinctrl_desc.name = dev_name(&pdev->dev); + capri_pinctrl_desc.pins = capri_pinctrl.pins; + capri_pinctrl_desc.npins = capri_pinctrl.npins; + + pctl = pinctrl_register(&capri_pinctrl_desc, + &pdev->dev, + pdata); + if (!pctl) { + dev_err(&pdev->dev, "Failed to register pinctrl\n"); + return -ENODEV; + } + + platform_set_drvdata(pdev, pdata); + + return 0; +} + +static struct of_device_id capri_pinctrl_of_match[] = { + { .compatible = "brcm,capri-pinctrl", }, + { }, +}; + +static struct platform_driver capri_pinctrl_driver = { + .driver = { + .name = "bcm-capri-pinctrl", + .owner = THIS_MODULE, + .of_match_table = capri_pinctrl_of_match, + }, +}; + +module_platform_driver_probe(capri_pinctrl_driver, capri_pinctrl_probe); + +MODULE_AUTHOR("Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>"); +MODULE_DESCRIPTION("Broadcom Capri pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-04 0:23 ` [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin @ 2013-10-09 9:10 ` Linus Walleij 2013-10-10 23:48 ` Sherman Yin 2013-10-17 6:03 ` Christian Daudt 1 sibling, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-10-09 9:10 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Fri, Oct 4, 2013 at 2:23 AM, Sherman Yin <syin@broadcom.com> wrote: > Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > Reviewed-by: Christian Daudt <bcm@fixthebug.org> > Reviewed-by: Matt Porter <matt.porter@linaro.org> (...) > +config PINCTRL_CAPRI > + bool "Broadcom Capri pinctrl driver" > + select PINMUX > + select PINCONF > + help > + Say Y here to support Broadcom Capri pinctrl driver, which is used for > + the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, > + BCM28145, and BCM28155 SoCs. This driver requires the pinctrl > + framework. GPIO is provided by a separate GPIO driver. As mentioned this should be selecting and using GENERIC_PINCONF. Basically I want that to happen before we look further at this code. (But I'll take a quick glance anyway...) > +#define CAPRI_PINCONF_PACK(val, mask) (((val) << 16) | ((mask) & 0xffff)) > +#define CAPRI_PINCONF_UNPACK_VAL(conf) ((conf) >> 16) > +#define CAPRI_PINCONF_UNPACK_MASK(conf) ((conf) & 0xffff) This custom horror goes away by using the macros from genric pin config <linux/pinctrl/pinconf-generic.h> instead. > +static const struct capri_cfg_param capri_pinconf_params[] = { > + {"brcm,hysteresis", CAPRI_PINCONF_PARAM_HYST}, > + {"brcm,pull", CAPRI_PINCONF_PARAM_PULL}, > + {"brcm,slew", CAPRI_PINCONF_PARAM_SLEW}, > + {"brcm,input_dis", CAPRI_PINCONF_PARAM_INPUT_DIS}, > + {"brcm,drive_str", CAPRI_PINCONF_PARAM_DRV_STR}, > + {"brcm,pull_up_str", CAPRI_PINCONF_PARAM_PULL_UP_STR}, > + {"brcm,mode", CAPRI_PINCONF_PARAM_MODE}, > +}; As well as all this stuff... > +/* Standard pin register */ Add some more elaborate explanation here. I am half-guessing that most of the registers are laid out like this and then there are two exceptions, then write that right here in the comment. (BTW: this is a HW/driver detail and should not be written in the device tree doc as was done in patch 2) > +/* Macro to update reg with new pin config param */ > +#define CAPRI_PIN_REG_SET(reg, type, param, val) \ > + (((reg) & ~CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK) \ > + | (((val) << CAPRI_ ## type ## _PIN_REG_ ## param ## _SHIFT) \ > + & CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK)) No thanks. Rewrite this into a static inline which has the same effect when compiling, but produces *WAY* more readable code than this horrid thing. Plus you can type the arguments. > +#define _PIN(offset) (offset) This macro isn't exactly useful. > +/* > + * Pin number definition. The order here must be the same as defined in the > + * PADCTRLREG block in the RDB. > + */ > +#define CAPRI_PIN_ADCSYNC _PIN(0) If it's just going to be like that, then skip the _PIN() macro. > +/* Process the pin configuration node */ > +static int capri_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, > + struct device_node *pnode, > + struct pinctrl_map **map, > + unsigned *nmaps) > +{ Make use of these from pinctrl-utils.c: pinctrl_utils_reserve_map() pinctrl_utils_add_map_mux() pinctrl_utils_add_map_configs() pinctrl_utils_dt_free_map() Then you get rid of another big chunk of boilerplate code. After these changes the driver will be much smaller and cleaner and we can take a closer look. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* RE: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-09 9:10 ` Linus Walleij @ 2013-10-10 23:48 ` Sherman Yin [not found] ` <051069C10411E24D9749790C498526FA1BE027EA-HXj2mutaA2pgyiERVvb/1Jr/X4hKkxxPpWgKQ6/u3Fg@public.gmane.org> 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-10-10 23:48 UTC (permalink / raw) To: Linus Walleij Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org >> +config PINCTRL_CAPRI >> + bool "Broadcom Capri pinctrl driver" >> + select PINMUX >> + select PINCONF >> + help >> + Say Y here to support Broadcom Capri pinctrl driver, which is used for >> + the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, >> + BCM28145, and BCM28155 SoCs. This driver requires the pinctrl >> + framework. GPIO is provided by a separate GPIO driver. > >As mentioned this should be selecting and using GENERIC_PINCONF. >Basically I want that to happen before we look further at this code. > >(But I'll take a quick glance anyway...) Sure, working on it. >> +#define CAPRI_PINCONF_PACK(val, mask) (((val) << 16) | ((mask) & 0xffff)) >> +#define CAPRI_PINCONF_UNPACK_VAL(conf) ((conf) >> 16) >> +#define CAPRI_PINCONF_UNPACK_MASK(conf) ((conf) & 0xffff) > >This custom horror goes away by using the macros from genric pin config ><linux/pinctrl/pinconf-generic.h> instead. Actually these are used differently than the pack/unpack functions in the pinconf- generic.h. These pack the bit value and bit mask to be written to a register, whereas the pinconf-generic ones pack the parameter id and value. But I get what you're saying and will try to reuse as much as possible from the pinconf generic functions and utils. >> +static const struct capri_cfg_param capri_pinconf_params[] = { >> + {"brcm,hysteresis", CAPRI_PINCONF_PARAM_HYST}, >> + {"brcm,pull", CAPRI_PINCONF_PARAM_PULL}, >> + {"brcm,slew", CAPRI_PINCONF_PARAM_SLEW}, >> + {"brcm,input_dis", CAPRI_PINCONF_PARAM_INPUT_DIS}, >> + {"brcm,drive_str", CAPRI_PINCONF_PARAM_DRV_STR}, >> + {"brcm,pull_up_str", CAPRI_PINCONF_PARAM_PULL_UP_STR}, >> + {"brcm,mode", CAPRI_PINCONF_PARAM_MODE}, >> +}; > >As well as all this stuff... OK. Will see if I can find something suitable for "input disable" and "mode" >> +/* Standard pin register */ > >Add some more elaborate explanation here. I am half-guessing that >most of the registers are laid out like this and then there are >two exceptions, then write that right here in the comment. > >(BTW: this is a HW/driver detail and should not be written in the >device tree doc as was done in patch 2) Yes you guessed correctly. Most of the pin have bit-field definitions like the "standard" or "std" pin register. There are 12 pins that have the i2c definitions, and 2 pins that have the hdmi definitions. Will add explanation to the code. However, I wanted to explain this in the DT doc as well because, for example, setting a slew rate for an hdmi pin would be invalid. >> +/* Macro to update reg with new pin config param */ >> +#define CAPRI_PIN_REG_SET(reg, type, param, val) \ >> + (((reg) & ~CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK) \ >> + | (((val) << CAPRI_ ## type ## _PIN_REG_ ## param ## _SHIFT) \ >> + & CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK)) > >No thanks. > >Rewrite this into a static inline which has the same effect when >compiling, but produces *WAY* more readable code than this >horrid thing. Plus you can type the arguments. Ok. The reason I used a macro is to take shortcuts given how the SHIFT and MASK #defines follow the format CAPRI_<pin type>_PIN_REG_<parameter name>_<mask or shift> I'll try to simply this. >> +#define _PIN(offset) (offset) > >This macro isn't exactly useful. > >> +/* >> + * Pin number definition. The order here must be the same as defined in the >> + * PADCTRLREG block in the RDB. >> + */ >> +#define CAPRI_PIN_ADCSYNC _PIN(0) > >If it's just going to be like that, then skip the _PIN() macro. Removed. Was following pinctrl-tegra20.c where they have the _GPIO and _PIN macros. I guess it would be useful if we need to change the order of the enums in the future, but that's not the case at the moment for capri. >> +/* Process the pin configuration node */ >> +static int capri_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, >> + struct device_node *pnode, >> + struct pinctrl_map **map, >> + unsigned *nmaps) >> +{ > >Make use of these from pinctrl-utils.c: >pinctrl_utils_reserve_map() >pinctrl_utils_add_map_mux() >pinctrl_utils_add_map_configs() >pinctrl_utils_dt_free_map() > >Then you get rid of another big chunk of boilerplate code. > >After these changes the driver will be much smaller and >cleaner and we can take a closer look. Yea actually the generic code is similar to what I have, there are some differences in terms of pre-allocating / re-allocating the pinctrl_maps. Seems like there are very few users of these functions at the moment. Anyway I'll try to make use of them. Thanks for the review. Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <051069C10411E24D9749790C498526FA1BE027EA-HXj2mutaA2pgyiERVvb/1Jr/X4hKkxxPpWgKQ6/u3Fg@public.gmane.org>]
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver [not found] ` <051069C10411E24D9749790C498526FA1BE027EA-HXj2mutaA2pgyiERVvb/1Jr/X4hKkxxPpWgKQ6/u3Fg@public.gmane.org> @ 2013-10-11 8:14 ` Linus Walleij 2013-10-11 18:25 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-10-11 8:14 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, bcm-kernel-feedback-list, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Fri, Oct 11, 2013 at 1:48 AM, Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote: >>> +static const struct capri_cfg_param capri_pinconf_params[] = { >>> + {"brcm,hysteresis", CAPRI_PINCONF_PARAM_HYST}, >>> + {"brcm,pull", CAPRI_PINCONF_PARAM_PULL}, >>> + {"brcm,slew", CAPRI_PINCONF_PARAM_SLEW}, >>> + {"brcm,input_dis", CAPRI_PINCONF_PARAM_INPUT_DIS}, >>> + {"brcm,drive_str", CAPRI_PINCONF_PARAM_DRV_STR}, >>> + {"brcm,pull_up_str", CAPRI_PINCONF_PARAM_PULL_UP_STR}, >>> + {"brcm,mode", CAPRI_PINCONF_PARAM_MODE}, >>> +}; >> >>As well as all this stuff... > > OK. Will see if I can find something suitable for "input disable" and "mode" Let's discuss this. What exactly does "input disable" and "mode" mean, in electrical terms? When you come down to what actually happens it may turn out that "input disable" is PIN_CONFIG_OUTPUT, which implicitly turns off input does it not? Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 85+ messages in thread
* RE: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-11 8:14 ` Linus Walleij @ 2013-10-11 18:25 ` Sherman Yin 2013-10-22 23:29 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-10-11 18:25 UTC (permalink / raw) To: Linus Walleij Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org >>>> +static const struct capri_cfg_param capri_pinconf_params[] = { >>>> + {"brcm,hysteresis", CAPRI_PINCONF_PARAM_HYST}, >>>> + {"brcm,pull", CAPRI_PINCONF_PARAM_PULL}, >>>> + {"brcm,slew", CAPRI_PINCONF_PARAM_SLEW}, >>>> + {"brcm,input_dis", CAPRI_PINCONF_PARAM_INPUT_DIS}, >>>> + {"brcm,drive_str", CAPRI_PINCONF_PARAM_DRV_STR}, >>>> + {"brcm,pull_up_str", CAPRI_PINCONF_PARAM_PULL_UP_STR}, >>>> + {"brcm,mode", CAPRI_PINCONF_PARAM_MODE}, >>>> +}; >>> >>>As well as all this stuff... >> >> OK. Will see if I can find something suitable for "input disable" and "mode" > >Let's discuss this. What exactly does "input disable" and "mode" >mean, in electrical terms? > >When you come down to what actually happens it may turn out that >"input disable" is PIN_CONFIG_OUTPUT, which implicitly turns >off input does it not? I'm going to verify the details with our hardware team first, and will let you know if we think we can use one of the existing generic parameters or if we need a new one. Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* RE: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-11 18:25 ` Sherman Yin @ 2013-10-22 23:29 ` Sherman Yin 2013-10-25 22:48 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-10-22 23:29 UTC (permalink / raw) To: Sherman Yin, Linus Walleij Cc: Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, Stephen Warren, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org >>>>> +static const struct capri_cfg_param capri_pinconf_params[] = { >>>>> + {"brcm,hysteresis", CAPRI_PINCONF_PARAM_HYST}, >>>>> + {"brcm,pull", CAPRI_PINCONF_PARAM_PULL}, >>>>> + {"brcm,slew", CAPRI_PINCONF_PARAM_SLEW}, >>>>> + {"brcm,input_dis", CAPRI_PINCONF_PARAM_INPUT_DIS}, >>>>> + {"brcm,drive_str", CAPRI_PINCONF_PARAM_DRV_STR}, >>>>> + {"brcm,pull_up_str", CAPRI_PINCONF_PARAM_PULL_UP_STR}, >>>>> + {"brcm,mode", CAPRI_PINCONF_PARAM_MODE}, >>>>> +}; >>>> >>>>As well as all this stuff... >>> >>> OK. Will see if I can find something suitable for "input disable" and "mode" >> >>Let's discuss this. What exactly does "input disable" and "mode" >>mean, in electrical terms? >> >>When you come down to what actually happens it may turn out that >>"input disable" is PIN_CONFIG_OUTPUT, which implicitly turns >>off input does it not? > >I'm going to verify the details with our hardware team first, and will let you >know if we think we can use one of the existing generic parameters or if we >need a new one. "input disable" This setting disconnects the input (DIN) to the internal logic from the pin pad. However, the output (DOUT) can still drive the pad. It seems to match PIN_CONFIG_OUTPUT, but the current generic option is either "output-low" or "output-high" - are these referring to a static output of 0 and 1? "mode" This controls several aspect of the pin (slew rate, pull up strength, etc) to meet I2C specs for Standard/Fast mode vs High Speed mode. I think the best way is to map this to slew rate, which would require some explanation because the meaning of slew rate differs depending on what pin function is selected: - When I2C (*_SCL or *_SDA) function is selected for the pin: 0: Standard (100kbps) & Fast mode (400kbps), 1: High Speed mode (3.4Mbps) - When IC_DM or IC_DP function is selected, 0: normal slew rate, 1: fast slew rate - Else: 0: fast slew rate, 1: normal slew rate Also, it seems like I have to add "slew-rate" to dt_params[] in pinconf-generic.c and pinctrl-bindings.txt. ^ permalink raw reply [flat|nested] 85+ messages in thread
* RE: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-22 23:29 ` Sherman Yin @ 2013-10-25 22:48 ` Sherman Yin 2013-11-04 12:24 ` Linus Walleij 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-10-25 22:48 UTC (permalink / raw) To: Linus Walleij Cc: Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, Stephen Warren, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org >>>>>As well as all this stuff... >>>> >>>> OK. Will see if I can find something suitable for "input disable" and "mode" >>> >>>Let's discuss this. What exactly does "input disable" and "mode" >>>mean, in electrical terms? >>> >>>When you come down to what actually happens it may turn out that >>>"input disable" is PIN_CONFIG_OUTPUT, which implicitly turns >>>off input does it not? >> >>I'm going to verify the details with our hardware team first, and will let you >>know if we think we can use one of the existing generic parameters or if we >>need a new one. > >"input disable" >This setting disconnects the input (DIN) to the internal logic from the pin pad. >However, the output (DOUT) can still drive the pad. It seems to match >PIN_CONFIG_OUTPUT, but the current generic option is either "output-low" or >"output-high" - are these referring to a static output of 0 and 1? > >"mode" >This controls several aspect of the pin (slew rate, pull up strength, etc) to meet >I2C specs for Standard/Fast mode vs High Speed mode. I think the best >way is to map this to slew rate, which would require some explanation because >the meaning of slew rate differs depending on what pin function is selected: >- When I2C (*_SCL or *_SDA) function is selected for the pin: 0: Standard (100kbps) > & Fast mode (400kbps), 1: High Speed mode (3.4Mbps) >- When IC_DM or IC_DP function is selected, 0: normal slew rate, 1: fast slew rate >- Else: 0: fast slew rate, 1: normal slew rate > >Also, it seems like I have to add "slew-rate" to dt_params[] in pinconf-generic.c and >pinctrl-bindings.txt. Hi Linus, So I will go ahead and make the change in pinconf-generic.c and pinctrl-bindings.txt to include parsing of the "slew-rate" property and submit it as part of my pinctrl changes. Question regarding pinctrl-generic: in pinctrl-bindings.txt, this is said about the "function" property: 169- function takes a list of function names/IDs as a required argument. The 170 specific binding for the hardware defines: 171 - Whether the entries are integers or strings, and their meaning. 172 - Whether only a single entry is allowed (which is applied to all entries 173 in the pins property), or whether there may alternatively be one entry per 174 entry in the pins property, in which case the list lengths must match, and 175 for each list index i, the function at list index i is applied to the pin 176 at list index i. (Although it looks like pinconf_generic_dt_subnode_to_map() does not support the "one entry per pin feature" for the "function" property yet.) In my driver, I have the "one entry per pin" support for all my properties instead of just the function property, like the "drive_str" property below: + grp_1 { + brcm,pins = "pin1", "pin2", "pin3"; + brcm,function = "alt1", "alt2", "alt1"; + brcm,drive_str = <2 4 6>; + brcm,slew = <1>; + }; I thought that would be convenient and allow users to group pins together based on functionality and without the restriction that the pins must have the same properties. Do you think that's a good idea and are there plans to support that in the generic pinconfig? If so, I can look into porting my implementation to pinconf-generic.c - but first I have to figure out how some of the properties would work if more than one value could be specified (eg. "bias-disable" which takes no values) Thanks, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-25 22:48 ` Sherman Yin @ 2013-11-04 12:24 ` Linus Walleij 2013-11-04 23:26 ` Heiko Stübner 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-11-04 12:24 UTC (permalink / raw) To: Sherman Yin, Heiko Stübner, Laxman Dewangan Cc: Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, Stephen Warren, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On Sat, Oct 26, 2013 at 12:48 AM, Sherman Yin <syin@broadcom.com> wrote: > So I will go ahead and make the change in pinconf-generic.c and pinctrl-bindings.txt > to include parsing of the "slew-rate" property and submit it as part of my pinctrl > changes. OK, good. > Question regarding pinctrl-generic: in pinctrl-bindings.txt, this is said about the > "function" property: > > 169- function takes a list of function names/IDs as a required argument. The > 170 specific binding for the hardware defines: > 171 - Whether the entries are integers or strings, and their meaning. > 172 - Whether only a single entry is allowed (which is applied to all entries > 173 in the pins property), or whether there may alternatively be one entry per > 174 entry in the pins property, in which case the list lengths must match, and > 175 for each list index i, the function at list index i is applied to the pin > 176 at list index i. > > (Although it looks like pinconf_generic_dt_subnode_to_map() does not support > the "one entry per pin feature" for the "function" property yet.) > > In my driver, I have the "one entry per pin" support for all my properties instead > of just the function property, like the "drive_str" property below: > > + grp_1 { > + brcm,pins = "pin1", "pin2", "pin3"; > + brcm,function = "alt1", "alt2", "alt1"; > + brcm,drive_str = <2 4 6>; > + brcm,slew = <1>; > + }; OK. > I thought that would be convenient and allow users to group pins together based > on functionality and without the restriction that the pins must have the same > properties. Do you think that's a good idea and are there plans to support that in > the generic pinconfig? If so, I can look into porting my implementation to > pinconf-generic.c - but first I have to figure out how some of the properties would > work if more than one value could be specified (eg. "bias-disable" which takes no > values) Hm I don't quite get it I think. It depends on the old bindings still working and full compatibility with old device trees. It might be a bit confusing. I need help from Heiko on this I think. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-11-04 12:24 ` Linus Walleij @ 2013-11-04 23:26 ` Heiko Stübner 2013-11-05 0:04 ` Stephen Warren 0 siblings, 1 reply; 85+ messages in thread From: Heiko Stübner @ 2013-11-04 23:26 UTC (permalink / raw) To: Linus Walleij Cc: Sherman Yin, Laxman Dewangan, Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, Stephen Warren, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org Am Montag, 4. November 2013, 13:24:10 schrieb Linus Walleij: > > In my driver, I have the "one entry per pin" support for all my > > properties instead of just the function property, like the "drive_str" > > property below: > > > > + grp_1 { > > + brcm,pins = "pin1", "pin2", "pin3"; > > + brcm,function = "alt1", "alt2", "alt1"; > > + brcm,drive_str = <2 4 6>; > > + brcm,slew = <1>; > > + }; > > On Sat, Oct 26, 2013 at 12:48 AM, Sherman Yin <syin@broadcom.com> wrote: > > I thought that would be convenient and allow users to group pins together > > based on functionality and without the restriction that the pins must > > have the same properties. > > Do you think that's a good idea and are there > > plans to support that in the generic pinconfig? If so, I can look into > > porting my implementation to pinconf-generic.c - but first I have to > > figure out how some of the properties would work if more than one value > > could be specified (eg. "bias-disable" which takes no values) > > Hm I don't quite get it I think. It depends on the old bindings still > working and full compatibility with old device trees. It might be a bit > confusing. > > I need help from Heiko on this I think. I remember we had a discussion about how things like bias-disable explicitly shouldn't have a value, when they are represented in the list-format: pcfg_pull_none: pcfg_pull_none { bias-disable; }; so a bias-disable = <1> was explicitly "forbidden" [for a lack of a better word]. And it was similar for other options, the parameter not meant to be indicating if they are active but really only setting the "strength" or so. But how to represent this in the list variant above, I don't know. Having a brcm,bias-disable = <0>, <1>, ... thus looks wrong and also does not seem to scale well to all the possible options (bias-* and the others). Having a brcm,bias = <x>, <y>, <z>, ... with constants denoting pull-up, - down, disable, etc might be possible, but I'm missing the electrical engineering knowledge on the possibility of those bias-things being combined. For example on my rockchip-pinctrl driver, the pins also do not need to have the same configuration to be grouped together - inspired at the time by the format the at91 driver uses. Here each pin forms a tuple instead of being identified by an index. In it the basic function is set directly and then references a predefined list of pinctrl options. pcfg_pull_none: pcfg_pull_none { bias-disable; }; uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>, <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; }; ... }; A switch to something like to following would also be a possibility: pcfg1: pcfg1 { bias-disable; slew-rate = <1>; }; pcfg2: pcfg2 { drive-strength = <2>; }; grp_1 { brcm,pins = "pin1", "pin2", "pin3"; brcm,function = "alt1", "alt2", "alt1"; brcm,pinconf = <&pcfg1>, <&pcfg2> }; So far my unsorted thoughts [and recoverable memory] on this :-) Heiko ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-11-04 23:26 ` Heiko Stübner @ 2013-11-05 0:04 ` Stephen Warren 2013-11-06 2:02 ` Sherman Yin 2013-11-06 9:29 ` Linus Walleij 0 siblings, 2 replies; 85+ messages in thread From: Stephen Warren @ 2013-11-05 0:04 UTC (permalink / raw) To: Heiko Stübner, Linus Walleij Cc: Sherman Yin, Laxman Dewangan, Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On 11/04/2013 04:26 PM, Heiko Stübner wrote: > I remember we had a discussion about how things like bias-disable explicitly > shouldn't have a value, when they are represented in the list-format: > > pcfg_pull_none: pcfg_pull_none { > bias-disable; > }; > > so a bias-disable = <1> was explicitly "forbidden" [for a lack of a better > word]. And it was similar for other options, the parameter not meant to be > indicating if they are active but really only setting the "strength" or so. Pure Boolean values should be represented as a valueless property. If the property is present, the value is true, otherwise false. However, pinctrl bindings often don't represent Boolean values, but rather tri-states, with the following values: * Don't touch this configuration option at all (missing) * Enable the option (<1>) * Disable the option (<0>) The reason for using tri-states being that you might want to write: xxx1 { pins = <PINA>, <PINB>, <PINC>; function = <...>; // this node doesn't affect pullup } xxx2 { pins = <PINA>, <PINB>; // this node doesn't affect function pull-up = <1>; // change, and enable } xxx3 { pins = <PINAC>; // this node doesn't affect function pull-up = <0>; // change, and disable } ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-11-05 0:04 ` Stephen Warren @ 2013-11-06 2:02 ` Sherman Yin 2013-11-06 9:40 ` Linus Walleij [not found] ` <5279A319.5060701-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> 2013-11-06 9:29 ` Linus Walleij 1 sibling, 2 replies; 85+ messages in thread From: Sherman Yin @ 2013-11-06 2:02 UTC (permalink / raw) To: Stephen Warren, Heiko Stübner, Linus Walleij Cc: Laxman Dewangan, Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On 13-11-04 04:04 PM, Stephen Warren wrote: > On 11/04/2013 04:26 PM, Heiko Stübner wrote: > >> I remember we had a discussion about how things like bias-disable explicitly >> shouldn't have a value, when they are represented in the list-format: >> >> pcfg_pull_none: pcfg_pull_none { >> bias-disable; >> }; >> >> so a bias-disable = <1> was explicitly "forbidden" [for a lack of a better >> word]. And it was similar for other options, the parameter not meant to be >> indicating if they are active but really only setting the "strength" or so. > > Pure Boolean values should be represented as a valueless property. If > the property is present, the value is true, otherwise false. > > However, pinctrl bindings often don't represent Boolean values, but > rather tri-states, with the following values: > > * Don't touch this configuration option at all (missing) > * Enable the option (<1>) > * Disable the option (<0>) > > The reason for using tri-states being that you might want to write: > > xxx1 { > pins = <PINA>, <PINB>, <PINC>; > function = <...>; > // this node doesn't affect pullup > } > xxx2 { > pins = <PINA>, <PINB>; > // this node doesn't affect function > pull-up = <1>; // change, and enable > } > xxx3 { > pins = <PINAC>; > // this node doesn't affect function > pull-up = <0>; // change, and disable > } If I understand correctly, in Stephen's example, if a certain driver wants to configure PINA PINB and PINC, the pin configuration nodes "xxx1", "xxx2", and "xxx3" will all have to be selected for the particular pin state. This works fine. However, I'm just thinking that it would have been easier if we could specify just one node: xxx { pins = <PINA>, <PINB>, <PINC>; function = <...>; pull-up = <1 1 0>; } This "feature" seems a bit more concise to me and is what I did for my original pinctrl driver. The only downside is that with this method, one cannot specify "don't touch this option for this pin" if the same property must provide values for other pins. When Linus asked me to try using generic pinconf instead, I ran into problems with this feature due to how the generic pinconf properties are defined differently than my properties - perhaps this feature just doesn't work for generic pinconf-based drivers with the (Unless we are ok with using 1/0 for boolean properties, but it has already been pointed out that these should be valueless.). While I'd love to be able define my pin config nodes this way, if I have to use generic pinconf for the driver to be upstreamed, then I'm fine with it. Going back to some questions regarding generic pinconf properties - could I get some help with these? >"input disable" >This setting disconnects the input (DIN) to the internal logic from >the pin pad. However, the output (DOUT) can still drive the pad. It >seems to match PIN_CONFIG_OUTPUT, but the current generic option is >either "output-low" or "output-high" - are these referring to a static >output of 0 and 1? What's the best property to use in this case? >"mode" >This controls several aspect of the pin (slew rate, pull up strength, >etc) to meet I2C specs for Standard/Fast mode vs High Speed mode. I >think the best way is to map this to slew rate, which would require >some explanation because the meaning of slew rate differs depending on >what pin function is selected: >- When I2C (*_SCL or *_SDA) function is selected for the pin: 0: > Standard (100kbps) > & Fast mode (400kbps), 1: High Speed mode (3.4Mbps) >- When IC_DM or IC_DP function is selected, 0: normal slew rate, 1: > fast slew rate >- Else: 0: fast slew rate, 1: normal slew rate Do we agree that the "slew rate" is the best property to use for "mode"? Thanks, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-11-06 2:02 ` Sherman Yin @ 2013-11-06 9:40 ` Linus Walleij 2013-11-08 0:29 ` Sherman Yin [not found] ` <5279A319.5060701-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> 1 sibling, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-11-06 9:40 UTC (permalink / raw) To: Sherman Yin Cc: Stephen Warren, Heiko Stübner, Laxman Dewangan, Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On Wed, Nov 6, 2013 at 3:02 AM, Sherman Yin <syin@broadcom.com> wrote: > If I understand correctly, in Stephen's example, if a certain driver wants > to configure PINA PINB and PINC, the pin configuration nodes "xxx1", "xxx2", > and "xxx3" will all have to be selected for the particular pin state. This > works fine. However, I'm just thinking that it would have been easier if we > could specify just one node: > > xxx { > > pins = <PINA>, <PINB>, <PINC>; > function = <...>; > pull-up = <1 1 0>; > } The property is named bias-pull-up, not just pull-up, but whatever. > When Linus asked me to try using generic pinconf instead, I ran into > problems with this feature due to how the generic pinconf properties are > defined differently than my properties - perhaps this feature just doesn't > work for generic pinconf-based drivers with the (Unless we are ok with using > 1/0 for boolean properties, but it has already been pointed out that these > should be valueless.). Well it seems you would need a way to pass an array of the same boolean property and that seems a bit more complex and hard to read than the generic boolean bindings. You would have to patch the OF core to do something like that: bias-pull-up = <true true false>; 1/0 isn't so good I think, what should the parser do with e.g. 2? This is more to the point. > While I'd love to be able define my pin config nodes this way, if I have to > use generic pinconf for the driver to be upstreamed, then I'm fine with it. Well you need to use generic pin config because all the custom stuff - i.MX comes to mind - is creating a mess. I prefer that we share bindings and code, as any programmer would... That said, if you can patch the OF core and the generic pin config parser to do what you want with lists like that, it's your pick. It may take some time though. > Going back to some questions regarding generic pinconf properties - could I > get some help with these? Sure... >>"input disable" >>This setting disconnects the input (DIN) to the internal logic from >the >> pin pad. However, the output (DOUT) can still drive the pad. It >>seems to match PIN_CONFIG_OUTPUT, but the current generic option is >>either "output-low" or "output-high" - are these referring to a static >>output of 0 and 1? > > What's the best property to use in this case? Seems like a new case. What about you patch include/linux/pinctrl/pinconf-generic.h to add PIN_CONFIG_INPUT_DISABLE with this semantic and also patch the generic pinconf parser in drivers/pinctrl/pinconf-generic.c to handle this? >>"mode" >>This controls several aspect of the pin (slew rate, pull up strength, >>etc) to meet I2C specs for Standard/Fast mode vs High Speed mode. I >>think the best way is to map this to slew rate, which would require >>some explanation because the meaning of slew rate differs depending on >>what pin function is selected: >>- When I2C (*_SCL or *_SDA) function is selected for the pin: 0: >> Standard (100kbps) >> & Fast mode (400kbps), 1: High Speed mode (3.4Mbps) >>- When IC_DM or IC_DP function is selected, 0: normal slew rate, 1: >> fast slew rate >>- Else: 0: fast slew rate, 1: normal slew rate > > Do we agree that the "slew rate" is the best property to use for "mode"? It seems to be indeed mostly related to slew rate. However if you want a custom brcm,mode binding that should be possible too, as well as augmenting the driver to use *both* generic pinconf *and* some custom config options on top. That has not been done so far though I think, so you might need a bit of hacking to do that. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-11-06 9:40 ` Linus Walleij @ 2013-11-08 0:29 ` Sherman Yin 2013-11-11 10:01 ` Linus Walleij 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-11-08 0:29 UTC (permalink / raw) To: Linus Walleij Cc: Stephen Warren, Heiko Stübner, Laxman Dewangan, Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On 13-11-06 01:40 AM, Linus Walleij wrote: > On Wed, Nov 6, 2013 at 3:02 AM, Sherman Yin <syin@broadcom.com> wrote: >> When Linus asked me to try using generic pinconf instead, I ran into >> problems with this feature due to how the generic pinconf properties are >> defined differently than my properties - perhaps this feature just doesn't >> work for generic pinconf-based drivers with the (Unless we are ok with using >> 1/0 for boolean properties, but it has already been pointed out that these >> should be valueless.). > > Well it seems you would need a way to pass an array of the same > boolean property and that seems a bit more complex and hard to > read than the generic boolean bindings. > > You would have to patch the OF core to do something like that: > > bias-pull-up = <true true false>; > > 1/0 isn't so good I think, what should the parser do with e.g. 2? > This is more to the point. I would imagine that the platform-specific device tree bindings would need to clearly explain what the valid values are, as they should. If we're using integers, we could either have a) !0 and 0, or b) just 1 and 0, and everything else is an error. Or c) the platform could decide that the value provides addition info like pull-up-strength, so 0 = no pull up, >0 = pull up enabled and the number is the pull up strength in Ohm (bindings should indicate which values are valid), and everything else is an error. >> While I'd love to be able define my pin config nodes this way, if I have to >> use generic pinconf for the driver to be upstreamed, then I'm fine with it. > > Well you need to use generic pin config because all the custom > stuff - i.MX comes to mind - is creating a mess. I prefer that we > share bindings and code, as any programmer would... Ok > That said, if you can patch the OF core and the generic pin config > parser to do what you want with lists like that, it's your pick. > It may take some time though. I don't mind patching the generic pin config, and I don't think the core needs to change, but first there needs to be an agreement on the changes since other drivers will need to use pinconf-generic. Am I the only one who would like to see this feature, or do others see value in being able to group more pins together - resulting in fewer sub-nodes? Do the pros out-weight the cons? >>> "input disable" >>> This setting disconnects the input (DIN) to the internal logic from >the >>> pin pad. However, the output (DOUT) can still drive the pad. It >>> seems to match PIN_CONFIG_OUTPUT, but the current generic option is >>> either "output-low" or "output-high" - are these referring to a static >>> output of 0 and 1? >> >> What's the best property to use in this case? > > Seems like a new case. > > What about you patch include/linux/pinctrl/pinconf-generic.h > to add PIN_CONFIG_INPUT_DISABLE with this semantic > and also patch the generic pinconf parser in drivers/pinctrl/pinconf-generic.c > to handle this? Sure, I can add PIN_CONFIG_INPUT_DISABLE. However I suspect people might be confused by this and PIN_CONFIG_OUTPUT. >>> "mode" >>> This controls several aspect of the pin (slew rate, pull up strength, >>> etc) to meet I2C specs for Standard/Fast mode vs High Speed mode. I >>> think the best way is to map this to slew rate, which would require >>> some explanation because the meaning of slew rate differs depending on >>> what pin function is selected: >>> - When I2C (*_SCL or *_SDA) function is selected for the pin: 0: >>> Standard (100kbps) >>> & Fast mode (400kbps), 1: High Speed mode (3.4Mbps) >>> - When IC_DM or IC_DP function is selected, 0: normal slew rate, 1: >>> fast slew rate >>> - Else: 0: fast slew rate, 1: normal slew rate >> >> Do we agree that the "slew rate" is the best property to use for "mode"? > > It seems to be indeed mostly related to slew rate. > > However if you want a custom brcm,mode binding that should > be possible too, as well as augmenting the driver to use > *both* generic pinconf *and* some custom config options > on top. That has not been done so far though I think, so you > might need a bit of hacking to do that. I think I'll stick with slew rate. :) Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-11-08 0:29 ` Sherman Yin @ 2013-11-11 10:01 ` Linus Walleij [not found] ` <CACRpkdaf9dVqpE5uFQ5L64n+wXO0AYr5-e1WvYc4rWjVTsTg1w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-11-11 10:01 UTC (permalink / raw) To: Sherman Yin Cc: Stephen Warren, Heiko Stübner, Laxman Dewangan, Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On Fri, Nov 8, 2013 at 1:29 AM, Sherman Yin <syin@broadcom.com> wrote: > [Me] >> On Wed, Nov 6, 2013 at 3:02 AM, Sherman Yin <syin@broadcom.com> wrote: >> You would have to patch the OF core to do something like that: >> >> bias-pull-up = <true true false>; >> >> 1/0 isn't so good I think, what should the parser do with e.g. 2? >> This is more to the point. > > I would imagine that the platform-specific device tree bindings would need > to clearly explain what the valid values are, as they should. But this is not a platform-specific binding. These are the generic pin configuration bindings we're talking about. > If we're > using integers, we could either have a) !0 and 0, or b) just 1 and 0, and > everything else is an error. Or c) the platform could decide that the value > provides addition info like pull-up-strength, so 0 = no pull up, >0 = pull > up enabled and the number is the pull up strength in Ohm (bindings should > indicate which values are valid), and everything else is an error. That seems to make sense, I've just not seen any system (using device tree) that can actually set the pull up/down resistance. >> That said, if you can patch the OF core and the generic pin config >> parser to do what you want with lists like that, it's your pick. >> It may take some time though. > > I don't mind patching the generic pin config, and I don't think the core > needs to change, If you want arrays of booleans that is a matter for the OF core parser I think. >> What about you patch include/linux/pinctrl/pinconf-generic.h >> to add PIN_CONFIG_INPUT_DISABLE with this semantic >> and also patch the generic pinconf parser in >> drivers/pinctrl/pinconf-generic.c >> to handle this? > > Sure, I can add PIN_CONFIG_INPUT_DISABLE. However I suspect people might be > confused by this and PIN_CONFIG_OUTPUT. Just make sure you put in good documentation in that file right there, it's using kerneldoc and for a good reason... Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <CACRpkdaf9dVqpE5uFQ5L64n+wXO0AYr5-e1WvYc4rWjVTsTg1w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver [not found] ` <CACRpkdaf9dVqpE5uFQ5L64n+wXO0AYr5-e1WvYc4rWjVTsTg1w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2013-11-13 23:43 ` Sherman Yin 2013-11-19 20:39 ` Linus Walleij 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-11-13 23:43 UTC (permalink / raw) To: Linus Walleij Cc: Stephen Warren, Heiko Stübner, Laxman Dewangan, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On 13-11-11 02:01 AM, Linus Walleij wrote: >> I would imagine that the platform-specific device tree bindings would need >> to clearly explain what the valid values are, as they should. > > But this is not a platform-specific binding. These are the > generic pin configuration bindings we're talking about. Yes, the properties are generic, but I was under the impression that the values can be "custom", such as these: * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in * schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis, * the threshold value is given on a custom format as argument when * setting pins to this mode. and * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to * this parameter (on a custom format) tells the driver which alternative * slew rate to use. > >> If we're >> using integers, we could either have a) !0 and 0, or b) just 1 and 0, and >> everything else is an error. Or c) the platform could decide that the value >> provides addition info like pull-up-strength, so 0 = no pull up, >0 = pull >> up enabled and the number is the pull up strength in Ohm (bindings should >> indicate which values are valid), and everything else is an error. > > That seems to make sense, I've just not seen any system (using > device tree) that can actually set the pull up/down resistance. > >>> That said, if you can patch the OF core and the generic pin config >>> parser to do what you want with lists like that, it's your pick. >>> It may take some time though. >> >> I don't mind patching the generic pin config, and I don't think the core >> needs to change, > > If you want arrays of booleans that is a matter for the OF core > parser I think. I was thinking of just using integers and accepting only 1 and 0, everything else is error. >>> What about you patch include/linux/pinctrl/pinconf-generic.h >>> to add PIN_CONFIG_INPUT_DISABLE with this semantic >>> and also patch the generic pinconf parser in >>> drivers/pinctrl/pinconf-generic.c >>> to handle this? >> >> Sure, I can add PIN_CONFIG_INPUT_DISABLE. However I suspect people might be >> confused by this and PIN_CONFIG_OUTPUT. > > Just make sure you put in good documentation in that file > right there, it's using kerneldoc and for a good reason... Thanks, Sherman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-11-13 23:43 ` Sherman Yin @ 2013-11-19 20:39 ` Linus Walleij 0 siblings, 0 replies; 85+ messages in thread From: Linus Walleij @ 2013-11-19 20:39 UTC (permalink / raw) To: Sherman Yin Cc: Stephen Warren, Heiko Stübner, Laxman Dewangan, Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On Thu, Nov 14, 2013 at 12:43 AM, Sherman Yin <syin@broadcom.com> wrote: > On 13-11-11 02:01 AM, Linus Walleij wrote: >>> >>> I would imagine that the platform-specific device tree bindings would >>> need >>> to clearly explain what the valid values are, as they should. >> >> But this is not a platform-specific binding. These are the >> generic pin configuration bindings we're talking about. > > Yes, the properties are generic, but I was under the impression that the > values can be "custom", such as these: Well if it makes sense, we should try to make them non-custom. And drivers should still try to be similar, if possible. >> If you want arrays of booleans that is a matter for the OF core >> parser I think. > > I was thinking of just using integers and accepting only 1 and 0, everything > else is error. Hm OK maybe. You need to talk to the OF people about that. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <5279A319.5060701-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver [not found] ` <5279A319.5060701-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2013-11-06 17:00 ` Stephen Warren 2013-11-07 22:01 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Stephen Warren @ 2013-11-06 17:00 UTC (permalink / raw) To: Sherman Yin, Heiko Stübner, Linus Walleij Cc: Laxman Dewangan, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On 11/05/2013 07:02 PM, Sherman Yin wrote: > On 13-11-04 04:04 PM, Stephen Warren wrote: >> On 11/04/2013 04:26 PM, Heiko Stübner wrote: >> >>> I remember we had a discussion about how things like bias-disable >>> explicitly >>> shouldn't have a value, when they are represented in the list-format: >>> >>> pcfg_pull_none: pcfg_pull_none { >>> bias-disable; >>> }; >>> >>> so a bias-disable = <1> was explicitly "forbidden" [for a lack of a >>> better >>> word]. And it was similar for other options, the parameter not meant >>> to be >>> indicating if they are active but really only setting the "strength" >>> or so. >> >> Pure Boolean values should be represented as a valueless property. If >> the property is present, the value is true, otherwise false. >> >> However, pinctrl bindings often don't represent Boolean values, but >> rather tri-states, with the following values: >> >> * Don't touch this configuration option at all (missing) >> * Enable the option (<1>) >> * Disable the option (<0>) >> >> The reason for using tri-states being that you might want to write: >> >> xxx1 { >> pins = <PINA>, <PINB>, <PINC>; >> function = <...>; >> // this node doesn't affect pullup >> } >> xxx2 { >> pins = <PINA>, <PINB>; >> // this node doesn't affect function >> pull-up = <1>; // change, and enable >> } >> xxx3 { >> pins = <PINAC>; >> // this node doesn't affect function >> pull-up = <0>; // change, and disable >> } > > If I understand correctly, in Stephen's example, if a certain driver > wants to configure PINA PINB and PINC, the pin configuration nodes > "xxx1", "xxx2", and "xxx3" will all have to be selected for the > particular pin state. You probably don't want to reference the individual xxx1/2/3 nodes in the client pinctrl properties, but instead wrap them in a higher-level node that represents the whole pinctrl state. Then, the client pinctrl properties can reference just that single parent node, instead of many small nodes. In other words: pinctrl@... { ... sx: state_xxx { xxx1 { ... }; xxx2 { ... }; xxx3 { ... }; }; sy: state_yyy { yyy1 { ... }; yyy2 { ... }; }; } some_client@... { ... pinctrl-names = "default"; pinctrl-0 = <&sx>; }; other_client@... { ... pinctrl-names = "default"; pinctrl-0 = <&sy>; }; rather than: pinctrl@... { ... sx1: xxx1 { ... }; sx2: xxx2 { ... }; sx3: xxx3 { ... }; sy1: yyy1 { ... }; sy2: yyy2 { ... }; } some_client@... { ... pinctrl-names = "default"; pinctrl-0 = <&sx1 &sx2 &sx3>; }; other_client@... { ... pinctrl-names = "default"; pinctrl-0 = <&sy1 &sy2>; }; This is exactly how the Tegra pinctrl bindings work for example. > This works fine. However, I'm just thinking that > it would have been easier if we could specify just one node: > > xxx { > pins = <PINA>, <PINB>, <PINC>; > function = <...>; > pull-up = <1 1 0>; > } > > This "feature" seems a bit more concise to me and is what I did for my > original pinctrl driver. The only downside is that with this method, > one cannot specify "don't touch this option for this pin" if the same > property must provide values for other pins. The other downside is that if the lists get even slightly long, it get really hard to match up the entries in the t properties. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-11-06 17:00 ` Stephen Warren @ 2013-11-07 22:01 ` Sherman Yin 0 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-11-07 22:01 UTC (permalink / raw) To: Stephen Warren, Heiko Stübner, Linus Walleij Cc: Laxman Dewangan, Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On 13-11-06 09:00 AM, Stephen Warren wrote: > You probably don't want to reference the individual xxx1/2/3 nodes in > the client pinctrl properties, but instead wrap them in a higher-level > node that represents the whole pinctrl state. Then, the client pinctrl > properties can reference just that single parent node, instead of many > small nodes. In other words: > > pinctrl@... { > ... > sx: state_xxx { > xxx1 { ... }; > xxx2 { ... }; > xxx3 { ... }; > }; > sy: state_yyy { > yyy1 { ... }; > yyy2 { ... }; > }; > } > > some_client@... { > ... > pinctrl-names = "default"; > pinctrl-0 = <&sx>; > }; > > other_client@... { > ... > pinctrl-names = "default"; > pinctrl-0 = <&sy>; > }; > > rather than: > > pinctrl@... { > ... > sx1: xxx1 { ... }; > sx2: xxx2 { ... }; > sx3: xxx3 { ... }; > sy1: yyy1 { ... }; > sy2: yyy2 { ... }; > } > > some_client@... { > ... > pinctrl-names = "default"; > pinctrl-0 = <&sx1 &sx2 &sx3>; > }; > > other_client@... { > ... > pinctrl-names = "default"; > pinctrl-0 = <&sy1 &sy2>; > }; > > This is exactly how the Tegra pinctrl bindings work for example. Ok, right, I mistakenly thought the "xxx1" nodes are pin config nodes. Actually that's the way my original driver works as well, other than the fact that I don't have as many "xxx1" type nodes as decribed in the "xxx" node below. >> This works fine. However, I'm just thinking that >> it would have been easier if we could specify just one node: >> >> xxx { >> pins = <PINA>, <PINB>, <PINC>; >> function = <...>; >> pull-up = <1 1 0>; >> } >> >> This "feature" seems a bit more concise to me and is what I did for my >> original pinctrl driver. The only downside is that with this method, >> one cannot specify "don't touch this option for this pin" if the same >> property must provide values for other pins. > > The other downside is that if the lists get even slightly long, it get > really hard to match up the entries in the t properties. Agree that it would start to get difficult to read if a subnode has too many pins. I guess the solution would be to somehow split up the pins to more subnodes with fewer pins each. Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-11-05 0:04 ` Stephen Warren 2013-11-06 2:02 ` Sherman Yin @ 2013-11-06 9:29 ` Linus Walleij 1 sibling, 0 replies; 85+ messages in thread From: Linus Walleij @ 2013-11-06 9:29 UTC (permalink / raw) To: Stephen Warren Cc: Heiko Stübner, Sherman Yin, Laxman Dewangan, Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Pawel Moll, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On Tue, Nov 5, 2013 at 1:04 AM, Stephen Warren <swarren@wwwdotorg.org> wrote: > On 11/04/2013 04:26 PM, Heiko Stübner wrote: > Pure Boolean values should be represented as a valueless property. If > the property is present, the value is true, otherwise false. > > However, pinctrl bindings often don't represent Boolean values, but > rather tri-states, with the following values: > > * Don't touch this configuration option at all (missing) > * Enable the option (<1>) > * Disable the option (<0>) But in this case we actually have these booleans to specify exactly what we want to do: bias-disable - disable any pin bias bias-high-impedance - high impedance mode ("third-state", "floating") bias-bus-hold - latch weakly bias-pull-up - pull up the pin bias-pull-down - pull down the pin bias-pull-pin-default - use pin-default pull state Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-04 0:23 ` [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin 2013-10-09 9:10 ` Linus Walleij @ 2013-10-17 6:03 ` Christian Daudt 2013-10-17 14:54 ` Stephen Warren 1 sibling, 1 reply; 85+ messages in thread From: Christian Daudt @ 2013-10-17 6:03 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Russell King, Linus Walleij, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Thu, Oct 3, 2013 at 5:23 PM, Sherman Yin <syin@broadcom.com> wrote: > Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > Reviewed-by: Christian Daudt <bcm@fixthebug.org> > Reviewed-by: Matt Porter <matt.porter@linaro.org> > --- > arch/arm/mach-bcm/Kconfig | 2 + > drivers/pinctrl/Kconfig | 10 + > drivers/pinctrl/Makefile | 1 + > drivers/pinctrl/pinctrl-capri.c | 1727 +++++++++++++++++++++++++++++++++++++++ > 4 files changed, 1740 insertions(+) > create mode 100644 drivers/pinctrl/pinctrl-capri.c > > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig > index 69d67f7..2546365 100644 > --- a/arch/arm/mach-bcm/Kconfig > +++ b/arch/arm/mach-bcm/Kconfig > @@ -10,6 +10,8 @@ config ARCH_BCM > select GENERIC_CLOCKEVENTS > select GENERIC_TIME > select GPIO_BCM > + select PINCTRL > + select PINCTRL_CAPRI > select SPARSE_IRQ > select TICK_ONESHOT > select CACHE_L2X0 On your subsequent patchset pls move this from Kconfig to arm/configs/bcm_defconfig, and break that modification into a separate patch from the drivers/* modification. thanks, csd ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-17 6:03 ` Christian Daudt @ 2013-10-17 14:54 ` Stephen Warren 2013-10-17 15:31 ` Christian Daudt 0 siblings, 1 reply; 85+ messages in thread From: Stephen Warren @ 2013-10-17 14:54 UTC (permalink / raw) To: Christian Daudt, Sherman Yin Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Rob Landley, Russell King, Linus Walleij, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On 10/17/2013 12:03 AM, Christian Daudt wrote: > On Thu, Oct 3, 2013 at 5:23 PM, Sherman Yin <syin@broadcom.com> wrote: >> Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. >> >> Signed-off-by: Sherman Yin <syin@broadcom.com> >> Reviewed-by: Christian Daudt <bcm@fixthebug.org> >> Reviewed-by: Matt Porter <matt.porter@linaro.org> >> --- >> arch/arm/mach-bcm/Kconfig | 2 + >> drivers/pinctrl/Kconfig | 10 + >> drivers/pinctrl/Makefile | 1 + >> drivers/pinctrl/pinctrl-capri.c | 1727 +++++++++++++++++++++++++++++++++++++++ >> 4 files changed, 1740 insertions(+) >> create mode 100644 drivers/pinctrl/pinctrl-capri.c >> >> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig >> index 69d67f7..2546365 100644 >> --- a/arch/arm/mach-bcm/Kconfig >> +++ b/arch/arm/mach-bcm/Kconfig >> @@ -10,6 +10,8 @@ config ARCH_BCM >> select GENERIC_CLOCKEVENTS >> select GENERIC_TIME >> select GPIO_BCM >> + select PINCTRL >> + select PINCTRL_CAPRI >> select SPARSE_IRQ >> select TICK_ONESHOT >> select CACHE_L2X0 > > On your subsequent patchset pls move this from Kconfig to > arm/configs/bcm_defconfig, and break that modification into a separate > patch from the drivers/* modification. The other SoCs I'm familiar with all select this from their ARCH_xxx config symbol. ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-17 14:54 ` Stephen Warren @ 2013-10-17 15:31 ` Christian Daudt 2013-12-11 0:05 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Christian Daudt @ 2013-10-17 15:31 UTC (permalink / raw) To: Stephen Warren, Kevin Hilman Cc: Sherman Yin, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Rob Landley, Russell King, Linus Walleij, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Thu, Oct 17, 2013 at 7:54 AM, Stephen Warren <swarren@wwwdotorg.org> wrote: > On 10/17/2013 12:03 AM, Christian Daudt wrote: >> On Thu, Oct 3, 2013 at 5:23 PM, Sherman Yin <syin@broadcom.com> wrote: >>> Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. >>> >>> Signed-off-by: Sherman Yin <syin@broadcom.com> >>> Reviewed-by: Christian Daudt <bcm@fixthebug.org> >>> Reviewed-by: Matt Porter <matt.porter@linaro.org> >>> --- >>> arch/arm/mach-bcm/Kconfig | 2 + >>> drivers/pinctrl/Kconfig | 10 + >>> drivers/pinctrl/Makefile | 1 + >>> drivers/pinctrl/pinctrl-capri.c | 1727 +++++++++++++++++++++++++++++++++++++++ >>> 4 files changed, 1740 insertions(+) >>> create mode 100644 drivers/pinctrl/pinctrl-capri.c >>> >>> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig >>> index 69d67f7..2546365 100644 >>> --- a/arch/arm/mach-bcm/Kconfig >>> +++ b/arch/arm/mach-bcm/Kconfig >>> @@ -10,6 +10,8 @@ config ARCH_BCM >>> select GENERIC_CLOCKEVENTS >>> select GENERIC_TIME >>> select GPIO_BCM >>> + select PINCTRL >>> + select PINCTRL_CAPRI >>> select SPARSE_IRQ >>> select TICK_ONESHOT >>> select CACHE_L2X0 >> >> On your subsequent patchset pls move this from Kconfig to >> arm/configs/bcm_defconfig, and break that modification into a separate >> patch from the drivers/* modification. > > The other SoCs I'm familiar with all select this from their ARCH_xxx > config symbol. > I had a discussion on what is best left under ARCH and what is best left to defconfig with Kevin Hilman a while back and the conclusion was that any config not strictly required for bootup is best left to defconfig. This will allow multiplatform kernels to switch to using them as loadable modules later on, something not possible with configs put under ARCH_xxx. Thanks, csd ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-17 15:31 ` Christian Daudt @ 2013-12-11 0:05 ` Sherman Yin 2013-12-12 20:43 ` Linus Walleij 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-12-11 0:05 UTC (permalink / raw) To: Christian Daudt, Stephen Warren, Kevin Hilman, Linus Walleij Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Rob Landley, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org, Markus Mayer On 13-10-17 08:31 AM, Christian Daudt wrote: > On Thu, Oct 17, 2013 at 7:54 AM, Stephen Warren <swarren@wwwdotorg.org> wrote: >> On 10/17/2013 12:03 AM, Christian Daudt wrote: >>> On Thu, Oct 3, 2013 at 5:23 PM, Sherman Yin <syin@broadcom.com> wrote: >>>> Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. >>>> >>>> Signed-off-by: Sherman Yin <syin@broadcom.com> >>>> Reviewed-by: Christian Daudt <bcm@fixthebug.org> >>>> Reviewed-by: Matt Porter <matt.porter@linaro.org> >>>> --- >>>> arch/arm/mach-bcm/Kconfig | 2 + >>>> drivers/pinctrl/Kconfig | 10 + >>>> drivers/pinctrl/Makefile | 1 + >>>> drivers/pinctrl/pinctrl-capri.c | 1727 +++++++++++++++++++++++++++++++++++++++ >>>> 4 files changed, 1740 insertions(+) >>>> create mode 100644 drivers/pinctrl/pinctrl-capri.c >>>> >>>> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig >>>> index 69d67f7..2546365 100644 >>>> --- a/arch/arm/mach-bcm/Kconfig >>>> +++ b/arch/arm/mach-bcm/Kconfig >>>> @@ -10,6 +10,8 @@ config ARCH_BCM >>>> select GENERIC_CLOCKEVENTS >>>> select GENERIC_TIME >>>> select GPIO_BCM >>>> + select PINCTRL >>>> + select PINCTRL_CAPRI >>>> select SPARSE_IRQ >>>> select TICK_ONESHOT >>>> select CACHE_L2X0 >>> >>> On your subsequent patchset pls move this from Kconfig to >>> arm/configs/bcm_defconfig, and break that modification into a separate >>> patch from the drivers/* modification. >> >> The other SoCs I'm familiar with all select this from their ARCH_xxx >> config symbol. >> > I had a discussion on what is best left under ARCH and what is best > left to defconfig with Kevin Hilman a while back and the conclusion > was that any config not strictly required for bootup is best left to > defconfig. This will allow multiplatform kernels to switch to using > them as loadable modules later on, something not possible with configs > put under ARCH_xxx. > > Thanks, > csd > I was just trying to move "select PINCTRL" to a defconfig as Christian suggested. However, CONFIG_PINCTRL is not selectable by a defconfig file (the option will be gone by the time .config is generated), even though PINCTRL has no dependency. Also, this option is not visible in menuconfig. I found that by adding a string after "bool" in the PINCTRL config definition (see diff below), CONFIG_PINCTRL will be selectable in a defconfig file and this option will also be visible in menuconfig. Was this intentional or is this a bug? To address Christian's comment, I'll need to add the following patch. Regards, Sherman ================== diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 6c70fc5..664c8e6 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -3,7 +3,7 @@ # config PINCTRL - bool + bool "Enable the pinctrl framework" if PINCTRL ================== ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-12-11 0:05 ` Sherman Yin @ 2013-12-12 20:43 ` Linus Walleij 0 siblings, 0 replies; 85+ messages in thread From: Linus Walleij @ 2013-12-12 20:43 UTC (permalink / raw) To: Sherman Yin Cc: Christian Daudt, Stephen Warren, Kevin Hilman, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Rob Landley, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org, Markus Mayer On Wed, Dec 11, 2013 at 1:05 AM, Sherman Yin <syin@broadcom.com> wrote: > I was just trying to move "select PINCTRL" to a defconfig as Christian > suggested. However, CONFIG_PINCTRL is not selectable by a defconfig file > (the option will be gone by the time .config is generated), even though > PINCTRL has no dependency. Also, this option is not visible in menuconfig. > > I found that by adding a string after "bool" in the PINCTRL config > definition (see diff below), CONFIG_PINCTRL will be selectable in a > defconfig file and this option will also be visible in menuconfig. > > Was this intentional or is this a bug? To address Christian's comment, I'll > need to add the following patch. This was intentional. Pin control was considered an intrinsic of specific embedded systems and not to be broadcasted to anyone running menuconfig. But if you really need this, we can discuss it. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs 2013-10-04 0:23 [PATCH 0/4] Add Broadcom Capri pinctrl driver Sherman Yin 2013-10-04 0:23 ` [PATCH 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin [not found] ` <1380846199-12829-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2013-10-04 0:23 ` Sherman Yin 2013-10-09 9:11 ` Linus Walleij 2013-10-07 19:28 ` [PATCH v2 0/4] Add Broadcom Capri pinctrl driver Sherman Yin 3 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-10-04 0:23 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin Enable pinctrl for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- arch/arm/boot/dts/bcm11351.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 05a5aab..f497a40 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -96,4 +96,8 @@ status = "disabled"; }; + pinctrl@35004800 { + compatible = "brcm,capri-pinctrl"; + reg = <0x35004800 0x430>; + }; }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs 2013-10-04 0:23 ` [PATCH 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin @ 2013-10-09 9:11 ` Linus Walleij 0 siblings, 0 replies; 85+ messages in thread From: Linus Walleij @ 2013-10-09 9:11 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Fri, Oct 4, 2013 at 2:23 AM, Sherman Yin <syin@broadcom.com> wrote: > Enable pinctrl for Broadcom Capri (BCM281xx) SoCs. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > Reviewed-by: Christian Daudt <bcm@fixthebug.org> > Reviewed-by: Matt Porter <matt.porter@linaro.org> (...) > + pinctrl@35004800 { > + compatible = "brcm,capri-pinctrl"; > + reg = <0x35004800 0x430>; > + }; What is the point of doing this without defining some pins and connecting them to some devices? Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v2 0/4] Add Broadcom Capri pinctrl driver 2013-10-04 0:23 [PATCH 0/4] Add Broadcom Capri pinctrl driver Sherman Yin ` (2 preceding siblings ...) 2013-10-04 0:23 ` [PATCH 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin @ 2013-10-07 19:28 ` Sherman Yin 2013-10-07 19:28 ` [PATCH v2 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin ` (4 more replies) 3 siblings, 5 replies; 85+ messages in thread From: Sherman Yin @ 2013-10-07 19:28 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin The following patches adds a pinctrl driver for Broadcom Capri (BCM281xx) SoCs. The first patch, adding the void * to pinctrl_pin_desc, has been previously discussed with LinusW. See this thread: http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/165880.html --- v2: Use hyphens instead of underscore in DT property names. Sherman Yin (4): pinctrl: Add void * to pinctrl_pin_desc pinctrl: Add pinctrl binding for Broadcom Capri SoCs ARM: pinctrl: Add Broadcom Capri pinctrl driver pinctrl: Enable pinctrl for Broadcom Capri SoCs .../bindings/pinctrl/brcm,capri-pinctrl.txt | 419 +++++ arch/arm/boot/dts/bcm11351.dtsi | 4 + arch/arm/mach-bcm/Kconfig | 2 + drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-capri.c | 1727 ++++++++++++++++++++ include/linux/pinctrl/pinctrl.h | 2 + 7 files changed, 2165 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-capri.c -- 1.7.9.5 ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v2 1/4] pinctrl: Add void * to pinctrl_pin_desc 2013-10-07 19:28 ` [PATCH v2 0/4] Add Broadcom Capri pinctrl driver Sherman Yin @ 2013-10-07 19:28 ` Sherman Yin 2013-10-07 19:28 ` [PATCH v2 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin ` (3 subsequent siblings) 4 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-10-07 19:28 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin drv_data is added to the pinctrl_pin_desc for drivers to define additional driver-specific per-pin data. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- Change-Id: I78b2c44b93d88b04897fd0af80ffce213e338d6b v2: Use hyphens instead of underscore in DT property names. --- include/linux/pinctrl/pinctrl.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 5979147..c8e42c4 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -32,10 +32,12 @@ struct device_node; * pins, pads or other muxable units in this struct * @number: unique pin number from the global pin number space * @name: a name for this pin + * @drv_data: driver-defined per-pin data. pinctrl core does not touch this */ struct pinctrl_pin_desc { unsigned number; const char *name; + void *drv_data; }; /* Convenience macro to define a single named or anonymous pin descriptor */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v2 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2013-10-07 19:28 ` [PATCH v2 0/4] Add Broadcom Capri pinctrl driver Sherman Yin 2013-10-07 19:28 ` [PATCH v2 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin @ 2013-10-07 19:28 ` Sherman Yin 2013-10-07 19:28 ` [PATCH v2 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin ` (2 subsequent siblings) 4 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-10-07 19:28 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- v2: Use hyphens instead of underscore in DT property names. --- .../bindings/pinctrl/brcm,capri-pinctrl.txt | 419 ++++++++++++++++++++ 1 file changed, 419 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt new file mode 100644 index 0000000..efee207 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt @@ -0,0 +1,419 @@ +Broadcom Capri Pin Controller + +This is a pin controller for the Broadcom BCM281xx SoC family, which includes +BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs. + +=== Pin Controller Node === + +Required Properties: + +- compatible: Must be "brcm,capri-pinctrl". +- reg: Base address of the PAD Controller register block and the size + of the block. + +For example, the following is the bare minimum node: + + pinctrl@35004800 { + compatible = "brcm,capri-pinctrl"; + reg = <0x35004800 0x430>; + }; + +As a Pin Controller Device, in addition to the required properties, this node +should also contain the pin configuration nodes that client devices reference, +if any. + +=== Pin Configuration Node === + +Each pin configuration node is a sub-node of the pin controller node and is a +container of an arbitrary number of subnodes, called group nodes. + +Please refer to the pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the definition of a +"pin configuration node". + +=== Group Node === + +A group node specifies the desired pin mux and/or pin configuration for an +arbitrary number of pins. The group node only affect the properties specified +in the node, and has no effect on any properties that are omitted. + +The names of the group nodes are optional and not used. The group nodes have +the following properties: + +Required Properties: + +- brcm,pins: Multiple strings. Specifies the name(s) of one or more pins to + be configured by this node. + +Optional Properties: + +- brcm,function: Multiple strings. Specifies the pin mux selection. Values are: + "alt1", "alt2", "alt3", "alt4" +- brcm,hysteresis: Multiple integers, applicable to standard pins only. Turns + on hysteresis of input. + 0: TTL input, 1: Schmitt Trigger input +- brcm,pull: Multiple integers, applicable to standard pins only. Specifies + pull-up or pull-down. + 0: neither, 1: pull-up, 2: pull-down, 3: both +- brcm,input-dis: Multiple integers, applicable to all pins. Input disable + control. + 0: off, 1: input disabled +- brcm,slew: Multiple integers. Slew rate of output. + 0: fast output, 1: normal output (most pins) + 0: normal output, 1: fast output (IC_DM and IC_DP) + 0: Fast mode, 1: High speed mode (I2C) +- brcm,drive-str: Multiple integers. Drive strength. + 0: 2 mA + 1: 4 mA + 2: 6 mA + 3: 8 mA + 4: 10 mA + 5: 12 mA + 6: 14 mA + 7: 16 mA +- brcm,pull-up-str: Multiple integers. Pull Up strength. + 0: No pull-up + 1: 1.2 kOhm + 2: 1.8 kOhm + 3: 720 Ohm + 4: 2.7 kOhm + 5: 831 Ohm + 6: 1.08 kOhm + 7: 568 Ohm +- brcm,mode: Multiple integers. Mode select. + 0: Fast mode, 1: High Speed mode (I2C) + +Any optional property must have 1 or n values, where n is the number of pins +specified in the brcm,pins property: +- If 1 value is specified for a property, this value is applied to all pins + listed in the brcm,pins property. +- If n values are specified, the i th value is applied to the i th pin, where + i is the index in the array of values and pins, and (0 <= i < n). This + provides an easy way to set different values for different pins in the same + group. + +Example: + + // pin configuration node + dev_a_active { + //group node + grp_1 { + brcm,pins = "pin1", "pin2", "pin3"; + brcm,function = "alt1"; + brcm,drive-str = <2 4 6>; + brcm,slew = <1>; + }; + + grp_2 { + ... + }; + + ... + }; + +In the example above, "dev_a_active" is a pin configuration node and has a +number of sub-nodes. In the group node "grp_1", 3 pins are defined in the +"brcm,pins" property. Thus, any optional properties must have either 1 or 3 +values. The "brcm,function" property has only one value, "alt1", therefore the +pin mux selection for all 3 pins is "alt1". Similarly, "brcm,slew" has only one +value, <1>, so all 3 pins are configured with a slew rate setting of <1>. +"brcm,drive-str" has 3 values, and they are applied in the same order of the pins +listed in "brcm,pins": the drive strength of "pin1" is set to <2>, <4> for +"pin2", and <6> for "pin3". Finally, no other parameters are sepcified, +implying no changes to any other parameters for these pins. + +=== Pin Names and Type === + +There are 3 types of pins in the BCM281xx SoC family, each type can be +configured by different properties in a group node. The following is a list of +node properties applicable to different pin types. + +Standard pins: +- brcm,function +- brcm,hysteresis +- brcm,pull +- brcm,input-dis +- brcm,slew +- brcm,drive-str + +I2C pins: +- brcm,function +- brcm,input-dis +- brcm,slew +- brcm,pull-up-str + +HDMI pins: +- brcm,function +- brcm,input-dis +- brcm,mode + +The following are valid pin names and their pin types: + + "adcsync", std + "bat_rm", std + "bsc1_scl", i2c + "bsc1_sda", i2c + "bsc2_scl", i2c + "bsc2_sda", i2c + "classgpwr", std + "clk_cx8", std + "clkout_0", std + "clkout_1", std + "clkout_2", std + "clkout_3", std + "clkreq_in_0", std + "clkreq_in_1", std + "cws_sys_req1", std + "cws_sys_req2", std + "cws_sys_req3", std + "digmic1_clk", std + "digmic1_dq", std + "digmic2_clk", std + "digmic2_dq", std + "gpen13", std + "gpen14", std + "gpen15", std + "gpio00", std + "gpio01", std + "gpio02", std + "gpio03", std + "gpio04", std + "gpio05", std + "gpio06", std + "gpio07", std + "gpio08", std + "gpio09", std + "gpio10", std + "gpio11", std + "gpio12", std + "gpio13", std + "gpio14", std + "gps_pablank", std + "gps_tmark", std + "hdmi_scl", hdmi + "hdmi_sda", hdmi + "ic_dm", std + "ic_dp", std + "kp_col_ip_0", std + "kp_col_ip_1", std + "kp_col_ip_2", std + "kp_col_ip_3", std + "kp_row_op_0", std + "kp_row_op_1", std + "kp_row_op_2", std + "kp_row_op_3", std + "lcd_b_0", std + "lcd_b_1", std + "lcd_b_2", std + "lcd_b_3", std + "lcd_b_4", std + "lcd_b_5", std + "lcd_b_6", std + "lcd_b_7", std + "lcd_g_0", std + "lcd_g_1", std + "lcd_g_2", std + "lcd_g_3", std + "lcd_g_4", std + "lcd_g_5", std + "lcd_g_6", std + "lcd_g_7", std + "lcd_hsync", std + "lcd_oe", std + "lcd_pclk", std + "lcd_r_0", std + "lcd_r_1", std + "lcd_r_2", std + "lcd_r_3", std + "lcd_r_4", std + "lcd_r_5", std + "lcd_r_6", std + "lcd_r_7", std + "lcd_vsync", std + "mdmgpio0", std + "mdmgpio1", std + "mdmgpio2", std + "mdmgpio3", std + "mdmgpio4", std + "mdmgpio5", std + "mdmgpio6", std + "mdmgpio7", std + "mdmgpio8", std + "mphi_data_0", std + "mphi_data_1", std + "mphi_data_2", std + "mphi_data_3", std + "mphi_data_4", std + "mphi_data_5", std + "mphi_data_6", std + "mphi_data_7", std + "mphi_data_8", std + "mphi_data_9", std + "mphi_data_10", std + "mphi_data_11", std + "mphi_data_12", std + "mphi_data_13", std + "mphi_data_14", std + "mphi_data_15", std + "mphi_ha0", std + "mphi_hat0", std + "mphi_hat1", std + "mphi_hce0_n", std + "mphi_hce1_n", std + "mphi_hrd_n", std + "mphi_hwr_n", std + "mphi_run0", std + "mphi_run1", std + "mtx_scan_clk", std + "mtx_scan_data", std + "nand_ad_0", std + "nand_ad_1", std + "nand_ad_2", std + "nand_ad_3", std + "nand_ad_4", std + "nand_ad_5", std + "nand_ad_6", std + "nand_ad_7", std + "nand_ale", std + "nand_cen_0", std + "nand_cen_1", std + "nand_cle", std + "nand_oen", std + "nand_rdy_0", std + "nand_rdy_1", std + "nand_wen", std + "nand_wp", std + "pc1", std + "pc2", std + "pmu_int", std + "pmu_scl", i2c + "pmu_sda", i2c + "rfst2g_mtsloten3g", std + "rgmii_0_rx_ctl", std + "rgmii_0_rxc", std + "rgmii_0_rxd_0", std + "rgmii_0_rxd_1", std + "rgmii_0_rxd_2", std + "rgmii_0_rxd_3", std + "rgmii_0_tx_ctl", std + "rgmii_0_txc", std + "rgmii_0_txd_0", std + "rgmii_0_txd_1", std + "rgmii_0_txd_2", std + "rgmii_0_txd_3", std + "rgmii_1_rx_ctl", std + "rgmii_1_rxc", std + "rgmii_1_rxd_0", std + "rgmii_1_rxd_1", std + "rgmii_1_rxd_2", std + "rgmii_1_rxd_3", std + "rgmii_1_tx_ctl", std + "rgmii_1_txc", std + "rgmii_1_txd_0", std + "rgmii_1_txd_1", std + "rgmii_1_txd_2", std + "rgmii_1_txd_3", std + "rgmii_gpio_0", std + "rgmii_gpio_1", std + "rgmii_gpio_2", std + "rgmii_gpio_3", std + "rtxdata2g_txdata3g1", std + "rtxen2g_txdata3g2", std + "rxdata3g0", std + "rxdata3g1", std + "rxdata3g2", std + "sdio1_clk", std + "sdio1_cmd", std + "sdio1_data_0", std + "sdio1_data_1", std + "sdio1_data_2", std + "sdio1_data_3", std + "sdio4_clk", std + "sdio4_cmd", std + "sdio4_data_0", std + "sdio4_data_1", std + "sdio4_data_2", std + "sdio4_data_3", std + "sim_clk", std + "sim_data", std + "sim_det", std + "sim_resetn", std + "sim2_clk", std + "sim2_data", std + "sim2_det", std + "sim2_resetn", std + "sri_c", std + "sri_d", std + "sri_e", std + "ssp_extclk", std + "ssp0_clk", std + "ssp0_fs", std + "ssp0_rxd", std + "ssp0_txd", std + "ssp2_clk", std + "ssp2_fs_0", std + "ssp2_fs_1", std + "ssp2_fs_2", std + "ssp2_fs_3", std + "ssp2_rxd_0", std + "ssp2_rxd_1", std + "ssp2_txd_0", std + "ssp2_txd_1", std + "ssp3_clk", std + "ssp3_fs", std + "ssp3_rxd", std + "ssp3_txd", std + "ssp4_clk", std + "ssp4_fs", std + "ssp4_rxd", std + "ssp4_txd", std + "ssp5_clk", std + "ssp5_fs", std + "ssp5_rxd", std + "ssp5_txd", std + "ssp6_clk", std + "ssp6_fs", std + "ssp6_rxd", std + "ssp6_txd", std + "stat_1", std + "stat_2", std + "sysclken", std + "traceclk", std + "tracedt00", std + "tracedt01", std + "tracedt02", std + "tracedt03", std + "tracedt04", std + "tracedt05", std + "tracedt06", std + "tracedt07", std + "tracedt08", std + "tracedt09", std + "tracedt10", std + "tracedt11", std + "tracedt12", std + "tracedt13", std + "tracedt14", std + "tracedt15", std + "txdata3g0", std + "txpwrind", std + "uartb1_ucts", std + "uartb1_urts", std + "uartb1_urxd", std + "uartb1_utxd", std + "uartb2_urxd", std + "uartb2_utxd", std + "uartb3_ucts", std + "uartb3_urts", std + "uartb3_urxd", std + "uartb3_utxd", std + "uartb4_ucts", std + "uartb4_urts", std + "uartb4_urxd", std + "uartb4_utxd", std + "vc_cam1_scl", i2c + "vc_cam1_sda", i2c + "vc_cam2_scl", i2c + "vc_cam2_sda", i2c + "vc_cam3_scl", i2c + "vc_cam3_sda", i2c -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v2 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-10-07 19:28 ` [PATCH v2 0/4] Add Broadcom Capri pinctrl driver Sherman Yin 2013-10-07 19:28 ` [PATCH v2 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin 2013-10-07 19:28 ` [PATCH v2 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin @ 2013-10-07 19:28 ` Sherman Yin 2013-10-07 19:28 ` [PATCH v2 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin 2013-12-11 18:37 ` [PATCH v3 0/6] Add Broadcom Capri pinctrl driver Sherman Yin 4 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-10-07 19:28 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- v2: Use hyphens instead of underscore in DT property names. --- arch/arm/mach-bcm/Kconfig | 2 + drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-capri.c | 1727 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 1740 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-capri.c diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 69d67f7..2546365 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -10,6 +10,8 @@ config ARCH_BCM select GENERIC_CLOCKEVENTS select GENERIC_TIME select GPIO_BCM + select PINCTRL + select PINCTRL_CAPRI select SPARSE_IRQ select TICK_ONESHOT select CACHE_L2X0 diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b6e864e..f97eb11 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -75,6 +75,16 @@ config PINCTRL_BCM2835 select PINMUX select PINCONF +config PINCTRL_CAPRI + bool "Broadcom Capri pinctrl driver" + select PINMUX + select PINCONF + help + Say Y here to support Broadcom Capri pinctrl driver, which is used for + the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, + BCM28145, and BCM28155 SoCs. This driver requires the pinctrl + framework. GPIO is provided by a separate GPIO driver. + config PINCTRL_IMX bool select PINMUX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 496d9bf..5e1a68e 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o +obj-$(CONFIG_PINCTRL_CAPRI) += pinctrl-capri.o obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o diff --git a/drivers/pinctrl/pinctrl-capri.c b/drivers/pinctrl/pinctrl-capri.c new file mode 100644 index 0000000..5ec17d0 --- /dev/null +++ b/drivers/pinctrl/pinctrl-capri.c @@ -0,0 +1,1727 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/slab.h> +#include "core.h" + +#define CAPRI_PINCONF_PACK(val, mask) (((val) << 16) | ((mask) & 0xffff)) +#define CAPRI_PINCONF_UNPACK_VAL(conf) ((conf) >> 16) +#define CAPRI_PINCONF_UNPACK_MASK(conf) ((conf) & 0xffff) + +enum capri_pinconf_param { + CAPRI_PINCONF_PARAM_NONE = 0, + CAPRI_PINCONF_PARAM_HYST, + CAPRI_PINCONF_PARAM_PULL, + CAPRI_PINCONF_PARAM_SLEW, + CAPRI_PINCONF_PARAM_INPUT_DIS, + CAPRI_PINCONF_PARAM_DRV_STR, + CAPRI_PINCONF_PARAM_PULL_UP_STR, + CAPRI_PINCONF_PARAM_MODE, +}; + +struct capri_cfg_param { + const char *property; + enum capri_pinconf_param id; +}; + +static const struct capri_cfg_param capri_pinconf_params[] = { + {"brcm,hysteresis", CAPRI_PINCONF_PARAM_HYST}, + {"brcm,pull", CAPRI_PINCONF_PARAM_PULL}, + {"brcm,slew", CAPRI_PINCONF_PARAM_SLEW}, + {"brcm,input-dis", CAPRI_PINCONF_PARAM_INPUT_DIS}, + {"brcm,drive-str", CAPRI_PINCONF_PARAM_DRV_STR}, + {"brcm,pull-up-str", CAPRI_PINCONF_PARAM_PULL_UP_STR}, + {"brcm,mode", CAPRI_PINCONF_PARAM_MODE}, +}; + +/* Capri Pin Control Registers Definitions */ + +/* Functionn Select bits are the same for all pin control registers */ +#define CAPRI_PIN_REG_F_SEL_MASK 0x0700 +#define CAPRI_PIN_REG_F_SEL_SHIFT 8 + +/* Standard pin register */ +#define CAPRI_STD_PIN_REG_DRV_STR_MASK 0x0007 +#define CAPRI_STD_PIN_REG_DRV_STR_SHIFT 0 +#define CAPRI_STD_PIN_REG_INPUT_DIS_MASK 0x0008 +#define CAPRI_STD_PIN_REG_INPUT_DIS_SHIFT 3 +#define CAPRI_STD_PIN_REG_SLEW_MASK 0x0010 +#define CAPRI_STD_PIN_REG_SLEW_SHIFT 4 +#define CAPRI_STD_PIN_REG_PULL_MASK 0x0060 +#define CAPRI_STD_PIN_REG_PULL_SHIFT 5 +#define CAPRI_STD_PIN_REG_HYST_MASK 0x0080 +#define CAPRI_STD_PIN_REG_HYST_SHIFT 7 + +/* I2C pin register */ +#define CAPRI_I2C_PIN_REG_INPUT_DIS_MASK 0x0004 +#define CAPRI_I2C_PIN_REG_INPUT_DIS_SHIFT 2 +#define CAPRI_I2C_PIN_REG_SLEW_MASK 0x0008 +#define CAPRI_I2C_PIN_REG_SLEW_SHIFT 3 +#define CAPRI_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070 +#define CAPRI_I2C_PIN_REG_PULL_UP_STR_SHIFT 4 + +/* HDMI pin register */ +#define CAPRI_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008 +#define CAPRI_HDMI_PIN_REG_INPUT_DIS_SHIFT 3 +#define CAPRI_HDMI_PIN_REG_MODE_MASK 0x0010 +#define CAPRI_HDMI_PIN_REG_MODE_SHIFT 4 + +/* Macro to update reg with new pin config param */ +#define CAPRI_PIN_REG_SET(reg, type, param, val) \ + (((reg) & ~CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK) \ + | (((val) << CAPRI_ ## type ## _PIN_REG_ ## param ## _SHIFT) \ + & CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK)) + +/** + * capri_pin_type - types of pin register + */ +enum capri_pin_type { + CAPRI_PIN_TYPE_UNKNOWN = 0, + CAPRI_PIN_TYPE_STD, + CAPRI_PIN_TYPE_I2C, + CAPRI_PIN_TYPE_HDMI, +}; + +static enum capri_pin_type std_pin = CAPRI_PIN_TYPE_STD; +static enum capri_pin_type i2c_pin = CAPRI_PIN_TYPE_I2C; +static enum capri_pin_type hdmi_pin = CAPRI_PIN_TYPE_HDMI; + +/** + * capri_pin_function- define pin function + */ +struct capri_pin_function { + const char *name; + const char * const *groups; + const unsigned ngroups; +}; + +/** + * capri_pinctrl_data - Broadcom-specific pinctrl data + * @reg_base - base of pinctrl registers + */ +struct capri_pinctrl_data { + void __iomem *reg_base; + + /* List of all pins */ + const struct pinctrl_pin_desc *pins; + const unsigned npins; + + const struct capri_pin_function *functions; + const unsigned nfunctions; +}; + +#define _PIN(offset) (offset) + +/* + * Pin number definition. The order here must be the same as defined in the + * PADCTRLREG block in the RDB. + */ +#define CAPRI_PIN_ADCSYNC _PIN(0) +#define CAPRI_PIN_BAT_RM _PIN(1) +#define CAPRI_PIN_BSC1_SCL _PIN(2) +#define CAPRI_PIN_BSC1_SDA _PIN(3) +#define CAPRI_PIN_BSC2_SCL _PIN(4) +#define CAPRI_PIN_BSC2_SDA _PIN(5) +#define CAPRI_PIN_CLASSGPWR _PIN(6) +#define CAPRI_PIN_CLK_CX8 _PIN(7) +#define CAPRI_PIN_CLKOUT_0 _PIN(8) +#define CAPRI_PIN_CLKOUT_1 _PIN(9) +#define CAPRI_PIN_CLKOUT_2 _PIN(10) +#define CAPRI_PIN_CLKOUT_3 _PIN(11) +#define CAPRI_PIN_CLKREQ_IN_0 _PIN(12) +#define CAPRI_PIN_CLKREQ_IN_1 _PIN(13) +#define CAPRI_PIN_CWS_SYS_REQ1 _PIN(14) +#define CAPRI_PIN_CWS_SYS_REQ2 _PIN(15) +#define CAPRI_PIN_CWS_SYS_REQ3 _PIN(16) +#define CAPRI_PIN_DIGMIC1_CLK _PIN(17) +#define CAPRI_PIN_DIGMIC1_DQ _PIN(18) +#define CAPRI_PIN_DIGMIC2_CLK _PIN(19) +#define CAPRI_PIN_DIGMIC2_DQ _PIN(20) +#define CAPRI_PIN_GPEN13 _PIN(21) +#define CAPRI_PIN_GPEN14 _PIN(22) +#define CAPRI_PIN_GPEN15 _PIN(23) +#define CAPRI_PIN_GPIO00 _PIN(24) +#define CAPRI_PIN_GPIO01 _PIN(25) +#define CAPRI_PIN_GPIO02 _PIN(26) +#define CAPRI_PIN_GPIO03 _PIN(27) +#define CAPRI_PIN_GPIO04 _PIN(28) +#define CAPRI_PIN_GPIO05 _PIN(29) +#define CAPRI_PIN_GPIO06 _PIN(30) +#define CAPRI_PIN_GPIO07 _PIN(31) +#define CAPRI_PIN_GPIO08 _PIN(32) +#define CAPRI_PIN_GPIO09 _PIN(33) +#define CAPRI_PIN_GPIO10 _PIN(34) +#define CAPRI_PIN_GPIO11 _PIN(35) +#define CAPRI_PIN_GPIO12 _PIN(36) +#define CAPRI_PIN_GPIO13 _PIN(37) +#define CAPRI_PIN_GPIO14 _PIN(38) +#define CAPRI_PIN_GPS_PABLANK _PIN(39) +#define CAPRI_PIN_GPS_TMARK _PIN(40) +#define CAPRI_PIN_HDMI_SCL _PIN(41) +#define CAPRI_PIN_HDMI_SDA _PIN(42) +#define CAPRI_PIN_IC_DM _PIN(43) +#define CAPRI_PIN_IC_DP _PIN(44) +#define CAPRI_PIN_KP_COL_IP_0 _PIN(45) +#define CAPRI_PIN_KP_COL_IP_1 _PIN(46) +#define CAPRI_PIN_KP_COL_IP_2 _PIN(47) +#define CAPRI_PIN_KP_COL_IP_3 _PIN(48) +#define CAPRI_PIN_KP_ROW_OP_0 _PIN(49) +#define CAPRI_PIN_KP_ROW_OP_1 _PIN(50) +#define CAPRI_PIN_KP_ROW_OP_2 _PIN(51) +#define CAPRI_PIN_KP_ROW_OP_3 _PIN(52) +#define CAPRI_PIN_LCD_B_0 _PIN(53) +#define CAPRI_PIN_LCD_B_1 _PIN(54) +#define CAPRI_PIN_LCD_B_2 _PIN(55) +#define CAPRI_PIN_LCD_B_3 _PIN(56) +#define CAPRI_PIN_LCD_B_4 _PIN(57) +#define CAPRI_PIN_LCD_B_5 _PIN(58) +#define CAPRI_PIN_LCD_B_6 _PIN(59) +#define CAPRI_PIN_LCD_B_7 _PIN(60) +#define CAPRI_PIN_LCD_G_0 _PIN(61) +#define CAPRI_PIN_LCD_G_1 _PIN(62) +#define CAPRI_PIN_LCD_G_2 _PIN(63) +#define CAPRI_PIN_LCD_G_3 _PIN(64) +#define CAPRI_PIN_LCD_G_4 _PIN(65) +#define CAPRI_PIN_LCD_G_5 _PIN(66) +#define CAPRI_PIN_LCD_G_6 _PIN(67) +#define CAPRI_PIN_LCD_G_7 _PIN(68) +#define CAPRI_PIN_LCD_HSYNC _PIN(69) +#define CAPRI_PIN_LCD_OE _PIN(70) +#define CAPRI_PIN_LCD_PCLK _PIN(71) +#define CAPRI_PIN_LCD_R_0 _PIN(72) +#define CAPRI_PIN_LCD_R_1 _PIN(73) +#define CAPRI_PIN_LCD_R_2 _PIN(74) +#define CAPRI_PIN_LCD_R_3 _PIN(75) +#define CAPRI_PIN_LCD_R_4 _PIN(76) +#define CAPRI_PIN_LCD_R_5 _PIN(77) +#define CAPRI_PIN_LCD_R_6 _PIN(78) +#define CAPRI_PIN_LCD_R_7 _PIN(79) +#define CAPRI_PIN_LCD_VSYNC _PIN(80) +#define CAPRI_PIN_MDMGPIO0 _PIN(81) +#define CAPRI_PIN_MDMGPIO1 _PIN(82) +#define CAPRI_PIN_MDMGPIO2 _PIN(83) +#define CAPRI_PIN_MDMGPIO3 _PIN(84) +#define CAPRI_PIN_MDMGPIO4 _PIN(85) +#define CAPRI_PIN_MDMGPIO5 _PIN(86) +#define CAPRI_PIN_MDMGPIO6 _PIN(87) +#define CAPRI_PIN_MDMGPIO7 _PIN(88) +#define CAPRI_PIN_MDMGPIO8 _PIN(89) +#define CAPRI_PIN_MPHI_DATA_0 _PIN(90) +#define CAPRI_PIN_MPHI_DATA_1 _PIN(91) +#define CAPRI_PIN_MPHI_DATA_2 _PIN(92) +#define CAPRI_PIN_MPHI_DATA_3 _PIN(93) +#define CAPRI_PIN_MPHI_DATA_4 _PIN(94) +#define CAPRI_PIN_MPHI_DATA_5 _PIN(95) +#define CAPRI_PIN_MPHI_DATA_6 _PIN(96) +#define CAPRI_PIN_MPHI_DATA_7 _PIN(97) +#define CAPRI_PIN_MPHI_DATA_8 _PIN(98) +#define CAPRI_PIN_MPHI_DATA_9 _PIN(99) +#define CAPRI_PIN_MPHI_DATA_10 _PIN(100) +#define CAPRI_PIN_MPHI_DATA_11 _PIN(101) +#define CAPRI_PIN_MPHI_DATA_12 _PIN(102) +#define CAPRI_PIN_MPHI_DATA_13 _PIN(103) +#define CAPRI_PIN_MPHI_DATA_14 _PIN(104) +#define CAPRI_PIN_MPHI_DATA_15 _PIN(105) +#define CAPRI_PIN_MPHI_HA0 _PIN(106) +#define CAPRI_PIN_MPHI_HAT0 _PIN(107) +#define CAPRI_PIN_MPHI_HAT1 _PIN(108) +#define CAPRI_PIN_MPHI_HCE0_N _PIN(109) +#define CAPRI_PIN_MPHI_HCE1_N _PIN(110) +#define CAPRI_PIN_MPHI_HRD_N _PIN(111) +#define CAPRI_PIN_MPHI_HWR_N _PIN(112) +#define CAPRI_PIN_MPHI_RUN0 _PIN(113) +#define CAPRI_PIN_MPHI_RUN1 _PIN(114) +#define CAPRI_PIN_MTX_SCAN_CLK _PIN(115) +#define CAPRI_PIN_MTX_SCAN_DATA _PIN(116) +#define CAPRI_PIN_NAND_AD_0 _PIN(117) +#define CAPRI_PIN_NAND_AD_1 _PIN(118) +#define CAPRI_PIN_NAND_AD_2 _PIN(119) +#define CAPRI_PIN_NAND_AD_3 _PIN(120) +#define CAPRI_PIN_NAND_AD_4 _PIN(121) +#define CAPRI_PIN_NAND_AD_5 _PIN(122) +#define CAPRI_PIN_NAND_AD_6 _PIN(123) +#define CAPRI_PIN_NAND_AD_7 _PIN(124) +#define CAPRI_PIN_NAND_ALE _PIN(125) +#define CAPRI_PIN_NAND_CEN_0 _PIN(126) +#define CAPRI_PIN_NAND_CEN_1 _PIN(127) +#define CAPRI_PIN_NAND_CLE _PIN(128) +#define CAPRI_PIN_NAND_OEN _PIN(129) +#define CAPRI_PIN_NAND_RDY_0 _PIN(130) +#define CAPRI_PIN_NAND_RDY_1 _PIN(131) +#define CAPRI_PIN_NAND_WEN _PIN(132) +#define CAPRI_PIN_NAND_WP _PIN(133) +#define CAPRI_PIN_PC1 _PIN(134) +#define CAPRI_PIN_PC2 _PIN(135) +#define CAPRI_PIN_PMU_INT _PIN(136) +#define CAPRI_PIN_PMU_SCL _PIN(137) +#define CAPRI_PIN_PMU_SDA _PIN(138) +#define CAPRI_PIN_RFST2G_MTSLOTEN3G _PIN(139) +#define CAPRI_PIN_RGMII_0_RX_CTL _PIN(140) +#define CAPRI_PIN_RGMII_0_RXC _PIN(141) +#define CAPRI_PIN_RGMII_0_RXD_0 _PIN(142) +#define CAPRI_PIN_RGMII_0_RXD_1 _PIN(143) +#define CAPRI_PIN_RGMII_0_RXD_2 _PIN(144) +#define CAPRI_PIN_RGMII_0_RXD_3 _PIN(145) +#define CAPRI_PIN_RGMII_0_TX_CTL _PIN(146) +#define CAPRI_PIN_RGMII_0_TXC _PIN(147) +#define CAPRI_PIN_RGMII_0_TXD_0 _PIN(148) +#define CAPRI_PIN_RGMII_0_TXD_1 _PIN(149) +#define CAPRI_PIN_RGMII_0_TXD_2 _PIN(150) +#define CAPRI_PIN_RGMII_0_TXD_3 _PIN(151) +#define CAPRI_PIN_RGMII_1_RX_CTL _PIN(152) +#define CAPRI_PIN_RGMII_1_RXC _PIN(153) +#define CAPRI_PIN_RGMII_1_RXD_0 _PIN(154) +#define CAPRI_PIN_RGMII_1_RXD_1 _PIN(155) +#define CAPRI_PIN_RGMII_1_RXD_2 _PIN(156) +#define CAPRI_PIN_RGMII_1_RXD_3 _PIN(157) +#define CAPRI_PIN_RGMII_1_TX_CTL _PIN(158) +#define CAPRI_PIN_RGMII_1_TXC _PIN(159) +#define CAPRI_PIN_RGMII_1_TXD_0 _PIN(160) +#define CAPRI_PIN_RGMII_1_TXD_1 _PIN(161) +#define CAPRI_PIN_RGMII_1_TXD_2 _PIN(162) +#define CAPRI_PIN_RGMII_1_TXD_3 _PIN(163) +#define CAPRI_PIN_RGMII_GPIO_0 _PIN(164) +#define CAPRI_PIN_RGMII_GPIO_1 _PIN(165) +#define CAPRI_PIN_RGMII_GPIO_2 _PIN(166) +#define CAPRI_PIN_RGMII_GPIO_3 _PIN(167) +#define CAPRI_PIN_RTXDATA2G_TXDATA3G1 _PIN(168) +#define CAPRI_PIN_RTXEN2G_TXDATA3G2 _PIN(169) +#define CAPRI_PIN_RXDATA3G0 _PIN(170) +#define CAPRI_PIN_RXDATA3G1 _PIN(171) +#define CAPRI_PIN_RXDATA3G2 _PIN(172) +#define CAPRI_PIN_SDIO1_CLK _PIN(173) +#define CAPRI_PIN_SDIO1_CMD _PIN(174) +#define CAPRI_PIN_SDIO1_DATA_0 _PIN(175) +#define CAPRI_PIN_SDIO1_DATA_1 _PIN(176) +#define CAPRI_PIN_SDIO1_DATA_2 _PIN(177) +#define CAPRI_PIN_SDIO1_DATA_3 _PIN(178) +#define CAPRI_PIN_SDIO4_CLK _PIN(179) +#define CAPRI_PIN_SDIO4_CMD _PIN(180) +#define CAPRI_PIN_SDIO4_DATA_0 _PIN(181) +#define CAPRI_PIN_SDIO4_DATA_1 _PIN(182) +#define CAPRI_PIN_SDIO4_DATA_2 _PIN(183) +#define CAPRI_PIN_SDIO4_DATA_3 _PIN(184) +#define CAPRI_PIN_SIM_CLK _PIN(185) +#define CAPRI_PIN_SIM_DATA _PIN(186) +#define CAPRI_PIN_SIM_DET _PIN(187) +#define CAPRI_PIN_SIM_RESETN _PIN(188) +#define CAPRI_PIN_SIM2_CLK _PIN(189) +#define CAPRI_PIN_SIM2_DATA _PIN(190) +#define CAPRI_PIN_SIM2_DET _PIN(191) +#define CAPRI_PIN_SIM2_RESETN _PIN(192) +#define CAPRI_PIN_SRI_C _PIN(193) +#define CAPRI_PIN_SRI_D _PIN(194) +#define CAPRI_PIN_SRI_E _PIN(195) +#define CAPRI_PIN_SSP_EXTCLK _PIN(196) +#define CAPRI_PIN_SSP0_CLK _PIN(197) +#define CAPRI_PIN_SSP0_FS _PIN(198) +#define CAPRI_PIN_SSP0_RXD _PIN(199) +#define CAPRI_PIN_SSP0_TXD _PIN(200) +#define CAPRI_PIN_SSP2_CLK _PIN(201) +#define CAPRI_PIN_SSP2_FS_0 _PIN(202) +#define CAPRI_PIN_SSP2_FS_1 _PIN(203) +#define CAPRI_PIN_SSP2_FS_2 _PIN(204) +#define CAPRI_PIN_SSP2_FS_3 _PIN(205) +#define CAPRI_PIN_SSP2_RXD_0 _PIN(206) +#define CAPRI_PIN_SSP2_RXD_1 _PIN(207) +#define CAPRI_PIN_SSP2_TXD_0 _PIN(208) +#define CAPRI_PIN_SSP2_TXD_1 _PIN(209) +#define CAPRI_PIN_SSP3_CLK _PIN(210) +#define CAPRI_PIN_SSP3_FS _PIN(211) +#define CAPRI_PIN_SSP3_RXD _PIN(212) +#define CAPRI_PIN_SSP3_TXD _PIN(213) +#define CAPRI_PIN_SSP4_CLK _PIN(214) +#define CAPRI_PIN_SSP4_FS _PIN(215) +#define CAPRI_PIN_SSP4_RXD _PIN(216) +#define CAPRI_PIN_SSP4_TXD _PIN(217) +#define CAPRI_PIN_SSP5_CLK _PIN(218) +#define CAPRI_PIN_SSP5_FS _PIN(219) +#define CAPRI_PIN_SSP5_RXD _PIN(220) +#define CAPRI_PIN_SSP5_TXD _PIN(221) +#define CAPRI_PIN_SSP6_CLK _PIN(222) +#define CAPRI_PIN_SSP6_FS _PIN(223) +#define CAPRI_PIN_SSP6_RXD _PIN(224) +#define CAPRI_PIN_SSP6_TXD _PIN(225) +#define CAPRI_PIN_STAT_1 _PIN(226) +#define CAPRI_PIN_STAT_2 _PIN(227) +#define CAPRI_PIN_SYSCLKEN _PIN(228) +#define CAPRI_PIN_TRACECLK _PIN(229) +#define CAPRI_PIN_TRACEDT00 _PIN(230) +#define CAPRI_PIN_TRACEDT01 _PIN(231) +#define CAPRI_PIN_TRACEDT02 _PIN(232) +#define CAPRI_PIN_TRACEDT03 _PIN(233) +#define CAPRI_PIN_TRACEDT04 _PIN(234) +#define CAPRI_PIN_TRACEDT05 _PIN(235) +#define CAPRI_PIN_TRACEDT06 _PIN(236) +#define CAPRI_PIN_TRACEDT07 _PIN(237) +#define CAPRI_PIN_TRACEDT08 _PIN(238) +#define CAPRI_PIN_TRACEDT09 _PIN(239) +#define CAPRI_PIN_TRACEDT10 _PIN(240) +#define CAPRI_PIN_TRACEDT11 _PIN(241) +#define CAPRI_PIN_TRACEDT12 _PIN(242) +#define CAPRI_PIN_TRACEDT13 _PIN(243) +#define CAPRI_PIN_TRACEDT14 _PIN(244) +#define CAPRI_PIN_TRACEDT15 _PIN(245) +#define CAPRI_PIN_TXDATA3G0 _PIN(246) +#define CAPRI_PIN_TXPWRIND _PIN(247) +#define CAPRI_PIN_UARTB1_UCTS _PIN(248) +#define CAPRI_PIN_UARTB1_URTS _PIN(249) +#define CAPRI_PIN_UARTB1_URXD _PIN(250) +#define CAPRI_PIN_UARTB1_UTXD _PIN(251) +#define CAPRI_PIN_UARTB2_URXD _PIN(252) +#define CAPRI_PIN_UARTB2_UTXD _PIN(253) +#define CAPRI_PIN_UARTB3_UCTS _PIN(254) +#define CAPRI_PIN_UARTB3_URTS _PIN(255) +#define CAPRI_PIN_UARTB3_URXD _PIN(256) +#define CAPRI_PIN_UARTB3_UTXD _PIN(257) +#define CAPRI_PIN_UARTB4_UCTS _PIN(258) +#define CAPRI_PIN_UARTB4_URTS _PIN(259) +#define CAPRI_PIN_UARTB4_URXD _PIN(260) +#define CAPRI_PIN_UARTB4_UTXD _PIN(261) +#define CAPRI_PIN_VC_CAM1_SCL _PIN(262) +#define CAPRI_PIN_VC_CAM1_SDA _PIN(263) +#define CAPRI_PIN_VC_CAM2_SCL _PIN(264) +#define CAPRI_PIN_VC_CAM2_SDA _PIN(265) +#define CAPRI_PIN_VC_CAM3_SCL _PIN(266) +#define CAPRI_PIN_VC_CAM3_SDA _PIN(267) + +#define CAPRI_PIN_DESC(a, b, c) \ + { .number = a, .name = b, .drv_data = &c##_pin } + +/* + * Pin description definition. The order here must be the same as defined in + * the PADCTRLREG block in the RDB, since the pin number is used as an index + * into this array. + */ +static const struct pinctrl_pin_desc capri_pinctrl_pins[] = { + CAPRI_PIN_DESC(CAPRI_PIN_ADCSYNC, "adcsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_BAT_RM, "bat_rm", std), + CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SCL, "bsc1_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SDA, "bsc1_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SCL, "bsc2_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SDA, "bsc2_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_CLASSGPWR, "classgpwr", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLK_CX8, "clk_cx8", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_0, "clkout_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_1, "clkout_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_2, "clkout_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_3, "clkout_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_0, "clkreq_in_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_1, "clkreq_in_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ1, "cws_sys_req1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ2, "cws_sys_req2", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ3, "cws_sys_req3", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_CLK, "digmic1_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_DQ, "digmic1_dq", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_CLK, "digmic2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_DQ, "digmic2_dq", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN13, "gpen13", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN14, "gpen14", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN15, "gpen15", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO00, "gpio00", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO01, "gpio01", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO02, "gpio02", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO03, "gpio03", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO04, "gpio04", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO05, "gpio05", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO06, "gpio06", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO07, "gpio07", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO08, "gpio08", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO09, "gpio09", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO10, "gpio10", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO11, "gpio11", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO12, "gpio12", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO13, "gpio13", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO14, "gpio14", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPS_PABLANK, "gps_pablank", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPS_TMARK, "gps_tmark", std), + CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SCL, "hdmi_scl", hdmi), + CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SDA, "hdmi_sda", hdmi), + CAPRI_PIN_DESC(CAPRI_PIN_IC_DM, "ic_dm", std), + CAPRI_PIN_DESC(CAPRI_PIN_IC_DP, "ic_dp", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_0, "kp_col_ip_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_1, "kp_col_ip_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_2, "kp_col_ip_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_3, "kp_col_ip_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_0, "kp_row_op_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_1, "kp_row_op_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_2, "kp_row_op_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_3, "kp_row_op_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_0, "lcd_b_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_1, "lcd_b_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_2, "lcd_b_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_3, "lcd_b_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_4, "lcd_b_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_5, "lcd_b_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_6, "lcd_b_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_7, "lcd_b_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_0, "lcd_g_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_1, "lcd_g_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_2, "lcd_g_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_3, "lcd_g_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_4, "lcd_g_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_5, "lcd_g_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_6, "lcd_g_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_7, "lcd_g_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_HSYNC, "lcd_hsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_OE, "lcd_oe", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_PCLK, "lcd_pclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_0, "lcd_r_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_1, "lcd_r_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_2, "lcd_r_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_3, "lcd_r_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_4, "lcd_r_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_5, "lcd_r_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_6, "lcd_r_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_7, "lcd_r_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_VSYNC, "lcd_vsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO0, "mdmgpio0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO1, "mdmgpio1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO2, "mdmgpio2", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO3, "mdmgpio3", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO4, "mdmgpio4", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO5, "mdmgpio5", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO6, "mdmgpio6", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO7, "mdmgpio7", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO8, "mdmgpio8", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_0, "mphi_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_1, "mphi_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_2, "mphi_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_3, "mphi_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_4, "mphi_data_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_5, "mphi_data_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_6, "mphi_data_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_7, "mphi_data_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_8, "mphi_data_8", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_9, "mphi_data_9", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_10, "mphi_data_10", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_11, "mphi_data_11", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_12, "mphi_data_12", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_13, "mphi_data_13", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_14, "mphi_data_14", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_15, "mphi_data_15", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HA0, "mphi_ha0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT0, "mphi_hat0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT1, "mphi_hat1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE0_N, "mphi_hce0_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE1_N, "mphi_hce1_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HRD_N, "mphi_hrd_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HWR_N, "mphi_hwr_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN0, "mphi_run0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN1, "mphi_run1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_DATA, "mtx_scan_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_0, "nand_ad_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_1, "nand_ad_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_2, "nand_ad_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_3, "nand_ad_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_4, "nand_ad_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_5, "nand_ad_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_6, "nand_ad_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_7, "nand_ad_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_ALE, "nand_ale", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_0, "nand_cen_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_1, "nand_cen_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CLE, "nand_cle", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_OEN, "nand_oen", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_0, "nand_rdy_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_1, "nand_rdy_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_WEN, "nand_wen", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_WP, "nand_wp", std), + CAPRI_PIN_DESC(CAPRI_PIN_PC1, "pc1", std), + CAPRI_PIN_DESC(CAPRI_PIN_PC2, "pc2", std), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_INT, "pmu_int", std), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_SCL, "pmu_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_SDA, "pmu_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXC, "rgmii_0_rxc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXC, "rgmii_0_txc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXC, "rgmii_1_rxc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXC, "rgmii_1_txc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RTXDATA2G_TXDATA3G1, "rtxdata2g_txdata3g1", + std), + CAPRI_PIN_DESC(CAPRI_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G0, "rxdata3g0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G1, "rxdata3g1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G2, "rxdata3g2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CLK, "sdio1_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CMD, "sdio1_cmd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_0, "sdio1_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_1, "sdio1_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_2, "sdio1_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_3, "sdio1_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CLK, "sdio4_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CMD, "sdio4_cmd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_0, "sdio4_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_1, "sdio4_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_2, "sdio4_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_3, "sdio4_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_CLK, "sim_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_DATA, "sim_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_DET, "sim_det", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_RESETN, "sim_resetn", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_CLK, "sim2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DATA, "sim2_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DET, "sim2_det", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_RESETN, "sim2_resetn", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_C, "sri_c", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_D, "sri_d", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_E, "sri_e", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP_EXTCLK, "ssp_extclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_CLK, "ssp0_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_FS, "ssp0_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_RXD, "ssp0_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_TXD, "ssp0_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_CLK, "ssp2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_0, "ssp2_fs_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_1, "ssp2_fs_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_2, "ssp2_fs_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_3, "ssp2_fs_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_0, "ssp2_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_1, "ssp2_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_0, "ssp2_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_1, "ssp2_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_CLK, "ssp3_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_FS, "ssp3_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_RXD, "ssp3_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_TXD, "ssp3_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_CLK, "ssp4_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_FS, "ssp4_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_RXD, "ssp4_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_TXD, "ssp4_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_CLK, "ssp5_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_FS, "ssp5_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_RXD, "ssp5_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_TXD, "ssp5_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_CLK, "ssp6_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_FS, "ssp6_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_RXD, "ssp6_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_TXD, "ssp6_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_STAT_1, "stat_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_STAT_2, "stat_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SYSCLKEN, "sysclken", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACECLK, "traceclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT00, "tracedt00", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT01, "tracedt01", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT02, "tracedt02", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT03, "tracedt03", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT04, "tracedt04", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT05, "tracedt05", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT06, "tracedt06", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT07, "tracedt07", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT08, "tracedt08", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT09, "tracedt09", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT10, "tracedt10", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT11, "tracedt11", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT12, "tracedt12", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT13, "tracedt13", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT14, "tracedt14", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT15, "tracedt15", std), + CAPRI_PIN_DESC(CAPRI_PIN_TXDATA3G0, "txdata3g0", std), + CAPRI_PIN_DESC(CAPRI_PIN_TXPWRIND, "txpwrind", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UCTS, "uartb1_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URTS, "uartb1_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URXD, "uartb1_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UTXD, "uartb1_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_URXD, "uartb2_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_UTXD, "uartb2_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UCTS, "uartb3_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URTS, "uartb3_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URXD, "uartb3_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UTXD, "uartb3_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UCTS, "uartb4_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URTS, "uartb4_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URXD, "uartb4_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UTXD, "uartb4_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c), +}; + +static const char * const capri_alt_groups[] = { + "adcsync", + "bat_rm", + "bsc1_scl", + "bsc1_sda", + "bsc2_scl", + "bsc2_sda", + "classgpwr", + "clk_cx8", + "clkout_0", + "clkout_1", + "clkout_2", + "clkout_3", + "clkreq_in_0", + "clkreq_in_1", + "cws_sys_req1", + "cws_sys_req2", + "cws_sys_req3", + "digmic1_clk", + "digmic1_dq", + "digmic2_clk", + "digmic2_dq", + "gpen13", + "gpen14", + "gpen15", + "gpio00", + "gpio01", + "gpio02", + "gpio03", + "gpio04", + "gpio05", + "gpio06", + "gpio07", + "gpio08", + "gpio09", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gps_pablank", + "gps_tmark", + "hdmi_scl", + "hdmi_sda", + "ic_dm", + "ic_dp", + "kp_col_ip_0", + "kp_col_ip_1", + "kp_col_ip_2", + "kp_col_ip_3", + "kp_row_op_0", + "kp_row_op_1", + "kp_row_op_2", + "kp_row_op_3", + "lcd_b_0", + "lcd_b_1", + "lcd_b_2", + "lcd_b_3", + "lcd_b_4", + "lcd_b_5", + "lcd_b_6", + "lcd_b_7", + "lcd_g_0", + "lcd_g_1", + "lcd_g_2", + "lcd_g_3", + "lcd_g_4", + "lcd_g_5", + "lcd_g_6", + "lcd_g_7", + "lcd_hsync", + "lcd_oe", + "lcd_pclk", + "lcd_r_0", + "lcd_r_1", + "lcd_r_2", + "lcd_r_3", + "lcd_r_4", + "lcd_r_5", + "lcd_r_6", + "lcd_r_7", + "lcd_vsync", + "mdmgpio0", + "mdmgpio1", + "mdmgpio2", + "mdmgpio3", + "mdmgpio4", + "mdmgpio5", + "mdmgpio6", + "mdmgpio7", + "mdmgpio8", + "mphi_data_0", + "mphi_data_1", + "mphi_data_2", + "mphi_data_3", + "mphi_data_4", + "mphi_data_5", + "mphi_data_6", + "mphi_data_7", + "mphi_data_8", + "mphi_data_9", + "mphi_data_10", + "mphi_data_11", + "mphi_data_12", + "mphi_data_13", + "mphi_data_14", + "mphi_data_15", + "mphi_ha0", + "mphi_hat0", + "mphi_hat1", + "mphi_hce0_n", + "mphi_hce1_n", + "mphi_hrd_n", + "mphi_hwr_n", + "mphi_run0", + "mphi_run1", + "mtx_scan_clk", + "mtx_scan_data", + "nand_ad_0", + "nand_ad_1", + "nand_ad_2", + "nand_ad_3", + "nand_ad_4", + "nand_ad_5", + "nand_ad_6", + "nand_ad_7", + "nand_ale", + "nand_cen_0", + "nand_cen_1", + "nand_cle", + "nand_oen", + "nand_rdy_0", + "nand_rdy_1", + "nand_wen", + "nand_wp", + "pc1", + "pc2", + "pmu_int", + "pmu_scl", + "pmu_sda", + "rfst2g_mtsloten3g", + "rgmii_0_rx_ctl", + "rgmii_0_rxc", + "rgmii_0_rxd_0", + "rgmii_0_rxd_1", + "rgmii_0_rxd_2", + "rgmii_0_rxd_3", + "rgmii_0_tx_ctl", + "rgmii_0_txc", + "rgmii_0_txd_0", + "rgmii_0_txd_1", + "rgmii_0_txd_2", + "rgmii_0_txd_3", + "rgmii_1_rx_ctl", + "rgmii_1_rxc", + "rgmii_1_rxd_0", + "rgmii_1_rxd_1", + "rgmii_1_rxd_2", + "rgmii_1_rxd_3", + "rgmii_1_tx_ctl", + "rgmii_1_txc", + "rgmii_1_txd_0", + "rgmii_1_txd_1", + "rgmii_1_txd_2", + "rgmii_1_txd_3", + "rgmii_gpio_0", + "rgmii_gpio_1", + "rgmii_gpio_2", + "rgmii_gpio_3", + "rtxdata2g_txdata3g1", + "rtxen2g_txdata3g2", + "rxdata3g0", + "rxdata3g1", + "rxdata3g2", + "sdio1_clk", + "sdio1_cmd", + "sdio1_data_0", + "sdio1_data_1", + "sdio1_data_2", + "sdio1_data_3", + "sdio4_clk", + "sdio4_cmd", + "sdio4_data_0", + "sdio4_data_1", + "sdio4_data_2", + "sdio4_data_3", + "sim_clk", + "sim_data", + "sim_det", + "sim_resetn", + "sim2_clk", + "sim2_data", + "sim2_det", + "sim2_resetn", + "sri_c", + "sri_d", + "sri_e", + "ssp_extclk", + "ssp0_clk", + "ssp0_fs", + "ssp0_rxd", + "ssp0_txd", + "ssp2_clk", + "ssp2_fs_0", + "ssp2_fs_1", + "ssp2_fs_2", + "ssp2_fs_3", + "ssp2_rxd_0", + "ssp2_rxd_1", + "ssp2_txd_0", + "ssp2_txd_1", + "ssp3_clk", + "ssp3_fs", + "ssp3_rxd", + "ssp3_txd", + "ssp4_clk", + "ssp4_fs", + "ssp4_rxd", + "ssp4_txd", + "ssp5_clk", + "ssp5_fs", + "ssp5_rxd", + "ssp5_txd", + "ssp6_clk", + "ssp6_fs", + "ssp6_rxd", + "ssp6_txd", + "stat_1", + "stat_2", + "sysclken", + "traceclk", + "tracedt00", + "tracedt01", + "tracedt02", + "tracedt03", + "tracedt04", + "tracedt05", + "tracedt06", + "tracedt07", + "tracedt08", + "tracedt09", + "tracedt10", + "tracedt11", + "tracedt12", + "tracedt13", + "tracedt14", + "tracedt15", + "txdata3g0", + "txpwrind", + "uartb1_ucts", + "uartb1_urts", + "uartb1_urxd", + "uartb1_utxd", + "uartb2_urxd", + "uartb2_utxd", + "uartb3_ucts", + "uartb3_urts", + "uartb3_urxd", + "uartb3_utxd", + "uartb4_ucts", + "uartb4_urts", + "uartb4_urxd", + "uartb4_utxd", + "vc_cam1_scl", + "vc_cam1_sda", + "vc_cam2_scl", + "vc_cam2_sda", + "vc_cam3_scl", + "vc_cam3_sda", +}; + +/* Every pin can implement all ALT1-ALT4 functions */ +#define CAPRI_PIN_FUNCTION(fcn_name) \ +{ \ + .name = #fcn_name, \ + .groups = capri_alt_groups, \ + .ngroups = ARRAY_SIZE(capri_alt_groups), \ +} + +static const struct capri_pin_function capri_functions[] = { + CAPRI_PIN_FUNCTION(alt1), + CAPRI_PIN_FUNCTION(alt2), + CAPRI_PIN_FUNCTION(alt3), + CAPRI_PIN_FUNCTION(alt4), +}; + +static struct capri_pinctrl_data capri_pinctrl = { + .pins = capri_pinctrl_pins, + .npins = ARRAY_SIZE(capri_pinctrl_pins), + .functions = capri_functions, + .nfunctions = ARRAY_SIZE(capri_functions), +}; + +static int capri_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->npins; +} + +static const char *capri_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->pins[group].name; +} + +static int capri_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pdata->pins[group].number; + *num_pins = 1; + + return 0; +} + +static void capri_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} + +static void capri_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned num_maps) +{ + int i; + + /* + * First free all the per-pin config arrays since they are dynamically + * allocated. + */ + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + + kfree(map); +} + +/** + * capri_resize_map - krealloc for pinctrl_map + * @pctldev: ptr to pinctrl_dev, for logging purposes + * @map: ptr to pinctrl_map array + * @nmaps: in - current size of pinctrl_map, out - new size of pinctrl_map + * @change: number of elements to expand/shrink pinctrl_map array by + * + * Shrinks or expands the existing pinctrl_map <maps> by <change> elements by + * memory reallocation. Sets the new elements to zero before returning. + * the new array is <nmaps + change> elements long. + */ +static int capri_resize_map(struct pinctrl_dev *pctldev, + struct pinctrl_map **map, + unsigned *nmaps, + int change) +{ + int old_num = *nmaps; + int new_num = old_num + change; + struct pinctrl_map *new_map; + + /* If no change, just return */ + if (!change) + goto resize_exit; + + /* New size should never be < 0 */ + if (new_num < 0) { + dev_warn(pctldev->dev, + "Negative size requested for pinctrl_map\n"); + new_num = 0; + } + + /* Shrink or expand map */ + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) { + dev_err(pctldev->dev, "No memory for new pinctrl mappings.\n"); + return -ENOMEM; + } + + /* Clear new maps */ + if (change > 0) + memset(new_map + old_num, 0, change * sizeof(*new_map)); + + *map = new_map; + *nmaps = new_num; + +resize_exit: + dev_dbg(pctldev->dev, "%s(): pinctrl_map size %d->%d\n", + __func__, old_num, new_num); + + return 0; +} + +/* Add a pinmux mapping for one pin */ +static int capri_dt_pinmux_to_map(struct pinctrl_dev *pctldev, + struct device_node *pnode, + struct pinctrl_map **map, + int *map_index, + int pin_count, + int pin_index, + const char *pin_name) +{ + int mux_count, index, ret; + const char *function = NULL; + + mux_count = of_property_count_strings(pnode, "brcm,function"); + + dev_dbg(pctldev->dev, "%s(): mux_count = %d\n", __func__, mux_count); + + if (mux_count <= 0) + /* Nothing to do, just return */ + return 0; + else if ((mux_count != 1) && (mux_count != pin_count)) { + dev_err(pctldev->dev, + "%s(): Invalid # of functions in DT node %s.\n", + __func__, pnode->name); + return -EINVAL; + } + + index = (mux_count == 1 ? 0 : pin_index); + + ret = of_property_read_string_index(pnode, + "brcm,function", + index, + &function); + if (ret < 0) { + dev_err(pctldev->dev, + "%s(): Error reading pinmux in node %s\n", + __func__, pnode->name); + return -EINVAL; + } + + /* + * dt_remember_or_free_map() will set the following members of + * struct pinctrl_map later: dev_name, name, ctrl_dev_name + */ + (*map)[*map_index].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*map_index].data.mux.group = pin_name; + (*map)[*map_index].data.mux.function = function; + + (*map_index)++; + + dev_dbg(pctldev->dev, "%s(): New pinmux mapping: %s->%s\n", + __func__, pin_name, function); + + return 0; +} + +/* Return the pin type for a given pin name */ +static enum capri_pin_type pin_type_get(struct pinctrl_dev *pctldev, + const char *pin_name) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + struct pinctrl_pin_desc const *desc; + int i; + + for (i = 0; i < pdata->npins; i++) { + desc = &pdata->pins[i]; + if (desc->name && !strcmp(pin_name, desc->name)) { + dev_dbg(pctldev->dev, + "%s(): Pin %s is pin number %d, type %d\n", + __func__, pin_name, desc->number, + *(enum capri_pin_type *)desc->drv_data); + + return *(enum capri_pin_type *)desc->drv_data; + } + } + + dev_warn(pctldev->dev, + "%s(): Cannot find pin named %s\n", + __func__, pin_name); + + return CAPRI_PIN_TYPE_UNKNOWN; +} + +static int capri_std_pin_update(struct pinctrl_dev *pctldev, + enum capri_pinconf_param param, + unsigned val, + u32 *reg_val, + u32 *reg_mask) +{ + switch (param) { + case CAPRI_PINCONF_PARAM_HYST: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Hysteresis.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, STD, HYST, val); + *reg_mask |= CAPRI_STD_PIN_REG_HYST_MASK; + break; + + case CAPRI_PINCONF_PARAM_PULL: + if (val > 3) { + dev_err(pctldev->dev, + "Invalid pin config for Pull up/down.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, STD, PULL, val); + *reg_mask |= CAPRI_STD_PIN_REG_PULL_MASK; + break; + + case CAPRI_PINCONF_PARAM_SLEW: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Slew Rate.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, STD, SLEW, val); + *reg_mask |= CAPRI_STD_PIN_REG_SLEW_MASK; + break; + + case CAPRI_PINCONF_PARAM_INPUT_DIS: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Input Disable.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, STD, INPUT_DIS, val); + *reg_mask |= CAPRI_STD_PIN_REG_INPUT_DIS_MASK; + break; + + case CAPRI_PINCONF_PARAM_DRV_STR: + /* Valid range is 2-16 mA, even numbers only */ + if ((val < 2) || (val > 16) || (val % 2)) { + dev_err(pctldev->dev, + "Invalid pin config for Drive Strength.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, STD, DRV_STR, (val/2)-1); + *reg_mask |= CAPRI_STD_PIN_REG_DRV_STR_MASK; + break; + + default: + dev_err(pctldev->dev, "Unrecognized pin config.\n"); + return -EINVAL; + + } /* switch config */ + + return 0; +} + +static int capri_i2c_pin_update(struct pinctrl_dev *pctldev, + enum capri_pinconf_param param, + unsigned val, + u32 *reg_val, + u32 *reg_mask) +{ + switch (param) { + case CAPRI_PINCONF_PARAM_PULL_UP_STR: + if (val > 7) { + dev_err(pctldev->dev, + "Invalid pin config for Pull Up Strength.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, I2C, PULL_UP_STR, val); + *reg_mask |= CAPRI_I2C_PIN_REG_PULL_UP_STR_MASK; + break; + + case CAPRI_PINCONF_PARAM_SLEW: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Slew Rate.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, I2C, SLEW, val); + *reg_mask |= CAPRI_I2C_PIN_REG_SLEW_MASK; + break; + + case CAPRI_PINCONF_PARAM_INPUT_DIS: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Input Disable.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, I2C, INPUT_DIS, val); + *reg_mask |= CAPRI_I2C_PIN_REG_INPUT_DIS_MASK; + break; + + default: + dev_err(pctldev->dev, "Unrecognized pin config.\n"); + return -EINVAL; + + } /* switch config */ + + return 0; +} + +static int capri_hdmi_pin_update(struct pinctrl_dev *pctldev, + enum capri_pinconf_param param, + unsigned val, + u32 *reg_val, + u32 *reg_mask) +{ + switch (param) { + case CAPRI_PINCONF_PARAM_MODE: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Mode.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, HDMI, MODE, val); + *reg_mask |= CAPRI_HDMI_PIN_REG_MODE_MASK; + break; + + case CAPRI_PINCONF_PARAM_INPUT_DIS: + if (val > 1) { + dev_err(pctldev->dev, + "Invalid pin config for Input Disable.\n"); + return -EINVAL; + } + *reg_val = CAPRI_PIN_REG_SET(*reg_val, HDMI, INPUT_DIS, val); + *reg_mask |= CAPRI_HDMI_PIN_REG_INPUT_DIS_MASK; + break; + + default: + dev_err(pctldev->dev, "Unrecognized pin config.\n"); + return -EINVAL; + + } /* switch config */ + + return 0; +} + +/** + * capri_dt_pincfg_to_map - Add a pincfg mapping for one pin + * @map_index - the index into the map array to write next + */ +static int capri_dt_pincfg_to_map(struct pinctrl_dev *pctldev, + struct device_node *pnode, + struct pinctrl_map **map, + int *map_index, + int pin_count, + int pin_index, + const char *pin_name) +{ + int val_count, prop_index, i, rc; + enum capri_pin_type pin_type; + unsigned long prop_val = 0; + u32 cfg_val, cfg_mask; + unsigned long *cfgs; + const struct capri_cfg_param *param; + struct property *prop; + + cfg_val = 0; + cfg_mask = 0; + + pin_type = pin_type_get(pctldev, pin_name); + if (pin_type == CAPRI_PIN_TYPE_UNKNOWN) + return -EINVAL; + + /* + * Loop through each of the defined pin config properties, and build + * cfg_val and cfg_mask as we go. cfg_val will be written straight to + * the pin config register when this pin config is applied. + */ + for (i = 0; i < ARRAY_SIZE(capri_pinconf_params); i++) { + param = &capri_pinconf_params[i]; + + /* TODO: replace with of_property_count_u32() */ + prop = of_find_property(pnode, param->property, NULL); + + if (!prop) + continue; + + val_count = prop->length / sizeof(u32); + + dev_dbg(pctldev->dev, "%s(): %d values for %s.\n", + __func__, val_count, param->property); + + if ((val_count != 1) && (val_count != pin_count)) { + dev_err(pctldev->dev, + "%s(): Invalid # of values for %s " + "in DT node %s\n", + __func__, param->property, pnode->name); + return -EINVAL; + } + + prop_index = (val_count == 1 ? 0 : pin_index); + + /* TODO: replace with of_property_read_u32_index() */ + prop_val = be32_to_cpup((u32 *)prop->value + prop_index); + + /* Different pins have different configuration options */ + switch (pin_type) { + case CAPRI_PIN_TYPE_STD: + rc = capri_std_pin_update(pctldev, + param->id, + prop_val, + &cfg_val, + &cfg_mask); + break; + + case CAPRI_PIN_TYPE_I2C: + rc = capri_i2c_pin_update(pctldev, + param->id, + prop_val, + &cfg_val, + &cfg_mask); + break; + + case CAPRI_PIN_TYPE_HDMI: + rc = capri_hdmi_pin_update(pctldev, + param->id, + prop_val, + &cfg_val, + &cfg_mask); + break; + + default: + dev_err(pctldev->dev, "Unknown pin type.\n"); + return -EINVAL; + + } /* switch pin type */ + + if (rc) { + dev_err(pctldev->dev, "Error setting pin config\n"); + return rc; + } + + dev_dbg(pctldev->dev, + "%s(): cfg_val=0x%x, cfg_mask=0x%x for pin %s\n", + __func__, cfg_val, cfg_mask, pin_name); + } /* for each defined pin config parameter */ + + /* + * In Capri, the top 16 bits of the pin control register are reserved, + * so we only need to set the lower 16 bits. Since the pinctrl core + * stores pin configs as an array of u32, we will pack the register + * value in the upper 16 bits and the mask in the lower 16 bits. + */ + cfgs = kmalloc(sizeof(unsigned long), GFP_KERNEL); + if (!cfgs) + return -ENOMEM; + + *cfgs = CAPRI_PINCONF_PACK(cfg_val, cfg_mask); + + /* + * dt_remember_or_free_map() will set the following members of + * struct pinctrl_map later: dev_name, name, ctrl_dev_name + */ + + dev_dbg(pctldev->dev, + "%s(): Add new pin conf map: config = 0x%lx for pin %s\n", + __func__, *cfgs, pin_name); + + (*map)[*map_index].type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)[*map_index].data.configs.group_or_pin = pin_name; + (*map)[*map_index].data.configs.configs = cfgs; + (*map)[*map_index].data.configs.num_configs = 1; + + (*map_index)++; + + return 0; +} + +/* Process the pin configuration node */ +static int capri_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *pnode, + struct pinctrl_map **map, + unsigned *nmaps) +{ + struct device_node *pchild; + int pin_count, pin_index, ret, map_index; + const char *pin_name; + struct property *prop; + + *map = NULL; + *nmaps = 0; + + /* Index of next spot to write in pinctrl_map array */ + map_index = 0; + + /* For each pin group */ + for_each_child_of_node(pnode, pchild) { + /* Requires at least 1 pin per group. */ + pin_count = of_property_count_strings(pchild, "brcm,pins"); + + dev_dbg(pctldev->dev, "%s(): Node %s configures %d pins.\n", + __func__, pchild->name, pin_count); + + if (pin_count <= 0) { + dev_err(pctldev->dev, + "%s(): No pins specified in DT node %s.\n", + __func__, pchild->name); + return -EINVAL; + } + + /* Pre-alloc a pinctrl_map array of size pin_count*2 */ + ret = capri_resize_map(pctldev, map, nmaps, pin_count * 2); + if (ret) + return ret; + + pin_index = 0; + + /* Create pin maps for each pin */ + of_property_for_each_string(pchild, + "brcm,pins", + prop, + pin_name) { + ret = capri_dt_pinmux_to_map(pctldev, + pchild, + map, + &map_index, + pin_count, + pin_index, + pin_name); + if (ret) + return ret; + + ret = capri_dt_pincfg_to_map(pctldev, + pchild, + map, + &map_index, + pin_count, + pin_index, + pin_name); + if (ret) + return ret; + dev_dbg(pctldev->dev, + "%s(): Done pin %s in, next map is %d\n", + __func__, pin_name, map_index); + pin_index++; + } /* for each pin */ + } /* for each group */ + + /* + * Clean up any over-allocated elements for the pinctrl_map array. This + * could be moved to the end of for each group loop, but it's probably + * more efficient here. + */ + if (map_index < *nmaps) { + ret = capri_resize_map(pctldev, map, nmaps, *nmaps-map_index); + if (ret) + return ret; + } + + return 0; +} + +static struct pinctrl_ops capri_pinctrl_ops = { + .get_groups_count = capri_pinctrl_get_groups_count, + .get_group_name = capri_pinctrl_get_group_name, + .get_group_pins = capri_pinctrl_get_group_pins, + .pin_dbg_show = capri_pinctrl_pin_dbg_show, + .dt_node_to_map = capri_pinctrl_dt_node_to_map, + .dt_free_map = capri_pinctrl_dt_free_map, +}; + +static int capri_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->nfunctions; +} + +static const char *capri_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->functions[function].name; +} + +static int capri_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *groups = pdata->functions[function].groups; + *num_groups = pdata->functions[function].ngroups; + + return 0; +} + +static int capri_pinmux_enable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + const struct capri_pin_function *f = &pdata->functions[function]; + void __iomem *reg = pdata->reg_base + (4 * pdata->pins[group].number); + u32 old_reg_val; + u32 new_reg_val; + + dev_dbg(pctldev->dev, + "%s(): Enable function %s (%d) of pin %s (%d) @reg 0x%p.\n", + __func__, f->name, function, pdata->pins[group].name, + pdata->pins[group].number, reg); + + old_reg_val = readl(reg); + new_reg_val = (old_reg_val & ~CAPRI_PIN_REG_F_SEL_MASK) + | ((function << CAPRI_PIN_REG_F_SEL_SHIFT) + & CAPRI_PIN_REG_F_SEL_MASK); + + if (new_reg_val != old_reg_val) { + dev_dbg(pctldev->dev, + "Reg 0x%p change from 0x%x to 0x%x\n", + reg, old_reg_val, new_reg_val); + writel(new_reg_val, reg); + } else + dev_dbg(pctldev->dev, + "Reg 0x%p=0x%x (no change)\n", + reg, old_reg_val); + + return 0; +} + +static struct pinmux_ops capri_pinctrl_pinmux_ops = { + .get_functions_count = capri_pinctrl_get_fcns_count, + .get_function_name = capri_pinctrl_get_fcn_name, + .get_function_groups = capri_pinctrl_get_fcn_groups, + .enable = capri_pinmux_enable, +}; + +static int capri_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + return -ENOTSUPP; +} + +static int capri_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + void __iomem *reg = pdata->reg_base + (4 * pin); + u32 old_reg_val; + u32 new_reg_val; + unsigned cfg_val, cfg_mask; + + /* + * This driver packs the pin config register value and mask into one + * 32 bit value, so it only expects 1 config. + */ + if ((num_configs != 1) || (!configs)) { + dev_err(pctldev->dev, + "Unable to set config pin %s - incorrect parameters", + pdata->pins[pin].name); + return -EPERM; + } + + cfg_val = CAPRI_PINCONF_UNPACK_VAL(*configs); + cfg_mask = CAPRI_PINCONF_UNPACK_MASK(*configs); + + dev_dbg(pctldev->dev, + "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n", + __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask); + + old_reg_val = readl(reg); + new_reg_val = (old_reg_val & ~cfg_mask) | cfg_val; + + if (new_reg_val != old_reg_val) { + dev_dbg(pctldev->dev, + "Reg 0x%p change from 0x%x to 0x%x\n", + reg, old_reg_val, new_reg_val); + writel(new_reg_val, reg); + } else + dev_dbg(pctldev->dev, + "Reg 0x%p=0x%x (no change)\n", + reg, old_reg_val); + + + return 0; +} + +static struct pinconf_ops capri_pinctrl_pinconf_ops = { + .pin_config_get = capri_pinctrl_pin_config_get, + .pin_config_set = capri_pinctrl_pin_config_set, +}; + +static struct pinctrl_desc capri_pinctrl_desc = { + /* name, pins, npins members initialized in probe function */ + .pctlops = &capri_pinctrl_ops, + .pmxops = &capri_pinctrl_pinmux_ops, + .confops = &capri_pinctrl_pinconf_ops, + .owner = THIS_MODULE, +}; + +int __init capri_pinctrl_probe(struct platform_device *pdev) +{ + struct capri_pinctrl_data *pdata = &capri_pinctrl; + struct resource *res; + struct pinctrl_dev *pctl; + + /* So far We can assume there is only 1 bank of registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Missing MEM resource\n"); + return -ENODEV; + } + + pdata->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pdata->reg_base)) { + dev_err(&pdev->dev, "Failed to ioremap MEM resource\n"); + return -ENODEV; + } + + /* Initialize the dynamic part of pinctrl_desc */ + capri_pinctrl_desc.name = dev_name(&pdev->dev); + capri_pinctrl_desc.pins = capri_pinctrl.pins; + capri_pinctrl_desc.npins = capri_pinctrl.npins; + + pctl = pinctrl_register(&capri_pinctrl_desc, + &pdev->dev, + pdata); + if (!pctl) { + dev_err(&pdev->dev, "Failed to register pinctrl\n"); + return -ENODEV; + } + + platform_set_drvdata(pdev, pdata); + + return 0; +} + +static struct of_device_id capri_pinctrl_of_match[] = { + { .compatible = "brcm,capri-pinctrl", }, + { }, +}; + +static struct platform_driver capri_pinctrl_driver = { + .driver = { + .name = "bcm-capri-pinctrl", + .owner = THIS_MODULE, + .of_match_table = capri_pinctrl_of_match, + }, +}; + +module_platform_driver_probe(capri_pinctrl_driver, capri_pinctrl_probe); + +MODULE_AUTHOR("Sherman Yin <syin@broadcom.com>"); +MODULE_DESCRIPTION("Broadcom Capri pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v2 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs 2013-10-07 19:28 ` [PATCH v2 0/4] Add Broadcom Capri pinctrl driver Sherman Yin ` (2 preceding siblings ...) 2013-10-07 19:28 ` [PATCH v2 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin @ 2013-10-07 19:28 ` Sherman Yin 2013-12-11 18:37 ` [PATCH v3 0/6] Add Broadcom Capri pinctrl driver Sherman Yin 4 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-10-07 19:28 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin Enable pinctrl for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- v2: Use hyphens instead of underscore in DT property names. --- arch/arm/boot/dts/bcm11351.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 05a5aab..f497a40 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -96,4 +96,8 @@ status = "disabled"; }; + pinctrl@35004800 { + compatible = "brcm,capri-pinctrl"; + reg = <0x35004800 0x430>; + }; }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v3 0/6] Add Broadcom Capri pinctrl driver 2013-10-07 19:28 ` [PATCH v2 0/4] Add Broadcom Capri pinctrl driver Sherman Yin ` (3 preceding siblings ...) 2013-10-07 19:28 ` [PATCH v2 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin @ 2013-12-11 18:37 ` Sherman Yin 2013-12-11 18:37 ` [PATCH v3 1/6] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin ` (6 more replies) 4 siblings, 7 replies; 85+ messages in thread From: Sherman Yin @ 2013-12-11 18:37 UTC (permalink / raw) To: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, Sherman Yin, bcm-kernel-feedback-list, linux-arm-kernel The following patches adds a pinctrl driver for Broadcom Capri (BCM281xx) SoCs. The first patch, adding the void * to pinctrl_pin_desc, has been previously discussed with LinusW. See this thread: http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/165880.html --- v3: Re-worked driver to be based on generic pinconfig, addressed review comments and other supporting changes: - moved config selection from Kconfig to defconfig - added slew-rate, input enable, input disable properties for generic pinconfig - added a description for PINCTRL config v2: Use hyphens instead of underscore in DT property names. Sherman Yin (6): pinctrl: Add void * to pinctrl_pin_desc pinctrl: Adds slew-rate, input-enable/disable pinctrl: Make PINCTRL selectable by defconfig/menuconfig pinctrl: Add pinctrl binding for Broadcom Capri SoCs ARM: pinctrl: Add Broadcom Capri pinctrl driver pinctrl: Enable pinctrl for Broadcom Capri SoCs .../bindings/pinctrl/brcm,capri-pinctrl.txt | 429 ++++++ .../bindings/pinctrl/pinctrl-bindings.txt | 3 + arch/arm/boot/dts/bcm11351.dtsi | 4 + arch/arm/configs/bcm_defconfig | 5 + drivers/pinctrl/Kconfig | 13 +- drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinconf-generic.c | 4 + drivers/pinctrl/pinctrl-capri.c | 1408 ++++++++++++++++++++ include/linux/pinctrl/pinconf-generic.h | 4 + include/linux/pinctrl/pinctrl.h | 2 + 10 files changed, 1872 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-capri.c -- 1.7.9.5 ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v3 1/6] pinctrl: Add void * to pinctrl_pin_desc 2013-12-11 18:37 ` [PATCH v3 0/6] Add Broadcom Capri pinctrl driver Sherman Yin @ 2013-12-11 18:37 ` Sherman Yin [not found] ` <1386787041-6035-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> ` (5 subsequent siblings) 6 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-12-11 18:37 UTC (permalink / raw) To: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin drv_data is added to the pinctrl_pin_desc for drivers to define additional driver-specific per-pin data. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- v3: no change v2: no change --- include/linux/pinctrl/pinctrl.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index fefb886..cc8e1af 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -32,10 +32,12 @@ struct device_node; * pins, pads or other muxable units in this struct * @number: unique pin number from the global pin number space * @name: a name for this pin + * @drv_data: driver-defined per-pin data. pinctrl core does not touch this */ struct pinctrl_pin_desc { unsigned number; const char *name; + void *drv_data; }; /* Convenience macro to define a single named or anonymous pin descriptor */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
[parent not found: <1386787041-6035-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>]
* [PATCH v3 2/6] pinctrl: Adds slew-rate, input-enable/disable [not found] ` <1386787041-6035-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2013-12-11 18:37 ` Sherman Yin 2013-12-12 20:41 ` Linus Walleij 2013-12-16 9:55 ` Linus Walleij 0 siblings, 2 replies; 85+ messages in thread From: Sherman Yin @ 2013-12-11 18:37 UTC (permalink / raw) To: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-doc-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sherman Yin This commit adds slew-rate and input-enable/disable support for pinconf -generic. Signed-off-by: Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> --- v3: added to patchset .../bindings/pinctrl/pinctrl-bindings.txt | 3 +++ drivers/pinctrl/pinconf-generic.c | 4 ++++ include/linux/pinctrl/pinconf-generic.h | 4 ++++ 3 files changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index 1958ca9..4414163 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -151,6 +151,8 @@ drive-push-pull - drive actively high and low drive-open-drain - drive with open drain drive-open-source - drive with open source drive-strength - sink or source at most X mA +input-enable - enable input on pin (no effect on output) +input-disable - disable input on pin (no effect on output) input-schmitt-enable - enable schmitt-trigger mode input-schmitt-disable - disable schmitt-trigger mode input-debounce - debounce mode with debound time X @@ -158,6 +160,7 @@ low-power-enable - enable low power mode low-power-disable - disable low power mode output-low - set the pin to output mode with low level output-high - set the pin to output mode with high level +slew-rate - set the slew rate Some of the generic properties take arguments. For those that do, the arguments are described below. diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 55a0ebe..3d9a999 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -48,6 +48,7 @@ static struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL), PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA"), + PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL), PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec"), @@ -160,6 +161,8 @@ static struct pinconf_generic_dt_params dt_params[] = { { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, @@ -167,6 +170,7 @@ static struct pinconf_generic_dt_params dt_params[] = { { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, { "output-low", PIN_CONFIG_OUTPUT, 0, }, { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0}, }; /** diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index fb90ef5..0db67bf 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -61,6 +61,9 @@ * argument is ignored. * @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current * passed as argument. The argument is in mA. + * @PIN_CONFIG_INPUT_ENABLE: enable the pin's input. Note that this does not + * affect the pin's ability to drive output. 1 enables input, 0 disables + * input. * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin. * If the argument != 0, schmitt-trigger mode is enabled. If it's 0, * schmitt-trigger mode is disabled. @@ -99,6 +102,7 @@ enum pin_config_param { PIN_CONFIG_DRIVE_OPEN_DRAIN, PIN_CONFIG_DRIVE_OPEN_SOURCE, PIN_CONFIG_DRIVE_STRENGTH, + PIN_CONFIG_INPUT_ENABLE, PIN_CONFIG_INPUT_SCHMITT_ENABLE, PIN_CONFIG_INPUT_SCHMITT, PIN_CONFIG_INPUT_DEBOUNCE, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v3 2/6] pinctrl: Adds slew-rate, input-enable/disable 2013-12-11 18:37 ` [PATCH v3 2/6] pinctrl: Adds slew-rate, input-enable/disable Sherman Yin @ 2013-12-12 20:41 ` Linus Walleij 2013-12-16 9:55 ` Linus Walleij 1 sibling, 0 replies; 85+ messages in thread From: Linus Walleij @ 2013-12-12 20:41 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Wed, Dec 11, 2013 at 7:37 PM, Sherman Yin <syin@broadcom.com> wrote: > This commit adds slew-rate and input-enable/disable support for pinconf > -generic. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > --- > v3: added to patchset I really like this patch and would like to apply it but I want to give the device tree people a few days to think about it. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 2/6] pinctrl: Adds slew-rate, input-enable/disable 2013-12-11 18:37 ` [PATCH v3 2/6] pinctrl: Adds slew-rate, input-enable/disable Sherman Yin 2013-12-12 20:41 ` Linus Walleij @ 2013-12-16 9:55 ` Linus Walleij 1 sibling, 0 replies; 85+ messages in thread From: Linus Walleij @ 2013-12-16 9:55 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Wed, Dec 11, 2013 at 7:37 PM, Sherman Yin <syin@broadcom.com> wrote: > This commit adds slew-rate and input-enable/disable support for pinconf > -generic. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > --- > v3: added to patchset Patch applied. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig 2013-12-11 18:37 ` [PATCH v3 0/6] Add Broadcom Capri pinctrl driver Sherman Yin 2013-12-11 18:37 ` [PATCH v3 1/6] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin [not found] ` <1386787041-6035-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2013-12-11 18:37 ` Sherman Yin 2013-12-12 20:39 ` Linus Walleij 2013-12-11 18:37 ` [PATCH v3 4/6] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin ` (3 subsequent siblings) 6 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-12-11 18:37 UTC (permalink / raw) To: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, Sherman Yin, bcm-kernel-feedback-list, linux-arm-kernel Adds a string to the PINCTRL config option so that 1) CONFIG_PINCTRL=y would not be erased by make config, and 2) PINCTRL option would show up in menuconfig. Signed-off-by: Sherman Yin <syin@broadcom.com> --- v3: added to patchset drivers/pinctrl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 33f9dc1..a921ff1 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -3,7 +3,7 @@ # config PINCTRL - bool + bool "Enable the pinctrl framework" if PINCTRL -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig 2013-12-11 18:37 ` [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig Sherman Yin @ 2013-12-12 20:39 ` Linus Walleij 2013-12-12 21:35 ` Christian Daudt 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-12-12 20:39 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Wed, Dec 11, 2013 at 7:37 PM, Sherman Yin <syin@broadcom.com> wrote: > Adds a string to the PINCTRL config option so that 1) CONFIG_PINCTRL=y would > not be erased by make config, and 2) PINCTRL option would show up in menuconfig. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > --- > v3: added to patchset NAK. The pin control subsystem has been designed so that you should select the pin controller through select statements from the SoC using it. This was requested at one time by Linus (Torvalds). You need to convince me that this is really needed. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig 2013-12-12 20:39 ` Linus Walleij @ 2013-12-12 21:35 ` Christian Daudt 2013-12-16 10:01 ` Linus Walleij 0 siblings, 1 reply; 85+ messages in thread From: Christian Daudt @ 2013-12-12 21:35 UTC (permalink / raw) To: Linus Walleij Cc: Sherman Yin, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Thu, Dec 12, 2013 at 12:39 PM, Linus Walleij <linus.walleij@linaro.org> wrote: > On Wed, Dec 11, 2013 at 7:37 PM, Sherman Yin <syin@broadcom.com> wrote: > >> Adds a string to the PINCTRL config option so that 1) CONFIG_PINCTRL=y would >> not be erased by make config, and 2) PINCTRL option would show up in menuconfig. >> >> Signed-off-by: Sherman Yin <syin@broadcom.com> >> --- >> v3: added to patchset > > NAK. The pin control subsystem has been designed so that > you should select the pin controller through select statements > from the SoC using it. > > This was requested at one time by Linus (Torvalds). > > You need to convince me that this is really needed. > > Yours, > Linus Walleij Hi Linus, I had requested this from Sherman. The reason is so that pinctrl can be selectable through defconfig, instead of through SoC select statements. And the reason for that is so that, in the future, some of these can be switched into loadable modules (which can't be done from Kconfig). This will become necessary with the move to multiplatform - we won't be able to have everything static anymore. Thanks, csd ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig 2013-12-12 21:35 ` Christian Daudt @ 2013-12-16 10:01 ` Linus Walleij [not found] ` <CACRpkdY2BExGiL6HBg7zn_szJQMnSNsxOSuo7RyrRmrz=cVe2A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-12-16 10:01 UTC (permalink / raw) To: Christian Daudt Cc: Mark Rutland, devicetree@vger.kernel.org, Russell King, Heiko Stübner, Pawel Moll, Stephen Warren, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, Sherman Yin, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org, Bjorn Andersson On Thu, Dec 12, 2013 at 10:35 PM, Christian Daudt <bcm@fixthebug.org> wrote: > I had requested this from Sherman. The reason is so that pinctrl can > be selectable through defconfig, instead of through SoC select > statements. And the reason for that is so that, in the future, some of > these can be switched into loadable modules (which can't be done from > Kconfig). This will become necessary with the move to multiplatform - > we won't be able to have everything static anymore. Isn't it sufficient to make the pin controller entry tristate rather than bool? And as mentioned elsewhere this does not at all solve the issue that we still need to have all basic IRQchips and timer drivers compiled into the kernel. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <CACRpkdY2BExGiL6HBg7zn_szJQMnSNsxOSuo7RyrRmrz=cVe2A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig [not found] ` <CACRpkdY2BExGiL6HBg7zn_szJQMnSNsxOSuo7RyrRmrz=cVe2A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2013-12-17 0:18 ` Bjorn Andersson 2013-12-20 9:37 ` Linus Walleij 0 siblings, 1 reply; 85+ messages in thread From: Bjorn Andersson @ 2013-12-17 0:18 UTC (permalink / raw) To: Linus Walleij Cc: Christian Daudt, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King, Heiko St?bner, Pawel Moll, Stephen Warren, Ian Campbell, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring, Sherman Yin, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Mon 16 Dec 02:01 PST 2013, Linus Walleij wrote: > On Thu, Dec 12, 2013 at 10:35 PM, Christian Daudt <bcm-xK7y4jjYLqYh9ZMKESR00Q@public.gmane.org> wrote: > > > I had requested this from Sherman. The reason is so that pinctrl can > > be selectable through defconfig, instead of through SoC select > > statements. And the reason for that is so that, in the future, some of > > these can be switched into loadable modules (which can't be done from > > Kconfig). This will become necessary with the move to multiplatform - > > we won't be able to have everything static anymore. > > Isn't it sufficient to make the pin controller entry tristate rather > than bool? > > And as mentioned elsewhere this does not at all solve the issue > that we still need to have all basic IRQchips and timer drivers > compiled into the kernel. No matter how we build the individual pinctrl drivers we will always need the pinctrl framework in a multi-soc zImage; so I can't see that we gain anything from being able to compile PINCTRL as a module. I don't like compiling the individual pinctrl drivers as modules, as it leaves us with a waterfall of PROBE_DEFERRs. Regards, Bjorn -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig 2013-12-17 0:18 ` Bjorn Andersson @ 2013-12-20 9:37 ` Linus Walleij 2013-12-20 20:58 ` Arnd Bergmann 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-12-20 9:37 UTC (permalink / raw) To: Bjorn Andersson, Arnd Bergmann Cc: Christian Daudt, Mark Rutland, devicetree@vger.kernel.org, Russell King, Heiko St?bner, Pawel Moll, Stephen Warren, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, Sherman Yin, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On Tue, Dec 17, 2013 at 1:18 AM, Bjorn Andersson <bjorn.andersson@sonymobile.com> wrote: > No matter how we build the individual pinctrl drivers we will always > need the pinctrl framework in a multi-soc zImage; so I can't see that > we gain anything from being able to compile PINCTRL as a module. I discussed this matter with Christian on IRC and I believe we could basically do "select PINCTRL" on ARCH_MULTIPLATFORM as the vast majority of multiplatforms appear to be using this anyway, this would make the submenu for pin control pop up in menuconfig for this, and make it possible to move different subdrivers to modules if desired. MULTIPLATFORM does not seem to be about saving footprint bytes on a very fine-granular level anyway, more about doing the module loading/unloading approach to footprint. (That drivers such as clk, regulator, pin control, GPIO, irqchip are usually impossible to rmmod as their tentacles will invariably be in all drivers everywhere is another issue, but this approach will solve modular *loading* atleast.) Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig 2013-12-20 9:37 ` Linus Walleij @ 2013-12-20 20:58 ` Arnd Bergmann 2013-12-21 2:15 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Arnd Bergmann @ 2013-12-20 20:58 UTC (permalink / raw) To: Linus Walleij Cc: Mark Rutland, devicetree@vger.kernel.org, Ian Campbell, Russell King, Heiko St?bner, Pawel Moll, Stephen Warren, Christian Daudt, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, Sherman Yin, bcm-kernel-feedback-list, Rob Landley, Bjorn Andersson, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On Friday 20 December 2013, Linus Walleij wrote: > On Tue, Dec 17, 2013 at 1:18 AM, Bjorn Andersson > <bjorn.andersson@sonymobile.com> wrote: > > > No matter how we build the individual pinctrl drivers we will always > > need the pinctrl framework in a multi-soc zImage; so I can't see that > > we gain anything from being able to compile PINCTRL as a module. > > I discussed this matter with Christian on IRC and I believe we could > basically do "select PINCTRL" on ARCH_MULTIPLATFORM as the > vast majority of multiplatforms appear to be using this anyway, this > would make the submenu for pin control pop up in menuconfig > for this, and make it possible to move different subdrivers to modules > if desired. > > MULTIPLATFORM does not seem to be about saving footprint bytes > on a very fine-granular level anyway, more about doing the module > loading/unloading approach to footprint. Let's review the list of platforms that don't select PINCTRL. There are some platforms that are indeed sensitive about memory footprint, and I promised people that converting to multiplatform won't cause a significant increase in kernel binary size as long as no other platforms are enabled. Arnd ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig 2013-12-20 20:58 ` Arnd Bergmann @ 2013-12-21 2:15 ` Sherman Yin 0 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-12-21 2:15 UTC (permalink / raw) To: Arnd Bergmann, Linus Walleij Cc: Bjorn Andersson, Christian Daudt, Mark Rutland, devicetree@vger.kernel.org, Russell King, Heiko St?bner, Pawel Moll, Stephen Warren, Ian Campbell, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On 13-12-20 12:58 PM, Arnd Bergmann wrote: > On Friday 20 December 2013, Linus Walleij wrote: >> On Tue, Dec 17, 2013 at 1:18 AM, Bjorn Andersson >> <bjorn.andersson@sonymobile.com> wrote: >> >>> No matter how we build the individual pinctrl drivers we will always >>> need the pinctrl framework in a multi-soc zImage; so I can't see that >>> we gain anything from being able to compile PINCTRL as a module. >> >> I discussed this matter with Christian on IRC and I believe we could >> basically do "select PINCTRL" on ARCH_MULTIPLATFORM as the >> vast majority of multiplatforms appear to be using this anyway, this >> would make the submenu for pin control pop up in menuconfig >> for this, and make it possible to move different subdrivers to modules >> if desired. >> >> MULTIPLATFORM does not seem to be about saving footprint bytes >> on a very fine-granular level anyway, more about doing the module >> loading/unloading approach to footprint. > > Let's review the list of platforms that don't select PINCTRL. There > are some platforms that are indeed sensitive about memory footprint, > and I promised people that converting to multiplatform won't cause > a significant increase in kernel binary size as long as no other > platforms are enabled. > > Arnd > Ok, for this driver, I'll just select PINCTRL under the ARCH_BCM_MOBILE. We can move this to ARCH_MULTIPLATFORM once we're sure this is okay for other platforms. Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v3 4/6] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2013-12-11 18:37 ` [PATCH v3 0/6] Add Broadcom Capri pinctrl driver Sherman Yin ` (2 preceding siblings ...) 2013-12-11 18:37 ` [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig Sherman Yin @ 2013-12-11 18:37 ` Sherman Yin 2013-12-12 20:37 ` Linus Walleij 2013-12-11 18:37 ` [PATCH v3 5/6] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin ` (2 subsequent siblings) 6 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-12-11 18:37 UTC (permalink / raw) To: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, Sherman Yin, bcm-kernel-feedback-list, linux-arm-kernel Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- v3: Use generic pin config properties instead of brcm-specific ones. Clarified pin types (standard, i2c, hdmi). v2: Use hyphens instead of underscore in DT property names. --- .../bindings/pinctrl/brcm,capri-pinctrl.txt | 429 ++++++++++++++++++++ 1 file changed, 429 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt new file mode 100644 index 0000000..7973cbd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt @@ -0,0 +1,429 @@ +Broadcom Capri Pin Controller + +This is a pin controller for the Broadcom BCM281xx SoC family, which includes +BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs. + +=== Pin Controller Node === + +Required Properties: + +- compatible: Must be "brcm,capri-pinctrl". +- reg: Base address of the PAD Controller register block and the size + of the block. + +For example, the following is the bare minimum node: + + pinctrl@35004800 { + compatible = "brcm,capri-pinctrl"; + reg = <0x35004800 0x430>; + }; + +As a pin controller device, in addition to the required properties, this node +should also contain the pin configuration nodes that client devices reference, +if any. + +=== Pin Configuration Node === + +Each pin configuration node is a sub-node of the pin controller node and is a +container of an arbitrary number of subnodes, called pin group nodes in this +document. + +Please refer to the pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the definition of a +"pin configuration node". + +=== Pin Group Node === + +A pin group node specifies the desired pin mux and/or pin configuration for an +arbitrary number of pins. The name of the pin group node is optional and not +used. + +A pin group node only affects the properties specified in the node, and has no +effect on any properties that are omitted. + +The pin group node accepts a subset of the generic pin config properties. For +details generic pin config properties, please refer to pinctrl-bindings.txt +and <include/linux/pinctrl/pinconfig-generic.h>. + +Each pin controlled by this pin controller belong to one of three types: +Standard, I2C, and HDMI. Each type accepts a different set of pin config +properties. A list of pins and their types is provided below. + +Required Properties (applicable to all pins): + +- pins: Multiple strings. Specifies the name(s) of one or more pins to + be configured by this node. + +Optional Properties (for standard pins): + +- function: String. Specifies the pin mux selection. Values + must be one of: "alt1", "alt2", "alt3", "alt4" +- input-schmitt-enable: No arguments. Enable schmitt-trigger mode. +- input-schmitt-disable: No arguments. Disable schmitt-trigger mode. +- bias-pull-up: No arguments. Pull up on pin. +- bias-pull-down: No arguments. Pull down on pin. +- bias-disable: No arguments. Disable pin bias. +- slew-rate: Integer. Meaning depends on configured pin mux: + *_SCL or *_SDA: + 0: Standard(100kbps)& Fast(400kbps) mode + 1: Highspeed (3.4Mbps) mode + IC_DM or IC_DP: + 0: normal slew rate + 1: fast slew rate + Otherwise: + 0: fast slew rate + 1: normal slew rate +- input-enable: No arguements. Enable input (does not affect + output.) +- input-disable: No arguements. Disable input (does not affect + output.) +- drive-strength: Integer. Drive strength in mA. Valid values are + 2, 4, 6, 8, 10, 12, 14, 16 mA. + +Optional Properties (for I2C pins): + +- function: String. Specifies the pin mux selection. Values + must be one of: "alt1", "alt2", "alt3", "alt4" +- bias-pull-up: Integer. Pull up strength in Ohm: + 1: 1.2 kOhm + 2: 1.8 kOhm + 3: 720 Ohm + 4: 2.7 kOhm + 5: 831 Ohm + 6: 1.08 kOhm + 7: 568 Ohm +- bias-disable: No arguments. Disable pin bias. +- slew-rate: Integer. Meaning depends on configured pin mux: + *_SCL or *_SDA: + 0: Standard(100kbps)& Fast(400kbps) mode + 1: Highspeed (3.4Mbps) mode + IC_DM or IC_DP: + 0: normal slew rate + 1: fast slew rate + Otherwise: + 0: fast slew rate + 1: normal slew rate +- input-enable: No arguements. Enable input (does not affect + output.) +- input-disable: No arguements. Disable input (does not affect + output.) + +Optional Properties (for HDMI pins): + +- function: String. Specifies the pin mux selection. Values + must be one of: "alt1", "alt2", "alt3", "alt4" +- slew-rate: Integer. Controls slew rate. + 0: Standard(100kbps)& Fast(400kbps) mode + 1: Highspeed (3.4Mbps) mode +- input-enable: No arguements. Enable input (does not affect + output.) +- input-disable: No arguements. Disable input (does not affect + output.) + +Example: +// pin controller node +pinctrl@35004800 { + compatible = "brcm,capri-pinctrl"; + reg = <0x35004800 0x430>; + + // pin configuration node + dev_a_default: dev_a_active { + //group node + grp_1 { + pins = "pin1", "pin2", "pin3"; + function = "alt1"; + drive-strength = <4>; + slew-rate = <1>; + }; + + grp_2 { + ... + }; + + // other pin group nodes + ... + }; + + // other pin configuration nodes + ... +}; + +In the example above, "dev_a_active" is a pin configuration node with a number +of sub-nodes. In the pin group node "grp_1", 3 pins are defined in the +"pins" property. Thus, the remaining properties in the "grp_1" node applies to +these 3 pins, including setting the pinmux to "alt1", setting the drive strength +to 4 mA, and seting the slew rate to normal. No other properties are sepcified, +implying no changes to any other parameters for these pins. + +=== Pin Names and Type === + +The following are valid pin names and their pin types: + + "adcsync", Standard + "bat_rm", Standard + "bsc1_scl", I2C + "bsc1_sda", I2C + "bsc2_scl", I2C + "bsc2_sda", I2C + "classgpwr", Standard + "clk_cx8", Standard + "clkout_0", Standard + "clkout_1", Standard + "clkout_2", Standard + "clkout_3", Standard + "clkreq_in_0", Standard + "clkreq_in_1", Standard + "cws_sys_req1", Standard + "cws_sys_req2", Standard + "cws_sys_req3", Standard + "digmic1_clk", Standard + "digmic1_dq", Standard + "digmic2_clk", Standard + "digmic2_dq", Standard + "gpen13", Standard + "gpen14", Standard + "gpen15", Standard + "gpio00", Standard + "gpio01", Standard + "gpio02", Standard + "gpio03", Standard + "gpio04", Standard + "gpio05", Standard + "gpio06", Standard + "gpio07", Standard + "gpio08", Standard + "gpio09", Standard + "gpio10", Standard + "gpio11", Standard + "gpio12", Standard + "gpio13", Standard + "gpio14", Standard + "gps_pablank", Standard + "gps_tmark", Standard + "hdmi_scl", HDMI + "hdmi_sda", HDMI + "ic_dm", Standard + "ic_dp", Standard + "kp_col_ip_0", Standard + "kp_col_ip_1", Standard + "kp_col_ip_2", Standard + "kp_col_ip_3", Standard + "kp_row_op_0", Standard + "kp_row_op_1", Standard + "kp_row_op_2", Standard + "kp_row_op_3", Standard + "lcd_b_0", Standard + "lcd_b_1", Standard + "lcd_b_2", Standard + "lcd_b_3", Standard + "lcd_b_4", Standard + "lcd_b_5", Standard + "lcd_b_6", Standard + "lcd_b_7", Standard + "lcd_g_0", Standard + "lcd_g_1", Standard + "lcd_g_2", Standard + "lcd_g_3", Standard + "lcd_g_4", Standard + "lcd_g_5", Standard + "lcd_g_6", Standard + "lcd_g_7", Standard + "lcd_hsync", Standard + "lcd_oe", Standard + "lcd_pclk", Standard + "lcd_r_0", Standard + "lcd_r_1", Standard + "lcd_r_2", Standard + "lcd_r_3", Standard + "lcd_r_4", Standard + "lcd_r_5", Standard + "lcd_r_6", Standard + "lcd_r_7", Standard + "lcd_vsync", Standard + "mdmgpio0", Standard + "mdmgpio1", Standard + "mdmgpio2", Standard + "mdmgpio3", Standard + "mdmgpio4", Standard + "mdmgpio5", Standard + "mdmgpio6", Standard + "mdmgpio7", Standard + "mdmgpio8", Standard + "mphi_data_0", Standard + "mphi_data_1", Standard + "mphi_data_2", Standard + "mphi_data_3", Standard + "mphi_data_4", Standard + "mphi_data_5", Standard + "mphi_data_6", Standard + "mphi_data_7", Standard + "mphi_data_8", Standard + "mphi_data_9", Standard + "mphi_data_10", Standard + "mphi_data_11", Standard + "mphi_data_12", Standard + "mphi_data_13", Standard + "mphi_data_14", Standard + "mphi_data_15", Standard + "mphi_ha0", Standard + "mphi_hat0", Standard + "mphi_hat1", Standard + "mphi_hce0_n", Standard + "mphi_hce1_n", Standard + "mphi_hrd_n", Standard + "mphi_hwr_n", Standard + "mphi_run0", Standard + "mphi_run1", Standard + "mtx_scan_clk", Standard + "mtx_scan_data", Standard + "nand_ad_0", Standard + "nand_ad_1", Standard + "nand_ad_2", Standard + "nand_ad_3", Standard + "nand_ad_4", Standard + "nand_ad_5", Standard + "nand_ad_6", Standard + "nand_ad_7", Standard + "nand_ale", Standard + "nand_cen_0", Standard + "nand_cen_1", Standard + "nand_cle", Standard + "nand_oen", Standard + "nand_rdy_0", Standard + "nand_rdy_1", Standard + "nand_wen", Standard + "nand_wp", Standard + "pc1", Standard + "pc2", Standard + "pmu_int", Standard + "pmu_scl", I2C + "pmu_sda", I2C + "rfst2g_mtsloten3g", Standard + "rgmii_0_rx_ctl", Standard + "rgmii_0_rxc", Standard + "rgmii_0_rxd_0", Standard + "rgmii_0_rxd_1", Standard + "rgmii_0_rxd_2", Standard + "rgmii_0_rxd_3", Standard + "rgmii_0_tx_ctl", Standard + "rgmii_0_txc", Standard + "rgmii_0_txd_0", Standard + "rgmii_0_txd_1", Standard + "rgmii_0_txd_2", Standard + "rgmii_0_txd_3", Standard + "rgmii_1_rx_ctl", Standard + "rgmii_1_rxc", Standard + "rgmii_1_rxd_0", Standard + "rgmii_1_rxd_1", Standard + "rgmii_1_rxd_2", Standard + "rgmii_1_rxd_3", Standard + "rgmii_1_tx_ctl", Standard + "rgmii_1_txc", Standard + "rgmii_1_txd_0", Standard + "rgmii_1_txd_1", Standard + "rgmii_1_txd_2", Standard + "rgmii_1_txd_3", Standard + "rgmii_gpio_0", Standard + "rgmii_gpio_1", Standard + "rgmii_gpio_2", Standard + "rgmii_gpio_3", Standard + "rtxdata2g_txdata3g1", Standard + "rtxen2g_txdata3g2", Standard + "rxdata3g0", Standard + "rxdata3g1", Standard + "rxdata3g2", Standard + "sdio1_clk", Standard + "sdio1_cmd", Standard + "sdio1_data_0", Standard + "sdio1_data_1", Standard + "sdio1_data_2", Standard + "sdio1_data_3", Standard + "sdio4_clk", Standard + "sdio4_cmd", Standard + "sdio4_data_0", Standard + "sdio4_data_1", Standard + "sdio4_data_2", Standard + "sdio4_data_3", Standard + "sim_clk", Standard + "sim_data", Standard + "sim_det", Standard + "sim_resetn", Standard + "sim2_clk", Standard + "sim2_data", Standard + "sim2_det", Standard + "sim2_resetn", Standard + "sri_c", Standard + "sri_d", Standard + "sri_e", Standard + "ssp_extclk", Standard + "ssp0_clk", Standard + "ssp0_fs", Standard + "ssp0_rxd", Standard + "ssp0_txd", Standard + "ssp2_clk", Standard + "ssp2_fs_0", Standard + "ssp2_fs_1", Standard + "ssp2_fs_2", Standard + "ssp2_fs_3", Standard + "ssp2_rxd_0", Standard + "ssp2_rxd_1", Standard + "ssp2_txd_0", Standard + "ssp2_txd_1", Standard + "ssp3_clk", Standard + "ssp3_fs", Standard + "ssp3_rxd", Standard + "ssp3_txd", Standard + "ssp4_clk", Standard + "ssp4_fs", Standard + "ssp4_rxd", Standard + "ssp4_txd", Standard + "ssp5_clk", Standard + "ssp5_fs", Standard + "ssp5_rxd", Standard + "ssp5_txd", Standard + "ssp6_clk", Standard + "ssp6_fs", Standard + "ssp6_rxd", Standard + "ssp6_txd", Standard + "stat_1", Standard + "stat_2", Standard + "sysclken", Standard + "traceclk", Standard + "tracedt00", Standard + "tracedt01", Standard + "tracedt02", Standard + "tracedt03", Standard + "tracedt04", Standard + "tracedt05", Standard + "tracedt06", Standard + "tracedt07", Standard + "tracedt08", Standard + "tracedt09", Standard + "tracedt10", Standard + "tracedt11", Standard + "tracedt12", Standard + "tracedt13", Standard + "tracedt14", Standard + "tracedt15", Standard + "txdata3g0", Standard + "txpwrind", Standard + "uartb1_ucts", Standard + "uartb1_urts", Standard + "uartb1_urxd", Standard + "uartb1_utxd", Standard + "uartb2_urxd", Standard + "uartb2_utxd", Standard + "uartb3_ucts", Standard + "uartb3_urts", Standard + "uartb3_urxd", Standard + "uartb3_utxd", Standard + "uartb4_ucts", Standard + "uartb4_urts", Standard + "uartb4_urxd", Standard + "uartb4_utxd", Standard + "vc_cam1_scl", I2C + "vc_cam1_sda", I2C + "vc_cam2_scl", I2C + "vc_cam2_sda", I2C + "vc_cam3_scl", I2C + "vc_cam3_sda", I2C -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v3 4/6] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2013-12-11 18:37 ` [PATCH v3 4/6] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin @ 2013-12-12 20:37 ` Linus Walleij 2013-12-14 1:16 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-12-12 20:37 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Wed, Dec 11, 2013 at 7:37 PM, Sherman Yin <syin@broadcom.com> wrote: > Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > Reviewed-by: Christian Daudt <bcm@fixthebug.org> > Reviewed-by: Matt Porter <matt.porter@linaro.org> > --- > v3: Use generic pin config properties instead of brcm-specific ones. Clarified > pin types (standard, i2c, hdmi). > v2: Use hyphens instead of underscore in DT property names. Overall this is very nice! > +- bias-pull-up: Integer. Pull up strength in Ohm: > + 1: 1.2 kOhm > + 2: 1.8 kOhm > + 3: 720 Ohm > + 4: 2.7 kOhm > + 5: 831 Ohm > + 6: 1.08 kOhm > + 7: 568 Ohm Please do not use these custom enumerators 1 thru 7. Instead say that the argument is given in ohms, so for example: bias-pull-up = <12000>; Then translate this into the proper enumerator in your driver instead. No full example provided in the binding! This needs to be there for understanding. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 4/6] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2013-12-12 20:37 ` Linus Walleij @ 2013-12-14 1:16 ` Sherman Yin 2013-12-16 13:17 ` Linus Walleij 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-12-14 1:16 UTC (permalink / raw) To: Linus Walleij Cc: Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Heiko Stübner, Pawel Moll, Ian Campbell, Stephen Warren, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On 13-12-12 12:37 PM, Linus Walleij wrote: > On Wed, Dec 11, 2013 at 7:37 PM, Sherman Yin <syin@broadcom.com> wrote: > >> Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. >> >> Signed-off-by: Sherman Yin <syin@broadcom.com> >> Reviewed-by: Christian Daudt <bcm@fixthebug.org> >> Reviewed-by: Matt Porter <matt.porter@linaro.org> >> --- >> v3: Use generic pin config properties instead of brcm-specific ones. Clarified >> pin types (standard, i2c, hdmi). >> v2: Use hyphens instead of underscore in DT property names. > > Overall this is very nice! Thanks! >> +- bias-pull-up: Integer. Pull up strength in Ohm: >> + 1: 1.2 kOhm >> + 2: 1.8 kOhm >> + 3: 720 Ohm >> + 4: 2.7 kOhm >> + 5: 831 Ohm >> + 6: 1.08 kOhm >> + 7: 568 Ohm > > Please do not use these custom enumerators 1 thru 7. > Instead say that the argument is given in ohms, so for > example: > > bias-pull-up = <12000>; > > Then translate this into the proper enumerator in your > driver instead. Ok. The 3 bits in this enumeration correspond to enabling the 3 pull up Rs (1.2k, 1.8k, 2.7k) in parallel, so the enum kind of make sense. But sure I can change it to actual ohms and will error out in the driver if specified value is not one of the 7. > No full example provided in the binding! This needs to > be there for understanding. Ok Will add some examples. Thanks, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 4/6] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2013-12-14 1:16 ` Sherman Yin @ 2013-12-16 13:17 ` Linus Walleij [not found] ` <CACRpkdZ5Cxii48CsVJzEaBhvZOs8JCcR_hJV=RczhHbW4aqG-w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2013-12-16 13:17 UTC (permalink / raw) To: Sherman Yin Cc: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Sat, Dec 14, 2013 at 2:16 AM, Sherman Yin <syin@broadcom.com> wrote: >>> +- bias-pull-up: Integer. Pull up strength in Ohm: >>> + 1: 1.2 kOhm >>> + 2: 1.8 kOhm >>> + 3: 720 Ohm >>> + 4: 2.7 kOhm >>> + 5: 831 Ohm >>> + 6: 1.08 kOhm >>> + 7: 568 Ohm >> >> >> Please do not use these custom enumerators 1 thru 7. >> Instead say that the argument is given in ohms, so for >> example: >> >> bias-pull-up = <12000>; >> >> Then translate this into the proper enumerator in your >> driver instead. > > Ok. The 3 bits in this enumeration correspond to enabling the 3 pull up Rs > (1.2k, 1.8k, 2.7k) in parallel, so the enum kind of make sense. But sure I > can change it to actual ohms and will error out in the driver if specified > value is not one of the 7. Aha, that's how they do it :-) Please write this in a comment in the driver because it makes it a lot easier to understand what is going on, and e.g. how to fuzz an apropriate resistance. Can you tell me something about how such resistors are produced in silicon? Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <CACRpkdZ5Cxii48CsVJzEaBhvZOs8JCcR_hJV=RczhHbW4aqG-w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v3 4/6] pinctrl: Add pinctrl binding for Broadcom Capri SoCs [not found] ` <CACRpkdZ5Cxii48CsVJzEaBhvZOs8JCcR_hJV=RczhHbW4aqG-w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2013-12-18 2:02 ` Sherman Yin 0 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-12-18 2:02 UTC (permalink / raw) To: Linus Walleij Cc: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, bcm-kernel-feedback-list, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On 13-12-16 05:17 AM, Linus Walleij wrote: > On Sat, Dec 14, 2013 at 2:16 AM, Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote: > >>>> +- bias-pull-up: Integer. Pull up strength in Ohm: >>>> + 1: 1.2 kOhm >>>> + 2: 1.8 kOhm >>>> + 3: 720 Ohm >>>> + 4: 2.7 kOhm >>>> + 5: 831 Ohm >>>> + 6: 1.08 kOhm >>>> + 7: 568 Ohm >>> >>> >>> Please do not use these custom enumerators 1 thru 7. >>> Instead say that the argument is given in ohms, so for >>> example: >>> >>> bias-pull-up = <12000>; >>> >>> Then translate this into the proper enumerator in your >>> driver instead. >> >> Ok. The 3 bits in this enumeration correspond to enabling the 3 pull up Rs >> (1.2k, 1.8k, 2.7k) in parallel, so the enum kind of make sense. But sure I >> can change it to actual ohms and will error out in the driver if specified >> value is not one of the 7. > > Aha, that's how they do it :-) > > Please write this in a comment in the driver because it makes > it a lot easier to understand what is going on, and e.g. how to > fuzz an apropriate resistance. Yes, I plan to explain where those odd numbers come from in this file. > Can you tell me something about how such resistors are produced > in silicon? Sorry I'm not quite sure. I only know a little bit of the circuitry down to the schematic level... Regards, Sherman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v3 5/6] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-12-11 18:37 ` [PATCH v3 0/6] Add Broadcom Capri pinctrl driver Sherman Yin ` (3 preceding siblings ...) 2013-12-11 18:37 ` [PATCH v3 4/6] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin @ 2013-12-11 18:37 ` Sherman Yin 2013-12-12 20:54 ` Linus Walleij 2013-12-11 18:37 ` [PATCH v3 6/6] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin 2013-12-21 2:13 ` [PATCH v4 0/6] Add Broadcom Capri pinctrl driver Sherman Yin 6 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-12-11 18:37 UTC (permalink / raw) To: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, Sherman Yin, bcm-kernel-feedback-list, linux-arm-kernel Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- v3: Re-work driver to be based on generic pin config. Moved config selection from Kconfig to bcm_defconfig. v2: Use hyphens instead of underscore in DT property names. --- arch/arm/configs/bcm_defconfig | 5 + drivers/pinctrl/Kconfig | 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-capri.c | 1408 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 1425 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-capri.c diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig index 287ac1d..6b94987 100644 --- a/arch/arm/configs/bcm_defconfig +++ b/arch/arm/configs/bcm_defconfig @@ -126,3 +126,8 @@ CONFIG_CRC_ITU_T=y CONFIG_CRC7=y CONFIG_XZ_DEC=y CONFIG_AVERAGE=y +CONFIG_PINCTRL=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +CONFIG_PINCTRL_CAPRI=y diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index a921ff1..664c8e6 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -104,6 +104,17 @@ config PINCTRL_BCM2835 select PINMUX select PINCONF +config PINCTRL_CAPRI + bool "Broadcom Capri pinctrl driver" + select PINMUX + select PINCONF + select GENERIC_PINCONF + help + Say Y here to support Broadcom Capri pinctrl driver, which is used for + the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, + BCM28145, and BCM28155 SoCs. This driver requires the pinctrl + framework. GPIO is provided by a separate GPIO driver. + config PINCTRL_IMX bool select PINMUX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 4f7be29..86cac40 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o +obj-$(CONFIG_PINCTRL_CAPRI) += pinctrl-capri.o obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o diff --git a/drivers/pinctrl/pinctrl-capri.c b/drivers/pinctrl/pinctrl-capri.c new file mode 100644 index 0000000..d468de6 --- /dev/null +++ b/drivers/pinctrl/pinctrl-capri.c @@ -0,0 +1,1408 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/slab.h> +#include "core.h" +#include "pinctrl-utils.h" + +/* Capri Pin Control Registers Definitions */ + +/* Function Select bits are the same for all pin control registers */ +#define CAPRI_PIN_REG_F_SEL_MASK 0x0700 +#define CAPRI_PIN_REG_F_SEL_SHIFT 8 + +/* Standard pin register */ +#define CAPRI_STD_PIN_REG_DRV_STR_MASK 0x0007 +#define CAPRI_STD_PIN_REG_DRV_STR_SHIFT 0 +#define CAPRI_STD_PIN_REG_INPUT_DIS_MASK 0x0008 +#define CAPRI_STD_PIN_REG_INPUT_DIS_SHIFT 3 +#define CAPRI_STD_PIN_REG_SLEW_MASK 0x0010 +#define CAPRI_STD_PIN_REG_SLEW_SHIFT 4 +#define CAPRI_STD_PIN_REG_PULL_UP_MASK 0x0020 +#define CAPRI_STD_PIN_REG_PULL_UP_SHIFT 5 +#define CAPRI_STD_PIN_REG_PULL_DN_MASK 0x0040 +#define CAPRI_STD_PIN_REG_PULL_DN_SHIFT 6 +#define CAPRI_STD_PIN_REG_HYST_MASK 0x0080 +#define CAPRI_STD_PIN_REG_HYST_SHIFT 7 + +/* I2C pin register */ +#define CAPRI_I2C_PIN_REG_INPUT_DIS_MASK 0x0004 +#define CAPRI_I2C_PIN_REG_INPUT_DIS_SHIFT 2 +#define CAPRI_I2C_PIN_REG_SLEW_MASK 0x0008 +#define CAPRI_I2C_PIN_REG_SLEW_SHIFT 3 +#define CAPRI_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070 +#define CAPRI_I2C_PIN_REG_PULL_UP_STR_SHIFT 4 + +/* HDMI pin register */ +#define CAPRI_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008 +#define CAPRI_HDMI_PIN_REG_INPUT_DIS_SHIFT 3 +#define CAPRI_HDMI_PIN_REG_MODE_MASK 0x0010 +#define CAPRI_HDMI_PIN_REG_MODE_SHIFT 4 + +/** + * capri_pin_type - types of pin register + */ +enum capri_pin_type { + CAPRI_PIN_TYPE_UNKNOWN = 0, + CAPRI_PIN_TYPE_STD, + CAPRI_PIN_TYPE_I2C, + CAPRI_PIN_TYPE_HDMI, +}; + +static enum capri_pin_type std_pin = CAPRI_PIN_TYPE_STD; +static enum capri_pin_type i2c_pin = CAPRI_PIN_TYPE_I2C; +static enum capri_pin_type hdmi_pin = CAPRI_PIN_TYPE_HDMI; + +/** + * capri_pin_function- define pin function + */ +struct capri_pin_function { + const char *name; + const char * const *groups; + const unsigned ngroups; +}; + +/** + * capri_pinctrl_data - Broadcom-specific pinctrl data + * @reg_base - base of pinctrl registers + */ +struct capri_pinctrl_data { + void __iomem *reg_base; + + /* List of all pins */ + const struct pinctrl_pin_desc *pins; + const unsigned npins; + + const struct capri_pin_function *functions; + const unsigned nfunctions; +}; + +/* + * Pin number definition. The order here must be the same as defined in the + * PADCTRLREG block in the RDB. + */ +#define CAPRI_PIN_ADCSYNC 0 +#define CAPRI_PIN_BAT_RM 1 +#define CAPRI_PIN_BSC1_SCL 2 +#define CAPRI_PIN_BSC1_SDA 3 +#define CAPRI_PIN_BSC2_SCL 4 +#define CAPRI_PIN_BSC2_SDA 5 +#define CAPRI_PIN_CLASSGPWR 6 +#define CAPRI_PIN_CLK_CX8 7 +#define CAPRI_PIN_CLKOUT_0 8 +#define CAPRI_PIN_CLKOUT_1 9 +#define CAPRI_PIN_CLKOUT_2 10 +#define CAPRI_PIN_CLKOUT_3 11 +#define CAPRI_PIN_CLKREQ_IN_0 12 +#define CAPRI_PIN_CLKREQ_IN_1 13 +#define CAPRI_PIN_CWS_SYS_REQ1 14 +#define CAPRI_PIN_CWS_SYS_REQ2 15 +#define CAPRI_PIN_CWS_SYS_REQ3 16 +#define CAPRI_PIN_DIGMIC1_CLK 17 +#define CAPRI_PIN_DIGMIC1_DQ 18 +#define CAPRI_PIN_DIGMIC2_CLK 19 +#define CAPRI_PIN_DIGMIC2_DQ 20 +#define CAPRI_PIN_GPEN13 21 +#define CAPRI_PIN_GPEN14 22 +#define CAPRI_PIN_GPEN15 23 +#define CAPRI_PIN_GPIO00 24 +#define CAPRI_PIN_GPIO01 25 +#define CAPRI_PIN_GPIO02 26 +#define CAPRI_PIN_GPIO03 27 +#define CAPRI_PIN_GPIO04 28 +#define CAPRI_PIN_GPIO05 29 +#define CAPRI_PIN_GPIO06 30 +#define CAPRI_PIN_GPIO07 31 +#define CAPRI_PIN_GPIO08 32 +#define CAPRI_PIN_GPIO09 33 +#define CAPRI_PIN_GPIO10 34 +#define CAPRI_PIN_GPIO11 35 +#define CAPRI_PIN_GPIO12 36 +#define CAPRI_PIN_GPIO13 37 +#define CAPRI_PIN_GPIO14 38 +#define CAPRI_PIN_GPS_PABLANK 39 +#define CAPRI_PIN_GPS_TMARK 40 +#define CAPRI_PIN_HDMI_SCL 41 +#define CAPRI_PIN_HDMI_SDA 42 +#define CAPRI_PIN_IC_DM 43 +#define CAPRI_PIN_IC_DP 44 +#define CAPRI_PIN_KP_COL_IP_0 45 +#define CAPRI_PIN_KP_COL_IP_1 46 +#define CAPRI_PIN_KP_COL_IP_2 47 +#define CAPRI_PIN_KP_COL_IP_3 48 +#define CAPRI_PIN_KP_ROW_OP_0 49 +#define CAPRI_PIN_KP_ROW_OP_1 50 +#define CAPRI_PIN_KP_ROW_OP_2 51 +#define CAPRI_PIN_KP_ROW_OP_3 52 +#define CAPRI_PIN_LCD_B_0 53 +#define CAPRI_PIN_LCD_B_1 54 +#define CAPRI_PIN_LCD_B_2 55 +#define CAPRI_PIN_LCD_B_3 56 +#define CAPRI_PIN_LCD_B_4 57 +#define CAPRI_PIN_LCD_B_5 58 +#define CAPRI_PIN_LCD_B_6 59 +#define CAPRI_PIN_LCD_B_7 60 +#define CAPRI_PIN_LCD_G_0 61 +#define CAPRI_PIN_LCD_G_1 62 +#define CAPRI_PIN_LCD_G_2 63 +#define CAPRI_PIN_LCD_G_3 64 +#define CAPRI_PIN_LCD_G_4 65 +#define CAPRI_PIN_LCD_G_5 66 +#define CAPRI_PIN_LCD_G_6 67 +#define CAPRI_PIN_LCD_G_7 68 +#define CAPRI_PIN_LCD_HSYNC 69 +#define CAPRI_PIN_LCD_OE 70 +#define CAPRI_PIN_LCD_PCLK 71 +#define CAPRI_PIN_LCD_R_0 72 +#define CAPRI_PIN_LCD_R_1 73 +#define CAPRI_PIN_LCD_R_2 74 +#define CAPRI_PIN_LCD_R_3 75 +#define CAPRI_PIN_LCD_R_4 76 +#define CAPRI_PIN_LCD_R_5 77 +#define CAPRI_PIN_LCD_R_6 78 +#define CAPRI_PIN_LCD_R_7 79 +#define CAPRI_PIN_LCD_VSYNC 80 +#define CAPRI_PIN_MDMGPIO0 81 +#define CAPRI_PIN_MDMGPIO1 82 +#define CAPRI_PIN_MDMGPIO2 83 +#define CAPRI_PIN_MDMGPIO3 84 +#define CAPRI_PIN_MDMGPIO4 85 +#define CAPRI_PIN_MDMGPIO5 86 +#define CAPRI_PIN_MDMGPIO6 87 +#define CAPRI_PIN_MDMGPIO7 88 +#define CAPRI_PIN_MDMGPIO8 89 +#define CAPRI_PIN_MPHI_DATA_0 90 +#define CAPRI_PIN_MPHI_DATA_1 91 +#define CAPRI_PIN_MPHI_DATA_2 92 +#define CAPRI_PIN_MPHI_DATA_3 93 +#define CAPRI_PIN_MPHI_DATA_4 94 +#define CAPRI_PIN_MPHI_DATA_5 95 +#define CAPRI_PIN_MPHI_DATA_6 96 +#define CAPRI_PIN_MPHI_DATA_7 97 +#define CAPRI_PIN_MPHI_DATA_8 98 +#define CAPRI_PIN_MPHI_DATA_9 99 +#define CAPRI_PIN_MPHI_DATA_10 100 +#define CAPRI_PIN_MPHI_DATA_11 101 +#define CAPRI_PIN_MPHI_DATA_12 102 +#define CAPRI_PIN_MPHI_DATA_13 103 +#define CAPRI_PIN_MPHI_DATA_14 104 +#define CAPRI_PIN_MPHI_DATA_15 105 +#define CAPRI_PIN_MPHI_HA0 106 +#define CAPRI_PIN_MPHI_HAT0 107 +#define CAPRI_PIN_MPHI_HAT1 108 +#define CAPRI_PIN_MPHI_HCE0_N 109 +#define CAPRI_PIN_MPHI_HCE1_N 110 +#define CAPRI_PIN_MPHI_HRD_N 111 +#define CAPRI_PIN_MPHI_HWR_N 112 +#define CAPRI_PIN_MPHI_RUN0 113 +#define CAPRI_PIN_MPHI_RUN1 114 +#define CAPRI_PIN_MTX_SCAN_CLK 115 +#define CAPRI_PIN_MTX_SCAN_DATA 116 +#define CAPRI_PIN_NAND_AD_0 117 +#define CAPRI_PIN_NAND_AD_1 118 +#define CAPRI_PIN_NAND_AD_2 119 +#define CAPRI_PIN_NAND_AD_3 120 +#define CAPRI_PIN_NAND_AD_4 121 +#define CAPRI_PIN_NAND_AD_5 122 +#define CAPRI_PIN_NAND_AD_6 123 +#define CAPRI_PIN_NAND_AD_7 124 +#define CAPRI_PIN_NAND_ALE 125 +#define CAPRI_PIN_NAND_CEN_0 126 +#define CAPRI_PIN_NAND_CEN_1 127 +#define CAPRI_PIN_NAND_CLE 128 +#define CAPRI_PIN_NAND_OEN 129 +#define CAPRI_PIN_NAND_RDY_0 130 +#define CAPRI_PIN_NAND_RDY_1 131 +#define CAPRI_PIN_NAND_WEN 132 +#define CAPRI_PIN_NAND_WP 133 +#define CAPRI_PIN_PC1 134 +#define CAPRI_PIN_PC2 135 +#define CAPRI_PIN_PMU_INT 136 +#define CAPRI_PIN_PMU_SCL 137 +#define CAPRI_PIN_PMU_SDA 138 +#define CAPRI_PIN_RFST2G_MTSLOTEN3G 139 +#define CAPRI_PIN_RGMII_0_RX_CTL 140 +#define CAPRI_PIN_RGMII_0_RXC 141 +#define CAPRI_PIN_RGMII_0_RXD_0 142 +#define CAPRI_PIN_RGMII_0_RXD_1 143 +#define CAPRI_PIN_RGMII_0_RXD_2 144 +#define CAPRI_PIN_RGMII_0_RXD_3 145 +#define CAPRI_PIN_RGMII_0_TX_CTL 146 +#define CAPRI_PIN_RGMII_0_TXC 147 +#define CAPRI_PIN_RGMII_0_TXD_0 148 +#define CAPRI_PIN_RGMII_0_TXD_1 149 +#define CAPRI_PIN_RGMII_0_TXD_2 150 +#define CAPRI_PIN_RGMII_0_TXD_3 151 +#define CAPRI_PIN_RGMII_1_RX_CTL 152 +#define CAPRI_PIN_RGMII_1_RXC 153 +#define CAPRI_PIN_RGMII_1_RXD_0 154 +#define CAPRI_PIN_RGMII_1_RXD_1 155 +#define CAPRI_PIN_RGMII_1_RXD_2 156 +#define CAPRI_PIN_RGMII_1_RXD_3 157 +#define CAPRI_PIN_RGMII_1_TX_CTL 158 +#define CAPRI_PIN_RGMII_1_TXC 159 +#define CAPRI_PIN_RGMII_1_TXD_0 160 +#define CAPRI_PIN_RGMII_1_TXD_1 161 +#define CAPRI_PIN_RGMII_1_TXD_2 162 +#define CAPRI_PIN_RGMII_1_TXD_3 163 +#define CAPRI_PIN_RGMII_GPIO_0 164 +#define CAPRI_PIN_RGMII_GPIO_1 165 +#define CAPRI_PIN_RGMII_GPIO_2 166 +#define CAPRI_PIN_RGMII_GPIO_3 167 +#define CAPRI_PIN_RTXDATA2G_TXDATA3G1 168 +#define CAPRI_PIN_RTXEN2G_TXDATA3G2 169 +#define CAPRI_PIN_RXDATA3G0 170 +#define CAPRI_PIN_RXDATA3G1 171 +#define CAPRI_PIN_RXDATA3G2 172 +#define CAPRI_PIN_SDIO1_CLK 173 +#define CAPRI_PIN_SDIO1_CMD 174 +#define CAPRI_PIN_SDIO1_DATA_0 175 +#define CAPRI_PIN_SDIO1_DATA_1 176 +#define CAPRI_PIN_SDIO1_DATA_2 177 +#define CAPRI_PIN_SDIO1_DATA_3 178 +#define CAPRI_PIN_SDIO4_CLK 179 +#define CAPRI_PIN_SDIO4_CMD 180 +#define CAPRI_PIN_SDIO4_DATA_0 181 +#define CAPRI_PIN_SDIO4_DATA_1 182 +#define CAPRI_PIN_SDIO4_DATA_2 183 +#define CAPRI_PIN_SDIO4_DATA_3 184 +#define CAPRI_PIN_SIM_CLK 185 +#define CAPRI_PIN_SIM_DATA 186 +#define CAPRI_PIN_SIM_DET 187 +#define CAPRI_PIN_SIM_RESETN 188 +#define CAPRI_PIN_SIM2_CLK 189 +#define CAPRI_PIN_SIM2_DATA 190 +#define CAPRI_PIN_SIM2_DET 191 +#define CAPRI_PIN_SIM2_RESETN 192 +#define CAPRI_PIN_SRI_C 193 +#define CAPRI_PIN_SRI_D 194 +#define CAPRI_PIN_SRI_E 195 +#define CAPRI_PIN_SSP_EXTCLK 196 +#define CAPRI_PIN_SSP0_CLK 197 +#define CAPRI_PIN_SSP0_FS 198 +#define CAPRI_PIN_SSP0_RXD 199 +#define CAPRI_PIN_SSP0_TXD 200 +#define CAPRI_PIN_SSP2_CLK 201 +#define CAPRI_PIN_SSP2_FS_0 202 +#define CAPRI_PIN_SSP2_FS_1 203 +#define CAPRI_PIN_SSP2_FS_2 204 +#define CAPRI_PIN_SSP2_FS_3 205 +#define CAPRI_PIN_SSP2_RXD_0 206 +#define CAPRI_PIN_SSP2_RXD_1 207 +#define CAPRI_PIN_SSP2_TXD_0 208 +#define CAPRI_PIN_SSP2_TXD_1 209 +#define CAPRI_PIN_SSP3_CLK 210 +#define CAPRI_PIN_SSP3_FS 211 +#define CAPRI_PIN_SSP3_RXD 212 +#define CAPRI_PIN_SSP3_TXD 213 +#define CAPRI_PIN_SSP4_CLK 214 +#define CAPRI_PIN_SSP4_FS 215 +#define CAPRI_PIN_SSP4_RXD 216 +#define CAPRI_PIN_SSP4_TXD 217 +#define CAPRI_PIN_SSP5_CLK 218 +#define CAPRI_PIN_SSP5_FS 219 +#define CAPRI_PIN_SSP5_RXD 220 +#define CAPRI_PIN_SSP5_TXD 221 +#define CAPRI_PIN_SSP6_CLK 222 +#define CAPRI_PIN_SSP6_FS 223 +#define CAPRI_PIN_SSP6_RXD 224 +#define CAPRI_PIN_SSP6_TXD 225 +#define CAPRI_PIN_STAT_1 226 +#define CAPRI_PIN_STAT_2 227 +#define CAPRI_PIN_SYSCLKEN 228 +#define CAPRI_PIN_TRACECLK 229 +#define CAPRI_PIN_TRACEDT00 230 +#define CAPRI_PIN_TRACEDT01 231 +#define CAPRI_PIN_TRACEDT02 232 +#define CAPRI_PIN_TRACEDT03 233 +#define CAPRI_PIN_TRACEDT04 234 +#define CAPRI_PIN_TRACEDT05 235 +#define CAPRI_PIN_TRACEDT06 236 +#define CAPRI_PIN_TRACEDT07 237 +#define CAPRI_PIN_TRACEDT08 238 +#define CAPRI_PIN_TRACEDT09 239 +#define CAPRI_PIN_TRACEDT10 240 +#define CAPRI_PIN_TRACEDT11 241 +#define CAPRI_PIN_TRACEDT12 242 +#define CAPRI_PIN_TRACEDT13 243 +#define CAPRI_PIN_TRACEDT14 244 +#define CAPRI_PIN_TRACEDT15 245 +#define CAPRI_PIN_TXDATA3G0 246 +#define CAPRI_PIN_TXPWRIND 247 +#define CAPRI_PIN_UARTB1_UCTS 248 +#define CAPRI_PIN_UARTB1_URTS 249 +#define CAPRI_PIN_UARTB1_URXD 250 +#define CAPRI_PIN_UARTB1_UTXD 251 +#define CAPRI_PIN_UARTB2_URXD 252 +#define CAPRI_PIN_UARTB2_UTXD 253 +#define CAPRI_PIN_UARTB3_UCTS 254 +#define CAPRI_PIN_UARTB3_URTS 255 +#define CAPRI_PIN_UARTB3_URXD 256 +#define CAPRI_PIN_UARTB3_UTXD 257 +#define CAPRI_PIN_UARTB4_UCTS 258 +#define CAPRI_PIN_UARTB4_URTS 259 +#define CAPRI_PIN_UARTB4_URXD 260 +#define CAPRI_PIN_UARTB4_UTXD 261 +#define CAPRI_PIN_VC_CAM1_SCL 262 +#define CAPRI_PIN_VC_CAM1_SDA 263 +#define CAPRI_PIN_VC_CAM2_SCL 264 +#define CAPRI_PIN_VC_CAM2_SDA 265 +#define CAPRI_PIN_VC_CAM3_SCL 266 +#define CAPRI_PIN_VC_CAM3_SDA 267 + +#define CAPRI_PIN_DESC(a, b, c) \ + { .number = a, .name = b, .drv_data = &c##_pin } + +/* + * Pin description definition. The order here must be the same as defined in + * the PADCTRLREG block in the RDB, since the pin number is used as an index + * into this array. + */ +static const struct pinctrl_pin_desc capri_pinctrl_pins[] = { + CAPRI_PIN_DESC(CAPRI_PIN_ADCSYNC, "adcsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_BAT_RM, "bat_rm", std), + CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SCL, "bsc1_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SDA, "bsc1_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SCL, "bsc2_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SDA, "bsc2_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_CLASSGPWR, "classgpwr", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLK_CX8, "clk_cx8", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_0, "clkout_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_1, "clkout_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_2, "clkout_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_3, "clkout_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_0, "clkreq_in_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_1, "clkreq_in_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ1, "cws_sys_req1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ2, "cws_sys_req2", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ3, "cws_sys_req3", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_CLK, "digmic1_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_DQ, "digmic1_dq", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_CLK, "digmic2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_DQ, "digmic2_dq", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN13, "gpen13", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN14, "gpen14", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN15, "gpen15", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO00, "gpio00", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO01, "gpio01", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO02, "gpio02", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO03, "gpio03", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO04, "gpio04", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO05, "gpio05", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO06, "gpio06", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO07, "gpio07", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO08, "gpio08", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO09, "gpio09", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO10, "gpio10", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO11, "gpio11", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO12, "gpio12", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO13, "gpio13", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO14, "gpio14", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPS_PABLANK, "gps_pablank", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPS_TMARK, "gps_tmark", std), + CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SCL, "hdmi_scl", hdmi), + CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SDA, "hdmi_sda", hdmi), + CAPRI_PIN_DESC(CAPRI_PIN_IC_DM, "ic_dm", std), + CAPRI_PIN_DESC(CAPRI_PIN_IC_DP, "ic_dp", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_0, "kp_col_ip_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_1, "kp_col_ip_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_2, "kp_col_ip_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_3, "kp_col_ip_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_0, "kp_row_op_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_1, "kp_row_op_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_2, "kp_row_op_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_3, "kp_row_op_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_0, "lcd_b_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_1, "lcd_b_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_2, "lcd_b_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_3, "lcd_b_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_4, "lcd_b_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_5, "lcd_b_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_6, "lcd_b_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_7, "lcd_b_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_0, "lcd_g_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_1, "lcd_g_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_2, "lcd_g_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_3, "lcd_g_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_4, "lcd_g_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_5, "lcd_g_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_6, "lcd_g_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_7, "lcd_g_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_HSYNC, "lcd_hsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_OE, "lcd_oe", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_PCLK, "lcd_pclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_0, "lcd_r_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_1, "lcd_r_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_2, "lcd_r_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_3, "lcd_r_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_4, "lcd_r_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_5, "lcd_r_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_6, "lcd_r_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_7, "lcd_r_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_VSYNC, "lcd_vsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO0, "mdmgpio0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO1, "mdmgpio1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO2, "mdmgpio2", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO3, "mdmgpio3", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO4, "mdmgpio4", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO5, "mdmgpio5", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO6, "mdmgpio6", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO7, "mdmgpio7", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO8, "mdmgpio8", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_0, "mphi_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_1, "mphi_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_2, "mphi_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_3, "mphi_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_4, "mphi_data_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_5, "mphi_data_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_6, "mphi_data_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_7, "mphi_data_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_8, "mphi_data_8", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_9, "mphi_data_9", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_10, "mphi_data_10", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_11, "mphi_data_11", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_12, "mphi_data_12", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_13, "mphi_data_13", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_14, "mphi_data_14", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_15, "mphi_data_15", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HA0, "mphi_ha0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT0, "mphi_hat0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT1, "mphi_hat1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE0_N, "mphi_hce0_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE1_N, "mphi_hce1_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HRD_N, "mphi_hrd_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HWR_N, "mphi_hwr_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN0, "mphi_run0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN1, "mphi_run1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_DATA, "mtx_scan_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_0, "nand_ad_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_1, "nand_ad_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_2, "nand_ad_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_3, "nand_ad_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_4, "nand_ad_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_5, "nand_ad_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_6, "nand_ad_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_7, "nand_ad_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_ALE, "nand_ale", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_0, "nand_cen_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_1, "nand_cen_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CLE, "nand_cle", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_OEN, "nand_oen", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_0, "nand_rdy_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_1, "nand_rdy_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_WEN, "nand_wen", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_WP, "nand_wp", std), + CAPRI_PIN_DESC(CAPRI_PIN_PC1, "pc1", std), + CAPRI_PIN_DESC(CAPRI_PIN_PC2, "pc2", std), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_INT, "pmu_int", std), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_SCL, "pmu_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_SDA, "pmu_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXC, "rgmii_0_rxc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXC, "rgmii_0_txc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXC, "rgmii_1_rxc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXC, "rgmii_1_txc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RTXDATA2G_TXDATA3G1, "rtxdata2g_txdata3g1", + std), + CAPRI_PIN_DESC(CAPRI_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G0, "rxdata3g0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G1, "rxdata3g1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G2, "rxdata3g2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CLK, "sdio1_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CMD, "sdio1_cmd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_0, "sdio1_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_1, "sdio1_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_2, "sdio1_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_3, "sdio1_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CLK, "sdio4_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CMD, "sdio4_cmd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_0, "sdio4_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_1, "sdio4_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_2, "sdio4_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_3, "sdio4_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_CLK, "sim_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_DATA, "sim_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_DET, "sim_det", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_RESETN, "sim_resetn", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_CLK, "sim2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DATA, "sim2_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DET, "sim2_det", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_RESETN, "sim2_resetn", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_C, "sri_c", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_D, "sri_d", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_E, "sri_e", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP_EXTCLK, "ssp_extclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_CLK, "ssp0_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_FS, "ssp0_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_RXD, "ssp0_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_TXD, "ssp0_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_CLK, "ssp2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_0, "ssp2_fs_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_1, "ssp2_fs_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_2, "ssp2_fs_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_3, "ssp2_fs_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_0, "ssp2_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_1, "ssp2_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_0, "ssp2_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_1, "ssp2_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_CLK, "ssp3_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_FS, "ssp3_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_RXD, "ssp3_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_TXD, "ssp3_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_CLK, "ssp4_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_FS, "ssp4_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_RXD, "ssp4_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_TXD, "ssp4_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_CLK, "ssp5_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_FS, "ssp5_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_RXD, "ssp5_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_TXD, "ssp5_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_CLK, "ssp6_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_FS, "ssp6_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_RXD, "ssp6_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_TXD, "ssp6_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_STAT_1, "stat_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_STAT_2, "stat_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SYSCLKEN, "sysclken", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACECLK, "traceclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT00, "tracedt00", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT01, "tracedt01", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT02, "tracedt02", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT03, "tracedt03", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT04, "tracedt04", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT05, "tracedt05", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT06, "tracedt06", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT07, "tracedt07", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT08, "tracedt08", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT09, "tracedt09", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT10, "tracedt10", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT11, "tracedt11", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT12, "tracedt12", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT13, "tracedt13", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT14, "tracedt14", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT15, "tracedt15", std), + CAPRI_PIN_DESC(CAPRI_PIN_TXDATA3G0, "txdata3g0", std), + CAPRI_PIN_DESC(CAPRI_PIN_TXPWRIND, "txpwrind", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UCTS, "uartb1_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URTS, "uartb1_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URXD, "uartb1_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UTXD, "uartb1_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_URXD, "uartb2_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_UTXD, "uartb2_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UCTS, "uartb3_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URTS, "uartb3_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URXD, "uartb3_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UTXD, "uartb3_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UCTS, "uartb4_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URTS, "uartb4_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URXD, "uartb4_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UTXD, "uartb4_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c), +}; + +static const char * const capri_alt_groups[] = { + "adcsync", + "bat_rm", + "bsc1_scl", + "bsc1_sda", + "bsc2_scl", + "bsc2_sda", + "classgpwr", + "clk_cx8", + "clkout_0", + "clkout_1", + "clkout_2", + "clkout_3", + "clkreq_in_0", + "clkreq_in_1", + "cws_sys_req1", + "cws_sys_req2", + "cws_sys_req3", + "digmic1_clk", + "digmic1_dq", + "digmic2_clk", + "digmic2_dq", + "gpen13", + "gpen14", + "gpen15", + "gpio00", + "gpio01", + "gpio02", + "gpio03", + "gpio04", + "gpio05", + "gpio06", + "gpio07", + "gpio08", + "gpio09", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gps_pablank", + "gps_tmark", + "hdmi_scl", + "hdmi_sda", + "ic_dm", + "ic_dp", + "kp_col_ip_0", + "kp_col_ip_1", + "kp_col_ip_2", + "kp_col_ip_3", + "kp_row_op_0", + "kp_row_op_1", + "kp_row_op_2", + "kp_row_op_3", + "lcd_b_0", + "lcd_b_1", + "lcd_b_2", + "lcd_b_3", + "lcd_b_4", + "lcd_b_5", + "lcd_b_6", + "lcd_b_7", + "lcd_g_0", + "lcd_g_1", + "lcd_g_2", + "lcd_g_3", + "lcd_g_4", + "lcd_g_5", + "lcd_g_6", + "lcd_g_7", + "lcd_hsync", + "lcd_oe", + "lcd_pclk", + "lcd_r_0", + "lcd_r_1", + "lcd_r_2", + "lcd_r_3", + "lcd_r_4", + "lcd_r_5", + "lcd_r_6", + "lcd_r_7", + "lcd_vsync", + "mdmgpio0", + "mdmgpio1", + "mdmgpio2", + "mdmgpio3", + "mdmgpio4", + "mdmgpio5", + "mdmgpio6", + "mdmgpio7", + "mdmgpio8", + "mphi_data_0", + "mphi_data_1", + "mphi_data_2", + "mphi_data_3", + "mphi_data_4", + "mphi_data_5", + "mphi_data_6", + "mphi_data_7", + "mphi_data_8", + "mphi_data_9", + "mphi_data_10", + "mphi_data_11", + "mphi_data_12", + "mphi_data_13", + "mphi_data_14", + "mphi_data_15", + "mphi_ha0", + "mphi_hat0", + "mphi_hat1", + "mphi_hce0_n", + "mphi_hce1_n", + "mphi_hrd_n", + "mphi_hwr_n", + "mphi_run0", + "mphi_run1", + "mtx_scan_clk", + "mtx_scan_data", + "nand_ad_0", + "nand_ad_1", + "nand_ad_2", + "nand_ad_3", + "nand_ad_4", + "nand_ad_5", + "nand_ad_6", + "nand_ad_7", + "nand_ale", + "nand_cen_0", + "nand_cen_1", + "nand_cle", + "nand_oen", + "nand_rdy_0", + "nand_rdy_1", + "nand_wen", + "nand_wp", + "pc1", + "pc2", + "pmu_int", + "pmu_scl", + "pmu_sda", + "rfst2g_mtsloten3g", + "rgmii_0_rx_ctl", + "rgmii_0_rxc", + "rgmii_0_rxd_0", + "rgmii_0_rxd_1", + "rgmii_0_rxd_2", + "rgmii_0_rxd_3", + "rgmii_0_tx_ctl", + "rgmii_0_txc", + "rgmii_0_txd_0", + "rgmii_0_txd_1", + "rgmii_0_txd_2", + "rgmii_0_txd_3", + "rgmii_1_rx_ctl", + "rgmii_1_rxc", + "rgmii_1_rxd_0", + "rgmii_1_rxd_1", + "rgmii_1_rxd_2", + "rgmii_1_rxd_3", + "rgmii_1_tx_ctl", + "rgmii_1_txc", + "rgmii_1_txd_0", + "rgmii_1_txd_1", + "rgmii_1_txd_2", + "rgmii_1_txd_3", + "rgmii_gpio_0", + "rgmii_gpio_1", + "rgmii_gpio_2", + "rgmii_gpio_3", + "rtxdata2g_txdata3g1", + "rtxen2g_txdata3g2", + "rxdata3g0", + "rxdata3g1", + "rxdata3g2", + "sdio1_clk", + "sdio1_cmd", + "sdio1_data_0", + "sdio1_data_1", + "sdio1_data_2", + "sdio1_data_3", + "sdio4_clk", + "sdio4_cmd", + "sdio4_data_0", + "sdio4_data_1", + "sdio4_data_2", + "sdio4_data_3", + "sim_clk", + "sim_data", + "sim_det", + "sim_resetn", + "sim2_clk", + "sim2_data", + "sim2_det", + "sim2_resetn", + "sri_c", + "sri_d", + "sri_e", + "ssp_extclk", + "ssp0_clk", + "ssp0_fs", + "ssp0_rxd", + "ssp0_txd", + "ssp2_clk", + "ssp2_fs_0", + "ssp2_fs_1", + "ssp2_fs_2", + "ssp2_fs_3", + "ssp2_rxd_0", + "ssp2_rxd_1", + "ssp2_txd_0", + "ssp2_txd_1", + "ssp3_clk", + "ssp3_fs", + "ssp3_rxd", + "ssp3_txd", + "ssp4_clk", + "ssp4_fs", + "ssp4_rxd", + "ssp4_txd", + "ssp5_clk", + "ssp5_fs", + "ssp5_rxd", + "ssp5_txd", + "ssp6_clk", + "ssp6_fs", + "ssp6_rxd", + "ssp6_txd", + "stat_1", + "stat_2", + "sysclken", + "traceclk", + "tracedt00", + "tracedt01", + "tracedt02", + "tracedt03", + "tracedt04", + "tracedt05", + "tracedt06", + "tracedt07", + "tracedt08", + "tracedt09", + "tracedt10", + "tracedt11", + "tracedt12", + "tracedt13", + "tracedt14", + "tracedt15", + "txdata3g0", + "txpwrind", + "uartb1_ucts", + "uartb1_urts", + "uartb1_urxd", + "uartb1_utxd", + "uartb2_urxd", + "uartb2_utxd", + "uartb3_ucts", + "uartb3_urts", + "uartb3_urxd", + "uartb3_utxd", + "uartb4_ucts", + "uartb4_urts", + "uartb4_urxd", + "uartb4_utxd", + "vc_cam1_scl", + "vc_cam1_sda", + "vc_cam2_scl", + "vc_cam2_sda", + "vc_cam3_scl", + "vc_cam3_sda", +}; + +/* Every pin can implement all ALT1-ALT4 functions */ +#define CAPRI_PIN_FUNCTION(fcn_name) \ +{ \ + .name = #fcn_name, \ + .groups = capri_alt_groups, \ + .ngroups = ARRAY_SIZE(capri_alt_groups), \ +} + +static const struct capri_pin_function capri_functions[] = { + CAPRI_PIN_FUNCTION(alt1), + CAPRI_PIN_FUNCTION(alt2), + CAPRI_PIN_FUNCTION(alt3), + CAPRI_PIN_FUNCTION(alt4), +}; + +static struct capri_pinctrl_data capri_pinctrl = { + .pins = capri_pinctrl_pins, + .npins = ARRAY_SIZE(capri_pinctrl_pins), + .functions = capri_functions, + .nfunctions = ARRAY_SIZE(capri_functions), +}; + +static inline enum capri_pin_type pin_type_get(struct pinctrl_dev *pctldev, + unsigned pin) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + if (pin >= pdata->npins) + return CAPRI_PIN_TYPE_UNKNOWN; + + return *(enum capri_pin_type *)(pdata->pins[pin].drv_data); +} + +#define CAPRI_PIN_SHIFT(type, param) \ + (CAPRI_ ## type ## _PIN_REG_ ## param ## _SHIFT) + +#define CAPRI_PIN_MASK(type, param) \ + (CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK) + +/* Macro to update reg with new pin config param */ +#define CAPRI_PIN_UPDATE(reg, type, param, val) \ + (((reg) & ~CAPRI_PIN_MASK(type, param)) | \ + (((val) << CAPRI_PIN_SHIFT(type, param)) & CAPRI_PIN_MASK(type, param))) + +/* + * Write to the register using the value and mask if current value is different + */ +static void capri_reg_write(struct pinctrl_dev *pctldev, + void __iomem *reg, + u32 val, + u32 mask) +{ + u32 old_val; + u32 new_val; + + old_val = readl(reg); + new_val = (old_val & ~mask) | (val & mask); + + if (new_val == old_val) { + dev_dbg(pctldev->dev, + "Reg 0x%p=0x%x (no change)\n", + reg, old_val); + return; + } + + dev_dbg(pctldev->dev, + "Reg 0x%p change from 0x%x to 0x%x\n", + reg, old_val, new_val); + writel(new_val, reg); +} + +static int capri_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->npins; +} + +static const char *capri_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->pins[group].name; +} + +static int capri_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pdata->pins[group].number; + *num_pins = 1; + + return 0; +} + +static void capri_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} + +static struct pinctrl_ops capri_pinctrl_ops = { + .get_groups_count = capri_pinctrl_get_groups_count, + .get_group_name = capri_pinctrl_get_group_name, + .get_group_pins = capri_pinctrl_get_group_pins, + .pin_dbg_show = capri_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int capri_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->nfunctions; +} + +static const char *capri_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->functions[function].name; +} + +static int capri_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *groups = pdata->functions[function].groups; + *num_groups = pdata->functions[function].ngroups; + + return 0; +} + +static int capri_pinmux_enable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + const struct capri_pin_function *f = &pdata->functions[function]; + void __iomem *reg = pdata->reg_base + (4 * pdata->pins[group].number); + + dev_dbg(pctldev->dev, + "%s(): Enable function %s (%d) of pin %s (%d) @reg 0x%p.\n", + __func__, f->name, function, pdata->pins[group].name, + pdata->pins[group].number, reg); + + capri_reg_write(pctldev, reg, function << CAPRI_PIN_REG_F_SEL_SHIFT, + CAPRI_PIN_REG_F_SEL_MASK); + + return 0; +} + +static struct pinmux_ops capri_pinctrl_pinmux_ops = { + .get_functions_count = capri_pinctrl_get_fcns_count, + .get_function_name = capri_pinctrl_get_fcn_name, + .get_function_groups = capri_pinctrl_get_fcn_groups, + .enable = capri_pinmux_enable, +}; + +static int capri_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + return -ENOTSUPP; +} + + +/* Goes through the configs and update register val/mask */ +static int capri_std_pin_update(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs, + u32 *val, + u32 *mask) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i; + enum pin_config_param param; + u16 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + arg = (arg >= 1 ? 1 : 0); + *val = CAPRI_PIN_UPDATE(*val, STD, HYST, arg); + *mask |= CAPRI_STD_PIN_REG_HYST_MASK; + break; + /* + * The pin bias can only be one of pull-up, pull-down, or + * disable. The user does not need to specify a value for the + * property, and the default value from pinconf-generic is + * ignored. + */ + case PIN_CONFIG_BIAS_DISABLE: + *val = CAPRI_PIN_UPDATE(*val, STD, PULL_UP, 0); + *val = CAPRI_PIN_UPDATE(*val, STD, PULL_DN, 0); + *mask |= CAPRI_STD_PIN_REG_PULL_UP_MASK; + *mask |= CAPRI_STD_PIN_REG_PULL_DN_MASK; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + *val = CAPRI_PIN_UPDATE(*val, STD, PULL_UP, 1); + *val = CAPRI_PIN_UPDATE(*val, STD, PULL_DN, 0); + *mask |= CAPRI_STD_PIN_REG_PULL_UP_MASK; + *mask |= CAPRI_STD_PIN_REG_PULL_DN_MASK; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + *val = CAPRI_PIN_UPDATE(*val, STD, PULL_UP, 0); + *val = CAPRI_PIN_UPDATE(*val, STD, PULL_DN, 1); + *mask |= CAPRI_STD_PIN_REG_PULL_UP_MASK; + *mask |= CAPRI_STD_PIN_REG_PULL_DN_MASK; + break; + + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + *val = CAPRI_PIN_UPDATE(*val, STD, SLEW, arg); + *mask |= CAPRI_STD_PIN_REG_SLEW_MASK; + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + *val = CAPRI_PIN_UPDATE(*val, STD, INPUT_DIS, arg); + *mask |= CAPRI_STD_PIN_REG_INPUT_DIS_MASK; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + /* Valid range is 2-16 mA, even numbers only */ + if ((arg < 2) || (arg > 16) || (arg % 2)) { + dev_err(pctldev->dev, + "Invalid Drive Strength value (%d) for " + "pin %s (%d). Valid values are " + "(2..16) mA, even numbers only.\n", + arg, pdata->pins[pin].name, pin); + return -EINVAL; + } + *val = CAPRI_PIN_UPDATE(*val, STD, DRV_STR, (arg/2)-1); + *mask |= CAPRI_STD_PIN_REG_DRV_STR_MASK; + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + +/* Goes through the configs and update register val/mask */ +static int capri_i2c_pin_update(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs, + u32 *val, + u32 *mask) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i; + enum pin_config_param param; + u16 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + if ((arg < 1) || (arg > 7)) { + dev_err(pctldev->dev, + "Invalid Pull Up value (%d) for pin %s " + "(%d). Valid values are (1..7).\n", + arg, pdata->pins[pin].name, pin); + return -EINVAL; + } + *val = CAPRI_PIN_UPDATE(*val, I2C, PULL_UP_STR, arg); + *mask |= CAPRI_I2C_PIN_REG_PULL_UP_STR_MASK; + break; + + case PIN_CONFIG_BIAS_DISABLE: + *val = CAPRI_PIN_UPDATE(*val, I2C, PULL_UP_STR, 0); + *mask |= CAPRI_I2C_PIN_REG_PULL_UP_STR_MASK; + break; + + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + *val = CAPRI_PIN_UPDATE(*val, I2C, SLEW, arg); + *mask |= CAPRI_I2C_PIN_REG_SLEW_MASK; + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + *val = CAPRI_PIN_UPDATE(*val, I2C, INPUT_DIS, arg); + *mask |= CAPRI_I2C_PIN_REG_INPUT_DIS_MASK; + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + +/* Goes through the configs and update register val/mask */ +static int capri_hdmi_pin_update(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs, + u32 *val, + u32 *mask) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i; + enum pin_config_param param; + u16 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + *val = CAPRI_PIN_UPDATE(*val, HDMI, MODE, arg); + *mask |= CAPRI_HDMI_PIN_REG_MODE_MASK; + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + *val = CAPRI_PIN_UPDATE(*val, HDMI, INPUT_DIS, arg); + *mask |= CAPRI_HDMI_PIN_REG_INPUT_DIS_MASK; + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + +static int capri_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + enum capri_pin_type pin_type; + void __iomem *reg = pdata->reg_base + (4 * pin); + u32 cfg_val, cfg_mask; + int rc; + + cfg_val = 0; + cfg_mask = 0; + pin_type = pin_type_get(pctldev, pin); + + /* Different pins have different configuration options */ + switch (pin_type) { + case CAPRI_PIN_TYPE_STD: + rc = capri_std_pin_update(pctldev, pin, configs, num_configs, + &cfg_val, &cfg_mask); + break; + + case CAPRI_PIN_TYPE_I2C: + rc = capri_i2c_pin_update(pctldev, pin, configs, num_configs, + &cfg_val, &cfg_mask); + break; + + case CAPRI_PIN_TYPE_HDMI: + rc = capri_hdmi_pin_update(pctldev, pin, configs, num_configs, + &cfg_val, &cfg_mask); + break; + + default: + dev_err(pctldev->dev, "Unknown pin type.\n"); + return -EINVAL; + + } /* switch pin type */ + + if (rc) + return rc; + + dev_dbg(pctldev->dev, + "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n", + __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask); + + capri_reg_write(pctldev, reg, cfg_val, cfg_mask); + + return 0; +} + +static struct pinconf_ops capri_pinctrl_pinconf_ops = { + .pin_config_get = capri_pinctrl_pin_config_get, + .pin_config_set = capri_pinctrl_pin_config_set, +}; + +static struct pinctrl_desc capri_pinctrl_desc = { + /* name, pins, npins members initialized in probe function */ + .pctlops = &capri_pinctrl_ops, + .pmxops = &capri_pinctrl_pinmux_ops, + .confops = &capri_pinctrl_pinconf_ops, + .owner = THIS_MODULE, +}; + +int __init capri_pinctrl_probe(struct platform_device *pdev) +{ + struct capri_pinctrl_data *pdata = &capri_pinctrl; + struct resource *res; + struct pinctrl_dev *pctl; + + /* So far We can assume there is only 1 bank of registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Missing MEM resource\n"); + return -ENODEV; + } + + pdata->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pdata->reg_base)) { + dev_err(&pdev->dev, "Failed to ioremap MEM resource\n"); + return -ENODEV; + } + + /* Initialize the dynamic part of pinctrl_desc */ + capri_pinctrl_desc.name = dev_name(&pdev->dev); + capri_pinctrl_desc.pins = capri_pinctrl.pins; + capri_pinctrl_desc.npins = capri_pinctrl.npins; + + pctl = pinctrl_register(&capri_pinctrl_desc, + &pdev->dev, + pdata); + if (!pctl) { + dev_err(&pdev->dev, "Failed to register pinctrl\n"); + return -ENODEV; + } + + platform_set_drvdata(pdev, pdata); + + return 0; +} + +static struct of_device_id capri_pinctrl_of_match[] = { + { .compatible = "brcm,capri-pinctrl", }, + { }, +}; + +static struct platform_driver capri_pinctrl_driver = { + .driver = { + .name = "bcm-capri-pinctrl", + .owner = THIS_MODULE, + .of_match_table = capri_pinctrl_of_match, + }, +}; + +module_platform_driver_probe(capri_pinctrl_driver, capri_pinctrl_probe); + +MODULE_AUTHOR("Sherman Yin <syin@broadcom.com>"); +MODULE_DESCRIPTION("Broadcom Capri pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v3 5/6] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-12-11 18:37 ` [PATCH v3 5/6] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin @ 2013-12-12 20:54 ` Linus Walleij 2013-12-13 10:22 ` Mark Brown 2013-12-18 23:56 ` Sherman Yin 0 siblings, 2 replies; 85+ messages in thread From: Linus Walleij @ 2013-12-12 20:54 UTC (permalink / raw) To: Sherman Yin, Mark Brown Cc: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Wed, Dec 11, 2013 at 7:37 PM, Sherman Yin <syin@broadcom.com> wrote: > Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > Reviewed-by: Christian Daudt <bcm@fixthebug.org> > Reviewed-by: Matt Porter <matt.porter@linaro.org> > --- > v3: Re-work driver to be based on generic pin config. Moved config selection > from Kconfig to bcm_defconfig. (...) > +#define CAPRI_PIN_SHIFT(type, param) \ > + (CAPRI_ ## type ## _PIN_REG_ ## param ## _SHIFT) > + > +#define CAPRI_PIN_MASK(type, param) \ > + (CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK) > + > +/* Macro to update reg with new pin config param */ > +#define CAPRI_PIN_UPDATE(reg, type, param, val) \ > + (((reg) & ~CAPRI_PIN_MASK(type, param)) | \ > + (((val) << CAPRI_PIN_SHIFT(type, param)) & CAPRI_PIN_MASK(type, param))) Yuck! Are you sure you cannot convert these to static inlines and make them much simpler in the process? We do have an optimizing compiler, you don't need to do everything on one line... besides we're not on the hotpath. > +/* > + * Write to the register using the value and mask if current value is different > + */ > +static void capri_reg_write(struct pinctrl_dev *pctldev, > + void __iomem *reg, > + u32 val, > + u32 mask) > +{ > + u32 old_val; > + u32 new_val; > + > + old_val = readl(reg); > + new_val = (old_val & ~mask) | (val & mask); > + > + if (new_val == old_val) { > + dev_dbg(pctldev->dev, > + "Reg 0x%p=0x%x (no change)\n", > + reg, old_val); > + return; > + } > + > + dev_dbg(pctldev->dev, > + "Reg 0x%p change from 0x%x to 0x%x\n", > + reg, old_val, new_val); > + writel(new_val, reg); > +} This is a reimplementation of regmap for MMIO. See drivers/base/regmap/regmap-mmio.c Notice how regmap_update_bits() is used throughout the kernel. If you want to do this, use regmap. > + case PIN_CONFIG_DRIVE_STRENGTH: > + /* Valid range is 2-16 mA, even numbers only */ > + if ((arg < 2) || (arg > 16) || (arg % 2)) { > + dev_err(pctldev->dev, > + "Invalid Drive Strength value (%d) for " > + "pin %s (%d). Valid values are " > + "(2..16) mA, even numbers only.\n", > + arg, pdata->pins[pin].name, pin); > + return -EINVAL; > + } > + *val = CAPRI_PIN_UPDATE(*val, STD, DRV_STR, (arg/2)-1); > + *mask |= CAPRI_STD_PIN_REG_DRV_STR_MASK; > + break; Hm rather nice integer math... > +/* Goes through the configs and update register val/mask */ > +static int capri_i2c_pin_update(struct pinctrl_dev *pctldev, > + unsigned pin, > + unsigned long *configs, > + unsigned num_configs, > + u32 *val, > + u32 *mask) > +{ > + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); > + int i; > + enum pin_config_param param; > + u16 arg; > + > + for (i = 0; i < num_configs; i++) { > + param = pinconf_to_config_param(configs[i]); > + arg = pinconf_to_config_argument(configs[i]); > + > + switch (param) { > + case PIN_CONFIG_BIAS_PULL_UP: > + if ((arg < 1) || (arg > 7)) { > + dev_err(pctldev->dev, > + "Invalid Pull Up value (%d) for pin %s " > + "(%d). Valid values are (1..7).\n", > + arg, pdata->pins[pin].name, pin); > + return -EINVAL; > + } No don't do that as mentioned in the other patch. Pass pull up strength in Ohms. Then have a translation table here, and do some best-effort fuzzy match. > + /* Different pins have different configuration options */ > + switch (pin_type) { > + case CAPRI_PIN_TYPE_STD: > + rc = capri_std_pin_update(pctldev, pin, configs, num_configs, > + &cfg_val, &cfg_mask); > + break; > + > + case CAPRI_PIN_TYPE_I2C: > + rc = capri_i2c_pin_update(pctldev, pin, configs, num_configs, > + &cfg_val, &cfg_mask); > + break; > + > + case CAPRI_PIN_TYPE_HDMI: > + rc = capri_hdmi_pin_update(pctldev, pin, configs, num_configs, > + &cfg_val, &cfg_mask); > + break; This is really nice and elegant. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 5/6] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-12-12 20:54 ` Linus Walleij @ 2013-12-13 10:22 ` Mark Brown 2013-12-19 0:12 ` Sherman Yin 2013-12-18 23:56 ` Sherman Yin 1 sibling, 1 reply; 85+ messages in thread From: Mark Brown @ 2013-12-13 10:22 UTC (permalink / raw) To: Linus Walleij Cc: Sherman Yin, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org [-- Attachment #1: Type: text/plain, Size: 405 bytes --] On Thu, Dec 12, 2013 at 09:54:50PM +0100, Linus Walleij wrote: > This is a reimplementation of regmap for MMIO. > See drivers/base/regmap/regmap-mmio.c > Notice how regmap_update_bits() is used throughout the > kernel. > If you want to do this, use regmap. Or if this is very performance sensitive (which I'd not expect for pinctrl) there's a helper in review at the minute which just uses a spinlock. [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 836 bytes --] ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 5/6] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-12-13 10:22 ` Mark Brown @ 2013-12-19 0:12 ` Sherman Yin 0 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-12-19 0:12 UTC (permalink / raw) To: Mark Brown, Linus Walleij Cc: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On 13-12-13 02:22 AM, Mark Brown wrote: > On Thu, Dec 12, 2013 at 09:54:50PM +0100, Linus Walleij wrote: > >> This is a reimplementation of regmap for MMIO. >> See drivers/base/regmap/regmap-mmio.c >> Notice how regmap_update_bits() is used throughout the >> kernel. > >> If you want to do this, use regmap. > > Or if this is very performance sensitive (which I'd not expect for > pinctrl) there's a helper in review at the minute which just uses a > spinlock. > Thanks Mark. It's not expected to be performance sensitive, so I'll probably go with regmap. Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 5/6] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-12-12 20:54 ` Linus Walleij 2013-12-13 10:22 ` Mark Brown @ 2013-12-18 23:56 ` Sherman Yin 2013-12-21 2:31 ` Sherman Yin 1 sibling, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-12-18 23:56 UTC (permalink / raw) To: Linus Walleij, Mark Brown Cc: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On 13-12-12 12:54 PM, Linus Walleij wrote: >> +#define CAPRI_PIN_SHIFT(type, param) \ >> + (CAPRI_ ## type ## _PIN_REG_ ## param ## _SHIFT) >> + >> +#define CAPRI_PIN_MASK(type, param) \ >> + (CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK) >> + >> +/* Macro to update reg with new pin config param */ >> +#define CAPRI_PIN_UPDATE(reg, type, param, val) \ >> + (((reg) & ~CAPRI_PIN_MASK(type, param)) | \ >> + (((val) << CAPRI_PIN_SHIFT(type, param)) & CAPRI_PIN_MASK(type, param))) > > Yuck! Are you sure you cannot convert these to static inlines and > make them much simpler in the process? > > We do have an optimizing compiler, you don't need to do > everything on one line... besides we're not on the hotpath. If I were to convert the first 2 #defines to functions, it would either be a 2-level switch statement or a 2D lookup table. IMO both of these options are more difficult to read than this simple concatenation, so I really rather keep them this way. CAPRI_PIN_UPDATE, OTOH, doesn't require any concatenation so I can easily make that into an inline. > >> +/* >> + * Write to the register using the value and mask if current value is different >> + */ >> +static void capri_reg_write(struct pinctrl_dev *pctldev, >> + void __iomem *reg, >> + u32 val, >> + u32 mask) >> +{ >> + u32 old_val; >> + u32 new_val; >> + >> + old_val = readl(reg); >> + new_val = (old_val & ~mask) | (val & mask); >> + >> + if (new_val == old_val) { >> + dev_dbg(pctldev->dev, >> + "Reg 0x%p=0x%x (no change)\n", >> + reg, old_val); >> + return; >> + } >> + >> + dev_dbg(pctldev->dev, >> + "Reg 0x%p change from 0x%x to 0x%x\n", >> + reg, old_val, new_val); >> + writel(new_val, reg); >> +} > > This is a reimplementation of regmap for MMIO. > See drivers/base/regmap/regmap-mmio.c > Notice how regmap_update_bits() is used throughout the > kernel. > > If you want to do this, use regmap. Ok. > >> + case PIN_CONFIG_DRIVE_STRENGTH: >> + /* Valid range is 2-16 mA, even numbers only */ >> + if ((arg < 2) || (arg > 16) || (arg % 2)) { >> + dev_err(pctldev->dev, >> + "Invalid Drive Strength value (%d) for " >> + "pin %s (%d). Valid values are " >> + "(2..16) mA, even numbers only.\n", >> + arg, pdata->pins[pin].name, pin); >> + return -EINVAL; >> + } >> + *val = CAPRI_PIN_UPDATE(*val, STD, DRV_STR, (arg/2)-1); >> + *mask |= CAPRI_STD_PIN_REG_DRV_STR_MASK; >> + break; > > Hm rather nice integer math... Sorry, I can't tell if you are being sarcastic :) Drive strength is represented by 3 bits in the register. If the values were 2-14 I could have done some bit-checking instead of those 3 conditions in the if statement. Or, if we use a enum of 0-7 then the check is much easier. But as we discussed re: pull-up resistance, we rather let users specify real numbers. The (arg/2)-1 is just to convert the mA into the 3 bits. >> +/* Goes through the configs and update register val/mask */ >> +static int capri_i2c_pin_update(struct pinctrl_dev *pctldev, >> + unsigned pin, >> + unsigned long *configs, >> + unsigned num_configs, >> + u32 *val, >> + u32 *mask) >> +{ >> + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); >> + int i; >> + enum pin_config_param param; >> + u16 arg; >> + >> + for (i = 0; i < num_configs; i++) { >> + param = pinconf_to_config_param(configs[i]); >> + arg = pinconf_to_config_argument(configs[i]); >> + >> + switch (param) { >> + case PIN_CONFIG_BIAS_PULL_UP: >> + if ((arg < 1) || (arg > 7)) { >> + dev_err(pctldev->dev, >> + "Invalid Pull Up value (%d) for pin %s " >> + "(%d). Valid values are (1..7).\n", >> + arg, pdata->pins[pin].name, pin); >> + return -EINVAL; >> + } > > No don't do that as mentioned in the other patch. Pass pull up strength > in Ohms. > > Then have a translation table here, and do some best-effort fuzzy match. Sure. I'm just going to error out if the user-supplied value is off, since it is very clear what is acceptable from the binding documentation. >> + /* Different pins have different configuration options */ >> + switch (pin_type) { >> + case CAPRI_PIN_TYPE_STD: >> + rc = capri_std_pin_update(pctldev, pin, configs, num_configs, >> + &cfg_val, &cfg_mask); >> + break; >> + >> + case CAPRI_PIN_TYPE_I2C: >> + rc = capri_i2c_pin_update(pctldev, pin, configs, num_configs, >> + &cfg_val, &cfg_mask); >> + break; >> + >> + case CAPRI_PIN_TYPE_HDMI: >> + rc = capri_hdmi_pin_update(pctldev, pin, configs, num_configs, >> + &cfg_val, &cfg_mask); >> + break; > > This is really nice and elegant. Thanks. :) Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v3 5/6] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-12-18 23:56 ` Sherman Yin @ 2013-12-21 2:31 ` Sherman Yin 0 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-12-21 2:31 UTC (permalink / raw) To: Linus Walleij, Mark Brown Cc: Mark Rutland, devicetree@vger.kernel.org, Christian Daudt, Russell King, Heiko Stübner, Pawel Moll, Ian Campbell, Stephen Warren, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring, bcm-kernel-feedback-list, Rob Landley, Grant Likely, Matt Porter, linux-arm-kernel@lists.infradead.org On 13-12-18 03:56 PM, Sherman Yin wrote: > On 13-12-12 12:54 PM, Linus Walleij wrote: >>> +/* >>> + * Write to the register using the value and mask if current value >>> is different >>> + */ >>> +static void capri_reg_write(struct pinctrl_dev *pctldev, >>> + void __iomem *reg, >>> + u32 val, >>> + u32 mask) >>> +{ >>> + u32 old_val; >>> + u32 new_val; >>> + >>> + old_val = readl(reg); >>> + new_val = (old_val & ~mask) | (val & mask); >>> + >>> + if (new_val == old_val) { >>> + dev_dbg(pctldev->dev, >>> + "Reg 0x%p=0x%x (no change)\n", >>> + reg, old_val); >>> + return; >>> + } >>> + >>> + dev_dbg(pctldev->dev, >>> + "Reg 0x%p change from 0x%x to 0x%x\n", >>> + reg, old_val, new_val); >>> + writel(new_val, reg); >>> +} >> >> This is a reimplementation of regmap for MMIO. >> See drivers/base/regmap/regmap-mmio.c >> Notice how regmap_update_bits() is used throughout the >> kernel. >> >> If you want to do this, use regmap. > > Ok. As you can see in v4 of my patchset, I've changed my driver to use the mmio regmap. However, as I was tracing through regmap_update_bits(), it looks like I have to go through a lot of checks and function pointers just to do a simple write to a register. Also, I have to select REGMAP_MMIO which brings in a bunch of code as well. I understand the benefits of using common code, but in this case it seems there is a lot of extra code and run-time overhead to use regmap. In the end it also doesn't buy much in terms of functionality. Just a quick note - it looks like the 2nd parameter of regmap_update_bits() wants the offset of a register (offset from regmap_mmio_context.regs). So calling the parameter "reg" is a little confusing, at least in the MMIO case. Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v3 6/6] pinctrl: Enable pinctrl for Broadcom Capri SoCs 2013-12-11 18:37 ` [PATCH v3 0/6] Add Broadcom Capri pinctrl driver Sherman Yin ` (4 preceding siblings ...) 2013-12-11 18:37 ` [PATCH v3 5/6] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin @ 2013-12-11 18:37 ` Sherman Yin 2013-12-21 2:13 ` [PATCH v4 0/6] Add Broadcom Capri pinctrl driver Sherman Yin 6 siblings, 0 replies; 85+ messages in thread From: Sherman Yin @ 2013-12-11 18:37 UTC (permalink / raw) To: Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, Sherman Yin, bcm-kernel-feedback-list, linux-arm-kernel Enable pinctrl for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- v3: no change v2: no change --- arch/arm/boot/dts/bcm11351.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index b0c0610..dd8e878 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -142,4 +142,8 @@ status = "disabled"; }; + pinctrl@35004800 { + compatible = "brcm,capri-pinctrl"; + reg = <0x35004800 0x430>; + }; }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v4 0/6] Add Broadcom Capri pinctrl driver 2013-12-11 18:37 ` [PATCH v3 0/6] Add Broadcom Capri pinctrl driver Sherman Yin ` (5 preceding siblings ...) 2013-12-11 18:37 ` [PATCH v3 6/6] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin @ 2013-12-21 2:13 ` Sherman Yin 2013-12-21 2:13 ` [PATCH v4 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin ` (3 more replies) 6 siblings, 4 replies; 85+ messages in thread From: Sherman Yin @ 2013-12-21 2:13 UTC (permalink / raw) To: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin The following patches adds a pinctrl driver for Broadcom Capri (BCM281xx) SoCs. The first patch, adding the void * to pinctrl_pin_desc, has been previously discussed with LinusW. See this thread: http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/165880.html --- v4: - removed patch to add new properties to generic pinconfig (merged) - Updated bias-pull-up property to accept R value in Ohms instead of an enum - move PINCTRL_CAPRI to defconfig - Use regmap MMIO v3: Re-worked driver to be based on generic pinconfig, addressed review comments and other supporting changes: - moved config selection from Kconfig to defconfig - added slew-rate, input enable, input disable properties for generic pinconfig - added a description for PINCTRL config v2: Use hyphens instead of underscore in DT property names. Sherman Yin (6): pinctrl: Add void * to pinctrl_pin_desc pinctrl: Adds slew-rate, input-enable/disable pinctrl: Make PINCTRL selectable by defconfig/menuconfig pinctrl: Add pinctrl binding for Broadcom Capri SoCs ARM: pinctrl: Add Broadcom Capri pinctrl driver pinctrl: Enable pinctrl for Broadcom Capri SoCs .../bindings/pinctrl/brcm,capri-pinctrl.txt | 429 ++++++ .../bindings/pinctrl/pinctrl-bindings.txt | 3 + arch/arm/boot/dts/bcm11351.dtsi | 4 + arch/arm/configs/bcm_defconfig | 5 + drivers/pinctrl/Kconfig | 13 +- drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinconf-generic.c | 4 + drivers/pinctrl/pinctrl-capri.c | 1408 ++++++++++++++++++++ include/linux/pinctrl/pinconf-generic.h | 4 + include/linux/pinctrl/pinctrl.h | 2 + 10 files changed, 1872 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-capri.c -- 1.7.9.5 ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v4 1/4] pinctrl: Add void * to pinctrl_pin_desc 2013-12-21 2:13 ` [PATCH v4 0/6] Add Broadcom Capri pinctrl driver Sherman Yin @ 2013-12-21 2:13 ` Sherman Yin 2014-01-16 13:26 ` Linus Walleij [not found] ` <1387592016-13740-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> ` (2 subsequent siblings) 3 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-12-21 2:13 UTC (permalink / raw) To: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin drv_data is added to the pinctrl_pin_desc for drivers to define additional driver-specific per-pin data. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- v4: no change v3: no change v2: no change --- include/linux/pinctrl/pinctrl.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index fefb886..cc8e1af 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -32,10 +32,12 @@ struct device_node; * pins, pads or other muxable units in this struct * @number: unique pin number from the global pin number space * @name: a name for this pin + * @drv_data: driver-defined per-pin data. pinctrl core does not touch this */ struct pinctrl_pin_desc { unsigned number; const char *name; + void *drv_data; }; /* Convenience macro to define a single named or anonymous pin descriptor */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v4 1/4] pinctrl: Add void * to pinctrl_pin_desc 2013-12-21 2:13 ` [PATCH v4 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin @ 2014-01-16 13:26 ` Linus Walleij 0 siblings, 0 replies; 85+ messages in thread From: Linus Walleij @ 2014-01-16 13:26 UTC (permalink / raw) To: Sherman Yin Cc: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Sat, Dec 21, 2013 at 3:13 AM, Sherman Yin <syin@broadcom.com> wrote: > drv_data is added to the pinctrl_pin_desc for drivers to define additional > driver-specific per-pin data. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > Reviewed-by: Christian Daudt <bcm@fixthebug.org> > Reviewed-by: Matt Porter <matt.porter@linaro.org> This patch applied as well. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <1387592016-13740-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>]
* [PATCH v4 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs [not found] ` <1387592016-13740-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2013-12-21 2:13 ` Sherman Yin 2014-01-07 17:15 ` Linus Walleij [not found] ` <1387592016-13740-3-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> 0 siblings, 2 replies; 85+ messages in thread From: Sherman Yin @ 2013-12-21 2:13 UTC (permalink / raw) To: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-doc-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sherman Yin Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> Reviewed-by: Christian Daudt <bcm-xK7y4jjYLqYh9ZMKESR00Q@public.gmane.org> Reviewed-by: Matt Porter <matt.porter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- v4: Changed valid values for "bias-pull-up" property for I2C pins. Expanded pin configuration node example. v3: Use generic pin config properties instead of brcm-specific ones. Clarified pin types (standard, i2c, hdmi). v2: Use hyphens instead of underscore in DT property names. --- .../bindings/pinctrl/brcm,capri-pinctrl.txt | 461 ++++++++++++++++++++ 1 file changed, 461 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt new file mode 100644 index 0000000..9e9e9ef --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt @@ -0,0 +1,461 @@ +Broadcom Capri Pin Controller + +This is a pin controller for the Broadcom BCM281xx SoC family, which includes +BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs. + +=== Pin Controller Node === + +Required Properties: + +- compatible: Must be "brcm,capri-pinctrl". +- reg: Base address of the PAD Controller register block and the size + of the block. + +For example, the following is the bare minimum node: + + pinctrl@35004800 { + compatible = "brcm,capri-pinctrl"; + reg = <0x35004800 0x430>; + }; + +As a pin controller device, in addition to the required properties, this node +should also contain the pin configuration nodes that client devices reference, +if any. + +=== Pin Configuration Node === + +Each pin configuration node is a sub-node of the pin controller node and is a +container of an arbitrary number of subnodes, called pin group nodes in this +document. + +Please refer to the pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the definition of a +"pin configuration node". + +=== Pin Group Node === + +A pin group node specifies the desired pin mux and/or pin configuration for an +arbitrary number of pins. The name of the pin group node is optional and not +used. + +A pin group node only affects the properties specified in the node, and has no +effect on any properties that are omitted. + +The pin group node accepts a subset of the generic pin config properties. For +details generic pin config properties, please refer to pinctrl-bindings.txt +and <include/linux/pinctrl/pinconfig-generic.h>. + +Each pin controlled by this pin controller belong to one of three types: +Standard, I2C, and HDMI. Each type accepts a different set of pin config +properties. A list of pins and their types is provided below. + +Required Properties (applicable to all pins): + +- pins: Multiple strings. Specifies the name(s) of one or more pins to + be configured by this node. + +Optional Properties (for standard pins): + +- function: String. Specifies the pin mux selection. Values + must be one of: "alt1", "alt2", "alt3", "alt4" +- input-schmitt-enable: No arguments. Enable schmitt-trigger mode. +- input-schmitt-disable: No arguments. Disable schmitt-trigger mode. +- bias-pull-up: No arguments. Pull up on pin. +- bias-pull-down: No arguments. Pull down on pin. +- bias-disable: No arguments. Disable pin bias. +- slew-rate: Integer. Meaning depends on configured pin mux: + *_SCL or *_SDA: + 0: Standard(100kbps)& Fast(400kbps) mode + 1: Highspeed (3.4Mbps) mode + IC_DM or IC_DP: + 0: normal slew rate + 1: fast slew rate + Otherwise: + 0: fast slew rate + 1: normal slew rate +- input-enable: No arguements. Enable input (does not affect + output.) +- input-disable: No arguements. Disable input (does not affect + output.) +- drive-strength: Integer. Drive strength in mA. Valid values are + 2, 4, 6, 8, 10, 12, 14, 16 mA. + +Optional Properties (for I2C pins): + +- function: String. Specifies the pin mux selection. Values + must be one of: "alt1", "alt2", "alt3", "alt4" +- bias-pull-up: Integer. Pull up strength in Ohm. There are 3 + pull-up resisitors (1.2k, 1.8k, 2.7k) available + in parallel for I2C pins, so the valid values + are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm. +- bias-disable: No arguments. Disable pin bias. +- slew-rate: Integer. Meaning depends on configured pin mux: + *_SCL or *_SDA: + 0: Standard(100kbps)& Fast(400kbps) mode + 1: Highspeed (3.4Mbps) mode + IC_DM or IC_DP: + 0: normal slew rate + 1: fast slew rate + Otherwise: + 0: fast slew rate + 1: normal slew rate +- input-enable: No arguements. Enable input (does not affect + output.) +- input-disable: No arguements. Disable input (does not affect + output.) + +Optional Properties (for HDMI pins): + +- function: String. Specifies the pin mux selection. Values + must be one of: "alt1", "alt2", "alt3", "alt4" +- slew-rate: Integer. Controls slew rate. + 0: Standard(100kbps)& Fast(400kbps) mode + 1: Highspeed (3.4Mbps) mode +- input-enable: No arguements. Enable input (does not affect + output.) +- input-disable: No arguements. Disable input (does not affect + output.) + +Example: +// pin controller node +pinctrl@35004800 { + compatible = "brcm,capri-pinctrl"; + reg = <0x35004800 0x430>; + + // pin configuration node + dev_a_default: dev_a_active { + //group node defining 1 standard pin + grp_1 { + pins = "std_pin1"; + function = "alt1"; + input-schmitt-enable; + bias-disable; + slew-rate = <1>; + drive-strength = <4>; + }; + + // group node defining 2 I2C pins + grp_2 { + pins = "i2c_pin1", "i2c_pin2"; + function = "alt2"; + bias-pull-up = <720>; + input-enable; + }; + + // group node defining 2 HDMI pins + grp_3 { + pins = "hdmi_pin1", "hdmi_pin2"; + function = "alt3"; + slew-rate = <1>; + }; + + // other pin group nodes + ... + }; + + // other pin configuration nodes + ... +}; + +In the example above, "dev_a_active" is a pin configuration node with a number +of sub-nodes. In the pin group node "grp_1", one pin, "std_pin1", is defined in +the "pins" property. Thus, the remaining properties in the "grp_1" node applies +only to this pin, including the following settings: + - setting pinmux to "alt1" + - enabling schmitt-trigger (hystersis) mode + - disabling pin bias + - setting the slew-rate to 1 + - setting the drive strength to 4 mA +Note that neither "input-enable" nor "input-disable" was specified - the pinctrl +subsystem will therefore leave this property unchanged from whatever state it +was in before applying these changes. + +The "pins" property in the pin group node "grp_2" specifies two pins - +"i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node, +therefore, applies to both of these pins. The properties include: + - setting pinmux to "alt2" + - setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors + in parallel) + - enabling both pins' input +"slew-rate" is not specified in this pin group node, so the slew-rate for these +pins are left as-is. + +Finally, "grp_3" defines two HDMI pins. The following properties are applied to +both pins: + - setting pinmux to "alt3" + - setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps + Highspeed mode +The input is neither enabled or disabled, and is left untouched. + +=== Pin Names and Type === + +The following are valid pin names and their pin types: + + "adcsync", Standard + "bat_rm", Standard + "bsc1_scl", I2C + "bsc1_sda", I2C + "bsc2_scl", I2C + "bsc2_sda", I2C + "classgpwr", Standard + "clk_cx8", Standard + "clkout_0", Standard + "clkout_1", Standard + "clkout_2", Standard + "clkout_3", Standard + "clkreq_in_0", Standard + "clkreq_in_1", Standard + "cws_sys_req1", Standard + "cws_sys_req2", Standard + "cws_sys_req3", Standard + "digmic1_clk", Standard + "digmic1_dq", Standard + "digmic2_clk", Standard + "digmic2_dq", Standard + "gpen13", Standard + "gpen14", Standard + "gpen15", Standard + "gpio00", Standard + "gpio01", Standard + "gpio02", Standard + "gpio03", Standard + "gpio04", Standard + "gpio05", Standard + "gpio06", Standard + "gpio07", Standard + "gpio08", Standard + "gpio09", Standard + "gpio10", Standard + "gpio11", Standard + "gpio12", Standard + "gpio13", Standard + "gpio14", Standard + "gps_pablank", Standard + "gps_tmark", Standard + "hdmi_scl", HDMI + "hdmi_sda", HDMI + "ic_dm", Standard + "ic_dp", Standard + "kp_col_ip_0", Standard + "kp_col_ip_1", Standard + "kp_col_ip_2", Standard + "kp_col_ip_3", Standard + "kp_row_op_0", Standard + "kp_row_op_1", Standard + "kp_row_op_2", Standard + "kp_row_op_3", Standard + "lcd_b_0", Standard + "lcd_b_1", Standard + "lcd_b_2", Standard + "lcd_b_3", Standard + "lcd_b_4", Standard + "lcd_b_5", Standard + "lcd_b_6", Standard + "lcd_b_7", Standard + "lcd_g_0", Standard + "lcd_g_1", Standard + "lcd_g_2", Standard + "lcd_g_3", Standard + "lcd_g_4", Standard + "lcd_g_5", Standard + "lcd_g_6", Standard + "lcd_g_7", Standard + "lcd_hsync", Standard + "lcd_oe", Standard + "lcd_pclk", Standard + "lcd_r_0", Standard + "lcd_r_1", Standard + "lcd_r_2", Standard + "lcd_r_3", Standard + "lcd_r_4", Standard + "lcd_r_5", Standard + "lcd_r_6", Standard + "lcd_r_7", Standard + "lcd_vsync", Standard + "mdmgpio0", Standard + "mdmgpio1", Standard + "mdmgpio2", Standard + "mdmgpio3", Standard + "mdmgpio4", Standard + "mdmgpio5", Standard + "mdmgpio6", Standard + "mdmgpio7", Standard + "mdmgpio8", Standard + "mphi_data_0", Standard + "mphi_data_1", Standard + "mphi_data_2", Standard + "mphi_data_3", Standard + "mphi_data_4", Standard + "mphi_data_5", Standard + "mphi_data_6", Standard + "mphi_data_7", Standard + "mphi_data_8", Standard + "mphi_data_9", Standard + "mphi_data_10", Standard + "mphi_data_11", Standard + "mphi_data_12", Standard + "mphi_data_13", Standard + "mphi_data_14", Standard + "mphi_data_15", Standard + "mphi_ha0", Standard + "mphi_hat0", Standard + "mphi_hat1", Standard + "mphi_hce0_n", Standard + "mphi_hce1_n", Standard + "mphi_hrd_n", Standard + "mphi_hwr_n", Standard + "mphi_run0", Standard + "mphi_run1", Standard + "mtx_scan_clk", Standard + "mtx_scan_data", Standard + "nand_ad_0", Standard + "nand_ad_1", Standard + "nand_ad_2", Standard + "nand_ad_3", Standard + "nand_ad_4", Standard + "nand_ad_5", Standard + "nand_ad_6", Standard + "nand_ad_7", Standard + "nand_ale", Standard + "nand_cen_0", Standard + "nand_cen_1", Standard + "nand_cle", Standard + "nand_oen", Standard + "nand_rdy_0", Standard + "nand_rdy_1", Standard + "nand_wen", Standard + "nand_wp", Standard + "pc1", Standard + "pc2", Standard + "pmu_int", Standard + "pmu_scl", I2C + "pmu_sda", I2C + "rfst2g_mtsloten3g", Standard + "rgmii_0_rx_ctl", Standard + "rgmii_0_rxc", Standard + "rgmii_0_rxd_0", Standard + "rgmii_0_rxd_1", Standard + "rgmii_0_rxd_2", Standard + "rgmii_0_rxd_3", Standard + "rgmii_0_tx_ctl", Standard + "rgmii_0_txc", Standard + "rgmii_0_txd_0", Standard + "rgmii_0_txd_1", Standard + "rgmii_0_txd_2", Standard + "rgmii_0_txd_3", Standard + "rgmii_1_rx_ctl", Standard + "rgmii_1_rxc", Standard + "rgmii_1_rxd_0", Standard + "rgmii_1_rxd_1", Standard + "rgmii_1_rxd_2", Standard + "rgmii_1_rxd_3", Standard + "rgmii_1_tx_ctl", Standard + "rgmii_1_txc", Standard + "rgmii_1_txd_0", Standard + "rgmii_1_txd_1", Standard + "rgmii_1_txd_2", Standard + "rgmii_1_txd_3", Standard + "rgmii_gpio_0", Standard + "rgmii_gpio_1", Standard + "rgmii_gpio_2", Standard + "rgmii_gpio_3", Standard + "rtxdata2g_txdata3g1", Standard + "rtxen2g_txdata3g2", Standard + "rxdata3g0", Standard + "rxdata3g1", Standard + "rxdata3g2", Standard + "sdio1_clk", Standard + "sdio1_cmd", Standard + "sdio1_data_0", Standard + "sdio1_data_1", Standard + "sdio1_data_2", Standard + "sdio1_data_3", Standard + "sdio4_clk", Standard + "sdio4_cmd", Standard + "sdio4_data_0", Standard + "sdio4_data_1", Standard + "sdio4_data_2", Standard + "sdio4_data_3", Standard + "sim_clk", Standard + "sim_data", Standard + "sim_det", Standard + "sim_resetn", Standard + "sim2_clk", Standard + "sim2_data", Standard + "sim2_det", Standard + "sim2_resetn", Standard + "sri_c", Standard + "sri_d", Standard + "sri_e", Standard + "ssp_extclk", Standard + "ssp0_clk", Standard + "ssp0_fs", Standard + "ssp0_rxd", Standard + "ssp0_txd", Standard + "ssp2_clk", Standard + "ssp2_fs_0", Standard + "ssp2_fs_1", Standard + "ssp2_fs_2", Standard + "ssp2_fs_3", Standard + "ssp2_rxd_0", Standard + "ssp2_rxd_1", Standard + "ssp2_txd_0", Standard + "ssp2_txd_1", Standard + "ssp3_clk", Standard + "ssp3_fs", Standard + "ssp3_rxd", Standard + "ssp3_txd", Standard + "ssp4_clk", Standard + "ssp4_fs", Standard + "ssp4_rxd", Standard + "ssp4_txd", Standard + "ssp5_clk", Standard + "ssp5_fs", Standard + "ssp5_rxd", Standard + "ssp5_txd", Standard + "ssp6_clk", Standard + "ssp6_fs", Standard + "ssp6_rxd", Standard + "ssp6_txd", Standard + "stat_1", Standard + "stat_2", Standard + "sysclken", Standard + "traceclk", Standard + "tracedt00", Standard + "tracedt01", Standard + "tracedt02", Standard + "tracedt03", Standard + "tracedt04", Standard + "tracedt05", Standard + "tracedt06", Standard + "tracedt07", Standard + "tracedt08", Standard + "tracedt09", Standard + "tracedt10", Standard + "tracedt11", Standard + "tracedt12", Standard + "tracedt13", Standard + "tracedt14", Standard + "tracedt15", Standard + "txdata3g0", Standard + "txpwrind", Standard + "uartb1_ucts", Standard + "uartb1_urts", Standard + "uartb1_urxd", Standard + "uartb1_utxd", Standard + "uartb2_urxd", Standard + "uartb2_utxd", Standard + "uartb3_ucts", Standard + "uartb3_urts", Standard + "uartb3_urxd", Standard + "uartb3_utxd", Standard + "uartb4_ucts", Standard + "uartb4_urts", Standard + "uartb4_urxd", Standard + "uartb4_utxd", Standard + "vc_cam1_scl", I2C + "vc_cam1_sda", I2C + "vc_cam2_scl", I2C + "vc_cam2_sda", I2C + "vc_cam3_scl", I2C + "vc_cam3_sda", I2C -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v4 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2013-12-21 2:13 ` [PATCH v4 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin @ 2014-01-07 17:15 ` Linus Walleij 2014-01-07 20:45 ` Sherman Yin [not found] ` <1387592016-13740-3-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> 1 sibling, 1 reply; 85+ messages in thread From: Linus Walleij @ 2014-01-07 17:15 UTC (permalink / raw) To: Sherman Yin Cc: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Sat, Dec 21, 2013 at 3:13 AM, Sherman Yin <syin@broadcom.com> wrote: > Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > Reviewed-by: Christian Daudt <bcm@fixthebug.org> > Reviewed-by: Matt Porter <matt.porter@linaro.org> > --- > v4: Changed valid values for "bias-pull-up" property for I2C pins. Expanded > pin configuration node example. Starting to look real good... > +Optional Properties (for standard pins): > + > +- function: String. Specifies the pin mux selection. Values > + must be one of: "alt1", "alt2", "alt3", "alt4" > +- input-schmitt-enable: No arguments. Enable schmitt-trigger mode. > +- input-schmitt-disable: No arguments. Disable schmitt-trigger mode. > +- bias-pull-up: No arguments. Pull up on pin. > +- bias-pull-down: No arguments. Pull down on pin. > +- bias-disable: No arguments. Disable pin bias. > +- slew-rate: Integer. Meaning depends on configured pin mux: > + *_SCL or *_SDA: > + 0: Standard(100kbps)& Fast(400kbps) mode > + 1: Highspeed (3.4Mbps) mode > + IC_DM or IC_DP: > + 0: normal slew rate > + 1: fast slew rate > + Otherwise: > + 0: fast slew rate > + 1: normal slew rate > +- input-enable: No arguements. Enable input (does not affect > + output.) > +- input-disable: No arguements. Disable input (does not affect > + output.) > +- drive-strength: Integer. Drive strength in mA. Valid values are > + 2, 4, 6, 8, 10, 12, 14, 16 mA. Also patch Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt Since you're adding generic properties. > +Optional Properties (for I2C pins): > + > +- function: String. Specifies the pin mux selection. Values > + must be one of: "alt1", "alt2", "alt3", "alt4" > +- bias-pull-up: Integer. Pull up strength in Ohm. There are 3 > + pull-up resisitors (1.2k, 1.8k, 2.7k) available > + in parallel for I2C pins, so the valid values > + are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm. Also patch Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt > +- bias-disable: No arguments. Disable pin bias. > +- slew-rate: Integer. Meaning depends on configured pin mux: > + *_SCL or *_SDA: > + 0: Standard(100kbps)& Fast(400kbps) mode > + 1: Highspeed (3.4Mbps) mode > + IC_DM or IC_DP: > + 0: normal slew rate > + 1: fast slew rate > + Otherwise: > + 0: fast slew rate > + 1: normal slew rate Hm that does not seem generic though, so let's not add this to the generic bindings. > +- input-enable: No arguements. Enable input (does not affect > + output.) > +- input-disable: No arguements. Disable input (does not affect > + output.) > + > +Optional Properties (for HDMI pins): > + > +- function: String. Specifies the pin mux selection. Values > + must be one of: "alt1", "alt2", "alt3", "alt4" > +- slew-rate: Integer. Controls slew rate. > + 0: Standard(100kbps)& Fast(400kbps) mode > + 1: Highspeed (3.4Mbps) mode Hmmmm slew rate is not specifiec in "bps" but rather in something like volts per second. But maybe it's best to keep this value driver-specific. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v4 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2014-01-07 17:15 ` Linus Walleij @ 2014-01-07 20:45 ` Sherman Yin 2014-01-14 10:16 ` Linus Walleij 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2014-01-07 20:45 UTC (permalink / raw) To: Linus Walleij Cc: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On 14-01-07 09:15 AM, Linus Walleij wrote: > On Sat, Dec 21, 2013 at 3:13 AM, Sherman Yin <syin@broadcom.com> wrote: >> +Optional Properties (for standard pins): >> + >> +- function: String. Specifies the pin mux selection. Values >> + must be one of: "alt1", "alt2", "alt3", "alt4" >> +- input-schmitt-enable: No arguments. Enable schmitt-trigger mode. >> +- input-schmitt-disable: No arguments. Disable schmitt-trigger mode. >> +- bias-pull-up: No arguments. Pull up on pin. >> +- bias-pull-down: No arguments. Pull down on pin. >> +- bias-disable: No arguments. Disable pin bias. >> +- slew-rate: Integer. Meaning depends on configured pin mux: >> + *_SCL or *_SDA: >> + 0: Standard(100kbps)& Fast(400kbps) mode >> + 1: Highspeed (3.4Mbps) mode >> + IC_DM or IC_DP: >> + 0: normal slew rate >> + 1: fast slew rate >> + Otherwise: >> + 0: fast slew rate >> + 1: normal slew rate >> +- input-enable: No arguements. Enable input (does not affect >> + output.) >> +- input-disable: No arguements. Disable input (does not affect >> + output.) >> +- drive-strength: Integer. Drive strength in mA. Valid values are >> + 2, 4, 6, 8, 10, 12, 14, 16 mA. > > Also patch > Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt > Since you're adding generic properties. Please note that I removed from this patchset the patch that you've merged to your for-next branch already: https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=8ba3f4d00078e7a49c60c0bd6298f29402c3a0a0 Is that what you wanted to see in pinctrl-bindings.txt, or is there something else you want to see added to that txt file? I didn't want to add the description of slew-rate arguments there because this is capri-specific. I'm not quite sure what else to add. >> +Optional Properties (for I2C pins): >> + >> +- function: String. Specifies the pin mux selection. Values >> + must be one of: "alt1", "alt2", "alt3", "alt4" >> +- bias-pull-up: Integer. Pull up strength in Ohm. There are 3 >> + pull-up resisitors (1.2k, 1.8k, 2.7k) available >> + in parallel for I2C pins, so the valid values >> + are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm. > > Also patch > Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt That doc already says bias-pull-up is specified in Ohm, and the specific values are chip-specific, so I don't think they should be mentioned there. >> +- bias-disable: No arguments. Disable pin bias. >> +- slew-rate: Integer. Meaning depends on configured pin mux: >> + *_SCL or *_SDA: >> + 0: Standard(100kbps)& Fast(400kbps) mode >> + 1: Highspeed (3.4Mbps) mode >> + IC_DM or IC_DP: >> + 0: normal slew rate >> + 1: fast slew rate >> + Otherwise: >> + 0: fast slew rate >> + 1: normal slew rate > > Hm that does not seem generic though, so let's not add this to the > generic bindings. > >> +- input-enable: No arguements. Enable input (does not affect >> + output.) >> +- input-disable: No arguements. Disable input (does not affect >> + output.) >> + >> +Optional Properties (for HDMI pins): >> + >> +- function: String. Specifies the pin mux selection. Values >> + must be one of: "alt1", "alt2", "alt3", "alt4" >> +- slew-rate: Integer. Controls slew rate. >> + 0: Standard(100kbps)& Fast(400kbps) mode >> + 1: Highspeed (3.4Mbps) mode > > Hmmmm slew rate is not specifiec in "bps" but rather in > something like volts per second. But maybe it's best to keep > this value driver-specific. Right, I think the slew-rates values are capri specific. Thanks for the review. Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v4 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2014-01-07 20:45 ` Sherman Yin @ 2014-01-14 10:16 ` Linus Walleij 2014-01-14 19:00 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2014-01-14 10:16 UTC (permalink / raw) To: Sherman Yin Cc: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Tue, Jan 7, 2014 at 9:45 PM, Sherman Yin <syin@broadcom.com> wrote: > On 14-01-07 09:15 AM, Linus Walleij wrote: > Is that what you wanted to see in pinctrl-bindings.txt, or is there > something else you want to see added to that txt file? I didn't want to add > the description of slew-rate arguments there because this is capri-specific. > I'm not quite sure what else to add. (...) > That doc already says bias-pull-up is specified in Ohm, and the specific > values are chip-specific, so I don't think they should be mentioned there. You're right, forget about this. I didn't realize the pinctrl bindings doc was that good... >>> +Optional Properties (for HDMI pins): >>> + >>> +- function: String. Specifies the pin mux selection. >>> Values >>> + must be one of: "alt1", "alt2", "alt3", >>> "alt4" >>> +- slew-rate: Integer. Controls slew rate. >>> + 0: Standard(100kbps)& >>> Fast(400kbps) mode >>> + 1: Highspeed (3.4Mbps) mode >> >> Hmmmm slew rate is not specifiec in "bps" but rather in >> something like volts per second. But maybe it's best to keep >> this value driver-specific. > > Right, I think the slew-rates values are capri specific. OK Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v4 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2014-01-14 10:16 ` Linus Walleij @ 2014-01-14 19:00 ` Sherman Yin 2014-01-15 9:40 ` Linus Walleij 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2014-01-14 19:00 UTC (permalink / raw) To: Linus Walleij Cc: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On 14-01-14 02:16 AM, Linus Walleij wrote: > On Tue, Jan 7, 2014 at 9:45 PM, Sherman Yin <syin@broadcom.com> wrote: >> On 14-01-07 09:15 AM, Linus Walleij wrote: > >> Is that what you wanted to see in pinctrl-bindings.txt, or is there >> something else you want to see added to that txt file? I didn't want to add >> the description of slew-rate arguments there because this is capri-specific. >> I'm not quite sure what else to add. > (...) >> That doc already says bias-pull-up is specified in Ohm, and the specific >> values are chip-specific, so I don't think they should be mentioned there. > > You're right, forget about this. I didn't realize the pinctrl bindings doc > was that good... > >>>> +Optional Properties (for HDMI pins): >>>> + >>>> +- function: String. Specifies the pin mux selection. >>>> Values >>>> + must be one of: "alt1", "alt2", "alt3", >>>> "alt4" >>>> +- slew-rate: Integer. Controls slew rate. >>>> + 0: Standard(100kbps)& >>>> Fast(400kbps) mode >>>> + 1: Highspeed (3.4Mbps) mode >>> >>> Hmmmm slew rate is not specifiec in "bps" but rather in >>> something like volts per second. But maybe it's best to keep >>> this value driver-specific. >> >> Right, I think the slew-rates values are capri specific. > > OK > Great! Is there anything else you would like to see changed before this patchset can be accepted? Thanks, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v4 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2014-01-14 19:00 ` Sherman Yin @ 2014-01-15 9:40 ` Linus Walleij 2014-01-15 16:39 ` Mark Rutland 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2014-01-15 9:40 UTC (permalink / raw) To: Sherman Yin Cc: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Tue, Jan 14, 2014 at 8:00 PM, Sherman Yin <syin@broadcom.com> wrote: > Great! Is there anything else you would like to see changed before this > patchset can be accepted? I'd like some sign of life from the DT binding maintainers. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v4 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs 2014-01-15 9:40 ` Linus Walleij @ 2014-01-15 16:39 ` Mark Rutland 0 siblings, 0 replies; 85+ messages in thread From: Mark Rutland @ 2014-01-15 16:39 UTC (permalink / raw) To: Linus Walleij Cc: Sherman Yin, Mark Brown, rob.herring@calxeda.com, Heiko Stübner, Pawel Moll, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, grant.likely@linaro.org, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org Hi Linus, On Wed, Jan 15, 2014 at 09:40:53AM +0000, Linus Walleij wrote: > On Tue, Jan 14, 2014 at 8:00 PM, Sherman Yin <syin@broadcom.com> wrote: > > > Great! Is there anything else you would like to see changed before this > > patchset can be accepted? > > I'd like some sign of life from the DT binding maintainers. Let's check the electrocardiogram... _ _ _ _ _ __________/ \ ________/ \ _____/ \ ___/ \ ___/ \ __ \_/ \_/ \_/ \_/ \_/ I don't see anything objectionable in the binding. Linus, if you think that this binding is sane, feel free to add my ack. Cheers, Mark. ^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <1387592016-13740-3-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH v4 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs [not found] ` <1387592016-13740-3-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2014-01-16 13:24 ` Linus Walleij 0 siblings, 0 replies; 85+ messages in thread From: Linus Walleij @ 2014-01-16 13:24 UTC (permalink / raw) To: Sherman Yin Cc: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, bcm-kernel-feedback-list, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Sat, Dec 21, 2013 at 3:13 AM, Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote: > Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. > > Signed-off-by: Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> > Reviewed-by: Christian Daudt <bcm-xK7y4jjYLqYh9ZMKESR00Q@public.gmane.org> > Reviewed-by: Matt Porter <matt.porter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > v4: Changed valid values for "bias-pull-up" property for I2C pins. Expanded > pin configuration node example. Patch applied with Mark R's ACK and a copy of his ECG. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-12-21 2:13 ` [PATCH v4 0/6] Add Broadcom Capri pinctrl driver Sherman Yin 2013-12-21 2:13 ` [PATCH v4 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin [not found] ` <1387592016-13740-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2013-12-21 2:13 ` Sherman Yin 2014-01-16 13:19 ` Linus Walleij 2013-12-21 2:13 ` [PATCH v4 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin 3 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-12-21 2:13 UTC (permalink / raw) To: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- v4: - PINCTRL selected in Kconfig, PINCTRL_CAPRI selected in bcm_defconfig - make use of regmap - change CAPRI_PIN_UPDATE from macro to inline function. - Handle pull-up strength arg in Ohm instead of enum v3: Re-work driver to be based on generic pin config. Moved config selection from Kconfig to bcm_defconfig. v2: Use hyphens instead of underscore in DT property names. --- arch/arm/configs/bcm_defconfig | 1 + arch/arm/mach-bcm/Kconfig | 1 + drivers/pinctrl/Kconfig | 12 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-capri.c | 1454 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 1469 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-capri.c diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig index 287ac1d..bede511 100644 --- a/arch/arm/configs/bcm_defconfig +++ b/arch/arm/configs/bcm_defconfig @@ -126,3 +126,4 @@ CONFIG_CRC_ITU_T=y CONFIG_CRC7=y CONFIG_XZ_DEC=y CONFIG_AVERAGE=y +CONFIG_PINCTRL_CAPRI=y diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 9fe6d88..b1aa6a9 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -25,6 +25,7 @@ config ARCH_BCM_MOBILE select TICK_ONESHOT select CACHE_L2X0 select HAVE_ARM_ARCH_TIMER + select PINCTRL help This enables support for systems based on Broadcom mobile SoCs. It currently supports the 'BCM281XX' family, which includes diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 33f9dc1..a9f6405 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -104,6 +104,18 @@ config PINCTRL_BCM2835 select PINMUX select PINCONF +config PINCTRL_CAPRI + bool "Broadcom Capri pinctrl driver" + select PINMUX + select PINCONF + select GENERIC_PINCONF + select REGMAP_MMIO + help + Say Y here to support Broadcom Capri pinctrl driver, which is used for + the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, + BCM28145, and BCM28155 SoCs. This driver requires the pinctrl + framework. GPIO is provided by a separate GPIO driver. + config PINCTRL_IMX bool select PINMUX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 4f7be29..86cac40 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o +obj-$(CONFIG_PINCTRL_CAPRI) += pinctrl-capri.o obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o diff --git a/drivers/pinctrl/pinctrl-capri.c b/drivers/pinctrl/pinctrl-capri.c new file mode 100644 index 0000000..4669c53 --- /dev/null +++ b/drivers/pinctrl/pinctrl-capri.c @@ -0,0 +1,1454 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include "core.h" +#include "pinctrl-utils.h" + +/* Capri Pin Control Registers Definitions */ + +/* Function Select bits are the same for all pin control registers */ +#define CAPRI_PIN_REG_F_SEL_MASK 0x0700 +#define CAPRI_PIN_REG_F_SEL_SHIFT 8 + +/* Standard pin register */ +#define CAPRI_STD_PIN_REG_DRV_STR_MASK 0x0007 +#define CAPRI_STD_PIN_REG_DRV_STR_SHIFT 0 +#define CAPRI_STD_PIN_REG_INPUT_DIS_MASK 0x0008 +#define CAPRI_STD_PIN_REG_INPUT_DIS_SHIFT 3 +#define CAPRI_STD_PIN_REG_SLEW_MASK 0x0010 +#define CAPRI_STD_PIN_REG_SLEW_SHIFT 4 +#define CAPRI_STD_PIN_REG_PULL_UP_MASK 0x0020 +#define CAPRI_STD_PIN_REG_PULL_UP_SHIFT 5 +#define CAPRI_STD_PIN_REG_PULL_DN_MASK 0x0040 +#define CAPRI_STD_PIN_REG_PULL_DN_SHIFT 6 +#define CAPRI_STD_PIN_REG_HYST_MASK 0x0080 +#define CAPRI_STD_PIN_REG_HYST_SHIFT 7 + +/* I2C pin register */ +#define CAPRI_I2C_PIN_REG_INPUT_DIS_MASK 0x0004 +#define CAPRI_I2C_PIN_REG_INPUT_DIS_SHIFT 2 +#define CAPRI_I2C_PIN_REG_SLEW_MASK 0x0008 +#define CAPRI_I2C_PIN_REG_SLEW_SHIFT 3 +#define CAPRI_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070 +#define CAPRI_I2C_PIN_REG_PULL_UP_STR_SHIFT 4 + +/* HDMI pin register */ +#define CAPRI_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008 +#define CAPRI_HDMI_PIN_REG_INPUT_DIS_SHIFT 3 +#define CAPRI_HDMI_PIN_REG_MODE_MASK 0x0010 +#define CAPRI_HDMI_PIN_REG_MODE_SHIFT 4 + +/** + * capri_pin_type - types of pin register + */ +enum capri_pin_type { + CAPRI_PIN_TYPE_UNKNOWN = 0, + CAPRI_PIN_TYPE_STD, + CAPRI_PIN_TYPE_I2C, + CAPRI_PIN_TYPE_HDMI, +}; + +static enum capri_pin_type std_pin = CAPRI_PIN_TYPE_STD; +static enum capri_pin_type i2c_pin = CAPRI_PIN_TYPE_I2C; +static enum capri_pin_type hdmi_pin = CAPRI_PIN_TYPE_HDMI; + +/** + * capri_pin_function- define pin function + */ +struct capri_pin_function { + const char *name; + const char * const *groups; + const unsigned ngroups; +}; + +/** + * capri_pinctrl_data - Broadcom-specific pinctrl data + * @reg_base - base of pinctrl registers + */ +struct capri_pinctrl_data { + void __iomem *reg_base; + + /* List of all pins */ + const struct pinctrl_pin_desc *pins; + const unsigned npins; + + const struct capri_pin_function *functions; + const unsigned nfunctions; + + struct regmap *regmap; +}; + +/* + * Pin number definition. The order here must be the same as defined in the + * PADCTRLREG block in the RDB. + */ +#define CAPRI_PIN_ADCSYNC 0 +#define CAPRI_PIN_BAT_RM 1 +#define CAPRI_PIN_BSC1_SCL 2 +#define CAPRI_PIN_BSC1_SDA 3 +#define CAPRI_PIN_BSC2_SCL 4 +#define CAPRI_PIN_BSC2_SDA 5 +#define CAPRI_PIN_CLASSGPWR 6 +#define CAPRI_PIN_CLK_CX8 7 +#define CAPRI_PIN_CLKOUT_0 8 +#define CAPRI_PIN_CLKOUT_1 9 +#define CAPRI_PIN_CLKOUT_2 10 +#define CAPRI_PIN_CLKOUT_3 11 +#define CAPRI_PIN_CLKREQ_IN_0 12 +#define CAPRI_PIN_CLKREQ_IN_1 13 +#define CAPRI_PIN_CWS_SYS_REQ1 14 +#define CAPRI_PIN_CWS_SYS_REQ2 15 +#define CAPRI_PIN_CWS_SYS_REQ3 16 +#define CAPRI_PIN_DIGMIC1_CLK 17 +#define CAPRI_PIN_DIGMIC1_DQ 18 +#define CAPRI_PIN_DIGMIC2_CLK 19 +#define CAPRI_PIN_DIGMIC2_DQ 20 +#define CAPRI_PIN_GPEN13 21 +#define CAPRI_PIN_GPEN14 22 +#define CAPRI_PIN_GPEN15 23 +#define CAPRI_PIN_GPIO00 24 +#define CAPRI_PIN_GPIO01 25 +#define CAPRI_PIN_GPIO02 26 +#define CAPRI_PIN_GPIO03 27 +#define CAPRI_PIN_GPIO04 28 +#define CAPRI_PIN_GPIO05 29 +#define CAPRI_PIN_GPIO06 30 +#define CAPRI_PIN_GPIO07 31 +#define CAPRI_PIN_GPIO08 32 +#define CAPRI_PIN_GPIO09 33 +#define CAPRI_PIN_GPIO10 34 +#define CAPRI_PIN_GPIO11 35 +#define CAPRI_PIN_GPIO12 36 +#define CAPRI_PIN_GPIO13 37 +#define CAPRI_PIN_GPIO14 38 +#define CAPRI_PIN_GPS_PABLANK 39 +#define CAPRI_PIN_GPS_TMARK 40 +#define CAPRI_PIN_HDMI_SCL 41 +#define CAPRI_PIN_HDMI_SDA 42 +#define CAPRI_PIN_IC_DM 43 +#define CAPRI_PIN_IC_DP 44 +#define CAPRI_PIN_KP_COL_IP_0 45 +#define CAPRI_PIN_KP_COL_IP_1 46 +#define CAPRI_PIN_KP_COL_IP_2 47 +#define CAPRI_PIN_KP_COL_IP_3 48 +#define CAPRI_PIN_KP_ROW_OP_0 49 +#define CAPRI_PIN_KP_ROW_OP_1 50 +#define CAPRI_PIN_KP_ROW_OP_2 51 +#define CAPRI_PIN_KP_ROW_OP_3 52 +#define CAPRI_PIN_LCD_B_0 53 +#define CAPRI_PIN_LCD_B_1 54 +#define CAPRI_PIN_LCD_B_2 55 +#define CAPRI_PIN_LCD_B_3 56 +#define CAPRI_PIN_LCD_B_4 57 +#define CAPRI_PIN_LCD_B_5 58 +#define CAPRI_PIN_LCD_B_6 59 +#define CAPRI_PIN_LCD_B_7 60 +#define CAPRI_PIN_LCD_G_0 61 +#define CAPRI_PIN_LCD_G_1 62 +#define CAPRI_PIN_LCD_G_2 63 +#define CAPRI_PIN_LCD_G_3 64 +#define CAPRI_PIN_LCD_G_4 65 +#define CAPRI_PIN_LCD_G_5 66 +#define CAPRI_PIN_LCD_G_6 67 +#define CAPRI_PIN_LCD_G_7 68 +#define CAPRI_PIN_LCD_HSYNC 69 +#define CAPRI_PIN_LCD_OE 70 +#define CAPRI_PIN_LCD_PCLK 71 +#define CAPRI_PIN_LCD_R_0 72 +#define CAPRI_PIN_LCD_R_1 73 +#define CAPRI_PIN_LCD_R_2 74 +#define CAPRI_PIN_LCD_R_3 75 +#define CAPRI_PIN_LCD_R_4 76 +#define CAPRI_PIN_LCD_R_5 77 +#define CAPRI_PIN_LCD_R_6 78 +#define CAPRI_PIN_LCD_R_7 79 +#define CAPRI_PIN_LCD_VSYNC 80 +#define CAPRI_PIN_MDMGPIO0 81 +#define CAPRI_PIN_MDMGPIO1 82 +#define CAPRI_PIN_MDMGPIO2 83 +#define CAPRI_PIN_MDMGPIO3 84 +#define CAPRI_PIN_MDMGPIO4 85 +#define CAPRI_PIN_MDMGPIO5 86 +#define CAPRI_PIN_MDMGPIO6 87 +#define CAPRI_PIN_MDMGPIO7 88 +#define CAPRI_PIN_MDMGPIO8 89 +#define CAPRI_PIN_MPHI_DATA_0 90 +#define CAPRI_PIN_MPHI_DATA_1 91 +#define CAPRI_PIN_MPHI_DATA_2 92 +#define CAPRI_PIN_MPHI_DATA_3 93 +#define CAPRI_PIN_MPHI_DATA_4 94 +#define CAPRI_PIN_MPHI_DATA_5 95 +#define CAPRI_PIN_MPHI_DATA_6 96 +#define CAPRI_PIN_MPHI_DATA_7 97 +#define CAPRI_PIN_MPHI_DATA_8 98 +#define CAPRI_PIN_MPHI_DATA_9 99 +#define CAPRI_PIN_MPHI_DATA_10 100 +#define CAPRI_PIN_MPHI_DATA_11 101 +#define CAPRI_PIN_MPHI_DATA_12 102 +#define CAPRI_PIN_MPHI_DATA_13 103 +#define CAPRI_PIN_MPHI_DATA_14 104 +#define CAPRI_PIN_MPHI_DATA_15 105 +#define CAPRI_PIN_MPHI_HA0 106 +#define CAPRI_PIN_MPHI_HAT0 107 +#define CAPRI_PIN_MPHI_HAT1 108 +#define CAPRI_PIN_MPHI_HCE0_N 109 +#define CAPRI_PIN_MPHI_HCE1_N 110 +#define CAPRI_PIN_MPHI_HRD_N 111 +#define CAPRI_PIN_MPHI_HWR_N 112 +#define CAPRI_PIN_MPHI_RUN0 113 +#define CAPRI_PIN_MPHI_RUN1 114 +#define CAPRI_PIN_MTX_SCAN_CLK 115 +#define CAPRI_PIN_MTX_SCAN_DATA 116 +#define CAPRI_PIN_NAND_AD_0 117 +#define CAPRI_PIN_NAND_AD_1 118 +#define CAPRI_PIN_NAND_AD_2 119 +#define CAPRI_PIN_NAND_AD_3 120 +#define CAPRI_PIN_NAND_AD_4 121 +#define CAPRI_PIN_NAND_AD_5 122 +#define CAPRI_PIN_NAND_AD_6 123 +#define CAPRI_PIN_NAND_AD_7 124 +#define CAPRI_PIN_NAND_ALE 125 +#define CAPRI_PIN_NAND_CEN_0 126 +#define CAPRI_PIN_NAND_CEN_1 127 +#define CAPRI_PIN_NAND_CLE 128 +#define CAPRI_PIN_NAND_OEN 129 +#define CAPRI_PIN_NAND_RDY_0 130 +#define CAPRI_PIN_NAND_RDY_1 131 +#define CAPRI_PIN_NAND_WEN 132 +#define CAPRI_PIN_NAND_WP 133 +#define CAPRI_PIN_PC1 134 +#define CAPRI_PIN_PC2 135 +#define CAPRI_PIN_PMU_INT 136 +#define CAPRI_PIN_PMU_SCL 137 +#define CAPRI_PIN_PMU_SDA 138 +#define CAPRI_PIN_RFST2G_MTSLOTEN3G 139 +#define CAPRI_PIN_RGMII_0_RX_CTL 140 +#define CAPRI_PIN_RGMII_0_RXC 141 +#define CAPRI_PIN_RGMII_0_RXD_0 142 +#define CAPRI_PIN_RGMII_0_RXD_1 143 +#define CAPRI_PIN_RGMII_0_RXD_2 144 +#define CAPRI_PIN_RGMII_0_RXD_3 145 +#define CAPRI_PIN_RGMII_0_TX_CTL 146 +#define CAPRI_PIN_RGMII_0_TXC 147 +#define CAPRI_PIN_RGMII_0_TXD_0 148 +#define CAPRI_PIN_RGMII_0_TXD_1 149 +#define CAPRI_PIN_RGMII_0_TXD_2 150 +#define CAPRI_PIN_RGMII_0_TXD_3 151 +#define CAPRI_PIN_RGMII_1_RX_CTL 152 +#define CAPRI_PIN_RGMII_1_RXC 153 +#define CAPRI_PIN_RGMII_1_RXD_0 154 +#define CAPRI_PIN_RGMII_1_RXD_1 155 +#define CAPRI_PIN_RGMII_1_RXD_2 156 +#define CAPRI_PIN_RGMII_1_RXD_3 157 +#define CAPRI_PIN_RGMII_1_TX_CTL 158 +#define CAPRI_PIN_RGMII_1_TXC 159 +#define CAPRI_PIN_RGMII_1_TXD_0 160 +#define CAPRI_PIN_RGMII_1_TXD_1 161 +#define CAPRI_PIN_RGMII_1_TXD_2 162 +#define CAPRI_PIN_RGMII_1_TXD_3 163 +#define CAPRI_PIN_RGMII_GPIO_0 164 +#define CAPRI_PIN_RGMII_GPIO_1 165 +#define CAPRI_PIN_RGMII_GPIO_2 166 +#define CAPRI_PIN_RGMII_GPIO_3 167 +#define CAPRI_PIN_RTXDATA2G_TXDATA3G1 168 +#define CAPRI_PIN_RTXEN2G_TXDATA3G2 169 +#define CAPRI_PIN_RXDATA3G0 170 +#define CAPRI_PIN_RXDATA3G1 171 +#define CAPRI_PIN_RXDATA3G2 172 +#define CAPRI_PIN_SDIO1_CLK 173 +#define CAPRI_PIN_SDIO1_CMD 174 +#define CAPRI_PIN_SDIO1_DATA_0 175 +#define CAPRI_PIN_SDIO1_DATA_1 176 +#define CAPRI_PIN_SDIO1_DATA_2 177 +#define CAPRI_PIN_SDIO1_DATA_3 178 +#define CAPRI_PIN_SDIO4_CLK 179 +#define CAPRI_PIN_SDIO4_CMD 180 +#define CAPRI_PIN_SDIO4_DATA_0 181 +#define CAPRI_PIN_SDIO4_DATA_1 182 +#define CAPRI_PIN_SDIO4_DATA_2 183 +#define CAPRI_PIN_SDIO4_DATA_3 184 +#define CAPRI_PIN_SIM_CLK 185 +#define CAPRI_PIN_SIM_DATA 186 +#define CAPRI_PIN_SIM_DET 187 +#define CAPRI_PIN_SIM_RESETN 188 +#define CAPRI_PIN_SIM2_CLK 189 +#define CAPRI_PIN_SIM2_DATA 190 +#define CAPRI_PIN_SIM2_DET 191 +#define CAPRI_PIN_SIM2_RESETN 192 +#define CAPRI_PIN_SRI_C 193 +#define CAPRI_PIN_SRI_D 194 +#define CAPRI_PIN_SRI_E 195 +#define CAPRI_PIN_SSP_EXTCLK 196 +#define CAPRI_PIN_SSP0_CLK 197 +#define CAPRI_PIN_SSP0_FS 198 +#define CAPRI_PIN_SSP0_RXD 199 +#define CAPRI_PIN_SSP0_TXD 200 +#define CAPRI_PIN_SSP2_CLK 201 +#define CAPRI_PIN_SSP2_FS_0 202 +#define CAPRI_PIN_SSP2_FS_1 203 +#define CAPRI_PIN_SSP2_FS_2 204 +#define CAPRI_PIN_SSP2_FS_3 205 +#define CAPRI_PIN_SSP2_RXD_0 206 +#define CAPRI_PIN_SSP2_RXD_1 207 +#define CAPRI_PIN_SSP2_TXD_0 208 +#define CAPRI_PIN_SSP2_TXD_1 209 +#define CAPRI_PIN_SSP3_CLK 210 +#define CAPRI_PIN_SSP3_FS 211 +#define CAPRI_PIN_SSP3_RXD 212 +#define CAPRI_PIN_SSP3_TXD 213 +#define CAPRI_PIN_SSP4_CLK 214 +#define CAPRI_PIN_SSP4_FS 215 +#define CAPRI_PIN_SSP4_RXD 216 +#define CAPRI_PIN_SSP4_TXD 217 +#define CAPRI_PIN_SSP5_CLK 218 +#define CAPRI_PIN_SSP5_FS 219 +#define CAPRI_PIN_SSP5_RXD 220 +#define CAPRI_PIN_SSP5_TXD 221 +#define CAPRI_PIN_SSP6_CLK 222 +#define CAPRI_PIN_SSP6_FS 223 +#define CAPRI_PIN_SSP6_RXD 224 +#define CAPRI_PIN_SSP6_TXD 225 +#define CAPRI_PIN_STAT_1 226 +#define CAPRI_PIN_STAT_2 227 +#define CAPRI_PIN_SYSCLKEN 228 +#define CAPRI_PIN_TRACECLK 229 +#define CAPRI_PIN_TRACEDT00 230 +#define CAPRI_PIN_TRACEDT01 231 +#define CAPRI_PIN_TRACEDT02 232 +#define CAPRI_PIN_TRACEDT03 233 +#define CAPRI_PIN_TRACEDT04 234 +#define CAPRI_PIN_TRACEDT05 235 +#define CAPRI_PIN_TRACEDT06 236 +#define CAPRI_PIN_TRACEDT07 237 +#define CAPRI_PIN_TRACEDT08 238 +#define CAPRI_PIN_TRACEDT09 239 +#define CAPRI_PIN_TRACEDT10 240 +#define CAPRI_PIN_TRACEDT11 241 +#define CAPRI_PIN_TRACEDT12 242 +#define CAPRI_PIN_TRACEDT13 243 +#define CAPRI_PIN_TRACEDT14 244 +#define CAPRI_PIN_TRACEDT15 245 +#define CAPRI_PIN_TXDATA3G0 246 +#define CAPRI_PIN_TXPWRIND 247 +#define CAPRI_PIN_UARTB1_UCTS 248 +#define CAPRI_PIN_UARTB1_URTS 249 +#define CAPRI_PIN_UARTB1_URXD 250 +#define CAPRI_PIN_UARTB1_UTXD 251 +#define CAPRI_PIN_UARTB2_URXD 252 +#define CAPRI_PIN_UARTB2_UTXD 253 +#define CAPRI_PIN_UARTB3_UCTS 254 +#define CAPRI_PIN_UARTB3_URTS 255 +#define CAPRI_PIN_UARTB3_URXD 256 +#define CAPRI_PIN_UARTB3_UTXD 257 +#define CAPRI_PIN_UARTB4_UCTS 258 +#define CAPRI_PIN_UARTB4_URTS 259 +#define CAPRI_PIN_UARTB4_URXD 260 +#define CAPRI_PIN_UARTB4_UTXD 261 +#define CAPRI_PIN_VC_CAM1_SCL 262 +#define CAPRI_PIN_VC_CAM1_SDA 263 +#define CAPRI_PIN_VC_CAM2_SCL 264 +#define CAPRI_PIN_VC_CAM2_SDA 265 +#define CAPRI_PIN_VC_CAM3_SCL 266 +#define CAPRI_PIN_VC_CAM3_SDA 267 + +#define CAPRI_PIN_DESC(a, b, c) \ + { .number = a, .name = b, .drv_data = &c##_pin } + +/* + * Pin description definition. The order here must be the same as defined in + * the PADCTRLREG block in the RDB, since the pin number is used as an index + * into this array. + */ +static const struct pinctrl_pin_desc capri_pinctrl_pins[] = { + CAPRI_PIN_DESC(CAPRI_PIN_ADCSYNC, "adcsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_BAT_RM, "bat_rm", std), + CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SCL, "bsc1_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SDA, "bsc1_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SCL, "bsc2_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SDA, "bsc2_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_CLASSGPWR, "classgpwr", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLK_CX8, "clk_cx8", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_0, "clkout_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_1, "clkout_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_2, "clkout_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_3, "clkout_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_0, "clkreq_in_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_1, "clkreq_in_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ1, "cws_sys_req1", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ2, "cws_sys_req2", std), + CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ3, "cws_sys_req3", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_CLK, "digmic1_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_DQ, "digmic1_dq", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_CLK, "digmic2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_DQ, "digmic2_dq", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN13, "gpen13", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN14, "gpen14", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPEN15, "gpen15", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO00, "gpio00", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO01, "gpio01", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO02, "gpio02", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO03, "gpio03", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO04, "gpio04", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO05, "gpio05", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO06, "gpio06", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO07, "gpio07", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO08, "gpio08", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO09, "gpio09", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO10, "gpio10", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO11, "gpio11", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO12, "gpio12", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO13, "gpio13", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPIO14, "gpio14", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPS_PABLANK, "gps_pablank", std), + CAPRI_PIN_DESC(CAPRI_PIN_GPS_TMARK, "gps_tmark", std), + CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SCL, "hdmi_scl", hdmi), + CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SDA, "hdmi_sda", hdmi), + CAPRI_PIN_DESC(CAPRI_PIN_IC_DM, "ic_dm", std), + CAPRI_PIN_DESC(CAPRI_PIN_IC_DP, "ic_dp", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_0, "kp_col_ip_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_1, "kp_col_ip_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_2, "kp_col_ip_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_3, "kp_col_ip_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_0, "kp_row_op_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_1, "kp_row_op_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_2, "kp_row_op_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_3, "kp_row_op_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_0, "lcd_b_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_1, "lcd_b_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_2, "lcd_b_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_3, "lcd_b_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_4, "lcd_b_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_5, "lcd_b_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_6, "lcd_b_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_7, "lcd_b_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_0, "lcd_g_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_1, "lcd_g_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_2, "lcd_g_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_3, "lcd_g_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_4, "lcd_g_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_5, "lcd_g_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_6, "lcd_g_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_7, "lcd_g_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_HSYNC, "lcd_hsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_OE, "lcd_oe", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_PCLK, "lcd_pclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_0, "lcd_r_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_1, "lcd_r_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_2, "lcd_r_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_3, "lcd_r_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_4, "lcd_r_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_5, "lcd_r_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_6, "lcd_r_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_7, "lcd_r_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_LCD_VSYNC, "lcd_vsync", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO0, "mdmgpio0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO1, "mdmgpio1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO2, "mdmgpio2", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO3, "mdmgpio3", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO4, "mdmgpio4", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO5, "mdmgpio5", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO6, "mdmgpio6", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO7, "mdmgpio7", std), + CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO8, "mdmgpio8", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_0, "mphi_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_1, "mphi_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_2, "mphi_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_3, "mphi_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_4, "mphi_data_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_5, "mphi_data_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_6, "mphi_data_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_7, "mphi_data_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_8, "mphi_data_8", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_9, "mphi_data_9", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_10, "mphi_data_10", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_11, "mphi_data_11", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_12, "mphi_data_12", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_13, "mphi_data_13", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_14, "mphi_data_14", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_15, "mphi_data_15", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HA0, "mphi_ha0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT0, "mphi_hat0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT1, "mphi_hat1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE0_N, "mphi_hce0_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE1_N, "mphi_hce1_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HRD_N, "mphi_hrd_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HWR_N, "mphi_hwr_n", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN0, "mphi_run0", std), + CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN1, "mphi_run1", std), + CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_DATA, "mtx_scan_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_0, "nand_ad_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_1, "nand_ad_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_2, "nand_ad_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_3, "nand_ad_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_4, "nand_ad_4", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_5, "nand_ad_5", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_6, "nand_ad_6", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_7, "nand_ad_7", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_ALE, "nand_ale", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_0, "nand_cen_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_1, "nand_cen_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_CLE, "nand_cle", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_OEN, "nand_oen", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_0, "nand_rdy_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_1, "nand_rdy_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_WEN, "nand_wen", std), + CAPRI_PIN_DESC(CAPRI_PIN_NAND_WP, "nand_wp", std), + CAPRI_PIN_DESC(CAPRI_PIN_PC1, "pc1", std), + CAPRI_PIN_DESC(CAPRI_PIN_PC2, "pc2", std), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_INT, "pmu_int", std), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_SCL, "pmu_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_PMU_SDA, "pmu_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXC, "rgmii_0_rxc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXC, "rgmii_0_txc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXC, "rgmii_1_rxc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXC, "rgmii_1_txc", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_RTXDATA2G_TXDATA3G1, "rtxdata2g_txdata3g1", + std), + CAPRI_PIN_DESC(CAPRI_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G0, "rxdata3g0", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G1, "rxdata3g1", std), + CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G2, "rxdata3g2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CLK, "sdio1_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CMD, "sdio1_cmd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_0, "sdio1_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_1, "sdio1_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_2, "sdio1_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_3, "sdio1_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CLK, "sdio4_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CMD, "sdio4_cmd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_0, "sdio4_data_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_1, "sdio4_data_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_2, "sdio4_data_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_3, "sdio4_data_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_CLK, "sim_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_DATA, "sim_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_DET, "sim_det", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM_RESETN, "sim_resetn", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_CLK, "sim2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DATA, "sim2_data", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DET, "sim2_det", std), + CAPRI_PIN_DESC(CAPRI_PIN_SIM2_RESETN, "sim2_resetn", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_C, "sri_c", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_D, "sri_d", std), + CAPRI_PIN_DESC(CAPRI_PIN_SRI_E, "sri_e", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP_EXTCLK, "ssp_extclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_CLK, "ssp0_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_FS, "ssp0_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_RXD, "ssp0_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP0_TXD, "ssp0_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_CLK, "ssp2_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_0, "ssp2_fs_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_1, "ssp2_fs_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_2, "ssp2_fs_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_3, "ssp2_fs_3", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_0, "ssp2_rxd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_1, "ssp2_rxd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_0, "ssp2_txd_0", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_1, "ssp2_txd_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_CLK, "ssp3_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_FS, "ssp3_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_RXD, "ssp3_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP3_TXD, "ssp3_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_CLK, "ssp4_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_FS, "ssp4_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_RXD, "ssp4_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP4_TXD, "ssp4_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_CLK, "ssp5_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_FS, "ssp5_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_RXD, "ssp5_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP5_TXD, "ssp5_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_CLK, "ssp6_clk", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_FS, "ssp6_fs", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_RXD, "ssp6_rxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_SSP6_TXD, "ssp6_txd", std), + CAPRI_PIN_DESC(CAPRI_PIN_STAT_1, "stat_1", std), + CAPRI_PIN_DESC(CAPRI_PIN_STAT_2, "stat_2", std), + CAPRI_PIN_DESC(CAPRI_PIN_SYSCLKEN, "sysclken", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACECLK, "traceclk", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT00, "tracedt00", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT01, "tracedt01", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT02, "tracedt02", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT03, "tracedt03", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT04, "tracedt04", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT05, "tracedt05", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT06, "tracedt06", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT07, "tracedt07", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT08, "tracedt08", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT09, "tracedt09", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT10, "tracedt10", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT11, "tracedt11", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT12, "tracedt12", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT13, "tracedt13", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT14, "tracedt14", std), + CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT15, "tracedt15", std), + CAPRI_PIN_DESC(CAPRI_PIN_TXDATA3G0, "txdata3g0", std), + CAPRI_PIN_DESC(CAPRI_PIN_TXPWRIND, "txpwrind", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UCTS, "uartb1_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URTS, "uartb1_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URXD, "uartb1_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UTXD, "uartb1_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_URXD, "uartb2_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_UTXD, "uartb2_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UCTS, "uartb3_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URTS, "uartb3_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URXD, "uartb3_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UTXD, "uartb3_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UCTS, "uartb4_ucts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URTS, "uartb4_urts", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URXD, "uartb4_urxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UTXD, "uartb4_utxd", std), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c), + CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c), +}; + +static const char * const capri_alt_groups[] = { + "adcsync", + "bat_rm", + "bsc1_scl", + "bsc1_sda", + "bsc2_scl", + "bsc2_sda", + "classgpwr", + "clk_cx8", + "clkout_0", + "clkout_1", + "clkout_2", + "clkout_3", + "clkreq_in_0", + "clkreq_in_1", + "cws_sys_req1", + "cws_sys_req2", + "cws_sys_req3", + "digmic1_clk", + "digmic1_dq", + "digmic2_clk", + "digmic2_dq", + "gpen13", + "gpen14", + "gpen15", + "gpio00", + "gpio01", + "gpio02", + "gpio03", + "gpio04", + "gpio05", + "gpio06", + "gpio07", + "gpio08", + "gpio09", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gps_pablank", + "gps_tmark", + "hdmi_scl", + "hdmi_sda", + "ic_dm", + "ic_dp", + "kp_col_ip_0", + "kp_col_ip_1", + "kp_col_ip_2", + "kp_col_ip_3", + "kp_row_op_0", + "kp_row_op_1", + "kp_row_op_2", + "kp_row_op_3", + "lcd_b_0", + "lcd_b_1", + "lcd_b_2", + "lcd_b_3", + "lcd_b_4", + "lcd_b_5", + "lcd_b_6", + "lcd_b_7", + "lcd_g_0", + "lcd_g_1", + "lcd_g_2", + "lcd_g_3", + "lcd_g_4", + "lcd_g_5", + "lcd_g_6", + "lcd_g_7", + "lcd_hsync", + "lcd_oe", + "lcd_pclk", + "lcd_r_0", + "lcd_r_1", + "lcd_r_2", + "lcd_r_3", + "lcd_r_4", + "lcd_r_5", + "lcd_r_6", + "lcd_r_7", + "lcd_vsync", + "mdmgpio0", + "mdmgpio1", + "mdmgpio2", + "mdmgpio3", + "mdmgpio4", + "mdmgpio5", + "mdmgpio6", + "mdmgpio7", + "mdmgpio8", + "mphi_data_0", + "mphi_data_1", + "mphi_data_2", + "mphi_data_3", + "mphi_data_4", + "mphi_data_5", + "mphi_data_6", + "mphi_data_7", + "mphi_data_8", + "mphi_data_9", + "mphi_data_10", + "mphi_data_11", + "mphi_data_12", + "mphi_data_13", + "mphi_data_14", + "mphi_data_15", + "mphi_ha0", + "mphi_hat0", + "mphi_hat1", + "mphi_hce0_n", + "mphi_hce1_n", + "mphi_hrd_n", + "mphi_hwr_n", + "mphi_run0", + "mphi_run1", + "mtx_scan_clk", + "mtx_scan_data", + "nand_ad_0", + "nand_ad_1", + "nand_ad_2", + "nand_ad_3", + "nand_ad_4", + "nand_ad_5", + "nand_ad_6", + "nand_ad_7", + "nand_ale", + "nand_cen_0", + "nand_cen_1", + "nand_cle", + "nand_oen", + "nand_rdy_0", + "nand_rdy_1", + "nand_wen", + "nand_wp", + "pc1", + "pc2", + "pmu_int", + "pmu_scl", + "pmu_sda", + "rfst2g_mtsloten3g", + "rgmii_0_rx_ctl", + "rgmii_0_rxc", + "rgmii_0_rxd_0", + "rgmii_0_rxd_1", + "rgmii_0_rxd_2", + "rgmii_0_rxd_3", + "rgmii_0_tx_ctl", + "rgmii_0_txc", + "rgmii_0_txd_0", + "rgmii_0_txd_1", + "rgmii_0_txd_2", + "rgmii_0_txd_3", + "rgmii_1_rx_ctl", + "rgmii_1_rxc", + "rgmii_1_rxd_0", + "rgmii_1_rxd_1", + "rgmii_1_rxd_2", + "rgmii_1_rxd_3", + "rgmii_1_tx_ctl", + "rgmii_1_txc", + "rgmii_1_txd_0", + "rgmii_1_txd_1", + "rgmii_1_txd_2", + "rgmii_1_txd_3", + "rgmii_gpio_0", + "rgmii_gpio_1", + "rgmii_gpio_2", + "rgmii_gpio_3", + "rtxdata2g_txdata3g1", + "rtxen2g_txdata3g2", + "rxdata3g0", + "rxdata3g1", + "rxdata3g2", + "sdio1_clk", + "sdio1_cmd", + "sdio1_data_0", + "sdio1_data_1", + "sdio1_data_2", + "sdio1_data_3", + "sdio4_clk", + "sdio4_cmd", + "sdio4_data_0", + "sdio4_data_1", + "sdio4_data_2", + "sdio4_data_3", + "sim_clk", + "sim_data", + "sim_det", + "sim_resetn", + "sim2_clk", + "sim2_data", + "sim2_det", + "sim2_resetn", + "sri_c", + "sri_d", + "sri_e", + "ssp_extclk", + "ssp0_clk", + "ssp0_fs", + "ssp0_rxd", + "ssp0_txd", + "ssp2_clk", + "ssp2_fs_0", + "ssp2_fs_1", + "ssp2_fs_2", + "ssp2_fs_3", + "ssp2_rxd_0", + "ssp2_rxd_1", + "ssp2_txd_0", + "ssp2_txd_1", + "ssp3_clk", + "ssp3_fs", + "ssp3_rxd", + "ssp3_txd", + "ssp4_clk", + "ssp4_fs", + "ssp4_rxd", + "ssp4_txd", + "ssp5_clk", + "ssp5_fs", + "ssp5_rxd", + "ssp5_txd", + "ssp6_clk", + "ssp6_fs", + "ssp6_rxd", + "ssp6_txd", + "stat_1", + "stat_2", + "sysclken", + "traceclk", + "tracedt00", + "tracedt01", + "tracedt02", + "tracedt03", + "tracedt04", + "tracedt05", + "tracedt06", + "tracedt07", + "tracedt08", + "tracedt09", + "tracedt10", + "tracedt11", + "tracedt12", + "tracedt13", + "tracedt14", + "tracedt15", + "txdata3g0", + "txpwrind", + "uartb1_ucts", + "uartb1_urts", + "uartb1_urxd", + "uartb1_utxd", + "uartb2_urxd", + "uartb2_utxd", + "uartb3_ucts", + "uartb3_urts", + "uartb3_urxd", + "uartb3_utxd", + "uartb4_ucts", + "uartb4_urts", + "uartb4_urxd", + "uartb4_utxd", + "vc_cam1_scl", + "vc_cam1_sda", + "vc_cam2_scl", + "vc_cam2_sda", + "vc_cam3_scl", + "vc_cam3_sda", +}; + +/* Every pin can implement all ALT1-ALT4 functions */ +#define CAPRI_PIN_FUNCTION(fcn_name) \ +{ \ + .name = #fcn_name, \ + .groups = capri_alt_groups, \ + .ngroups = ARRAY_SIZE(capri_alt_groups), \ +} + +static const struct capri_pin_function capri_functions[] = { + CAPRI_PIN_FUNCTION(alt1), + CAPRI_PIN_FUNCTION(alt2), + CAPRI_PIN_FUNCTION(alt3), + CAPRI_PIN_FUNCTION(alt4), +}; + +static struct capri_pinctrl_data capri_pinctrl = { + .pins = capri_pinctrl_pins, + .npins = ARRAY_SIZE(capri_pinctrl_pins), + .functions = capri_functions, + .nfunctions = ARRAY_SIZE(capri_functions), +}; + +static inline enum capri_pin_type pin_type_get(struct pinctrl_dev *pctldev, + unsigned pin) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + if (pin >= pdata->npins) + return CAPRI_PIN_TYPE_UNKNOWN; + + return *(enum capri_pin_type *)(pdata->pins[pin].drv_data); +} + +#define CAPRI_PIN_SHIFT(type, param) \ + (CAPRI_ ## type ## _PIN_REG_ ## param ## _SHIFT) + +#define CAPRI_PIN_MASK(type, param) \ + (CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK) + +/* + * This helper function is used to build up the value and mask used to write to + * a pin register, but does not actually write to the register. + */ +static inline void capri_pin_update(u32 *reg_val, u32 *reg_mask, u32 param_val, + u32 param_shift, u32 param_mask) +{ + *reg_val &= ~param_mask; + *reg_val |= (param_val << param_shift) & param_mask; + *reg_mask |= param_mask; +} + +static struct regmap_config capri_pinctrl_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = CAPRI_PIN_VC_CAM3_SDA, +}; + +static int capri_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->npins; +} + +static const char *capri_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->pins[group].name; +} + +static int capri_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pdata->pins[group].number; + *num_pins = 1; + + return 0; +} + +static void capri_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} + +static struct pinctrl_ops capri_pinctrl_ops = { + .get_groups_count = capri_pinctrl_get_groups_count, + .get_group_name = capri_pinctrl_get_group_name, + .get_group_pins = capri_pinctrl_get_group_pins, + .pin_dbg_show = capri_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int capri_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->nfunctions; +} + +static const char *capri_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->functions[function].name; +} + +static int capri_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *groups = pdata->functions[function].groups; + *num_groups = pdata->functions[function].ngroups; + + return 0; +} + +static int capri_pinmux_enable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + const struct capri_pin_function *f = &pdata->functions[function]; + u32 offset = 4 * pdata->pins[group].number; + int rc = 0; + + dev_dbg(pctldev->dev, + "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n", + __func__, f->name, function, pdata->pins[group].name, + pdata->pins[group].number, offset); + + rc = regmap_update_bits(pdata->regmap, offset, CAPRI_PIN_REG_F_SEL_MASK, + function << CAPRI_PIN_REG_F_SEL_SHIFT); + if (rc) + dev_err(pctldev->dev, + "Error updating register for pin %s (%d).\n", + pdata->pins[group].name, pdata->pins[group].number); + + return rc; +} + +static struct pinmux_ops capri_pinctrl_pinmux_ops = { + .get_functions_count = capri_pinctrl_get_fcns_count, + .get_function_name = capri_pinctrl_get_fcn_name, + .get_function_groups = capri_pinctrl_get_fcn_groups, + .enable = capri_pinmux_enable, +}; + +static int capri_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + return -ENOTSUPP; +} + + +/* Goes through the configs and update register val/mask */ +static int capri_std_pin_update(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs, + u32 *val, + u32 *mask) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i; + enum pin_config_param param; + u16 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + arg = (arg >= 1 ? 1 : 0); + capri_pin_update(val, mask, arg, + CAPRI_PIN_SHIFT(STD, HYST), + CAPRI_PIN_MASK(STD, HYST)); + break; + /* + * The pin bias can only be one of pull-up, pull-down, or + * disable. The user does not need to specify a value for the + * property, and the default value from pinconf-generic is + * ignored. + */ + case PIN_CONFIG_BIAS_DISABLE: + capri_pin_update(val, mask, 0, + CAPRI_PIN_SHIFT(STD, PULL_UP), + CAPRI_PIN_MASK(STD, PULL_UP)); + capri_pin_update(val, mask, 0, + CAPRI_PIN_SHIFT(STD, PULL_DN), + CAPRI_PIN_MASK(STD, PULL_DN)); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + capri_pin_update(val, mask, 1, + CAPRI_PIN_SHIFT(STD, PULL_UP), + CAPRI_PIN_MASK(STD, PULL_UP)); + capri_pin_update(val, mask, 0, + CAPRI_PIN_SHIFT(STD, PULL_DN), + CAPRI_PIN_MASK(STD, PULL_DN)); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + capri_pin_update(val, mask, 0, + CAPRI_PIN_SHIFT(STD, PULL_UP), + CAPRI_PIN_MASK(STD, PULL_UP)); + capri_pin_update(val, mask, 1, + CAPRI_PIN_SHIFT(STD, PULL_DN), + CAPRI_PIN_MASK(STD, PULL_DN)); + break; + + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + capri_pin_update(val, mask, arg, + CAPRI_PIN_SHIFT(STD, SLEW), + CAPRI_PIN_MASK(STD, SLEW)); + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + capri_pin_update(val, mask, arg, + CAPRI_PIN_SHIFT(STD, INPUT_DIS), + CAPRI_PIN_MASK(STD, INPUT_DIS)); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + /* Valid range is 2-16 mA, even numbers only */ + if ((arg < 2) || (arg > 16) || (arg % 2)) { + dev_err(pctldev->dev, + "Invalid Drive Strength value (%d) for " + "pin %s (%d). Valid values are " + "(2..16) mA, even numbers only.\n", + arg, pdata->pins[pin].name, pin); + return -EINVAL; + } + capri_pin_update(val, mask, (arg/2)-1, + CAPRI_PIN_SHIFT(STD, DRV_STR), + CAPRI_PIN_MASK(STD, DRV_STR)); + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + +/* + * The pull-up strength for an I2C pin is represented by bits 4-6 in the + * register with the following mapping: + * 0b000: No pull-up + * 0b001: 1200 Ohm + * 0b010: 1800 Ohm + * 0b011: 720 Ohm + * 0b100: 2700 Ohm + * 0b101: 831 Ohm + * 0b110: 1080 Ohm + * 0b111: 568 Ohm + * This array maps pull-up strength in Ohms to register values (1+index). + */ +static const u16 capri_pullup_map[] = {1200, 1800, 720, 2700, 831, 1080, 568}; + +/* Goes through the configs and update register val/mask */ +static int capri_i2c_pin_update(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs, + u32 *val, + u32 *mask) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i, j; + enum pin_config_param param; + u16 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + for (j = 0; j < ARRAY_SIZE(capri_pullup_map); j++) + if (capri_pullup_map[j] == arg) + break; + + if (j == ARRAY_SIZE(capri_pullup_map)) { + dev_err(pctldev->dev, + "Invalid pull-up value (%d) for pin %s " + "(%d). Valid values are 568, 720, 831, " + "1080, 1200, 1800, 2700 Ohms.\n", + arg, pdata->pins[pin].name, pin); + return -EINVAL; + } + + capri_pin_update(val, mask, j+1, + CAPRI_PIN_SHIFT(I2C, PULL_UP_STR), + CAPRI_PIN_MASK(I2C, PULL_UP_STR)); + break; + + case PIN_CONFIG_BIAS_DISABLE: + capri_pin_update(val, mask, 0, + CAPRI_PIN_SHIFT(I2C, PULL_UP_STR), + CAPRI_PIN_MASK(I2C, PULL_UP_STR)); + break; + + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + capri_pin_update(val, mask, arg, + CAPRI_PIN_SHIFT(I2C, SLEW), + CAPRI_PIN_MASK(I2C, SLEW)); + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + capri_pin_update(val, mask, arg, + CAPRI_PIN_SHIFT(I2C, INPUT_DIS), + CAPRI_PIN_MASK(I2C, INPUT_DIS)); + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + +/* Goes through the configs and update register val/mask */ +static int capri_hdmi_pin_update(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs, + u32 *val, + u32 *mask) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i; + enum pin_config_param param; + u16 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + capri_pin_update(val, mask, arg, + CAPRI_PIN_SHIFT(HDMI, MODE), + CAPRI_PIN_MASK(HDMI, MODE)); + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + capri_pin_update(val, mask, arg, + CAPRI_PIN_SHIFT(HDMI, INPUT_DIS), + CAPRI_PIN_MASK(HDMI, INPUT_DIS)); + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + +static int capri_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs) +{ + struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + enum capri_pin_type pin_type; + u32 offset = 4 * pin; + u32 cfg_val, cfg_mask; + int rc; + + cfg_val = 0; + cfg_mask = 0; + pin_type = pin_type_get(pctldev, pin); + + /* Different pins have different configuration options */ + switch (pin_type) { + case CAPRI_PIN_TYPE_STD: + rc = capri_std_pin_update(pctldev, pin, configs, num_configs, + &cfg_val, &cfg_mask); + break; + + case CAPRI_PIN_TYPE_I2C: + rc = capri_i2c_pin_update(pctldev, pin, configs, num_configs, + &cfg_val, &cfg_mask); + break; + + case CAPRI_PIN_TYPE_HDMI: + rc = capri_hdmi_pin_update(pctldev, pin, configs, num_configs, + &cfg_val, &cfg_mask); + break; + + default: + dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n", + pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch pin type */ + + if (rc) + return rc; + + dev_dbg(pctldev->dev, + "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n", + __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask); + + rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); + if (rc) { + dev_err(pctldev->dev, + "Error updating register for pin %s (%d).\n", + pdata->pins[pin].name, pin); + return rc; + } + + return 0; +} + +static struct pinconf_ops capri_pinctrl_pinconf_ops = { + .pin_config_get = capri_pinctrl_pin_config_get, + .pin_config_set = capri_pinctrl_pin_config_set, +}; + +static struct pinctrl_desc capri_pinctrl_desc = { + /* name, pins, npins members initialized in probe function */ + .pctlops = &capri_pinctrl_ops, + .pmxops = &capri_pinctrl_pinmux_ops, + .confops = &capri_pinctrl_pinconf_ops, + .owner = THIS_MODULE, +}; + +int __init capri_pinctrl_probe(struct platform_device *pdev) +{ + struct capri_pinctrl_data *pdata = &capri_pinctrl; + struct resource *res; + struct pinctrl_dev *pctl; + + /* So far We can assume there is only 1 bank of registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Missing MEM resource\n"); + return -ENODEV; + } + + pdata->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pdata->reg_base)) { + dev_err(&pdev->dev, "Failed to ioremap MEM resource\n"); + return -ENODEV; + } + + /* Initialize the dynamic part of pinctrl_desc */ + pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base, + &capri_pinctrl_regmap_config); + if (IS_ERR(pdata->regmap)) { + dev_err(&pdev->dev, "Regmap MMIO init failed.\n"); + return -ENODEV; + } + + capri_pinctrl_desc.name = dev_name(&pdev->dev); + capri_pinctrl_desc.pins = capri_pinctrl.pins; + capri_pinctrl_desc.npins = capri_pinctrl.npins; + + pctl = pinctrl_register(&capri_pinctrl_desc, + &pdev->dev, + pdata); + if (!pctl) { + dev_err(&pdev->dev, "Failed to register pinctrl\n"); + return -ENODEV; + } + + platform_set_drvdata(pdev, pdata); + + return 0; +} + +static struct of_device_id capri_pinctrl_of_match[] = { + { .compatible = "brcm,capri-pinctrl", }, + { }, +}; + +static struct platform_driver capri_pinctrl_driver = { + .driver = { + .name = "bcm-capri-pinctrl", + .owner = THIS_MODULE, + .of_match_table = capri_pinctrl_of_match, + }, +}; + +module_platform_driver_probe(capri_pinctrl_driver, capri_pinctrl_probe); + +MODULE_AUTHOR("Sherman Yin <syin@broadcom.com>"); +MODULE_DESCRIPTION("Broadcom Capri pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2013-12-21 2:13 ` [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin @ 2014-01-16 13:19 ` Linus Walleij 2014-01-17 19:59 ` Sherman Yin 0 siblings, 1 reply; 85+ messages in thread From: Linus Walleij @ 2014-01-16 13:19 UTC (permalink / raw) To: Sherman Yin, arm@kernel.org Cc: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Sat, Dec 21, 2013 at 3:13 AM, Sherman Yin <syin@broadcom.com> wrote: '> Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > Reviewed-by: Christian Daudt <bcm@fixthebug.org> > Reviewed-by: Matt Porter <matt.porter@linaro.org> > --- > v4: - PINCTRL selected in Kconfig, PINCTRL_CAPRI selected in bcm_defconfig > - make use of regmap > - change CAPRI_PIN_UPDATE from macro to inline function. > - Handle pull-up strength arg in Ohm instead of enum Patch applied. It is really good now! It's late before the merge window, but you've done a tremendous work on this driver and I don't want to delay its deployment further. But note: > arch/arm/configs/bcm_defconfig | 1 + > arch/arm/mach-bcm/Kconfig | 1 + I've optimistically applied these two hunks of the patch as well, but if there is any conflict with the ARM SoC tree I will just rebase the patch and pull these *out*. ARM SoC maintainers: be warned if something collides. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2014-01-16 13:19 ` Linus Walleij @ 2014-01-17 19:59 ` Sherman Yin [not found] ` <52D98B99.5050604-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> 0 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2014-01-17 19:59 UTC (permalink / raw) To: Linus Walleij, arm@kernel.org Cc: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On 14-01-16 05:19 AM, Linus Walleij wrote: > On Sat, Dec 21, 2013 at 3:13 AM, Sherman Yin <syin@broadcom.com> wrote: > > '> Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. >> >> Signed-off-by: Sherman Yin <syin@broadcom.com> >> Reviewed-by: Christian Daudt <bcm@fixthebug.org> >> Reviewed-by: Matt Porter <matt.porter@linaro.org> >> --- >> v4: - PINCTRL selected in Kconfig, PINCTRL_CAPRI selected in bcm_defconfig >> - make use of regmap >> - change CAPRI_PIN_UPDATE from macro to inline function. >> - Handle pull-up strength arg in Ohm instead of enum > > Patch applied. It is really good now! It's late before the merge > window, but you've done a tremendous work on this driver and > I don't want to delay its deployment further. Great, thanks for the support and reviews! > But note: > >> arch/arm/configs/bcm_defconfig | 1 + >> arch/arm/mach-bcm/Kconfig | 1 + > > I've optimistically applied these two hunks of the patch as well, > but if there is any conflict with the ARM SoC tree I will just rebase > the patch and pull these *out*. > > ARM SoC maintainers: be warned if something collides. Ok, will keep an eye on this and fix accordingly. Should be simple fixes. Regards, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <52D98B99.5050604-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver [not found] ` <52D98B99.5050604-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @ 2014-01-18 2:56 ` Matt Porter 2014-01-20 8:16 ` Linus Walleij 0 siblings, 1 reply; 85+ messages in thread From: Matt Porter @ 2014-01-18 2:56 UTC (permalink / raw) To: Sherman Yin Cc: Linus Walleij, arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, bcm-kernel-feedback-list, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Fri, Jan 17, 2014 at 11:59:21AM -0800, Sherman Yin wrote: > On 14-01-16 05:19 AM, Linus Walleij wrote: > >On Sat, Dec 21, 2013 at 3:13 AM, Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote: > > > >'> Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. > >> > >>Signed-off-by: Sherman Yin <syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> > >>Reviewed-by: Christian Daudt <bcm-xK7y4jjYLqYh9ZMKESR00Q@public.gmane.org> > >>Reviewed-by: Matt Porter <matt.porter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > >>--- > >>v4: - PINCTRL selected in Kconfig, PINCTRL_CAPRI selected in bcm_defconfig > >> - make use of regmap > >> - change CAPRI_PIN_UPDATE from macro to inline function. > >> - Handle pull-up strength arg in Ohm instead of enum > > > >Patch applied. It is really good now! It's late before the merge > >window, but you've done a tremendous work on this driver and > >I don't want to delay its deployment further. > > Great, thanks for the support and reviews! Very nice! Now after having completely missing something fundamental on my reviews, I feel compelled to bring it up at the 11^H^H12th hour. That is, this is the *only* BCM281xx driver to be named Capri, both in the filename and driver code, but also in the binding compatible. We didn't do that on anything else that's gone upstream to date. This really introduces an unfortunate inconsistency as it obscures which SoC family this binding and driver belong with. I wonder if Linus would accept a rename at this point (too late for 3.14 presumably, but for 3.15) of s/capri/bcm281xx throughout, bcm11351 for the compatible string, as we have for the machine compatible, and also BCM281XX for the Kconfig option. If not, I'll survive, but it pains me to see one thing completely different out of this entire family. If nothing else, it would be great to address the compatible string before this hits the 3.14 release. Linus? -Matt -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2014-01-18 2:56 ` Matt Porter @ 2014-01-20 8:16 ` Linus Walleij 2014-01-20 19:14 ` Sherman Yin 2014-01-21 13:49 ` Matt Porter 0 siblings, 2 replies; 85+ messages in thread From: Linus Walleij @ 2014-01-20 8:16 UTC (permalink / raw) To: Matt Porter Cc: Sherman Yin, arm@kernel.org, Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Sat, Jan 18, 2014 at 3:56 AM, Matt Porter <mporter@linaro.org> wrote: > I wonder if Linus would accept a rename at this point (too late for 3.14 > presumably, but for 3.15) of s/capri/bcm281xx throughout, bcm11351 for > the compatible string, as we have for the machine compatible, and also > BCM281XX for the Kconfig option. Yes, if there is some consensus that this is what we want to do. I can certainly merge that during the 3.14-rc phase for that matter. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2014-01-20 8:16 ` Linus Walleij @ 2014-01-20 19:14 ` Sherman Yin 2014-01-21 12:35 ` Linus Walleij 2014-01-21 13:49 ` Matt Porter 1 sibling, 1 reply; 85+ messages in thread From: Sherman Yin @ 2014-01-20 19:14 UTC (permalink / raw) To: Linus Walleij, Matt Porter Cc: arm@kernel.org, Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On 14-01-20 12:16 AM, Linus Walleij wrote: > On Sat, Jan 18, 2014 at 3:56 AM, Matt Porter <mporter@linaro.org> wrote: > >> I wonder if Linus would accept a rename at this point (too late for 3.14 >> presumably, but for 3.15) of s/capri/bcm281xx throughout, bcm11351 for >> the compatible string, as we have for the machine compatible, and also >> BCM281XX for the Kconfig option. > > Yes, if there is some consensus that this is what we want to do. > > I can certainly merge that during the 3.14-rc phase for that matter. Hi Linus, I'll confirm the new name with Matt before sending out another patch. Which would work better for you - a) a set of patches replacing my previous ones, b) a set of patches on top of my previous ones, c) a single patch on top of my previous ones? d) something else? Thanks, Sherman ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2014-01-20 19:14 ` Sherman Yin @ 2014-01-21 12:35 ` Linus Walleij 0 siblings, 0 replies; 85+ messages in thread From: Linus Walleij @ 2014-01-21 12:35 UTC (permalink / raw) To: Sherman Yin Cc: Matt Porter, arm@kernel.org, Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Mon, Jan 20, 2014 at 8:14 PM, Sherman Yin <syin@broadcom.com> wrote: > I'll confirm the new name with Matt before sending out another patch. Which > would work better for you - a) a set of patches replacing my previous ones, > b) a set of patches on top of my previous ones, c) a single patch on top of > my previous ones? d) something else? (c) The tree goes upstream now, you have to make this fix on top. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver 2014-01-20 8:16 ` Linus Walleij 2014-01-20 19:14 ` Sherman Yin @ 2014-01-21 13:49 ` Matt Porter 1 sibling, 0 replies; 85+ messages in thread From: Matt Porter @ 2014-01-21 13:49 UTC (permalink / raw) To: Linus Walleij Cc: Sherman Yin, arm@kernel.org, Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Mon, Jan 20, 2014 at 09:16:24AM +0100, Linus Walleij wrote: > On Sat, Jan 18, 2014 at 3:56 AM, Matt Porter <mporter@linaro.org> wrote: > > > I wonder if Linus would accept a rename at this point (too late for 3.14 > > presumably, but for 3.15) of s/capri/bcm281xx throughout, bcm11351 for > > the compatible string, as we have for the machine compatible, and also > > BCM281XX for the Kconfig option. > > Yes, if there is some consensus that this is what we want to do. > > I can certainly merge that during the 3.14-rc phase for that matter. Ok, sounds great, thanks. -Matt ^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v4 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs 2013-12-21 2:13 ` [PATCH v4 0/6] Add Broadcom Capri pinctrl driver Sherman Yin ` (2 preceding siblings ...) 2013-12-21 2:13 ` [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin @ 2013-12-21 2:13 ` Sherman Yin 2014-01-16 13:28 ` Linus Walleij 3 siblings, 1 reply; 85+ messages in thread From: Sherman Yin @ 2013-12-21 2:13 UTC (permalink / raw) To: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Linus Walleij, Grant Likely, Matt Porter Cc: devicetree, linux-doc, linux-kernel, bcm-kernel-feedback-list, linux-arm-kernel, Sherman Yin Enable pinctrl for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> --- v4: no change v3: No change. v2: Use hyphens instead of underscore in DT property names. --- arch/arm/boot/dts/bcm11351.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index b0c0610..dd8e878 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -142,4 +142,8 @@ status = "disabled"; }; + pinctrl@35004800 { + compatible = "brcm,capri-pinctrl"; + reg = <0x35004800 0x430>; + }; }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v4 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs 2013-12-21 2:13 ` [PATCH v4 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin @ 2014-01-16 13:28 ` Linus Walleij 0 siblings, 0 replies; 85+ messages in thread From: Linus Walleij @ 2014-01-16 13:28 UTC (permalink / raw) To: Sherman Yin, arm@kernel.org Cc: Mark Brown, Rob Herring, Heiko Stübner, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell, Rob Landley, Christian Daudt, Russell King, Grant Likely, Matt Porter, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list, linux-arm-kernel@lists.infradead.org On Sat, Dec 21, 2013 at 3:13 AM, Sherman Yin <syin@broadcom.com> wrote: > Enable pinctrl for Broadcom Capri (BCM281xx) SoCs. > > Signed-off-by: Sherman Yin <syin@broadcom.com> > Reviewed-by: Christian Daudt <bcm@fixthebug.org> > Reviewed-by: Matt Porter <matt.porter@linaro.org> I've applied this to the pinctrl tree as well. Same thing here: if it conflicts with ARM SoC it goes out. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 85+ messages in thread
end of thread, other threads:[~2014-01-21 13:49 UTC | newest]
Thread overview: 85+ messages (download: mbox.gz follow: Atom feed
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2013-10-04 0:23 [PATCH 0/4] Add Broadcom Capri pinctrl driver Sherman Yin
2013-10-04 0:23 ` [PATCH 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin
[not found] ` <1380846199-12829-2-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2013-10-09 8:55 ` Linus Walleij
2013-10-09 22:57 ` Sherman Yin
[not found] ` <1380846199-12829-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2013-10-04 0:23 ` [PATCH 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin
2013-10-04 12:51 ` Matt Porter
[not found] ` <1380846199-12829-3-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2013-10-09 8:53 ` Linus Walleij
2013-10-10 17:57 ` Sherman Yin
2013-10-04 0:23 ` [PATCH 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin
2013-10-09 9:10 ` Linus Walleij
2013-10-10 23:48 ` Sherman Yin
[not found] ` <051069C10411E24D9749790C498526FA1BE027EA-HXj2mutaA2pgyiERVvb/1Jr/X4hKkxxPpWgKQ6/u3Fg@public.gmane.org>
2013-10-11 8:14 ` Linus Walleij
2013-10-11 18:25 ` Sherman Yin
2013-10-22 23:29 ` Sherman Yin
2013-10-25 22:48 ` Sherman Yin
2013-11-04 12:24 ` Linus Walleij
2013-11-04 23:26 ` Heiko Stübner
2013-11-05 0:04 ` Stephen Warren
2013-11-06 2:02 ` Sherman Yin
2013-11-06 9:40 ` Linus Walleij
2013-11-08 0:29 ` Sherman Yin
2013-11-11 10:01 ` Linus Walleij
[not found] ` <CACRpkdaf9dVqpE5uFQ5L64n+wXO0AYr5-e1WvYc4rWjVTsTg1w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-11-13 23:43 ` Sherman Yin
2013-11-19 20:39 ` Linus Walleij
[not found] ` <5279A319.5060701-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2013-11-06 17:00 ` Stephen Warren
2013-11-07 22:01 ` Sherman Yin
2013-11-06 9:29 ` Linus Walleij
2013-10-17 6:03 ` Christian Daudt
2013-10-17 14:54 ` Stephen Warren
2013-10-17 15:31 ` Christian Daudt
2013-12-11 0:05 ` Sherman Yin
2013-12-12 20:43 ` Linus Walleij
2013-10-04 0:23 ` [PATCH 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin
2013-10-09 9:11 ` Linus Walleij
2013-10-07 19:28 ` [PATCH v2 0/4] Add Broadcom Capri pinctrl driver Sherman Yin
2013-10-07 19:28 ` [PATCH v2 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin
2013-10-07 19:28 ` [PATCH v2 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin
2013-10-07 19:28 ` [PATCH v2 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin
2013-10-07 19:28 ` [PATCH v2 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin
2013-12-11 18:37 ` [PATCH v3 0/6] Add Broadcom Capri pinctrl driver Sherman Yin
2013-12-11 18:37 ` [PATCH v3 1/6] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin
[not found] ` <1386787041-6035-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2013-12-11 18:37 ` [PATCH v3 2/6] pinctrl: Adds slew-rate, input-enable/disable Sherman Yin
2013-12-12 20:41 ` Linus Walleij
2013-12-16 9:55 ` Linus Walleij
2013-12-11 18:37 ` [PATCH v3 3/6] pinctrl: Make PINCTRL selectable by defconfig/menuconfig Sherman Yin
2013-12-12 20:39 ` Linus Walleij
2013-12-12 21:35 ` Christian Daudt
2013-12-16 10:01 ` Linus Walleij
[not found] ` <CACRpkdY2BExGiL6HBg7zn_szJQMnSNsxOSuo7RyrRmrz=cVe2A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-12-17 0:18 ` Bjorn Andersson
2013-12-20 9:37 ` Linus Walleij
2013-12-20 20:58 ` Arnd Bergmann
2013-12-21 2:15 ` Sherman Yin
2013-12-11 18:37 ` [PATCH v3 4/6] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin
2013-12-12 20:37 ` Linus Walleij
2013-12-14 1:16 ` Sherman Yin
2013-12-16 13:17 ` Linus Walleij
[not found] ` <CACRpkdZ5Cxii48CsVJzEaBhvZOs8JCcR_hJV=RczhHbW4aqG-w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-12-18 2:02 ` Sherman Yin
2013-12-11 18:37 ` [PATCH v3 5/6] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin
2013-12-12 20:54 ` Linus Walleij
2013-12-13 10:22 ` Mark Brown
2013-12-19 0:12 ` Sherman Yin
2013-12-18 23:56 ` Sherman Yin
2013-12-21 2:31 ` Sherman Yin
2013-12-11 18:37 ` [PATCH v3 6/6] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin
2013-12-21 2:13 ` [PATCH v4 0/6] Add Broadcom Capri pinctrl driver Sherman Yin
2013-12-21 2:13 ` [PATCH v4 1/4] pinctrl: Add void * to pinctrl_pin_desc Sherman Yin
2014-01-16 13:26 ` Linus Walleij
[not found] ` <1387592016-13740-1-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2013-12-21 2:13 ` [PATCH v4 2/4] pinctrl: Add pinctrl binding for Broadcom Capri SoCs Sherman Yin
2014-01-07 17:15 ` Linus Walleij
2014-01-07 20:45 ` Sherman Yin
2014-01-14 10:16 ` Linus Walleij
2014-01-14 19:00 ` Sherman Yin
2014-01-15 9:40 ` Linus Walleij
2014-01-15 16:39 ` Mark Rutland
[not found] ` <1387592016-13740-3-git-send-email-syin-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2014-01-16 13:24 ` Linus Walleij
2013-12-21 2:13 ` [PATCH v4 3/4] ARM: pinctrl: Add Broadcom Capri pinctrl driver Sherman Yin
2014-01-16 13:19 ` Linus Walleij
2014-01-17 19:59 ` Sherman Yin
[not found] ` <52D98B99.5050604-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2014-01-18 2:56 ` Matt Porter
2014-01-20 8:16 ` Linus Walleij
2014-01-20 19:14 ` Sherman Yin
2014-01-21 12:35 ` Linus Walleij
2014-01-21 13:49 ` Matt Porter
2013-12-21 2:13 ` [PATCH v4 4/4] pinctrl: Enable pinctrl for Broadcom Capri SoCs Sherman Yin
2014-01-16 13:28 ` Linus Walleij
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