[PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Sricharan R]

Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the interrupt
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the controllers appropriately.
In such places a interrupt controllers are preceded by an
IRQ CROSSBAR that provides flexibility in muxing the device interrupt
requests to the controller inputs.

This series models the peripheral interrupts that can be routed through
the crossbar to the GIC as 'routable-irqs'. The routable irqs are added
in a separate linear domain inside the GIC. The registered routable domain's
callback are invoked as a part of the GIC's callback, which in turn should
allocate a free irq line and configure the IP accordingly. So every peripheral
in the dts files mentions the fixed crossbar number as its interrupt. A free
gic line for that gets allocated and configured when the peripheral interrupts
are mapped.

The minimal crossbar driver to track and allocate free GIC lines and configure the
crossbar is added here, along with the DT bindings.

V5:
   Addressed a comment from Mark Rutland <mark.rutland@arm.com>,
   updated tags and rebased on 3.13-rc2

V4:
   Addressed a couple of comments and split the DTS file updates in to
   a separate series.

V3:
   Addressed few more comments from Thomas Gleixner <tglx@linutronix.de>

   Rebased patches 3,4,5,7 which updates the DTS file on top of below branch
	   git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
	   for_3.13/dts

   Rebased patches 1,2,6 on top of 3.12 mainline
   Updated Commit tags

V2:
   Addressed Thomas Gleixner <tglx@linutronix.de> comments and
   Kumar Gala <galak@codeaurora.org>

   Split updating the DRA7.dtsi file for adding the routable-irqs

Previous discussions that led to this is at
	https://lkml.org/lkml/2013/9/18/540

The V1,V2,V3,V4 post of these patches is at
      [V1]  https://lkml.org/lkml/2013/9/30/283
      [V2]  http://www.spinics.net/lists/linux-omap/msg99540.html
      [V3]  http://www.kernelhub.org/?msg=356470&p=2
      [V4]  http://www.spinics.net/lists/linux-doc/msg16726.html

Sricharan R (4):
  DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
  DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
  ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
  ARM: DRA: Enable Crossbar IP support for DRA7XX

 Documentation/devicetree/bindings/arm/gic.txt      |    6 +
 .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
 arch/arm/mach-omap2/Kconfig                        |    1 +
 arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
 arch/arm/mach-omap2/omap4-common.c                 |    2 +
 drivers/irqchip/Kconfig                            |    8 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-crossbar.c                     |  208 ++++++++++++++++++++
 drivers/irqchip/irq-gic.c                          |   81 +++++++-
 include/linux/irqchip/arm-gic.h                    |    7 +-
 include/linux/irqchip/irq-crossbar.h               |   11 ++
 11 files changed, 343 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
 create mode 100644 drivers/irqchip/irq-crossbar.c
 create mode 100644 include/linux/irqchip/irq-crossbar.h

-- 
1.7.9.5

[PATCH V5 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

[Sricharan R]

In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.

The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
 Documentation/devicetree/bindings/arm/gic.txt |    6 ++
 drivers/irqchip/irq-gic.c                     |   82 ++++++++++++++++++++++---
 include/linux/irqchip/arm-gic.h               |    7 ++-
 3 files changed, 84 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 3dfb0c0..5357745 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -49,6 +49,11 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
+- arm,routable-irqs : Total number of gic irq inputs which are not directly
+		  connected from the peripherals, but are routed dynamically
+		  by a crossbar/multiplexer preceding the GIC. The GIC irq
+		  input line is assigned dynamically when the corresponding
+		  peripheral's crossbar line is mapped.
 Example:
 
 	intc: interrupt-controller@fff11000 {
@@ -56,6 +61,7 @@ Example:
 		#interrupt-cells = <3>;
 		#address-cells = <1>;
 		interrupt-controller;
+		arm,routable-irqs = <160>;
 		reg = <0xfff11000 0x1000>,
 		      <0xfff10100 0x100>;
 	};
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9031171..5cfb602 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -824,16 +824,25 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 		irq_set_chip_and_handler(irq, &gic_chip,
 					 handle_fasteoi_irq);
 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+		gic_routable_irq_domain_ops->map(d, irq, hw);
 	}
 	irq_set_chip_data(irq, d->host_data);
 	return 0;
 }
 
+static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+	gic_routable_irq_domain_ops->unmap(d, irq);
+}
+
 static int gic_irq_domain_xlate(struct irq_domain *d,
 				struct device_node *controller,
 				const u32 *intspec, unsigned int intsize,
 				unsigned long *out_hwirq, unsigned int *out_type)
 {
+	unsigned long ret = 0;
+
 	if (d->of_node != controller)
 		return -EINVAL;
 	if (intsize < 3)
@@ -843,11 +852,20 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
 	*out_hwirq = intspec[1] + 16;
 
 	/* For SPIs, we need to add 16 more to get the GIC irq ID number */
-	if (!intspec[0])
-		*out_hwirq += 16;
+	if (!intspec[0]) {
+		ret = gic_routable_irq_domain_ops->xlate(d, controller,
+							 intspec,
+							 intsize,
+							 out_hwirq,
+							 out_type);
+
+		if (IS_ERR_VALUE(ret))
+			return ret;
+	}
 
 	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
-	return 0;
+
+	return ret;
 }
 
 #ifdef CONFIG_SMP
@@ -871,9 +889,41 @@ static struct notifier_block gic_cpu_notifier = {
 
 const struct irq_domain_ops gic_irq_domain_ops = {
 	.map = gic_irq_domain_map,
+	.unmap = gic_irq_domain_unmap,
 	.xlate = gic_irq_domain_xlate,
 };
 
+/* Default functions for routable irq domain */
+static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
+			      irq_hw_number_t hw)
+{
+	return 0;
+}
+
+static void gic_routable_irq_domain_unmap(struct irq_domain *d,
+					  unsigned int irq)
+{
+}
+
+static int gic_routable_irq_domain_xlate(struct irq_domain *d,
+				struct device_node *controller,
+				const u32 *intspec, unsigned int intsize,
+				unsigned long *out_hwirq,
+				unsigned int *out_type)
+{
+	*out_hwirq += 16;
+	return 0;
+}
+
+const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
+	.map = gic_routable_irq_domain_map,
+	.unmap = gic_routable_irq_domain_unmap,
+	.xlate = gic_routable_irq_domain_xlate,
+};
+
+const struct irq_domain_ops *gic_routable_irq_domain_ops =
+					&gic_default_routable_irq_domain_ops;
+
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 			   void __iomem *dist_base, void __iomem *cpu_base,
 			   u32 percpu_offset, struct device_node *node)
@@ -881,6 +931,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 	irq_hw_number_t hwirq_base;
 	struct gic_chip_data *gic;
 	int gic_irqs, irq_base, i;
+	int nr_routable_irqs;
 
 	BUG_ON(gic_nr >= MAX_GIC_NR);
 
@@ -946,14 +997,25 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 	gic->gic_irqs = gic_irqs;
 
 	gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
-	irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
-	if (IS_ERR_VALUE(irq_base)) {
-		WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
-		     irq_start);
-		irq_base = irq_start;
+
+	if (of_property_read_u32(node, "arm,routable-irqs",
+				 &nr_routable_irqs)) {
+		irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
+					   numa_node_id());
+		if (IS_ERR_VALUE(irq_base)) {
+			WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
+			     irq_start);
+			irq_base = irq_start;
+		}
+
+		gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
+					hwirq_base, &gic_irq_domain_ops, gic);
+	} else {
+		gic->domain = irq_domain_add_linear(node, nr_routable_irqs,
+						    &gic_irq_domain_ops,
+						    gic);
 	}
-	gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
-				    hwirq_base, &gic_irq_domain_ops, gic);
+
 	if (WARN_ON(!gic->domain))
 		return;
 
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index cac496b..fcb02d7 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -81,6 +81,11 @@ int gic_get_cpu_id(unsigned int cpu);
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
 
+extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
+static inline void __init register_routable_domain_ops
+					(const struct irq_domain_ops *ops)
+{
+	gic_routable_irq_domain_ops = ops;
+}
 #endif /* __ASSEMBLY */
-
 #endif
-- 
1.7.9.5

[PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Sricharan R]

Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.

This driver takes care a allocating a free irq and then configuring the
crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
be called right before the irqchip_init, so that it is setup to handle the
irqchip callbacks.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion)
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
 [v5] Used the function of_property_read_u32_index instead of raw reading
      from DT as per comments from Mark Rutland <mark.rutland@arm.com>

 .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
 drivers/irqchip/Kconfig                            |    8 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-crossbar.c                     |  208 ++++++++++++++++++++
 include/linux/irqchip/irq-crossbar.h               |   11 ++
 5 files changed, 255 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
 create mode 100644 drivers/irqchip/irq-crossbar.c
 create mode 100644 include/linux/irqchip/irq-crossbar.h

diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
new file mode 100644
index 0000000..fb88585
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -0,0 +1,27 @@
+Some socs have a large number of interrupts requests to service
+the needs of its many peripherals and subsystems. All of the
+interrupt lines from the subsystems are not needed at the same
+time, so they have to be muxed to the irq-controller appropriately.
+In such places a interrupt controllers are preceded by an CROSSBAR
+that provides flexibility in muxing the device requests to the controller
+inputs.
+
+Required properties:
+- compatible : Should be "ti,irq-crossbar"
+- reg: Base address and the size of the crossbar registers.
+- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- ti,reg-size: Size of a individual register in bytes. Every individual
+	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
+- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
+		 crossbar. These interrupt lines are reserved in the soc,
+		 so crossbar bar driver should not consider them as free
+		 lines.
+
+Examples:
+		crossbar_mpu: @4a020000 {
+			compatible = "ti,irq-crossbar";
+			reg = <0x4a002a48 0x130>;
+			ti,max-irqs = <160>;
+			ti,reg-size = <2>;
+			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
+		};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3792a1a..2efcde6 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -61,3 +61,11 @@ config VERSATILE_FPGA_IRQ_NR
        int
        default 4
        depends on VERSATILE_FPGA_IRQ
+
+config IRQ_CROSSBAR
+	bool
+	help
+	  Support for a CROSSBAR ip that preceeds the main interrupt controller.
+	  The primary irqchip invokes the crossbar's callback which inturn allocates
+	  a free irq and configures the IP. Thus the peripheral interrupts are
+	  routed to one of the free irqchip interrupt lines.
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c60b901..2edead9 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
 obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o
 obj-$(CONFIG_TB10X_IRQC)		+= irq-tb10x.o
+obj-$(CONFIG_IRQ_CROSSBAR)		+= irq-crossbar.o
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
new file mode 100644
index 0000000..ae605a3
--- /dev/null
+++ b/drivers/irqchip/irq-crossbar.c
@@ -0,0 +1,208 @@
+/*
+ *  drivers/irqchip/irq-crossbar.c
+ *
+ *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *  Author: Sricharan R <r.sricharan@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/irqchip/arm-gic.h>
+
+#define IRQ_FREE	-1
+#define GIC_IRQ_START	32
+
+/*
+ * @int_max: maximum number of supported interrupts
+ * @irq_map: array of interrupts to crossbar number mapping
+ * @crossbar_base: crossbar base address
+ * @register_offsets: offsets for each irq number
+ */
+struct crossbar_device {
+	uint int_max;
+	uint *irq_map;
+	void __iomem *crossbar_base;
+	int *register_offsets;
+	void (*write) (int, int);
+};
+
+static struct crossbar_device *cb;
+
+static inline void crossbar_writel(int irq_no, int cb_no)
+{
+	writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
+}
+
+static inline void crossbar_writew(int irq_no, int cb_no)
+{
+	writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
+}
+
+static inline void crossbar_writeb(int irq_no, int cb_no)
+{
+	writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
+}
+
+static inline int allocate_free_irq(int cb_no)
+{
+	int i;
+
+	for (i = 0; i < cb->int_max; i++) {
+		if (cb->irq_map[i] == IRQ_FREE) {
+			cb->irq_map[i] = cb_no;
+			return i;
+		}
+	}
+
+	return -ENODEV;
+}
+
+static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
+			       irq_hw_number_t hw)
+{
+	cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
+	return 0;
+}
+
+static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+	irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
+
+	if (hw > GIC_IRQ_START)
+		cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
+}
+
+static int crossbar_domain_xlate(struct irq_domain *d,
+				 struct device_node *controller,
+				 const u32 *intspec, unsigned int intsize,
+				 unsigned long *out_hwirq,
+				 unsigned int *out_type)
+{
+	unsigned long ret;
+
+	ret = allocate_free_irq(intspec[1]);
+
+	if (IS_ERR_VALUE(ret))
+		return ret;
+
+	*out_hwirq = ret + GIC_IRQ_START;
+	return 0;
+}
+
+const struct irq_domain_ops routable_irq_domain_ops = {
+	.map = crossbar_domain_map,
+	.unmap = crossbar_domain_unmap,
+	.xlate = crossbar_domain_xlate
+};
+
+static int __init crossbar_of_init(struct device_node *node)
+{
+	int i, size, max, reserved = 0, entry;
+	const __be32 *irqsr;
+
+	cb = kzalloc(sizeof(struct cb_device *), GFP_KERNEL);
+
+	if (!cb)
+		return -ENOMEM;
+
+	cb->crossbar_base = of_iomap(node, 0);
+	if (!cb->crossbar_base)
+		goto err1;
+
+	of_property_read_u32(node, "ti,max-irqs", &max);
+	cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL);
+	if (!cb->irq_map)
+		goto err2;
+
+	cb->int_max = max;
+
+	for (i = 0; i < max; i++)
+		cb->irq_map[i] = IRQ_FREE;
+
+	/* Get and mark reserved irqs */
+	irqsr = of_get_property(node, "ti,irqs-reserved", &size);
+	if (irqsr) {
+		size /= sizeof(__be32);
+
+		for (i = 0; i < size; i++) {
+			of_property_read_u32_index(node,
+						   "ti,irqs-reserved",
+						   i, &entry);
+			if (entry > max) {
+				pr_err("Invalid reserved entry\n");
+				goto err3;
+			}
+			cb->irq_map[entry] = 0;
+		}
+	}
+
+	cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
+	if (!cb->register_offsets)
+		goto err3;
+
+	of_property_read_u32(node, "ti,reg-size", &size);
+
+	switch (size) {
+	case 1:
+		cb->write = crossbar_writeb;
+		break;
+	case 2:
+		cb->write = crossbar_writew;
+		break;
+	case 4:
+		cb->write = crossbar_writel;
+		break;
+	default:
+		pr_err("Invalid reg-size property\n");
+		goto err4;
+		break;
+	}
+
+	/*
+	 * Register offsets are not linear because of the
+	 * reserved irqs. so find and store the offsets once.
+	 */
+	for (i = 0; i < max; i++) {
+		if (!cb->irq_map[i])
+			continue;
+
+		cb->register_offsets[i] = reserved;
+		reserved += size;
+	}
+
+	register_routable_domain_ops(&routable_irq_domain_ops);
+	return 0;
+
+err4:
+	kfree(cb->register_offsets);
+err3:
+	kfree(cb->irq_map);
+err2:
+	iounmap(cb->crossbar_base);
+err1:
+	kfree(cb);
+	return -ENOMEM;
+}
+
+static const struct of_device_id crossbar_match[] __initconst = {
+	{ .compatible = "ti,irq-crossbar" },
+	{}
+};
+
+int irqcrossbar_init(void)
+{
+	struct device_node *np;
+	np = of_find_matching_node(NULL, crossbar_match);
+	if (!np)
+		return -ENODEV;
+
+	crossbar_of_init(np);
+	return 0;
+}
diff --git a/include/linux/irqchip/irq-crossbar.h b/include/linux/irqchip/irq-crossbar.h
new file mode 100644
index 0000000..e5537b8
--- /dev/null
+++ b/include/linux/irqchip/irq-crossbar.h
@@ -0,0 +1,11 @@
+/*
+ *  drivers/irqchip/irq-crossbar.h
+ *
+ *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+int irqcrossbar_init(void);
-- 
1.7.9.5

Re: [PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Felipe Balbi]

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Hi,

On Tue, Dec 03, 2013 at 03:57:23PM +0530, Sricharan R wrote:
> +static const struct of_device_id crossbar_match[] __initconst = {
> +	{ .compatible = "ti,irq-crossbar" },
> +	{}
> +};
> +
> +int irqcrossbar_init(void)
> +{
> +	struct device_node *np;
> +	np = of_find_matching_node(NULL, crossbar_match);
> +	if (!np)
> +		return -ENODEV;
> +
> +	crossbar_of_init(np);
> +	return 0;
> +}

instead, please use IRQCHIP_DECLARE() then you won't need to expose this
symbol to be used by arch/arm/ code.

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Sricharan R]

Hi Felipe,

On Friday 27 December 2013 01:31 AM, Felipe Balbi wrote:
> Hi,
> 
> On Tue, Dec 03, 2013 at 03:57:23PM +0530, Sricharan R wrote:
>> +static const struct of_device_id crossbar_match[] __initconst = {
>> +	{ .compatible = "ti,irq-crossbar" },
>> +	{}
>> +};
>> +
>> +int irqcrossbar_init(void)
>> +{
>> +	struct device_node *np;
>> +	np = of_find_matching_node(NULL, crossbar_match);
>> +	if (!np)
>> +		return -ENODEV;
>> +
>> +	crossbar_of_init(np);
>> +	return 0;
>> +}
> 
> instead, please use IRQCHIP_DECLARE() then you won't need to expose this
> symbol to be used by arch/arm/ code.
> 

Crossbar node does not have a "interrupt-controller" property and
not a regular Interrupt controller. This was added in here
after all below discussions

 https://lkml.org/lkml/2013/9/18/540

So IRQCHIP_DECLARE() macro cannot be used here.

Regards,
 Sricharan

Re: [PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Sricharan R]

Hi Thomas,

On Tuesday 03 December 2013 03:57 PM, Sricharan R wrote:
> Some socs have a large number of interrupts requests to service
> the needs of its many peripherals and subsystems. All of the
> interrupt lines from the subsystems are not needed at the same
> time, so they have to be muxed to the irq-controller appropriately.
> In such places a interrupt controllers are preceded by an CROSSBAR
> that provides flexibility in muxing the device requests to the controller
> inputs.
> 
> This driver takes care a allocating a free irq and then configuring the
> crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
> be called right before the irqchip_init, so that it is setup to handle the
> irqchip callbacks.
> 
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Grant Likely <grant.likely@linaro.org>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Signed-off-by: Sricharan R <r.sricharan@ti.com>
> Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion)
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  [v5] Used the function of_property_read_u32_index instead of raw reading
>       from DT as per comments from Mark Rutland <mark.rutland@arm.com>
> 
>  .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
>  drivers/irqchip/Kconfig                            |    8 +
>  drivers/irqchip/Makefile                           |    1 +
>  drivers/irqchip/irq-crossbar.c                     |  208 ++++++++++++++++++++
>  include/linux/irqchip/irq-crossbar.h               |   11 ++
>  5 files changed, 255 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
>  create mode 100644 drivers/irqchip/irq-crossbar.c
>  create mode 100644 include/linux/irqchip/irq-crossbar.h
> 
> diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> new file mode 100644
> index 0000000..fb88585
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> @@ -0,0 +1,27 @@
> +Some socs have a large number of interrupts requests to service
> +the needs of its many peripherals and subsystems. All of the
> +interrupt lines from the subsystems are not needed at the same
> +time, so they have to be muxed to the irq-controller appropriately.
> +In such places a interrupt controllers are preceded by an CROSSBAR
> +that provides flexibility in muxing the device requests to the controller
> +inputs.
> +
> +Required properties:
> +- compatible : Should be "ti,irq-crossbar"
> +- reg: Base address and the size of the crossbar registers.
> +- ti,max-irqs: Total number of irqs available at the interrupt controller.
> +- ti,reg-size: Size of a individual register in bytes. Every individual
> +	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
> +- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
> +		 crossbar. These interrupt lines are reserved in the soc,
> +		 so crossbar bar driver should not consider them as free
> +		 lines.
> +
> +Examples:
> +		crossbar_mpu: @4a020000 {
> +			compatible = "ti,irq-crossbar";
> +			reg = <0x4a002a48 0x130>;
> +			ti,max-irqs = <160>;
> +			ti,reg-size = <2>;
> +			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
> +		};
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 3792a1a..2efcde6 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -61,3 +61,11 @@ config VERSATILE_FPGA_IRQ_NR
>         int
>         default 4
>         depends on VERSATILE_FPGA_IRQ
> +
> +config IRQ_CROSSBAR
> +	bool
> +	help
> +	  Support for a CROSSBAR ip that preceeds the main interrupt controller.
> +	  The primary irqchip invokes the crossbar's callback which inturn allocates
> +	  a free irq and configures the IP. Thus the peripheral interrupts are
> +	  routed to one of the free irqchip interrupt lines.
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index c60b901..2edead9 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -22,3 +22,4 @@ obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
>  obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
>  obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o
>  obj-$(CONFIG_TB10X_IRQC)		+= irq-tb10x.o
> +obj-$(CONFIG_IRQ_CROSSBAR)		+= irq-crossbar.o
> diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
> new file mode 100644
> index 0000000..ae605a3
> --- /dev/null
> +++ b/drivers/irqchip/irq-crossbar.c
> @@ -0,0 +1,208 @@
> +/*
> + *  drivers/irqchip/irq-crossbar.c
> + *
> + *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
> + *  Author: Sricharan R <r.sricharan@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/slab.h>
> +#include <linux/irqchip/arm-gic.h>
> +
> +#define IRQ_FREE	-1
> +#define GIC_IRQ_START	32
> +
> +/*
> + * @int_max: maximum number of supported interrupts
> + * @irq_map: array of interrupts to crossbar number mapping
> + * @crossbar_base: crossbar base address
> + * @register_offsets: offsets for each irq number
> + */
> +struct crossbar_device {
> +	uint int_max;
> +	uint *irq_map;
> +	void __iomem *crossbar_base;
> +	int *register_offsets;
> +	void (*write) (int, int);
> +};
> +
> +static struct crossbar_device *cb;
> +
> +static inline void crossbar_writel(int irq_no, int cb_no)
> +{
> +	writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
> +}
> +
> +static inline void crossbar_writew(int irq_no, int cb_no)
> +{
> +	writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
> +}
> +
> +static inline void crossbar_writeb(int irq_no, int cb_no)
> +{
> +	writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
> +}
> +
> +static inline int allocate_free_irq(int cb_no)
> +{
> +	int i;
> +
> +	for (i = 0; i < cb->int_max; i++) {
> +		if (cb->irq_map[i] == IRQ_FREE) {
> +			cb->irq_map[i] = cb_no;
> +			return i;
> +		}
> +	}
> +
> +	return -ENODEV;
> +}
> +
> +static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
> +			       irq_hw_number_t hw)
> +{
> +	cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
> +	return 0;
> +}
> +
> +static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
> +{
> +	irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
> +
> +	if (hw > GIC_IRQ_START)
> +		cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
> +}
> +
> +static int crossbar_domain_xlate(struct irq_domain *d,
> +				 struct device_node *controller,
> +				 const u32 *intspec, unsigned int intsize,
> +				 unsigned long *out_hwirq,
> +				 unsigned int *out_type)
> +{
> +	unsigned long ret;
> +
> +	ret = allocate_free_irq(intspec[1]);
> +
> +	if (IS_ERR_VALUE(ret))
> +		return ret;
> +
> +	*out_hwirq = ret + GIC_IRQ_START;
> +	return 0;
> +}
> +
> +const struct irq_domain_ops routable_irq_domain_ops = {
> +	.map = crossbar_domain_map,
> +	.unmap = crossbar_domain_unmap,
> +	.xlate = crossbar_domain_xlate
> +};
> +
> +static int __init crossbar_of_init(struct device_node *node)
> +{
> +	int i, size, max, reserved = 0, entry;
> +	const __be32 *irqsr;
> +
> +	cb = kzalloc(sizeof(struct cb_device *), GFP_KERNEL);
> +
> +	if (!cb)
> +		return -ENOMEM;
> +
> +	cb->crossbar_base = of_iomap(node, 0);
> +	if (!cb->crossbar_base)
> +		goto err1;
> +
> +	of_property_read_u32(node, "ti,max-irqs", &max);
> +	cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL);
> +	if (!cb->irq_map)
> +		goto err2;
> +
> +	cb->int_max = max;
> +
> +	for (i = 0; i < max; i++)
> +		cb->irq_map[i] = IRQ_FREE;
> +
> +	/* Get and mark reserved irqs */
> +	irqsr = of_get_property(node, "ti,irqs-reserved", &size);
> +	if (irqsr) {
> +		size /= sizeof(__be32);
> +
> +		for (i = 0; i < size; i++) {
> +			of_property_read_u32_index(node,
> +						   "ti,irqs-reserved",
> +						   i, &entry);
> +			if (entry > max) {
> +				pr_err("Invalid reserved entry\n");
> +				goto err3;
> +			}
> +			cb->irq_map[entry] = 0;
> +		}
> +	}
> +
> +	cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
> +	if (!cb->register_offsets)
> +		goto err3;
> +
> +	of_property_read_u32(node, "ti,reg-size", &size);
> +
> +	switch (size) {
> +	case 1:
> +		cb->write = crossbar_writeb;
> +		break;
> +	case 2:
> +		cb->write = crossbar_writew;
> +		break;
> +	case 4:
> +		cb->write = crossbar_writel;
> +		break;
> +	default:
> +		pr_err("Invalid reg-size property\n");
> +		goto err4;
> +		break;
> +	}
> +
> +	/*
> +	 * Register offsets are not linear because of the
> +	 * reserved irqs. so find and store the offsets once.
> +	 */
> +	for (i = 0; i < max; i++) {
> +		if (!cb->irq_map[i])
> +			continue;
> +
> +		cb->register_offsets[i] = reserved;
> +		reserved += size;
> +	}
> +
> +	register_routable_domain_ops(&routable_irq_domain_ops);
> +	return 0;
> +
> +err4:
> +	kfree(cb->register_offsets);
> +err3:
> +	kfree(cb->irq_map);
> +err2:
> +	iounmap(cb->crossbar_base);
> +err1:
> +	kfree(cb);
> +	return -ENOMEM;
> +}
> +
> +static const struct of_device_id crossbar_match[] __initconst = {
> +	{ .compatible = "ti,irq-crossbar" },
> +	{}
> +};
> +
> +int irqcrossbar_init(void)
> +{
> +	struct device_node *np;
> +	np = of_find_matching_node(NULL, crossbar_match);
> +	if (!np)
> +		return -ENODEV;
> +
> +	crossbar_of_init(np);
> +	return 0;
> +}
> diff --git a/include/linux/irqchip/irq-crossbar.h b/include/linux/irqchip/irq-crossbar.h
> new file mode 100644
> index 0000000..e5537b8
> --- /dev/null
> +++ b/include/linux/irqchip/irq-crossbar.h
> @@ -0,0 +1,11 @@
> +/*
> + *  drivers/irqchip/irq-crossbar.h
> + *
> + *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +int irqcrossbar_init(void);

I already have your reviewed-by tag for the first patch in this series.

Kevin was pointing out that irqchip maintainer tag is needed for this patch as well
to be merged. We are planning to take this series through arm-soc tree.

Can i please have your tag for this patch as well ?

Regards,
 Sricharan

Re: [PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Sricharan R]

Hi Thomas,

On Thursday 16 January 2014 03:52 PM, Sricharan R wrote:
> Hi Thomas,
> 
> On Tuesday 03 December 2013 03:57 PM, Sricharan R wrote:
>> Some socs have a large number of interrupts requests to service
>> the needs of its many peripherals and subsystems. All of the
>> interrupt lines from the subsystems are not needed at the same
>> time, so they have to be muxed to the irq-controller appropriately.
>> In such places a interrupt controllers are preceded by an CROSSBAR
>> that provides flexibility in muxing the device requests to the controller
>> inputs.
>>
>> This driver takes care a allocating a free irq and then configuring the
>> crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
>> be called right before the irqchip_init, so that it is setup to handle the
>> irqchip callbacks.
>>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> Cc: Tony Lindgren <tony@atomide.com>
>> Cc: Rajendra Nayak <rnayak@ti.com>
>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>> Cc: Grant Likely <grant.likely@linaro.org>
>> Cc: Rob Herring <rob.herring@calxeda.com>
>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>> Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion)
>> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>> ---
>>  [v5] Used the function of_property_read_u32_index instead of raw reading
>>       from DT as per comments from Mark Rutland <mark.rutland@arm.com>
>>
>>  .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
>>  drivers/irqchip/Kconfig                            |    8 +
>>  drivers/irqchip/Makefile                           |    1 +
>>  drivers/irqchip/irq-crossbar.c                     |  208 ++++++++++++++++++++
>>  include/linux/irqchip/irq-crossbar.h               |   11 ++
>>  5 files changed, 255 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
>>  create mode 100644 drivers/irqchip/irq-crossbar.c
>>  create mode 100644 include/linux/irqchip/irq-crossbar.h
>>
>> diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
>> new file mode 100644
>> index 0000000..fb88585
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
>> @@ -0,0 +1,27 @@
>> +Some socs have a large number of interrupts requests to service
>> +the needs of its many peripherals and subsystems. All of the
>> +interrupt lines from the subsystems are not needed at the same
>> +time, so they have to be muxed to the irq-controller appropriately.
>> +In such places a interrupt controllers are preceded by an CROSSBAR
>> +that provides flexibility in muxing the device requests to the controller
>> +inputs.
>> +
>> +Required properties:
>> +- compatible : Should be "ti,irq-crossbar"
>> +- reg: Base address and the size of the crossbar registers.
>> +- ti,max-irqs: Total number of irqs available at the interrupt controller.
>> +- ti,reg-size: Size of a individual register in bytes. Every individual
>> +	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
>> +- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
>> +		 crossbar. These interrupt lines are reserved in the soc,
>> +		 so crossbar bar driver should not consider them as free
>> +		 lines.
>> +
>> +Examples:
>> +		crossbar_mpu: @4a020000 {
>> +			compatible = "ti,irq-crossbar";
>> +			reg = <0x4a002a48 0x130>;
>> +			ti,max-irqs = <160>;
>> +			ti,reg-size = <2>;
>> +			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
>> +		};
>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
>> index 3792a1a..2efcde6 100644
>> --- a/drivers/irqchip/Kconfig
>> +++ b/drivers/irqchip/Kconfig
>> @@ -61,3 +61,11 @@ config VERSATILE_FPGA_IRQ_NR
>>         int
>>         default 4
>>         depends on VERSATILE_FPGA_IRQ
>> +
>> +config IRQ_CROSSBAR
>> +	bool
>> +	help
>> +	  Support for a CROSSBAR ip that preceeds the main interrupt controller.
>> +	  The primary irqchip invokes the crossbar's callback which inturn allocates
>> +	  a free irq and configures the IP. Thus the peripheral interrupts are
>> +	  routed to one of the free irqchip interrupt lines.
>> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
>> index c60b901..2edead9 100644
>> --- a/drivers/irqchip/Makefile
>> +++ b/drivers/irqchip/Makefile
>> @@ -22,3 +22,4 @@ obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
>>  obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
>>  obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o
>>  obj-$(CONFIG_TB10X_IRQC)		+= irq-tb10x.o
>> +obj-$(CONFIG_IRQ_CROSSBAR)		+= irq-crossbar.o
>> diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
>> new file mode 100644
>> index 0000000..ae605a3
>> --- /dev/null
>> +++ b/drivers/irqchip/irq-crossbar.c
>> @@ -0,0 +1,208 @@
>> +/*
>> + *  drivers/irqchip/irq-crossbar.c
>> + *
>> + *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
>> + *  Author: Sricharan R <r.sricharan@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + */
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/slab.h>
>> +#include <linux/irqchip/arm-gic.h>
>> +
>> +#define IRQ_FREE	-1
>> +#define GIC_IRQ_START	32
>> +
>> +/*
>> + * @int_max: maximum number of supported interrupts
>> + * @irq_map: array of interrupts to crossbar number mapping
>> + * @crossbar_base: crossbar base address
>> + * @register_offsets: offsets for each irq number
>> + */
>> +struct crossbar_device {
>> +	uint int_max;
>> +	uint *irq_map;
>> +	void __iomem *crossbar_base;
>> +	int *register_offsets;
>> +	void (*write) (int, int);
>> +};
>> +
>> +static struct crossbar_device *cb;
>> +
>> +static inline void crossbar_writel(int irq_no, int cb_no)
>> +{
>> +	writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
>> +}
>> +
>> +static inline void crossbar_writew(int irq_no, int cb_no)
>> +{
>> +	writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
>> +}
>> +
>> +static inline void crossbar_writeb(int irq_no, int cb_no)
>> +{
>> +	writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
>> +}
>> +
>> +static inline int allocate_free_irq(int cb_no)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < cb->int_max; i++) {
>> +		if (cb->irq_map[i] == IRQ_FREE) {
>> +			cb->irq_map[i] = cb_no;
>> +			return i;
>> +		}
>> +	}
>> +
>> +	return -ENODEV;
>> +}
>> +
>> +static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
>> +			       irq_hw_number_t hw)
>> +{
>> +	cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
>> +	return 0;
>> +}
>> +
>> +static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
>> +{
>> +	irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
>> +
>> +	if (hw > GIC_IRQ_START)
>> +		cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
>> +}
>> +
>> +static int crossbar_domain_xlate(struct irq_domain *d,
>> +				 struct device_node *controller,
>> +				 const u32 *intspec, unsigned int intsize,
>> +				 unsigned long *out_hwirq,
>> +				 unsigned int *out_type)
>> +{
>> +	unsigned long ret;
>> +
>> +	ret = allocate_free_irq(intspec[1]);
>> +
>> +	if (IS_ERR_VALUE(ret))
>> +		return ret;
>> +
>> +	*out_hwirq = ret + GIC_IRQ_START;
>> +	return 0;
>> +}
>> +
>> +const struct irq_domain_ops routable_irq_domain_ops = {
>> +	.map = crossbar_domain_map,
>> +	.unmap = crossbar_domain_unmap,
>> +	.xlate = crossbar_domain_xlate
>> +};
>> +
>> +static int __init crossbar_of_init(struct device_node *node)
>> +{
>> +	int i, size, max, reserved = 0, entry;
>> +	const __be32 *irqsr;
>> +
>> +	cb = kzalloc(sizeof(struct cb_device *), GFP_KERNEL);
>> +
>> +	if (!cb)
>> +		return -ENOMEM;
>> +
>> +	cb->crossbar_base = of_iomap(node, 0);
>> +	if (!cb->crossbar_base)
>> +		goto err1;
>> +
>> +	of_property_read_u32(node, "ti,max-irqs", &max);
>> +	cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL);
>> +	if (!cb->irq_map)
>> +		goto err2;
>> +
>> +	cb->int_max = max;
>> +
>> +	for (i = 0; i < max; i++)
>> +		cb->irq_map[i] = IRQ_FREE;
>> +
>> +	/* Get and mark reserved irqs */
>> +	irqsr = of_get_property(node, "ti,irqs-reserved", &size);
>> +	if (irqsr) {
>> +		size /= sizeof(__be32);
>> +
>> +		for (i = 0; i < size; i++) {
>> +			of_property_read_u32_index(node,
>> +						   "ti,irqs-reserved",
>> +						   i, &entry);
>> +			if (entry > max) {
>> +				pr_err("Invalid reserved entry\n");
>> +				goto err3;
>> +			}
>> +			cb->irq_map[entry] = 0;
>> +		}
>> +	}
>> +
>> +	cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
>> +	if (!cb->register_offsets)
>> +		goto err3;
>> +
>> +	of_property_read_u32(node, "ti,reg-size", &size);
>> +
>> +	switch (size) {
>> +	case 1:
>> +		cb->write = crossbar_writeb;
>> +		break;
>> +	case 2:
>> +		cb->write = crossbar_writew;
>> +		break;
>> +	case 4:
>> +		cb->write = crossbar_writel;
>> +		break;
>> +	default:
>> +		pr_err("Invalid reg-size property\n");
>> +		goto err4;
>> +		break;
>> +	}
>> +
>> +	/*
>> +	 * Register offsets are not linear because of the
>> +	 * reserved irqs. so find and store the offsets once.
>> +	 */
>> +	for (i = 0; i < max; i++) {
>> +		if (!cb->irq_map[i])
>> +			continue;
>> +
>> +		cb->register_offsets[i] = reserved;
>> +		reserved += size;
>> +	}
>> +
>> +	register_routable_domain_ops(&routable_irq_domain_ops);
>> +	return 0;
>> +
>> +err4:
>> +	kfree(cb->register_offsets);
>> +err3:
>> +	kfree(cb->irq_map);
>> +err2:
>> +	iounmap(cb->crossbar_base);
>> +err1:
>> +	kfree(cb);
>> +	return -ENOMEM;
>> +}
>> +
>> +static const struct of_device_id crossbar_match[] __initconst = {
>> +	{ .compatible = "ti,irq-crossbar" },
>> +	{}
>> +};
>> +
>> +int irqcrossbar_init(void)
>> +{
>> +	struct device_node *np;
>> +	np = of_find_matching_node(NULL, crossbar_match);
>> +	if (!np)
>> +		return -ENODEV;
>> +
>> +	crossbar_of_init(np);
>> +	return 0;
>> +}
>> diff --git a/include/linux/irqchip/irq-crossbar.h b/include/linux/irqchip/irq-crossbar.h
>> new file mode 100644
>> index 0000000..e5537b8
>> --- /dev/null
>> +++ b/include/linux/irqchip/irq-crossbar.h
>> @@ -0,0 +1,11 @@
>> +/*
>> + *  drivers/irqchip/irq-crossbar.h
>> + *
>> + *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + */
>> +int irqcrossbar_init(void);
> 
> I already have your reviewed-by tag for the first patch in this series.
> 
> Kevin was pointing out that irqchip maintainer tag is needed for this patch as well
> to be merged. We are planning to take this series through arm-soc tree.
> 
> Can i please have your tag for this patch as well ?
> 
  Ping..

Regards,
 Sricharan

Re: [PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Thomas Gleixner]

On Mon, 3 Feb 2014, Sricharan R wrote:
> > I already have your reviewed-by tag for the first patch in this series.
> > 
> > Kevin was pointing out that irqchip maintainer tag is needed for this patch as well
> > to be merged. We are planning to take this series through arm-soc tree.
> > 
> > Can i please have your tag for this patch as well ?

Acked-by-me

Re: [PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Sricharan R]

On Tuesday 04 February 2014 09:44 PM, Thomas Gleixner wrote:
> On Mon, 3 Feb 2014, Sricharan R wrote:
>>> I already have your reviewed-by tag for the first patch in this series.
>>>
>>> Kevin was pointing out that irqchip maintainer tag is needed for this patch as well
>>> to be merged. We are planning to take this series through arm-soc tree.
>>>
>>> Can i please have your tag for this patch as well ?
> 
> Acked-by-me
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Thanks Thomas.

Kevin,
    I will re-send a branch based on rc1 for this.

Regards,
 Sricharan

Re: [PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Sricharan R]

Tony,

On Wednesday 05 February 2014 06:41 PM, Sricharan R wrote:
> On Tuesday 04 February 2014 09:44 PM, Thomas Gleixner wrote:
>> On Mon, 3 Feb 2014, Sricharan R wrote:
>>>> I already have your reviewed-by tag for the first patch in this series.
>>>>
>>>> Kevin was pointing out that irqchip maintainer tag is needed for this patch as well
>>>> to be merged. We are planning to take this series through arm-soc tree.
>>>>
>>>> Can i please have your tag for this patch as well ?
>>
>> Acked-by-me
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> Thanks Thomas.
> 
> Kevin,
>     I will re-send a branch based on rc1 for this.
> 

I have pushed a branch based on mainline,
   git://github.com/Sricharanti/sricharan.git
   branch: crossbar_3.14_rc1

Regards,
 Sricharan

Re: [PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Sricharan R]

Hi Tony,

On Wednesday 05 February 2014 07:41 PM, Sricharan R wrote:
> Tony,
> 
> On Wednesday 05 February 2014 06:41 PM, Sricharan R wrote:
>> On Tuesday 04 February 2014 09:44 PM, Thomas Gleixner wrote:
>>> On Mon, 3 Feb 2014, Sricharan R wrote:
>>>>> I already have your reviewed-by tag for the first patch in this series.
>>>>>
>>>>> Kevin was pointing out that irqchip maintainer tag is needed for this patch as well
>>>>> to be merged. We are planning to take this series through arm-soc tree.
>>>>>
>>>>> Can i please have your tag for this patch as well ?
>>>
>>> Acked-by-me
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>> Thanks Thomas.
>>
>> Kevin,
>>     I will re-send a branch based on rc1 for this.
>>
> 
> I have pushed a branch based on mainline,
>    git://github.com/Sricharanti/sricharan.git
>    branch: crossbar_3.14_rc1
> 
 Ping on this..

Regards,
 Sricharan

Re: [PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

[Tony Lindgren]

* Sricharan R <r.sricharan-l0cyMroinI0@public.gmane.org> [140205 06:13]:
> Tony,
> 
> On Wednesday 05 February 2014 06:41 PM, Sricharan R wrote:
> > On Tuesday 04 February 2014 09:44 PM, Thomas Gleixner wrote:
> >> On Mon, 3 Feb 2014, Sricharan R wrote:
> >>>> I already have your reviewed-by tag for the first patch in this series.
> >>>>
> >>>> Kevin was pointing out that irqchip maintainer tag is needed for this patch as well
> >>>> to be merged. We are planning to take this series through arm-soc tree.
> >>>>
> >>>> Can i please have your tag for this patch as well ?
> >>
> >> Acked-by-me
> >> --
> >> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> >> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> > 
> > Thanks Thomas.
> > 
> > Kevin,
> >     I will re-send a branch based on rc1 for this.
> > 
> 
> I have pushed a branch based on mainline,
>    git://github.com/Sricharanti/sricharan.git
>    branch: crossbar_3.14_rc1

OK pulling into omap-for-v3.15/crossbar thanks.

Tony
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[PATCH V5 3/4] ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number

[Sricharan R]

The wakeup gen mask/unmask callback uses the irq element of the
irq_data to setup. The irq is the linux virtual irq number and
is same as the hardware irq number only when the parent irqchip
is setup as a legacy domain. When it is used as a linear domain,
the virtual irqs are allocated dynamically and wakeup gen code
cannot rely on these numbers to access the irq registers. Instead
use the hwirq element of the irq_data which represent the physical
irq number.

Cc: Santosh Shilimkar <santosh.shilimkar-l0cyMroinI0@public.gmane.org>
Cc: Rajendra Nayak <rnayak-l0cyMroinI0@public.gmane.org>
Cc: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Sricharan R <r.sricharan-l0cyMroinI0@public.gmane.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar-l0cyMroinI0@public.gmane.org>
Acked-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 arch/arm/mach-omap2/omap-wakeupgen.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 3664562..693fe48 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -138,7 +138,7 @@ static void wakeupgen_mask(struct irq_data *d)
 	unsigned long flags;
 
 	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
-	_wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
+	_wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
 	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 
@@ -150,7 +150,7 @@ static void wakeupgen_unmask(struct irq_data *d)
 	unsigned long flags;
 
 	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
-	_wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
+	_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
 	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 
-- 
1.7.9.5

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[PATCH V5 4/4] ARM: DRA: Enable Crossbar IP support for DRA7XX

[Sricharan R]

Enable the crossbar IP support for DRA7xx soc.

Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/mach-omap2/Kconfig        |    1 +
 arch/arm/mach-omap2/omap4-common.c |    2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dc21df1..d538df6 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -135,6 +135,7 @@ config SOC_DRA7XX
 	select ARM_GIC
 	select HAVE_SMP
 	select COMMON_CLK
+	select IRQ_CROSSBAR
 
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index b39efd4..9880a16 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,6 +22,7 @@
 #include <linux/of_platform.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/irq-crossbar.h>
 #include <linux/of_address.h>
 #include <linux/reboot.h>
 
@@ -281,5 +282,6 @@ void __init omap_gic_of_init(void)
 
 skip_errata_init:
 	omap_wakeupgen_init();
+	irqcrossbar_init();
 	irqchip_init();
 }
-- 
1.7.9.5

Re: [PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Sricharan R]

Hi Thomas,

On Tuesday 03 December 2013 03:57 PM, Sricharan R wrote:
> Some socs have a large number of interrupts requests to service
> the needs of its many peripherals and subsystems. All of the interrupt
> requests lines from the subsystems are not needed at the same
> time, so they have to be muxed to the controllers appropriately.
> In such places a interrupt controllers are preceded by an
> IRQ CROSSBAR that provides flexibility in muxing the device interrupt
> requests to the controller inputs.
> 
> This series models the peripheral interrupts that can be routed through
> the crossbar to the GIC as 'routable-irqs'. The routable irqs are added
> in a separate linear domain inside the GIC. The registered routable domain's
> callback are invoked as a part of the GIC's callback, which in turn should
> allocate a free irq line and configure the IP accordingly. So every peripheral
> in the dts files mentions the fixed crossbar number as its interrupt. A free
> gic line for that gets allocated and configured when the peripheral interrupts
> are mapped.
> 
> The minimal crossbar driver to track and allocate free GIC lines and configure the
> crossbar is added here, along with the DT bindings.
> 
> V5:
>    Addressed a comment from Mark Rutland <mark.rutland@arm.com>,
>    updated tags and rebased on 3.13-rc2
> 
> V4:
>    Addressed a couple of comments and split the DTS file updates in to
>    a separate series.
> 
> V3:
>    Addressed few more comments from Thomas Gleixner <tglx@linutronix.de>
> 
>    Rebased patches 3,4,5,7 which updates the DTS file on top of below branch
> 	   git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
> 	   for_3.13/dts
> 
>    Rebased patches 1,2,6 on top of 3.12 mainline
>    Updated Commit tags
> 
> V2:
>    Addressed Thomas Gleixner <tglx@linutronix.de> comments and
>    Kumar Gala <galak@codeaurora.org>
> 
>    Split updating the DRA7.dtsi file for adding the routable-irqs
> 
> Previous discussions that led to this is at
> 	https://lkml.org/lkml/2013/9/18/540
> 
> The V1,V2,V3,V4 post of these patches is at
>       [V1]  https://lkml.org/lkml/2013/9/30/283
>       [V2]  http://www.spinics.net/lists/linux-omap/msg99540.html
>       [V3]  http://www.kernelhub.org/?msg=356470&p=2
>       [V4]  http://www.spinics.net/lists/linux-doc/msg16726.html
> 
> Sricharan R (4):
>   DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
>   DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
>   ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
>   ARM: DRA: Enable Crossbar IP support for DRA7XX
> 
>  Documentation/devicetree/bindings/arm/gic.txt      |    6 +
>  .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
>  arch/arm/mach-omap2/Kconfig                        |    1 +
>  arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
>  arch/arm/mach-omap2/omap4-common.c                 |    2 +
>  drivers/irqchip/Kconfig                            |    8 +
>  drivers/irqchip/Makefile                           |    1 +
>  drivers/irqchip/irq-crossbar.c                     |  208 ++++++++++++++++++++
>  drivers/irqchip/irq-gic.c                          |   81 +++++++-
>  include/linux/irqchip/arm-gic.h                    |    7 +-
>  include/linux/irqchip/irq-crossbar.h               |   11 ++
>  11 files changed, 343 insertions(+), 13 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
>  create mode 100644 drivers/irqchip/irq-crossbar.c
>  create mode 100644 include/linux/irqchip/irq-crossbar.h
> 

I have addressed all the comments on this series, can this be merged now ?

Regards,
 Sricharan

Re: [PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Sricharan R]

Hi Thomas,
On Wednesday 18 December 2013 02:49 PM, Sricharan R wrote:
> Hi Thomas,
> 
> On Tuesday 03 December 2013 03:57 PM, Sricharan R wrote:
>> Some socs have a large number of interrupts requests to service
>> the needs of its many peripherals and subsystems. All of the interrupt
>> requests lines from the subsystems are not needed at the same
>> time, so they have to be muxed to the controllers appropriately.
>> In such places a interrupt controllers are preceded by an
>> IRQ CROSSBAR that provides flexibility in muxing the device interrupt
>> requests to the controller inputs.
>>
>> This series models the peripheral interrupts that can be routed through
>> the crossbar to the GIC as 'routable-irqs'. The routable irqs are added
>> in a separate linear domain inside the GIC. The registered routable domain's
>> callback are invoked as a part of the GIC's callback, which in turn should
>> allocate a free irq line and configure the IP accordingly. So every peripheral
>> in the dts files mentions the fixed crossbar number as its interrupt. A free
>> gic line for that gets allocated and configured when the peripheral interrupts
>> are mapped.
>>
>> The minimal crossbar driver to track and allocate free GIC lines and configure the
>> crossbar is added here, along with the DT bindings.
>>
>> V5:
>>    Addressed a comment from Mark Rutland <mark.rutland@arm.com>,
>>    updated tags and rebased on 3.13-rc2
>>
>> V4:
>>    Addressed a couple of comments and split the DTS file updates in to
>>    a separate series.
>>
>> V3:
>>    Addressed few more comments from Thomas Gleixner <tglx@linutronix.de>
>>
>>    Rebased patches 3,4,5,7 which updates the DTS file on top of below branch
>> 	   git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
>> 	   for_3.13/dts
>>
>>    Rebased patches 1,2,6 on top of 3.12 mainline
>>    Updated Commit tags
>>
>> V2:
>>    Addressed Thomas Gleixner <tglx@linutronix.de> comments and
>>    Kumar Gala <galak@codeaurora.org>
>>
>>    Split updating the DRA7.dtsi file for adding the routable-irqs
>>
>> Previous discussions that led to this is at
>> 	https://lkml.org/lkml/2013/9/18/540
>>
>> The V1,V2,V3,V4 post of these patches is at
>>       [V1]  https://lkml.org/lkml/2013/9/30/283
>>       [V2]  http://www.spinics.net/lists/linux-omap/msg99540.html
>>       [V3]  http://www.kernelhub.org/?msg=356470&p=2
>>       [V4]  http://www.spinics.net/lists/linux-doc/msg16726.html
>>
>> Sricharan R (4):
>>   DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
>>   DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
>>   ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
>>   ARM: DRA: Enable Crossbar IP support for DRA7XX
>>
>>  Documentation/devicetree/bindings/arm/gic.txt      |    6 +
>>  .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
>>  arch/arm/mach-omap2/Kconfig                        |    1 +
>>  arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
>>  arch/arm/mach-omap2/omap4-common.c                 |    2 +
>>  drivers/irqchip/Kconfig                            |    8 +
>>  drivers/irqchip/Makefile                           |    1 +
>>  drivers/irqchip/irq-crossbar.c                     |  208 ++++++++++++++++++++
>>  drivers/irqchip/irq-gic.c                          |   81 +++++++-
>>  include/linux/irqchip/arm-gic.h                    |    7 +-
>>  include/linux/irqchip/irq-crossbar.h               |   11 ++
>>  11 files changed, 343 insertions(+), 13 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
>>  create mode 100644 drivers/irqchip/irq-crossbar.c
>>  create mode 100644 include/linux/irqchip/irq-crossbar.h
>>
> 
> I have addressed all the comments on this series, can this be merged now ?
> 
  Ping..

Regards,
 Sricharan

Re: [PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Santosh Shilimkar]

Sricharan,

On Wednesday 25 December 2013 11:52 PM, Sricharan R wrote:
> Hi Thomas,
> On Wednesday 18 December 2013 02:49 PM, Sricharan R wrote:
>> Hi Thomas,
>>
>> On Tuesday 03 December 2013 03:57 PM, Sricharan R wrote:
>>> Some socs have a large number of interrupts requests to service
>>> the needs of its many peripherals and subsystems. All of the interrupt
>>> requests lines from the subsystems are not needed at the same
>>> time, so they have to be muxed to the controllers appropriately.
>>> In such places a interrupt controllers are preceded by an
>>> IRQ CROSSBAR that provides flexibility in muxing the device interrupt
>>> requests to the controller inputs.
>>>
>>> This series models the peripheral interrupts that can be routed through
>>> the crossbar to the GIC as 'routable-irqs'. The routable irqs are added
>>> in a separate linear domain inside the GIC. The registered routable domain's
>>> callback are invoked as a part of the GIC's callback, which in turn should
>>> allocate a free irq line and configure the IP accordingly. So every peripheral
>>> in the dts files mentions the fixed crossbar number as its interrupt. A free
>>> gic line for that gets allocated and configured when the peripheral interrupts
>>> are mapped.
>>>
>>> The minimal crossbar driver to track and allocate free GIC lines and configure the
>>> crossbar is added here, along with the DT bindings.
>>>
>>> V5:
>>>    Addressed a comment from Mark Rutland <mark.rutland@arm.com>,
>>>    updated tags and rebased on 3.13-rc2
>>>
>>> V4:
>>>    Addressed a couple of comments and split the DTS file updates in to
>>>    a separate series.
>>>
>>> V3:
>>>    Addressed few more comments from Thomas Gleixner <tglx@linutronix.de>
>>>
>>>    Rebased patches 3,4,5,7 which updates the DTS file on top of below branch
>>> 	   git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
>>> 	   for_3.13/dts
>>>
>>>    Rebased patches 1,2,6 on top of 3.12 mainline
>>>    Updated Commit tags
>>>
>>> V2:
>>>    Addressed Thomas Gleixner <tglx@linutronix.de> comments and
>>>    Kumar Gala <galak@codeaurora.org>
>>>
>>>    Split updating the DRA7.dtsi file for adding the routable-irqs
>>>
>>> Previous discussions that led to this is at
>>> 	https://lkml.org/lkml/2013/9/18/540
>>>
>>> The V1,V2,V3,V4 post of these patches is at
>>>       [V1]  https://lkml.org/lkml/2013/9/30/283
>>>       [V2]  http://www.spinics.net/lists/linux-omap/msg99540.html
>>>       [V3]  http://www.kernelhub.org/?msg=356470&p=2
>>>       [V4]  http://www.spinics.net/lists/linux-doc/msg16726.html
>>>
>>> Sricharan R (4):
>>>   DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
>>>   DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
>>>   ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
>>>   ARM: DRA: Enable Crossbar IP support for DRA7XX
>>>
>>>  Documentation/devicetree/bindings/arm/gic.txt      |    6 +
>>>  .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
>>>  arch/arm/mach-omap2/Kconfig                        |    1 +
>>>  arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
>>>  arch/arm/mach-omap2/omap4-common.c                 |    2 +
>>>  drivers/irqchip/Kconfig                            |    8 +
>>>  drivers/irqchip/Makefile                           |    1 +
>>>  drivers/irqchip/irq-crossbar.c                     |  208 ++++++++++++++++++++
>>>  drivers/irqchip/irq-gic.c                          |   81 +++++++-
>>>  include/linux/irqchip/arm-gic.h                    |    7 +-
>>>  include/linux/irqchip/irq-crossbar.h               |   11 ++
>>>  11 files changed, 343 insertions(+), 13 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
>>>  create mode 100644 drivers/irqchip/irq-crossbar.c
>>>  create mode 100644 include/linux/irqchip/irq-crossbar.h
>>>
>>
>> I have addressed all the comments on this series, can this be merged now ?
>>
>   Ping..
> 
Thomas has already given his reviewed-by tag so the patches can be
taken via arm-soc tree considering OMAP and GIC changes. Can you
create a branch with all these patches applied and send it
to Tony ?

Tony, Will you able to pull this and send it up to arm-soc ?

Regards,
Santosh

Re: [PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Sricharan R]

On Thursday 26 December 2013 11:14 PM, Santosh Shilimkar wrote:
> Sricharan,
> 
> On Wednesday 25 December 2013 11:52 PM, Sricharan R wrote:
>> Hi Thomas,
>> On Wednesday 18 December 2013 02:49 PM, Sricharan R wrote:
>>> Hi Thomas,
>>>
>>> On Tuesday 03 December 2013 03:57 PM, Sricharan R wrote:
>>>> Some socs have a large number of interrupts requests to service
>>>> the needs of its many peripherals and subsystems. All of the interrupt
>>>> requests lines from the subsystems are not needed at the same
>>>> time, so they have to be muxed to the controllers appropriately.
>>>> In such places a interrupt controllers are preceded by an
>>>> IRQ CROSSBAR that provides flexibility in muxing the device interrupt
>>>> requests to the controller inputs.
>>>>
>>>> This series models the peripheral interrupts that can be routed through
>>>> the crossbar to the GIC as 'routable-irqs'. The routable irqs are added
>>>> in a separate linear domain inside the GIC. The registered routable domain's
>>>> callback are invoked as a part of the GIC's callback, which in turn should
>>>> allocate a free irq line and configure the IP accordingly. So every peripheral
>>>> in the dts files mentions the fixed crossbar number as its interrupt. A free
>>>> gic line for that gets allocated and configured when the peripheral interrupts
>>>> are mapped.
>>>>
>>>> The minimal crossbar driver to track and allocate free GIC lines and configure the
>>>> crossbar is added here, along with the DT bindings.
>>>>
>>>> V5:
>>>>    Addressed a comment from Mark Rutland <mark.rutland@arm.com>,
>>>>    updated tags and rebased on 3.13-rc2
>>>>
>>>> V4:
>>>>    Addressed a couple of comments and split the DTS file updates in to
>>>>    a separate series.
>>>>
>>>> V3:
>>>>    Addressed few more comments from Thomas Gleixner <tglx@linutronix.de>
>>>>
>>>>    Rebased patches 3,4,5,7 which updates the DTS file on top of below branch
>>>> 	   git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
>>>> 	   for_3.13/dts
>>>>
>>>>    Rebased patches 1,2,6 on top of 3.12 mainline
>>>>    Updated Commit tags
>>>>
>>>> V2:
>>>>    Addressed Thomas Gleixner <tglx@linutronix.de> comments and
>>>>    Kumar Gala <galak@codeaurora.org>
>>>>
>>>>    Split updating the DRA7.dtsi file for adding the routable-irqs
>>>>
>>>> Previous discussions that led to this is at
>>>> 	https://lkml.org/lkml/2013/9/18/540
>>>>
>>>> The V1,V2,V3,V4 post of these patches is at
>>>>       [V1]  https://lkml.org/lkml/2013/9/30/283
>>>>       [V2]  http://www.spinics.net/lists/linux-omap/msg99540.html
>>>>       [V3]  http://www.kernelhub.org/?msg=356470&p=2
>>>>       [V4]  http://www.spinics.net/lists/linux-doc/msg16726.html
>>>>
>>>> Sricharan R (4):
>>>>   DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
>>>>   DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
>>>>   ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
>>>>   ARM: DRA: Enable Crossbar IP support for DRA7XX
>>>>
>>>>  Documentation/devicetree/bindings/arm/gic.txt      |    6 +
>>>>  .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
>>>>  arch/arm/mach-omap2/Kconfig                        |    1 +
>>>>  arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
>>>>  arch/arm/mach-omap2/omap4-common.c                 |    2 +
>>>>  drivers/irqchip/Kconfig                            |    8 +
>>>>  drivers/irqchip/Makefile                           |    1 +
>>>>  drivers/irqchip/irq-crossbar.c                     |  208 ++++++++++++++++++++
>>>>  drivers/irqchip/irq-gic.c                          |   81 +++++++-
>>>>  include/linux/irqchip/arm-gic.h                    |    7 +-
>>>>  include/linux/irqchip/irq-crossbar.h               |   11 ++
>>>>  11 files changed, 343 insertions(+), 13 deletions(-)
>>>>  create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
>>>>  create mode 100644 drivers/irqchip/irq-crossbar.c
>>>>  create mode 100644 include/linux/irqchip/irq-crossbar.h
>>>>
>>>
>>> I have addressed all the comments on this series, can this be merged now ?
>>>
>>   Ping..
>>
> Thomas has already given his reviewed-by tag so the patches can be
> taken via arm-soc tree considering OMAP and GIC changes. Can you
> create a branch with all these patches applied and send it
> to Tony ?
> 
Ok, i will send out a branch for this.

Regards,
 Sricharan

Re: [PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Sricharan R]

Hi Tony,

On Friday 27 December 2013 07:19 PM, Sricharan R wrote:
> On Thursday 26 December 2013 11:14 PM, Santosh Shilimkar wrote:
>> Sricharan,
>>
>> On Wednesday 25 December 2013 11:52 PM, Sricharan R wrote:
>>> Hi Thomas,
>>> On Wednesday 18 December 2013 02:49 PM, Sricharan R wrote:
>>>> Hi Thomas,
>>>>
>>>> On Tuesday 03 December 2013 03:57 PM, Sricharan R wrote:
>>>>> Some socs have a large number of interrupts requests to service
>>>>> the needs of its many peripherals and subsystems. All of the interrupt
>>>>> requests lines from the subsystems are not needed at the same
>>>>> time, so they have to be muxed to the controllers appropriately.
>>>>> In such places a interrupt controllers are preceded by an
>>>>> IRQ CROSSBAR that provides flexibility in muxing the device interrupt
>>>>> requests to the controller inputs.
>>>>>
>>>>> This series models the peripheral interrupts that can be routed through
>>>>> the crossbar to the GIC as 'routable-irqs'. The routable irqs are added
>>>>> in a separate linear domain inside the GIC. The registered routable domain's
>>>>> callback are invoked as a part of the GIC's callback, which in turn should
>>>>> allocate a free irq line and configure the IP accordingly. So every peripheral
>>>>> in the dts files mentions the fixed crossbar number as its interrupt. A free
>>>>> gic line for that gets allocated and configured when the peripheral interrupts
>>>>> are mapped.
>>>>>
>>>>> The minimal crossbar driver to track and allocate free GIC lines and configure the
>>>>> crossbar is added here, along with the DT bindings.
>>>>>
>>>>> V5:
>>>>>    Addressed a comment from Mark Rutland <mark.rutland@arm.com>,
>>>>>    updated tags and rebased on 3.13-rc2
>>>>>
>>>>> V4:
>>>>>    Addressed a couple of comments and split the DTS file updates in to
>>>>>    a separate series.
>>>>>
>>>>> V3:
>>>>>    Addressed few more comments from Thomas Gleixner <tglx@linutronix.de>
>>>>>
>>>>>    Rebased patches 3,4,5,7 which updates the DTS file on top of below branch
>>>>> 	   git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
>>>>> 	   for_3.13/dts
>>>>>
>>>>>    Rebased patches 1,2,6 on top of 3.12 mainline
>>>>>    Updated Commit tags
>>>>>
>>>>> V2:
>>>>>    Addressed Thomas Gleixner <tglx@linutronix.de> comments and
>>>>>    Kumar Gala <galak@codeaurora.org>
>>>>>
>>>>>    Split updating the DRA7.dtsi file for adding the routable-irqs
>>>>>
>>>>> Previous discussions that led to this is at
>>>>> 	https://lkml.org/lkml/2013/9/18/540
>>>>>
>>>>> The V1,V2,V3,V4 post of these patches is at
>>>>>       [V1]  https://lkml.org/lkml/2013/9/30/283
>>>>>       [V2]  http://www.spinics.net/lists/linux-omap/msg99540.html
>>>>>       [V3]  http://www.kernelhub.org/?msg=356470&p=2
>>>>>       [V4]  http://www.spinics.net/lists/linux-doc/msg16726.html
>>>>>
>>>>> Sricharan R (4):
>>>>>   DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
>>>>>   DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
>>>>>   ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
>>>>>   ARM: DRA: Enable Crossbar IP support for DRA7XX
>>>>>
>>>>>  Documentation/devicetree/bindings/arm/gic.txt      |    6 +
>>>>>  .../devicetree/bindings/arm/omap/crossbar.txt      |   27 +++
>>>>>  arch/arm/mach-omap2/Kconfig                        |    1 +
>>>>>  arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
>>>>>  arch/arm/mach-omap2/omap4-common.c                 |    2 +
>>>>>  drivers/irqchip/Kconfig                            |    8 +
>>>>>  drivers/irqchip/Makefile                           |    1 +
>>>>>  drivers/irqchip/irq-crossbar.c                     |  208 ++++++++++++++++++++
>>>>>  drivers/irqchip/irq-gic.c                          |   81 +++++++-
>>>>>  include/linux/irqchip/arm-gic.h                    |    7 +-
>>>>>  include/linux/irqchip/irq-crossbar.h               |   11 ++
>>>>>  11 files changed, 343 insertions(+), 13 deletions(-)
>>>>>  create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
>>>>>  create mode 100644 drivers/irqchip/irq-crossbar.c
>>>>>  create mode 100644 include/linux/irqchip/irq-crossbar.h
>>>>>
>>>>
>>>> I have addressed all the comments on this series, can this be merged now ?
>>>>
>>>   Ping..
>>>
>> Thomas has already given his reviewed-by tag so the patches can be
>> taken via arm-soc tree considering OMAP and GIC changes. Can you
>> create a branch with all these patches applied and send it
>> to Tony ?
>>
> Ok, i will send out a branch for this.
> 
 
 I have pushed the below branch

git://github.com/Sricharanti/sricharan.git
branch: crossbar

This is on top of Tony's linux-omap master branch

Regards,
 Sricharan

Re: [PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Tony Lindgren]

* Sricharan R <r.sricharan@ti.com> [131229 22:30]:
> On Friday 27 December 2013 07:19 PM, Sricharan R wrote:
> > On Thursday 26 December 2013 11:14 PM, Santosh Shilimkar wrote:
> >> On Wednesday 25 December 2013 11:52 PM, Sricharan R wrote:
> >>> On Wednesday 18 December 2013 02:49 PM, Sricharan R wrote:
> >>>> I have addressed all the comments on this series, can this be merged now ?
> >>>>
> >>>   Ping..
> >>>
> >> Thomas has already given his reviewed-by tag so the patches can be
> >> taken via arm-soc tree considering OMAP and GIC changes. Can you
> >> create a branch with all these patches applied and send it
> >> to Tony ?
> >>
> > Ok, i will send out a branch for this.
> > 
>  
>  I have pushed the below branch
> 
> git://github.com/Sricharanti/sricharan.git
> branch: crossbar
> 
> This is on top of Tony's linux-omap master branch

The linux-omap master branch cannot be used as a base as it
contains tons of commit history not in mainline. So I'll
manually applied these patches into omap-for-v3.14/crosbar
branch.

Regards,

Tony

Re: [PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Tony Lindgren]

* Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> [140107 15:10]:
> * Sricharan R <r.sricharan-l0cyMroinI0@public.gmane.org> [131229 22:30]:
> > On Friday 27 December 2013 07:19 PM, Sricharan R wrote:
> > > On Thursday 26 December 2013 11:14 PM, Santosh Shilimkar wrote:
> > >> On Wednesday 25 December 2013 11:52 PM, Sricharan R wrote:
> > >>> On Wednesday 18 December 2013 02:49 PM, Sricharan R wrote:
> > >>>> I have addressed all the comments on this series, can this be merged now ?
> > >>>>
> > >>>   Ping..
> > >>>
> > >> Thomas has already given his reviewed-by tag so the patches can be
> > >> taken via arm-soc tree considering OMAP and GIC changes. Can you
> > >> create a branch with all these patches applied and send it
> > >> to Tony ?
> > >>
> > > Ok, i will send out a branch for this.
> > > 
> >  
> >  I have pushed the below branch
> > 
> > git://github.com/Sricharanti/sricharan.git
> > branch: crossbar
> > 
> > This is on top of Tony's linux-omap master branch
> 
> The linux-omap master branch cannot be used as a base as it
> contains tons of commit history not in mainline. So I'll
> manually applied these patches into omap-for-v3.14/crosbar
> branch.

Oops, I noticed some errors on these:

WARNING: drivers/built-in.o(.text+0xcd0): Section mismatch in reference from the function irqcrossbar_init() to the function .init.text:crossbar_of_init()
The function irqcrossbar_init() references
the function __init crossbar_of_init().
This is often because irqcrossbar_init lacks a __init 
annotation or the annotation of crossbar_of_init is wrong.

WARNING: drivers/built-in.o(.text+0xcdc): Section mismatch in reference from the function irqcrossbar_init() to the (unknown reference) .init.rodata:(unknown)
The function irqcrossbar_init() references
the (unknown reference) __initconst (unknown).
This is often because irqcrossbar_init lacks a __initconst 
annotation or the annotation of (unknown) is wrong.

So I've dropped them for now. Care to fix up those errors and
base your patches against let's say v3.13-rc5?

Regards,

Tony
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Re: [PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Sricharan R]

Hi Tony,

On Wednesday 08 January 2014 05:25 AM, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [140107 15:10]:
>> * Sricharan R <r.sricharan@ti.com> [131229 22:30]:
>>> On Friday 27 December 2013 07:19 PM, Sricharan R wrote:
>>>> On Thursday 26 December 2013 11:14 PM, Santosh Shilimkar wrote:
>>>>> On Wednesday 25 December 2013 11:52 PM, Sricharan R wrote:
>>>>>> On Wednesday 18 December 2013 02:49 PM, Sricharan R wrote:
>>>>>>> I have addressed all the comments on this series, can this be merged now ?
>>>>>>>
>>>>>>   Ping..
>>>>>>
>>>>> Thomas has already given his reviewed-by tag so the patches can be
>>>>> taken via arm-soc tree considering OMAP and GIC changes. Can you
>>>>> create a branch with all these patches applied and send it
>>>>> to Tony ?
>>>>>
>>>> Ok, i will send out a branch for this.
>>>>
>>>  
>>>  I have pushed the below branch
>>>
>>> git://github.com/Sricharanti/sricharan.git
>>> branch: crossbar
>>>
>>> This is on top of Tony's linux-omap master branch
>>
>> The linux-omap master branch cannot be used as a base as it
>> contains tons of commit history not in mainline. So I'll
>> manually applied these patches into omap-for-v3.14/crosbar
>> branch.
> 
> Oops, I noticed some errors on these:
> 
> WARNING: drivers/built-in.o(.text+0xcd0): Section mismatch in reference from the function irqcrossbar_init() to the function .init.text:crossbar_of_init()
> The function irqcrossbar_init() references
> the function __init crossbar_of_init().
> This is often because irqcrossbar_init lacks a __init 
> annotation or the annotation of crossbar_of_init is wrong.
> 
> WARNING: drivers/built-in.o(.text+0xcdc): Section mismatch in reference from the function irqcrossbar_init() to the (unknown reference) .init.rodata:(unknown)
> The function irqcrossbar_init() references
> the (unknown reference) __initconst (unknown).
> This is often because irqcrossbar_init lacks a __initconst 
> annotation or the annotation of (unknown) is wrong.
> 
> So I've dropped them for now. Care to fix up those errors and
> base your patches against let's say v3.13-rc5?
> 
   Very Sorry for the section mismatch warning.
   I have fixed it and pushed a new branch below based on v3.13-rc5

   git://github.com/Sricharanti/sricharan.git
   branch: crossbar_3.13_rc5

Regards,
 Sricharan

Re: [PATCH V5 0/4] DRIVERS: IRQCHIP: Add support for crossbar IP

[Tony Lindgren]

* Sricharan R <r.sricharan-l0cyMroinI0@public.gmane.org> [140108 05:20]:
> On Wednesday 08 January 2014 05:25 AM, Tony Lindgren wrote:
> > 
> > Oops, I noticed some errors on these:
> > 
> > WARNING: drivers/built-in.o(.text+0xcd0): Section mismatch in reference from the function irqcrossbar_init() to the function .init.text:crossbar_of_init()
> > The function irqcrossbar_init() references
> > the function __init crossbar_of_init().
> > This is often because irqcrossbar_init lacks a __init 
> > annotation or the annotation of crossbar_of_init is wrong.
> > 
> > WARNING: drivers/built-in.o(.text+0xcdc): Section mismatch in reference from the function irqcrossbar_init() to the (unknown reference) .init.rodata:(unknown)
> > The function irqcrossbar_init() references
> > the (unknown reference) __initconst (unknown).
> > This is often because irqcrossbar_init lacks a __initconst 
> > annotation or the annotation of (unknown) is wrong.
> > 
> > So I've dropped them for now. Care to fix up those errors and
> > base your patches against let's say v3.13-rc5?
> > 
>    Very Sorry for the section mismatch warning.
>    I have fixed it and pushed a new branch below based on v3.13-rc5
> 
>    git://github.com/Sricharanti/sricharan.git
>    branch: crossbar_3.13_rc5

Thanks, applying again.

Regards,

Tony
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