[PATCH V4 0/2] Exynos5250 SATA Support

[PATCH V4 0/2] Exynos5250 SATA Support

[Yuvaraj Kumar C D]

This patch series enable the SATA support on Exynos5250 based boards.
It incorporates the generic phy framework to deal with sata phy.

This patch depends on the below patches
	[1]. drivers: phy: add generic PHY framework
		by Kishon Vijay Abraham I<kishon@ti.com>
	[2]. ata: ahci_platform: Manage SATA PHY
		by Roger Quadros <rogerq@ti.com>
	[3].ARM: dts: Add pmu sysreg node to exynos5250 and
		exynos5420 dtsi files
		by Leela Krishna Amudala <l.krishna@samsung.com>
	[4]. i2c: s3c2410 : Add polling mode support
		by Vasanth Ananthan <vasanth.a@samsung.com>

Changes from V3:
	1.Moved the devicetree binding documentation
	from /bindings/ata/ to bindings/phy/ .
	2.Moved devm_phy_create call before to 
	the devm_phy_provider_register. 

Changes from V2:
	1.Removed of_match_table
	2.Moved to syscon interface for PMU handling.

Changes from V1:
	1. Dropped the patch 
	ahci: exynos: add ahci sata support on Exynos platform

	2.Adapt to latest generic PHY framework available in 
	git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git next

Yuvaraj Kumar C D (2):
  Phy: Exynos: Add Exynos5250 sata phy driver
  ARM: dts: Enable ahci sata and sata phy

 .../devicetree/bindings/ata/exynos-sata-phy.txt    |   14 --
 .../devicetree/bindings/ata/exynos-sata.txt        |   25 ++-
 .../devicetree/bindings/phy/samsung-phy.txt        |   40 ++++
 arch/arm/boot/dts/exynos5250-arndale.dts           |   11 +
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    8 +-
 arch/arm/boot/dts/exynos5250.dtsi                  |   16 +-
 drivers/phy/Kconfig                                |   11 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/exynos5250_phy_i2c.c                   |   44 ++++
 drivers/phy/sata_phy_exynos5250.c                  |  220 ++++++++++++++++++++
 drivers/phy/sata_phy_exynos5250.h                  |   35 ++++
 11 files changed, 392 insertions(+), 33 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
 create mode 100644 drivers/phy/exynos5250_phy_i2c.c
 create mode 100644 drivers/phy/sata_phy_exynos5250.c
 create mode 100644 drivers/phy/sata_phy_exynos5250.h

-- 
1.7.9.5

[PATCH V4 1/2] Phy: Exynos: Add Exynos5250 sata phy driver

[Yuvaraj Kumar C D]

This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
phy comprises of CMU and TRSV blocks which are of I2C register Map.
So this patch also adds a i2c client driver, which is used configure
the CMU and TRSV block of exynos5250 SATA PHY.

This patch incorporates the generic phy framework to deal with sata
phy.

This patch depends on the below patches
	[1].drivers: phy: add generic PHY framework
		by Kishon Vijay Abraham I<kishon@ti.com>
	[2].ata: ahci_platform: Manage SATA PHY
		by Roger Quadros <rogerq@ti.com>

Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Girish K S <ks.giri@samsung.com>
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
---
Changes from V3:
	1.Moved devm_phy_create before to devm_phy_provider_register.

Changes from V2:
	1.Removed of_match_table
	2.Moved to syscon interface for PMU handling.

Changes from V1:
	1.Adapted to latest version of Generic PHY framework
	2.Removed exynos_sata_i2c_remove function.


 drivers/phy/Kconfig               |   11 ++
 drivers/phy/Makefile              |    1 +
 drivers/phy/exynos5250_phy_i2c.c  |   44 ++++++++
 drivers/phy/sata_phy_exynos5250.c |  220 +++++++++++++++++++++++++++++++++++++
 drivers/phy/sata_phy_exynos5250.h |   35 ++++++
 5 files changed, 311 insertions(+)
 create mode 100644 drivers/phy/exynos5250_phy_i2c.c
 create mode 100644 drivers/phy/sata_phy_exynos5250.c
 create mode 100644 drivers/phy/sata_phy_exynos5250.h

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index d0611b8..6ea124d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -57,4 +57,15 @@ config PHY_EXYNOS_DP_VIDEO
 	help
 	  Support for Display Port PHY found on Samsung EXYNOS SoCs.
 
+config EXYNOS5250_SATA_PHY
+	tristate "Exynos5250 Sata SerDes/PHY driver"
+	depends on SOC_EXYNOS5250
+	select GENERIC_PHY
+	select MFD_SYSCON if ARCH_EXYNOS5
+	help
+	  Enable this to support SATA SerDes/Phy found on Samsung's
+	  Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
+	  SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.It supports one SATA host
+	  port to accept one SATA device.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 4e4adc9..b73eb73 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
 obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
+obj-$(CONFIG_EXYNOS5250_SATA_PHY)	+= sata_phy_exynos5250.o exynos5250_phy_i2c.o
diff --git a/drivers/phy/exynos5250_phy_i2c.c b/drivers/phy/exynos5250_phy_i2c.c
new file mode 100644
index 0000000..c0c1150
--- /dev/null
+++ b/drivers/phy/exynos5250_phy_i2c.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Author:
+ *	Yuvaraj C D <yuvaraj.cd@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include "sata_phy_exynos5250.h"
+
+static int exynos_sata_i2c_probe(struct i2c_client *client,
+		const struct i2c_device_id *i2c_id)
+{
+	int ret = 0;
+	ret = sataphy_attach_i2c_client(client);
+	if (ret < 0)
+		return ret;
+
+	dev_info(&client->adapter->dev,
+		"attached %s into sataphy i2c adapter successfully\n",
+		client->name);
+
+	return ret;
+}
+
+static const struct i2c_device_id sataphy_i2c_device_match[] = {
+	{ "exynos-sataphy-i2c", 0 },
+};
+
+struct i2c_driver sataphy_i2c_driver = {
+	.probe		= exynos_sata_i2c_probe,
+	.id_table	= sataphy_i2c_device_match,
+	.driver   = {
+		.name = "exynos-sataphy-i2c",
+		.owner = THIS_MODULE,
+		},
+};
diff --git a/drivers/phy/sata_phy_exynos5250.c b/drivers/phy/sata_phy_exynos5250.c
new file mode 100644
index 0000000..0765863
--- /dev/null
+++ b/drivers/phy/sata_phy_exynos5250.c
@@ -0,0 +1,220 @@
+/*
+ * Samsung SATA SerDes(PHY) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Authors: Girish K S <ks.giri@samsung.com>
+ *         Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/spinlock.h>
+#include <linux/mfd/syscon.h>
+#include "sata_phy_exynos5250.h"
+
+static struct i2c_client *phy_i2c_client;
+
+struct exynos_sata_phy {
+	struct phy *phy;
+	struct clk *phyclk;
+	void __iomem *regs;
+	void __iomem *pmureg;
+};
+
+static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
+				u32 status)
+{
+	unsigned long timeout = jiffies + usecs_to_jiffies(1000);
+	while (time_before(jiffies, timeout)) {
+		if ((readl(base + reg) & checkbit) == status)
+			return true;
+	}
+	return false;
+}
+
+int sataphy_attach_i2c_client(struct i2c_client *sata_phy)
+{
+	if (!sata_phy)
+		return -EPROBE_DEFER;
+	else
+		phy_i2c_client = sata_phy;
+
+	return 0;
+}
+
+static int exynos_sata_phy_power_on(struct phy *phy)
+{
+	struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
+
+	if (sata_phy->pmureg)
+		regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
+			EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
+
+	return 0;
+}
+
+static int exynos_sata_phy_power_off(struct phy *phy)
+{
+	struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
+
+	if (sata_phy->pmureg)
+		regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
+			EXYNOS5_SATAPHY_PMU_ENABLE, ~EXYNOS_SATA_PHY_EN);
+
+	return 0;
+}
+
+static int exynos_sata_phy_init(struct phy *phy)
+{
+	u32 val = 0;
+	int ret = 0;
+	u8 buf[] = { 0x3A, 0x0B };
+	struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
+
+	if (sata_phy->pmureg)
+		regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
+			EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
+
+	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
+	val |= 0xFF;
+	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
+	val |= LINK_RESET;
+	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
+	val |= RESET_CMN_RST_N;
+	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+	val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
+	val &= ~PHCTRLM_REF_RATE;
+	writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
+
+	/* High speed enable for Gen3 */
+	val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
+	val |= PHCTRLM_HIGH_SPEED;
+	writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
+
+	val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
+	writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
+
+	writel(0x2, sata_phy->regs + EXYNOS5_SATA_MODE0);
+
+	ret = i2c_master_send(phy_i2c_client, buf, sizeof(buf));
+	if (ret < 0)
+		return -ENXIO;
+
+	/* release cmu reset */
+	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
+	val &= ~RESET_CMN_RST_N;
+	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
+	val |= RESET_CMN_RST_N;
+	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+	return (wait_for_reg_status(sata_phy->regs, EXYNOS5_SATA_PHSATA_STATM,
+		PHSTATM_PLL_LOCKED, 1)) ? 0 : -EINVAL;
+
+}
+
+static struct phy_ops exynos_sata_phy_ops = {
+	.init		= exynos_sata_phy_init,
+	.power_on	= exynos_sata_phy_power_on,
+	.power_off	= exynos_sata_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int exynos_sata_phy_probe(struct platform_device *pdev)
+{
+	struct exynos_sata_phy *sata;
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct phy_provider *phy_provider;
+	int ret = 0;
+
+	sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
+	if (!sata)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	sata->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(sata->regs))
+		return PTR_ERR(sata->regs);
+
+	sata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
+					"samsung,syscon-phandle");
+	if (!sata->pmureg) {
+		dev_err(dev, "syscon regmap lookup failed.\n");
+		return PTR_ERR(sata->pmureg);
+	}
+	dev_set_drvdata(dev, sata);
+
+	if (i2c_add_driver(&sataphy_i2c_driver)) {
+		dev_err(dev, "failed to register sataphy i2c driver\n");
+		return -ENOENT;
+	}
+
+	sata->phyclk = devm_clk_get(dev, "sata_phyctrl");
+	if (IS_ERR(sata->phyclk)) {
+		dev_err(dev, "failed to get clk for PHY\n");
+		return PTR_ERR(sata->phyclk);
+	}
+
+	ret = clk_prepare_enable(sata->phyclk);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable source clk\n");
+		return ret;
+	}
+
+	sata->phy = devm_phy_create(dev, &exynos_sata_phy_ops, NULL);
+	if (IS_ERR(sata->phy)) {
+		dev_err(dev, "failed to create PHY\n");
+		return PTR_ERR(sata->phy);
+	}
+
+	phy_provider = devm_of_phy_provider_register(dev,
+					of_phy_simple_xlate);
+	if (IS_ERR(phy_provider))
+		return PTR_ERR(phy_provider);
+
+	phy_set_drvdata(sata->phy, sata);
+	return 0;
+}
+
+static const struct of_device_id exynos_sata_phy_of_match[] = {
+	{ .compatible = "samsung,exynos5250-sata-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, exynos_sata_phy_of_match);
+
+static struct platform_driver exynos_sata_phy_driver = {
+	.probe	= exynos_sata_phy_probe,
+	.driver = {
+		.of_match_table	= exynos_sata_phy_of_match,
+		.name  = "samsung,sata-phy",
+		.owner = THIS_MODULE,
+	}
+};
+module_platform_driver(exynos_sata_phy_driver);
+
+MODULE_DESCRIPTION("Samsung SerDes PHY driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("ks.giri <ks.giri@samsung.com>");
+MODULE_AUTHOR("Yuvaraj C D <yuvaraj.cd@samsung.com>");
diff --git a/drivers/phy/sata_phy_exynos5250.h b/drivers/phy/sata_phy_exynos5250.h
new file mode 100644
index 0000000..3e2089d
--- /dev/null
+++ b/drivers/phy/sata_phy_exynos5250.h
@@ -0,0 +1,35 @@
+/*
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author:
+ *	Yuvaraj Kumar C D<yuvaraj.cd@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#define EXYNOS5_SATA_RESET		0x4
+#define EXYNOS5_SATA_MODE0		0x10
+#define EXYNOS5_SATA_CTRL0		0x14
+#define EXYNOS5_SATA_STAT0		0x18
+#define EXYNOS5_SATA_PHSATA_CTRLM	0xE0
+#define EXYNOS5_SATA_PHSATA_CTRL0	0xE4
+#define EXYNOS5_SATA_PHSATA_STATM	0xF0
+#define EXYNOS5_SATA_PHSTAT0		0xF4
+
+#define RESET_CMN_RST_N			(1 << 1)
+#define LINK_RESET			0xF0000
+#define CTRL0_P0_PHY_CALIBRATED_SEL	(1 << 9)
+#define CTRL0_P0_PHY_CALIBRATED		(1 << 8)
+#define PHCTRLM_REF_RATE		(1 << 1)
+#define PHCTRLM_HIGH_SPEED		(1 << 0)
+#define PHSTATM_PLL_LOCKED		(1 << 0)
+#define SATA_PHY_CON_RESET		(LINK_RESET | 3F)
+#define EXYNOS_SATA_PHY_EN		(1 << 0)
+#define SATAPHY_CONTROL_OFFSET		0x0724
+#define EXYNOS5_SATAPHY_PMU_ENABLE	(1 << 0)
+
+int sataphy_attach_i2c_client(struct i2c_client *sata_phy);
+extern struct i2c_driver sataphy_i2c_driver;
-- 
1.7.9.5

[PATCH V4 2/2] ARM: dts: Enable ahci sata and sata phy

[Yuvaraj Kumar C D]

This patch adds dt entry for ahci sata controller and its
corresponding phy controller.phy node has been added w.r.t
new generic phy framework.

Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
---

Changes since V3:
	1.Moved the binding info to the /bindings/phy/

Changes since V2:
	1.Used syscon interface to PMU handling.
	2.Changed "sata-phy-i2c" to "exynos-sataphy-i2c".

Changes since V1:
	1.Minor changes to node name convention.
	2.Updated binding document.

 .../devicetree/bindings/ata/exynos-sata-phy.txt    |   14 -------
 .../devicetree/bindings/ata/exynos-sata.txt        |   25 +++++++-----
 .../devicetree/bindings/phy/samsung-phy.txt        |   40 ++++++++++++++++++++
 arch/arm/boot/dts/exynos5250-arndale.dts           |   11 ++++++
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    8 +---
 arch/arm/boot/dts/exynos5250.dtsi                  |   16 ++++++--
 6 files changed, 81 insertions(+), 33 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/ata/exynos-sata-phy.txt

diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
deleted file mode 100644
index 37824fa..0000000
--- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Samsung SATA PHY Controller
-
-SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
-Each SATA PHY controller should have its own node.
-
-Required properties:
-- compatible        : compatible list, contains "samsung,exynos5-sata-phy"
-- reg               : <registers mapping>
-
-Example:
-        sata@ffe07000 {
-                compatible = "samsung,exynos5-sata-phy";
-                reg = <0xffe07000 0x1000>;
-        };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
index 0849f10..b2adb1f 100644
--- a/Documentation/devicetree/bindings/ata/exynos-sata.txt
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -4,14 +4,21 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 
 Required properties:
-- compatible        : compatible list, contains "samsung,exynos5-sata"
-- interrupts        : <interrupt mapping for SATA IRQ>
-- reg               : <registers mapping>
-- samsung,sata-freq : <frequency in MHz>
+- compatible		: compatible list, contains "samsung,exynos5-sata"
+- interrupts		: <interrupt mapping for SATA IRQ>
+- reg			: <registers mapping>
+- samsung,sata-freq	: <frequency in MHz>
+- phys			: as mentioned in phy-bindings.txt
+- phy-names		: as mentioned in phy-bindings.txt
 
 Example:
-        sata@ffe08000 {
-                compatible = "samsung,exynos5-sata";
-                reg = <0xffe08000 0x1000>;
-                interrupts = <115>;
-        };
+	sata@122f0000 {
+		compatible = "snps,dwc-ahci";
+		samsung,sata-freq = <66>;
+		reg = <0x122f0000 0x1ff>;
+		interrupts = <0 115 0>;
+		clocks = <&clock 277>, <&clock 143>;
+		clock-names = "sata", "sclk_sata";
+		phys = <&sata_phy>;
+		phy-names = "sata-phy";
+	};
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..876fe9b 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,43 @@ Required properties:
 - compatible : should be "samsung,exynos5250-dp-video-phy";
 - reg : offset and length of the Display Port PHY register set;
 - #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung SATA PHY Controller
+---------------------------
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible        : compatible list, contains "samsung,exynos5250-sata-phy"
+- reg : offset and length of the SATA PHY register set;
+- #phy-cells : from the generic phy bindings;
+
+Example:
+	sata_phy: sata-phy@12170000 {
+		compatible = "samsung,exynos5250-sata-phy";
+		reg = <0x12170000 0x1ff>;
+		clocks = <&clock 287>;
+		clock-names = "sata_phyctrl";
+		#phy-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		sataphy-pmu {
+			reg = <0x10040724 0x4>;
+		};
+	};
+
+Device-Tree bindings for sataphy i2c client driver
+--------------------------------------------------
+
+Required properties:
+compatible: Should be "samsung,exynos-sataphy-i2c"
+- reg: I2C address of the sataphy i2c device.
+
+Example:
+
+	sata-phy@38 {
+		compatible = "samsung,exynos-sataphy-i2c";
+		reg = <0x38>;
+	};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index b42e658..25fe5a3 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -370,6 +370,17 @@
 		};
 	};
 
+	i2c@121D0000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-max-bus-freq = <40000>;
+		samsung,i2c-slave-addr = <0x38>;
+
+		sata-phy@38 {
+			compatible = "samsung,exynos-sataphy-i2c";
+			reg = <0x38>;
+		};
+	};
+
 	mmc_0: mmc@12200000 {
 		status = "okay";
 		num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e69837..9e449e6 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -96,16 +96,12 @@
 		samsung,i2c-slave-addr = <0x38>;
 		status = "okay";
 
-		sata-phy {
-			compatible = "samsung,sata-phy";
+		sata-phy@38 {
+			compatible = "samsung,exynos-sataphy-i2c";
 			reg = <0x38>;
 		};
 	};
 
-	sata@122F0000 {
-		samsung,sata-freq = <66>;
-	};
-
 	i2c@12C80000 {
 		samsung,i2c-sda-delay = <100>;
 		samsung,i2c-max-bus-freq = <66000>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dbb4a47..626a7d1 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -46,6 +46,7 @@
 		i2c6 = &i2c_6;
 		i2c7 = &i2c_7;
 		i2c8 = &i2c_8;
+		i2c9 = &i2c_9;
 		pinctrl0 = &pinctrl_0;
 		pinctrl1 = &pinctrl_1;
 		pinctrl2 = &pinctrl_2;
@@ -231,16 +232,23 @@
 	};
 
 	sata@122F0000 {
-		compatible = "samsung,exynos5-sata-ahci";
+		compatible = "snps,dwc-ahci";
+		samsung,sata-freq = <66>;
 		reg = <0x122F0000 0x1ff>;
 		interrupts = <0 115 0>;
 		clocks = <&clock 277>, <&clock 143>;
 		clock-names = "sata", "sclk_sata";
+		phys = <&sata_phy>;
+		phy-names = "sata-phy";
 	};
 
-	sata-phy@12170000 {
-		compatible = "samsung,exynos5-sata-phy";
+	sata_phy: sata-phy@12170000 {
+		compatible = "samsung,exynos5250-sata-phy";
 		reg = <0x12170000 0x1ff>;
+		clocks = <&clock 287>;
+		clock-names = "sata_phyctrl";
+		#phy-cells = <0>;
+		samsung,syscon-phandle = <&pmu_syscon>;
 	};
 
 	i2c_0: i2c@12C60000 {
@@ -358,7 +366,7 @@
 		status = "disabled";
 	};
 
-	i2c@121D0000 {
+	i2c_9: i2c@121D0000 {
                 compatible = "samsung,exynos5-sata-phy-i2c";
                 reg = <0x121D0000 0x100>;
                 #address-cells = <1>;
-- 
1.7.9.5

Re: [PATCH V4 1/2] Phy: Exynos: Add Exynos5250 sata phy driver

[Kishon Vijay Abraham I]

Hi Yuvaraj,

On Monday 30 December 2013 06:37 PM, Yuvaraj Kumar C D wrote:
> This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
> phy comprises of CMU and TRSV blocks which are of I2C register Map.
> So this patch also adds a i2c client driver, which is used configure
> the CMU and TRSV block of exynos5250 SATA PHY.
>
> This patch incorporates the generic phy framework to deal with sata
> phy.
>
> This patch depends on the below patches
> 	[1].drivers: phy: add generic PHY framework
> 		by Kishon Vijay Abraham I<kishon@ti.com>
> 	[2].ata: ahci_platform: Manage SATA PHY
> 		by Roger Quadros <rogerq@ti.com>
>
> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> Signed-off-by: Girish K S <ks.giri@samsung.com>
> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> ---
> Changes from V3:
> 	1.Moved devm_phy_create before to devm_phy_provider_register.
>
> Changes from V2:
> 	1.Removed of_match_table
> 	2.Moved to syscon interface for PMU handling.
>
> Changes from V1:
> 	1.Adapted to latest version of Generic PHY framework
> 	2.Removed exynos_sata_i2c_remove function.
>
>
>   drivers/phy/Kconfig               |   11 ++
>   drivers/phy/Makefile              |    1 +
>   drivers/phy/exynos5250_phy_i2c.c  |   44 ++++++++
>   drivers/phy/sata_phy_exynos5250.c |  220 +++++++++++++++++++++++++++++++++++++
>   drivers/phy/sata_phy_exynos5250.h |   35 ++++++
>   5 files changed, 311 insertions(+)
>   create mode 100644 drivers/phy/exynos5250_phy_i2c.c
>   create mode 100644 drivers/phy/sata_phy_exynos5250.c
>   create mode 100644 drivers/phy/sata_phy_exynos5250.h
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index d0611b8..6ea124d 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -57,4 +57,15 @@ config PHY_EXYNOS_DP_VIDEO
>   	help
>   	  Support for Display Port PHY found on Samsung EXYNOS SoCs.
>
> +config EXYNOS5250_SATA_PHY
> +	tristate "Exynos5250 Sata SerDes/PHY driver"
> +	depends on SOC_EXYNOS5250
> +	select GENERIC_PHY
> +	select MFD_SYSCON if ARCH_EXYNOS5
> +	help
> +	  Enable this to support SATA SerDes/Phy found on Samsung's
> +	  Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
> +	  SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.It supports one SATA host
> +	  port to accept one SATA device.
> +
>   endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 4e4adc9..b73eb73 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
>   obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
>   obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>   obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> +obj-$(CONFIG_EXYNOS5250_SATA_PHY)	+= sata_phy_exynos5250.o exynos5250_phy_i2c.o
> diff --git a/drivers/phy/exynos5250_phy_i2c.c b/drivers/phy/exynos5250_phy_i2c.c
> new file mode 100644
> index 0000000..c0c1150
> --- /dev/null
> +++ b/drivers/phy/exynos5250_phy_i2c.c
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright (C) 2013 Samsung Electronics Co.Ltd
> + * Author:
> + *	Yuvaraj C D <yuvaraj.cd@samsung.com>
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + *
> + */
> +
> +#include <linux/i2c.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include "sata_phy_exynos5250.h"
> +
> +static int exynos_sata_i2c_probe(struct i2c_client *client,
> +		const struct i2c_device_id *i2c_id)
> +{
> +	int ret = 0;
> +	ret = sataphy_attach_i2c_client(client);
> +	if (ret < 0)
> +		return ret;
> +
> +	dev_info(&client->adapter->dev,
> +		"attached %s into sataphy i2c adapter successfully\n",
> +		client->name);
> +
> +	return ret;
> +}
> +
> +static const struct i2c_device_id sataphy_i2c_device_match[] = {
> +	{ "exynos-sataphy-i2c", 0 },
> +};
> +
> +struct i2c_driver sataphy_i2c_driver = {
> +	.probe		= exynos_sata_i2c_probe,
> +	.id_table	= sataphy_i2c_device_match,
> +	.driver   = {
> +		.name = "exynos-sataphy-i2c",
> +		.owner = THIS_MODULE,
> +		},
> +};
> diff --git a/drivers/phy/sata_phy_exynos5250.c b/drivers/phy/sata_phy_exynos5250.c
> new file mode 100644
> index 0000000..0765863
> --- /dev/null
> +++ b/drivers/phy/sata_phy_exynos5250.c
> @@ -0,0 +1,220 @@
> +/*
> + * Samsung SATA SerDes(PHY) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Authors: Girish K S <ks.giri@samsung.com>
> + *         Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/i2c.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/spinlock.h>
> +#include <linux/mfd/syscon.h>
> +#include "sata_phy_exynos5250.h"
> +
> +static struct i2c_client *phy_i2c_client;
> +
> +struct exynos_sata_phy {
> +	struct phy *phy;
> +	struct clk *phyclk;
> +	void __iomem *regs;
> +	void __iomem *pmureg;
> +};
> +
> +static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
> +				u32 status)
> +{
> +	unsigned long timeout = jiffies + usecs_to_jiffies(1000);
> +	while (time_before(jiffies, timeout)) {
> +		if ((readl(base + reg) & checkbit) == status)
> +			return true;
> +	}
> +	return false;
> +}
> +
> +int sataphy_attach_i2c_client(struct i2c_client *sata_phy)
> +{
> +	if (!sata_phy)
> +		return -EPROBE_DEFER;
> +	else
> +		phy_i2c_client = sata_phy;
> +
> +	return 0;
> +}
> +
> +static int exynos_sata_phy_power_on(struct phy *phy)
> +{
> +	struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
> +
> +	if (sata_phy->pmureg)
> +		regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
> +			EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
> +
> +	return 0;
> +}
> +
> +static int exynos_sata_phy_power_off(struct phy *phy)
> +{
> +	struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
> +
> +	if (sata_phy->pmureg)
> +		regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
> +			EXYNOS5_SATAPHY_PMU_ENABLE, ~EXYNOS_SATA_PHY_EN);
> +
> +	return 0;
> +}
> +
> +static int exynos_sata_phy_init(struct phy *phy)
> +{
> +	u32 val = 0;
> +	int ret = 0;
> +	u8 buf[] = { 0x3A, 0x0B };
> +	struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
> +
> +	if (sata_phy->pmureg)
> +		regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
> +			EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
> +
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val |= 0xFF;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val |= LINK_RESET;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val |= RESET_CMN_RST_N;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
> +	val &= ~PHCTRLM_REF_RATE;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
> +
> +	/* High speed enable for Gen3 */
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
> +	val |= PHCTRLM_HIGH_SPEED;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
> +
> +	val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
> +
> +	writel(0x2, sata_phy->regs + EXYNOS5_SATA_MODE0);
> +
> +	ret = i2c_master_send(phy_i2c_client, buf, sizeof(buf));
> +	if (ret < 0)
> +		return -ENXIO;
> +
> +	/* release cmu reset */
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val &= ~RESET_CMN_RST_N;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val |= RESET_CMN_RST_N;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +
> +	return (wait_for_reg_status(sata_phy->regs, EXYNOS5_SATA_PHSATA_STATM,
> +		PHSTATM_PLL_LOCKED, 1)) ? 0 : -EINVAL;
> +
> +}
> +
> +static struct phy_ops exynos_sata_phy_ops = {
> +	.init		= exynos_sata_phy_init,
> +	.power_on	= exynos_sata_phy_power_on,
> +	.power_off	= exynos_sata_phy_power_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int exynos_sata_phy_probe(struct platform_device *pdev)
> +{
> +	struct exynos_sata_phy *sata;
> +	struct device *dev = &pdev->dev;
> +	struct resource *res;
> +	struct phy_provider *phy_provider;
> +	int ret = 0;
> +
> +	sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
> +	if (!sata)
> +		return -ENOMEM;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> +	sata->regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(sata->regs))
> +		return PTR_ERR(sata->regs);
> +
> +	sata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
> +					"samsung,syscon-phandle");
> +	if (!sata->pmureg) {
> +		dev_err(dev, "syscon regmap lookup failed.\n");
> +		return PTR_ERR(sata->pmureg);
> +	}
> +	dev_set_drvdata(dev, sata);
> +
> +	if (i2c_add_driver(&sataphy_i2c_driver)) {
> +		dev_err(dev, "failed to register sataphy i2c driver\n");
> +		return -ENOENT;
> +	}
> +
> +	sata->phyclk = devm_clk_get(dev, "sata_phyctrl");
> +	if (IS_ERR(sata->phyclk)) {
> +		dev_err(dev, "failed to get clk for PHY\n");
> +		return PTR_ERR(sata->phyclk);
> +	}
> +
> +	ret = clk_prepare_enable(sata->phyclk);
> +	if (ret < 0) {
> +		dev_err(dev, "failed to enable source clk\n");
> +		return ret;
> +	}
> +
> +	sata->phy = devm_phy_create(dev, &exynos_sata_phy_ops, NULL);
> +	if (IS_ERR(sata->phy)) {
> +		dev_err(dev, "failed to create PHY\n");
> +		return PTR_ERR(sata->phy);
> +	}
> +
> +	phy_provider = devm_of_phy_provider_register(dev,
> +					of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider))
> +		return PTR_ERR(phy_provider);
> +
> +	phy_set_drvdata(sata->phy, sata);

huh.. phy_provider_register should be after phy_set_drvdata.

Cheers
Kishon

Re: [PATCH V4 1/2] Phy: Exynos: Add Exynos5250 sata phy driver

[Bartlomiej Zolnierkiewicz]

[ added linux-ide ML to Cc: ]

Hi,

Overall the code looks good, thank you for working on this.

I still have some review comments though..

On Monday, December 30, 2013 06:37:02 PM Yuvaraj Kumar C D wrote:
> This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
> phy comprises of CMU and TRSV blocks which are of I2C register Map.
> So this patch also adds a i2c client driver, which is used configure
> the CMU and TRSV block of exynos5250 SATA PHY.
> 
> This patch incorporates the generic phy framework to deal with sata
> phy.

Two minor nits here:

- Some consistency in using of "SATA", "PHY" and "Exynos" would be
  nice, i.e.:

  s/sata/SATA/
  s/phy/PHY/
  s/exynos/Exynos/

- Please add two spaces after each "." and before new sentence.

> This patch depends on the below patches
> 	[1].drivers: phy: add generic PHY framework
> 		by Kishon Vijay Abraham I<kishon@ti.com>
> 	[2].ata: ahci_platform: Manage SATA PHY
> 		by Roger Quadros <rogerq@ti.com>
> 
> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> Signed-off-by: Girish K S <ks.giri@samsung.com>
> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> ---
> Changes from V3:
> 	1.Moved devm_phy_create before to devm_phy_provider_register.
> 
> Changes from V2:
> 	1.Removed of_match_table
> 	2.Moved to syscon interface for PMU handling.
> 
> Changes from V1:
> 	1.Adapted to latest version of Generic PHY framework
> 	2.Removed exynos_sata_i2c_remove function.
> 
> 
>  drivers/phy/Kconfig               |   11 ++
>  drivers/phy/Makefile              |    1 +
>  drivers/phy/exynos5250_phy_i2c.c  |   44 ++++++++
>  drivers/phy/sata_phy_exynos5250.c |  220 +++++++++++++++++++++++++++++++++++++

For consistency with other PHY drivers this file should be named
diffirently (phy-exynos5250-sata.c).

>  drivers/phy/sata_phy_exynos5250.h |   35 ++++++
>  5 files changed, 311 insertions(+)
>  create mode 100644 drivers/phy/exynos5250_phy_i2c.c
>  create mode 100644 drivers/phy/sata_phy_exynos5250.c
>  create mode 100644 drivers/phy/sata_phy_exynos5250.h
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index d0611b8..6ea124d 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -57,4 +57,15 @@ config PHY_EXYNOS_DP_VIDEO
>  	help
>  	  Support for Display Port PHY found on Samsung EXYNOS SoCs.
>  
> +config EXYNOS5250_SATA_PHY

I think that for consistency with other config options it should be
named PHY_EXYNOS5250_SATA instead.

> +	tristate "Exynos5250 Sata SerDes/PHY driver"
> +	depends on SOC_EXYNOS5250
> +	select GENERIC_PHY
> +	select MFD_SYSCON if ARCH_EXYNOS5

"if ARCH_EXYNOS5" check shouldn't be needed given SOC_EXYNOS5250
dependency.

> +	help
> +	  Enable this to support SATA SerDes/Phy found on Samsung's
> +	  Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
> +	  SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.It supports one SATA host
> +	  port to accept one SATA device.
> +
>  endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 4e4adc9..b73eb73 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
>  obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
>  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> +obj-$(CONFIG_EXYNOS5250_SATA_PHY)	+= sata_phy_exynos5250.o exynos5250_phy_i2c.o

Will this compile/work without I2C support?

CONFIG_EXYNOS5250_SATA_PHY doesn't require it currently.

> diff --git a/drivers/phy/exynos5250_phy_i2c.c b/drivers/phy/exynos5250_phy_i2c.c
> new file mode 100644
> index 0000000..c0c1150
> --- /dev/null
> +++ b/drivers/phy/exynos5250_phy_i2c.c
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright (C) 2013 Samsung Electronics Co.Ltd
> + * Author:
> + *	Yuvaraj C D <yuvaraj.cd@samsung.com>
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + *
> + */
> +
> +#include <linux/i2c.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>

Please add a newline here.

> +#include "sata_phy_exynos5250.h"
> +
> +static int exynos_sata_i2c_probe(struct i2c_client *client,
> +		const struct i2c_device_id *i2c_id)
> +{
> +	int ret = 0;

No need to initialize "ret", also please add a newline here.

> +	ret = sataphy_attach_i2c_client(client);
> +	if (ret < 0)
> +		return ret;
> +
> +	dev_info(&client->adapter->dev,
> +		"attached %s into sataphy i2c adapter successfully\n",
> +		client->name);
> +
> +	return ret;
> +}
> +
> +static const struct i2c_device_id sataphy_i2c_device_match[] = {
> +	{ "exynos-sataphy-i2c", 0 },
> +};
> +
> +struct i2c_driver sataphy_i2c_driver = {

Keeping it global together with sataphy_attach_i2c_client() is not very
nice.  I've talked with our local device tree guru (a.k.a. Tomasz Figa)
about this and it may be that this i2c driver is not even necessary.

If you manage to extract i2c adapter and address data from the device
tree (using proper of_* methods) they can be used instead of i2c client
data in the SATA PHY driver.

> +	.probe		= exynos_sata_i2c_probe,
> +	.id_table	= sataphy_i2c_device_match,
> +	.driver   = {
> +		.name = "exynos-sataphy-i2c",
> +		.owner = THIS_MODULE,
> +		},
> +};
> diff --git a/drivers/phy/sata_phy_exynos5250.c b/drivers/phy/sata_phy_exynos5250.c
> new file mode 100644
> index 0000000..0765863
> --- /dev/null
> +++ b/drivers/phy/sata_phy_exynos5250.c
> @@ -0,0 +1,220 @@
> +/*
> + * Samsung SATA SerDes(PHY) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Authors: Girish K S <ks.giri@samsung.com>
> + *         Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/i2c.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/spinlock.h>
> +#include <linux/mfd/syscon.h>

Please add a newline here.

> +#include "sata_phy_exynos5250.h"
> +
> +static struct i2c_client *phy_i2c_client;
> +
> +struct exynos_sata_phy {
> +	struct phy *phy;
> +	struct clk *phyclk;
> +	void __iomem *regs;
> +	void __iomem *pmureg;
> +};
> +
> +static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
> +				u32 status)
> +{
> +	unsigned long timeout = jiffies + usecs_to_jiffies(1000);

ditto

> +	while (time_before(jiffies, timeout)) {
> +		if ((readl(base + reg) & checkbit) == status)
> +			return true;
> +	}

ditto

> +	return false;
> +}
> +
> +int sataphy_attach_i2c_client(struct i2c_client *sata_phy)

sata_phy is not a best variable name here, maybe just use "client"
instead?

> +{
> +	if (!sata_phy)
> +		return -EPROBE_DEFER;
> +	else
> +		phy_i2c_client = sata_phy;
> +
> +	return 0;
> +}
> +
> +static int exynos_sata_phy_power_on(struct phy *phy)
> +{
> +	struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
> +
> +	if (sata_phy->pmureg)

No need to check it, exynos_sata_phy_probe() fails early if pmureg
cannot be find.

> +		regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
> +			EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
> +
> +	return 0;
> +}
> +
> +static int exynos_sata_phy_power_off(struct phy *phy)
> +{
> +	struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
> +
> +	if (sata_phy->pmureg)

ditto

> +		regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
> +			EXYNOS5_SATAPHY_PMU_ENABLE, ~EXYNOS_SATA_PHY_EN);
> +
> +	return 0;
> +}
> +
> +static int exynos_sata_phy_init(struct phy *phy)
> +{
> +	u32 val = 0;
> +	int ret = 0;
> +	u8 buf[] = { 0x3A, 0x0B };
> +	struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
> +
> +	if (sata_phy->pmureg)

ditto

> +		regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
> +			EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
> +
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val |= 0xFF;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val |= LINK_RESET;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val |= RESET_CMN_RST_N;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);

Please add a newline here.

> +	val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
> +	val &= ~PHCTRLM_REF_RATE;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
> +
> +	/* High speed enable for Gen3 */
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
> +	val |= PHCTRLM_HIGH_SPEED;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
> +
> +	val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;

This doesn't look correct.  The "val" variable still contains value
used previously for PHCTRLM register and now (after setting bits 8-9)
it will be reused for CTRL0 register.  I believe that there is a

	val = readl(sata_phy->regs + EXYNOS5_SATA_CTRL0);

missing here.

> +	writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
> +
> +	writel(0x2, sata_phy->regs + EXYNOS5_SATA_MODE0);

Please add a define instead of using a magic number.  Morever the code
should read the content of MODE0 register first and then set bit1 (in
the documentation that I have bits 2-31 are marked as Reserved, which
means that they are not necessarily hard-wired to zero).

Also:

This code sets PHY# speed mode to 6.0 Gb/s.  Does this setting need to
be updated when 3.0 Gb/s or 1.5 Gb/s devices are used instead?  Do such
devices work fine with the current code?

[ There is a patch adding set_speed method to the generic PHY framework:

	http://permalink.gmane.org/gmane.linux.scsi/86660

  but AHCI platform driver would still need to be updated to use it. ]

> +	ret = i2c_master_send(phy_i2c_client, buf, sizeof(buf));
> +	if (ret < 0)
> +		return -ENXIO;
> +
> +	/* release cmu reset */
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val &= ~RESET_CMN_RST_N;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +
> +	val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
> +	val |= RESET_CMN_RST_N;
> +	writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
> +
> +	return (wait_for_reg_status(sata_phy->regs, EXYNOS5_SATA_PHSATA_STATM,
> +		PHSTATM_PLL_LOCKED, 1)) ? 0 : -EINVAL;
> +
> +}
> +
> +static struct phy_ops exynos_sata_phy_ops = {
> +	.init		= exynos_sata_phy_init,
> +	.power_on	= exynos_sata_phy_power_on,
> +	.power_off	= exynos_sata_phy_power_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int exynos_sata_phy_probe(struct platform_device *pdev)
> +{
> +	struct exynos_sata_phy *sata;

Why not name it sata_phy like in other functions?

> +	struct device *dev = &pdev->dev;
> +	struct resource *res;
> +	struct phy_provider *phy_provider;
> +	int ret = 0;
> +
> +	sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
> +	if (!sata)
> +		return -ENOMEM;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> +	sata->regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(sata->regs))
> +		return PTR_ERR(sata->regs);
> +
> +	sata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
> +					"samsung,syscon-phandle");
> +	if (!sata->pmureg) {
> +		dev_err(dev, "syscon regmap lookup failed.\n");
> +		return PTR_ERR(sata->pmureg);
> +	}
> +	dev_set_drvdata(dev, sata);
> +
> +	if (i2c_add_driver(&sataphy_i2c_driver)) {
> +		dev_err(dev, "failed to register sataphy i2c driver\n");
> +		return -ENOENT;
> +	}
> +
> +	sata->phyclk = devm_clk_get(dev, "sata_phyctrl");
> +	if (IS_ERR(sata->phyclk)) {

Don't we need to also unregister i2c driver on failure?

> +		dev_err(dev, "failed to get clk for PHY\n");
> +		return PTR_ERR(sata->phyclk);
> +	}
> +
> +	ret = clk_prepare_enable(sata->phyclk);
> +	if (ret < 0) {

ditto

> +		dev_err(dev, "failed to enable source clk\n");
> +		return ret;
> +	}
> +
> +	sata->phy = devm_phy_create(dev, &exynos_sata_phy_ops, NULL);
> +	if (IS_ERR(sata->phy)) {

ditto + clk_disable_unprepare(sata->phyclk)

> +		dev_err(dev, "failed to create PHY\n");
> +		return PTR_ERR(sata->phy);
> +	}
> +
> +	phy_provider = devm_of_phy_provider_register(dev,
> +					of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider))

ditto

> +		return PTR_ERR(phy_provider);
> +
> +	phy_set_drvdata(sata->phy, sata);
> +	return 0;
> +}
> +
> +static const struct of_device_id exynos_sata_phy_of_match[] = {
> +	{ .compatible = "samsung,exynos5250-sata-phy" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, exynos_sata_phy_of_match);
> +
> +static struct platform_driver exynos_sata_phy_driver = {
> +	.probe	= exynos_sata_phy_probe,
> +	.driver = {
> +		.of_match_table	= exynos_sata_phy_of_match,
> +		.name  = "samsung,sata-phy",
> +		.owner = THIS_MODULE,
> +	}
> +};
> +module_platform_driver(exynos_sata_phy_driver);
> +
> +MODULE_DESCRIPTION("Samsung SerDes PHY driver");
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("ks.giri <ks.giri@samsung.com>");
> +MODULE_AUTHOR("Yuvaraj C D <yuvaraj.cd@samsung.com>");
> diff --git a/drivers/phy/sata_phy_exynos5250.h b/drivers/phy/sata_phy_exynos5250.h
> new file mode 100644
> index 0000000..3e2089d
> --- /dev/null
> +++ b/drivers/phy/sata_phy_exynos5250.h
> @@ -0,0 +1,35 @@
> +/*
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * Author:
> + *	Yuvaraj Kumar C D<yuvaraj.cd@samsung.com>
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +#define EXYNOS5_SATA_RESET		0x4
> +#define EXYNOS5_SATA_MODE0		0x10
> +#define EXYNOS5_SATA_CTRL0		0x14
> +#define EXYNOS5_SATA_STAT0		0x18

This one seems to be unused and can be removed.

> +#define EXYNOS5_SATA_PHSATA_CTRLM	0xE0
> +#define EXYNOS5_SATA_PHSATA_CTRL0	0xE4

ditto

> +#define EXYNOS5_SATA_PHSATA_STATM	0xF0
> +#define EXYNOS5_SATA_PHSTAT0		0xF4

ditto

> +#define RESET_CMN_RST_N			(1 << 1)
> +#define LINK_RESET			0xF0000
> +#define CTRL0_P0_PHY_CALIBRATED_SEL	(1 << 9)
> +#define CTRL0_P0_PHY_CALIBRATED		(1 << 8)
> +#define PHCTRLM_REF_RATE		(1 << 1)
> +#define PHCTRLM_HIGH_SPEED		(1 << 0)
> +#define PHSTATM_PLL_LOCKED		(1 << 0)
> +#define SATA_PHY_CON_RESET		(LINK_RESET | 3F)

ditto (LINK_RESET can also be removed)

> +#define EXYNOS_SATA_PHY_EN		(1 << 0)
> +#define SATAPHY_CONTROL_OFFSET		0x0724
> +#define EXYNOS5_SATAPHY_PMU_ENABLE	(1 << 0)

All above defines can be moved into the SATA PHY driver as they are
not intended to be shared with other code.

To make the code easier to read you can also group the defines for
specific register below this register offset define, i.e.:

#define EXYNOS5_SATA_RESET		0x4
#define RESET_CMN_RST_N			(1 << 1)
#define LINK_RESET			0xF0000
#define EXYNOS5_SATA_MODE0		0x10
...

> +int sataphy_attach_i2c_client(struct i2c_client *sata_phy);
> +extern struct i2c_driver sataphy_i2c_driver;

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH V4 2/2] ARM: dts: Enable ahci sata and sata phy

[Bartlomiej Zolnierkiewicz]

[ added linux-ide ML to Cc: ]

On Monday, December 30, 2013 06:37:03 PM Yuvaraj Kumar C D wrote:
> This patch adds dt entry for ahci sata controller and its
> corresponding phy controller.phy node has been added w.r.t
> new generic phy framework.
> 
> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
> 
> Changes since V3:
> 	1.Moved the binding info to the /bindings/phy/
> 
> Changes since V2:
> 	1.Used syscon interface to PMU handling.
> 	2.Changed "sata-phy-i2c" to "exynos-sataphy-i2c".
> 
> Changes since V1:
> 	1.Minor changes to node name convention.
> 	2.Updated binding document.
> 
>  .../devicetree/bindings/ata/exynos-sata-phy.txt    |   14 -------
>  .../devicetree/bindings/ata/exynos-sata.txt        |   25 +++++++-----
>  .../devicetree/bindings/phy/samsung-phy.txt        |   40 ++++++++++++++++++++
>  arch/arm/boot/dts/exynos5250-arndale.dts           |   11 ++++++
>  arch/arm/boot/dts/exynos5250-smdk5250.dts          |    8 +---
>  arch/arm/boot/dts/exynos5250.dtsi                  |   16 ++++++--
>  6 files changed, 81 insertions(+), 33 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
> deleted file mode 100644
> index 37824fa..0000000
> --- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -* Samsung SATA PHY Controller
> -
> -SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
> -Each SATA PHY controller should have its own node.
> -
> -Required properties:
> -- compatible        : compatible list, contains "samsung,exynos5-sata-phy"
> -- reg               : <registers mapping>
> -
> -Example:
> -        sata@ffe07000 {
> -                compatible = "samsung,exynos5-sata-phy";
> -                reg = <0xffe07000 0x1000>;
> -        };
> diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
> index 0849f10..b2adb1f 100644
> --- a/Documentation/devicetree/bindings/ata/exynos-sata.txt
> +++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
> @@ -4,14 +4,21 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
>  Each SATA controller should have its own node.
>  
>  Required properties:
> -- compatible        : compatible list, contains "samsung,exynos5-sata"
> -- interrupts        : <interrupt mapping for SATA IRQ>
> -- reg               : <registers mapping>
> -- samsung,sata-freq : <frequency in MHz>
> +- compatible		: compatible list, contains "samsung,exynos5-sata"
> +- interrupts		: <interrupt mapping for SATA IRQ>
> +- reg			: <registers mapping>
> +- samsung,sata-freq	: <frequency in MHz>
> +- phys			: as mentioned in phy-bindings.txt
> +- phy-names		: as mentioned in phy-bindings.txt
>  
>  Example:
> -        sata@ffe08000 {
> -                compatible = "samsung,exynos5-sata";
> -                reg = <0xffe08000 0x1000>;
> -                interrupts = <115>;
> -        };
> +	sata@122f0000 {
> +		compatible = "snps,dwc-ahci";
> +		samsung,sata-freq = <66>;
> +		reg = <0x122f0000 0x1ff>;
> +		interrupts = <0 115 0>;
> +		clocks = <&clock 277>, <&clock 143>;
> +		clock-names = "sata", "sclk_sata";
> +		phys = <&sata_phy>;
> +		phy-names = "sata-phy";
> +	};
> diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
> index c0fccaa..876fe9b 100644
> --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
> @@ -20,3 +20,43 @@ Required properties:
>  - compatible : should be "samsung,exynos5250-dp-video-phy";
>  - reg : offset and length of the Display Port PHY register set;
>  - #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Samsung SATA PHY Controller
> +---------------------------
> +
> +SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
> +Each SATA PHY controller should have its own node.
> +
> +Required properties:
> +- compatible        : compatible list, contains "samsung,exynos5250-sata-phy"
> +- reg : offset and length of the SATA PHY register set;
> +- #phy-cells : from the generic phy bindings;
> +
> +Example:
> +	sata_phy: sata-phy@12170000 {
> +		compatible = "samsung,exynos5250-sata-phy";
> +		reg = <0x12170000 0x1ff>;
> +		clocks = <&clock 287>;
> +		clock-names = "sata_phyctrl";
> +		#phy-cells = <0>;

This example needs to be updated as the code below evolved to be just:

samsung,syscon-phandle = <&pmu_syscon>;

> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +		sataphy-pmu {
> +			reg = <0x10040724 0x4>;
> +		};

Otherwise the patch looks good.

> +	};
> +
> +Device-Tree bindings for sataphy i2c client driver
> +--------------------------------------------------
> +
> +Required properties:
> +compatible: Should be "samsung,exynos-sataphy-i2c"
> +- reg: I2C address of the sataphy i2c device.
> +
> +Example:
> +
> +	sata-phy@38 {
> +		compatible = "samsung,exynos-sataphy-i2c";
> +		reg = <0x38>;
> +	};
> diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
> index b42e658..25fe5a3 100644
> --- a/arch/arm/boot/dts/exynos5250-arndale.dts
> +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
> @@ -370,6 +370,17 @@
>  		};
>  	};
>  
> +	i2c@121D0000 {
> +		samsung,i2c-sda-delay = <100>;
> +		samsung,i2c-max-bus-freq = <40000>;
> +		samsung,i2c-slave-addr = <0x38>;
> +
> +		sata-phy@38 {
> +			compatible = "samsung,exynos-sataphy-i2c";
> +			reg = <0x38>;
> +		};
> +	};
> +
>  	mmc_0: mmc@12200000 {
>  		status = "okay";
>  		num-slots = <1>;
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 3e69837..9e449e6 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -96,16 +96,12 @@
>  		samsung,i2c-slave-addr = <0x38>;
>  		status = "okay";
>  
> -		sata-phy {
> -			compatible = "samsung,sata-phy";
> +		sata-phy@38 {
> +			compatible = "samsung,exynos-sataphy-i2c";
>  			reg = <0x38>;
>  		};
>  	};
>  
> -	sata@122F0000 {
> -		samsung,sata-freq = <66>;
> -	};
> -
>  	i2c@12C80000 {
>  		samsung,i2c-sda-delay = <100>;
>  		samsung,i2c-max-bus-freq = <66000>;
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index dbb4a47..626a7d1 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -46,6 +46,7 @@
>  		i2c6 = &i2c_6;
>  		i2c7 = &i2c_7;
>  		i2c8 = &i2c_8;
> +		i2c9 = &i2c_9;
>  		pinctrl0 = &pinctrl_0;
>  		pinctrl1 = &pinctrl_1;
>  		pinctrl2 = &pinctrl_2;
> @@ -231,16 +232,23 @@
>  	};
>  
>  	sata@122F0000 {
> -		compatible = "samsung,exynos5-sata-ahci";
> +		compatible = "snps,dwc-ahci";
> +		samsung,sata-freq = <66>;
>  		reg = <0x122F0000 0x1ff>;
>  		interrupts = <0 115 0>;
>  		clocks = <&clock 277>, <&clock 143>;
>  		clock-names = "sata", "sclk_sata";
> +		phys = <&sata_phy>;
> +		phy-names = "sata-phy";
>  	};
>  
> -	sata-phy@12170000 {
> -		compatible = "samsung,exynos5-sata-phy";
> +	sata_phy: sata-phy@12170000 {
> +		compatible = "samsung,exynos5250-sata-phy";
>  		reg = <0x12170000 0x1ff>;
> +		clocks = <&clock 287>;
> +		clock-names = "sata_phyctrl";
> +		#phy-cells = <0>;
> +		samsung,syscon-phandle = <&pmu_syscon>;
>  	};
>  
>  	i2c_0: i2c@12C60000 {
> @@ -358,7 +366,7 @@
>  		status = "disabled";
>  	};
>  
> -	i2c@121D0000 {
> +	i2c_9: i2c@121D0000 {
>                  compatible = "samsung,exynos5-sata-phy-i2c";
>                  reg = <0x121D0000 0x100>;
>                  #address-cells = <1>;

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

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Re: [PATCH V4 1/2] Phy: Exynos: Add Exynos5250 sata phy driver

[Yuvaraj Kumar]

On Tue, Dec 31, 2013 at 9:00 PM, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
>
> [ added linux-ide ML to Cc: ]
>
> Hi,
>
> Overall the code looks good, thank you for working on this.
Thanks for the review.
>
> I still have some review comments though..
Thats Good :)
>
> On Monday, December 30, 2013 06:37:02 PM Yuvaraj Kumar C D wrote:
>> This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
>> phy comprises of CMU and TRSV blocks which are of I2C register Map.
>> So this patch also adds a i2c client driver, which is used configure
>> the CMU and TRSV block of exynos5250 SATA PHY.
>>
>> This patch incorporates the generic phy framework to deal with sata
>> phy.
>
> Two minor nits here:
>
> - Some consistency in using of "SATA", "PHY" and "Exynos" would be
>   nice, i.e.:
>
>   s/sata/SATA/
>   s/phy/PHY/
>   s/exynos/Exynos/
Ok
>
> - Please add two spaces after each "." and before new sentence.
Ok
>
>> This patch depends on the below patches
>>       [1].drivers: phy: add generic PHY framework
>>               by Kishon Vijay Abraham I<kishon@ti.com>
>>       [2].ata: ahci_platform: Manage SATA PHY
>>               by Roger Quadros <rogerq@ti.com>
>>
>> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> Signed-off-by: Girish K S <ks.giri@samsung.com>
>> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
>> ---
>> Changes from V3:
>>       1.Moved devm_phy_create before to devm_phy_provider_register.
>>
>> Changes from V2:
>>       1.Removed of_match_table
>>       2.Moved to syscon interface for PMU handling.
>>
>> Changes from V1:
>>       1.Adapted to latest version of Generic PHY framework
>>       2.Removed exynos_sata_i2c_remove function.
>>
>>
>>  drivers/phy/Kconfig               |   11 ++
>>  drivers/phy/Makefile              |    1 +
>>  drivers/phy/exynos5250_phy_i2c.c  |   44 ++++++++
>>  drivers/phy/sata_phy_exynos5250.c |  220 +++++++++++++++++++++++++++++++++++++
>
> For consistency with other PHY drivers this file should be named
> diffirently (phy-exynos5250-sata.c).
>
>>  drivers/phy/sata_phy_exynos5250.h |   35 ++++++
>>  5 files changed, 311 insertions(+)
>>  create mode 100644 drivers/phy/exynos5250_phy_i2c.c
>>  create mode 100644 drivers/phy/sata_phy_exynos5250.c
>>  create mode 100644 drivers/phy/sata_phy_exynos5250.h
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index d0611b8..6ea124d 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -57,4 +57,15 @@ config PHY_EXYNOS_DP_VIDEO
>>       help
>>         Support for Display Port PHY found on Samsung EXYNOS SoCs.
>>
>> +config EXYNOS5250_SATA_PHY
>
> I think that for consistency with other config options it should be
> named PHY_EXYNOS5250_SATA instead.
Yup.I will change.
>
>> +     tristate "Exynos5250 Sata SerDes/PHY driver"
>> +     depends on SOC_EXYNOS5250
>> +     select GENERIC_PHY
>> +     select MFD_SYSCON if ARCH_EXYNOS5
>
> "if ARCH_EXYNOS5" check shouldn't be needed given SOC_EXYNOS5250
> dependency.
Ok
>
>> +     help
>> +       Enable this to support SATA SerDes/Phy found on Samsung's
>> +       Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
>> +       SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.It supports one SATA host
>> +       port to accept one SATA device.
>> +
>>  endmenu
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 4e4adc9..b73eb73 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)   += phy-exynos-mipi-video.o
>>  obj-$(CONFIG_PHY_MVEBU_SATA)         += phy-mvebu-sata.o
>>  obj-$(CONFIG_OMAP_USB2)                      += phy-omap-usb2.o
>>  obj-$(CONFIG_TWL4030_USB)            += phy-twl4030-usb.o
>> +obj-$(CONFIG_EXYNOS5250_SATA_PHY)    += sata_phy_exynos5250.o exynos5250_phy_i2c.o
>
> Will this compile/work without I2C support?
No.I missed this.It will not compile without I2C support.
How about  below change in drivers/phy/Kconfig ?
config EXYNOS5250_SATA_PHY
select I2C
select I2C_S3C2410
>
> CONFIG_EXYNOS5250_SATA_PHY doesn't require it currently.
I didnt get this. what it doesn't require?
>
>> diff --git a/drivers/phy/exynos5250_phy_i2c.c b/drivers/phy/exynos5250_phy_i2c.c
>> new file mode 100644
>> index 0000000..c0c1150
>> --- /dev/null
>> +++ b/drivers/phy/exynos5250_phy_i2c.c
>> @@ -0,0 +1,44 @@
>> +/*
>> + * Copyright (C) 2013 Samsung Electronics Co.Ltd
>> + * Author:
>> + *   Yuvaraj C D <yuvaraj.cd@samsung.com>
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + *
>> + */
>> +
>> +#include <linux/i2c.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>
> Please add a newline here.
Ok
>
>> +#include "sata_phy_exynos5250.h"
>> +
>> +static int exynos_sata_i2c_probe(struct i2c_client *client,
>> +             const struct i2c_device_id *i2c_id)
>> +{
>> +     int ret = 0;
>
> No need to initialize "ret", also please add a newline here.
Ok
>
>> +     ret = sataphy_attach_i2c_client(client);
>> +     if (ret < 0)
>> +             return ret;
>> +
>> +     dev_info(&client->adapter->dev,
>> +             "attached %s into sataphy i2c adapter successfully\n",
>> +             client->name);
>> +
>> +     return ret;
>> +}
>> +
>> +static const struct i2c_device_id sataphy_i2c_device_match[] = {
>> +     { "exynos-sataphy-i2c", 0 },
>> +};
>> +
>> +struct i2c_driver sataphy_i2c_driver = {
>
> Keeping it global together with sataphy_attach_i2c_client() is not very
> nice.  I've talked with our local device tree guru (a.k.a. Tomasz Figa)
> about this and it may be that this i2c driver is not even necessary.
Can you elaborate more on this?
>
> If you manage to extract i2c adapter and address data from the device
> tree (using proper of_* methods) they can be used instead of i2c client
> data in the SATA PHY driver.
I think the above is true, if the complete SATA PHY controller sits on
the i2c adapter.
But in Exynos5250 case,only the few configurations ( CMU and TRSV
blocks ) SATA PHY
are done through I2C(channel 9). Correct me if i am wrong.
>
>> +     .probe          = exynos_sata_i2c_probe,
>> +     .id_table       = sataphy_i2c_device_match,
>> +     .driver   = {
>> +             .name = "exynos-sataphy-i2c",
>> +             .owner = THIS_MODULE,
>> +             },
>> +};
>> diff --git a/drivers/phy/sata_phy_exynos5250.c b/drivers/phy/sata_phy_exynos5250.c
>> new file mode 100644
>> index 0000000..0765863
>> --- /dev/null
>> +++ b/drivers/phy/sata_phy_exynos5250.c
>> @@ -0,0 +1,220 @@
>> +/*
>> + * Samsung SATA SerDes(PHY) driver
>> + *
>> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>> + * Authors: Girish K S <ks.giri@samsung.com>
>> + *         Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/i2c.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/mfd/syscon.h>
>
> Please add a newline here.
Ok
>
>> +#include "sata_phy_exynos5250.h"
>> +
>> +static struct i2c_client *phy_i2c_client;
>> +
>> +struct exynos_sata_phy {
>> +     struct phy *phy;
>> +     struct clk *phyclk;
>> +     void __iomem *regs;
>> +     void __iomem *pmureg;
>> +};
>> +
>> +static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
>> +                             u32 status)
>> +{
>> +     unsigned long timeout = jiffies + usecs_to_jiffies(1000);
>
> ditto
Ok
>
>> +     while (time_before(jiffies, timeout)) {
>> +             if ((readl(base + reg) & checkbit) == status)
>> +                     return true;
>> +     }
>
> ditto
Ok
>
>> +     return false;
>> +}
>> +
>> +int sataphy_attach_i2c_client(struct i2c_client *sata_phy)
>
> sata_phy is not a best variable name here, maybe just use "client"
> instead?
Ok
>
>> +{
>> +     if (!sata_phy)
>> +             return -EPROBE_DEFER;
>> +     else
>> +             phy_i2c_client = sata_phy;
>> +
>> +     return 0;
>> +}
>> +
>> +static int exynos_sata_phy_power_on(struct phy *phy)
>> +{
>> +     struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>> +
>> +     if (sata_phy->pmureg)
>
> No need to check it, exynos_sata_phy_probe() fails early if pmureg
> cannot be find.
Ok
>
>> +             regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
>> +                     EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
>> +
>> +     return 0;
>> +}
>> +
>> +static int exynos_sata_phy_power_off(struct phy *phy)
>> +{
>> +     struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>> +
>> +     if (sata_phy->pmureg)
>
> ditto
Ok
>
>> +             regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
>> +                     EXYNOS5_SATAPHY_PMU_ENABLE, ~EXYNOS_SATA_PHY_EN);
>> +
>> +     return 0;
>> +}
>> +
>> +static int exynos_sata_phy_init(struct phy *phy)
>> +{
>> +     u32 val = 0;
>> +     int ret = 0;
>> +     u8 buf[] = { 0x3A, 0x0B };
>> +     struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>> +
>> +     if (sata_phy->pmureg)
>
> ditto
Ok
>
>> +             regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
>> +                     EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
>> +
>> +     writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> +     val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> +     val |= 0xFF;
>> +     writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> +     val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> +     val |= LINK_RESET;
>> +     writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> +     val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> +     val |= RESET_CMN_RST_N;
>> +     writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>
> Please add a newline here.
Ok
>
>> +     val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> +     val &= ~PHCTRLM_REF_RATE;
>> +     writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> +
>> +     /* High speed enable for Gen3 */
>> +     val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> +     val |= PHCTRLM_HIGH_SPEED;
>> +     writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> +
>> +     val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
>
> This doesn't look correct.  The "val" variable still contains value
> used previously for PHCTRLM register and now (after setting bits 8-9)
> it will be reused for CTRL0 register.  I believe that there is a
>
>         val = readl(sata_phy->regs + EXYNOS5_SATA_CTRL0);
>
> missing here.
Yes,I will change.
>
>> +     writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
>> +
>> +     writel(0x2, sata_phy->regs + EXYNOS5_SATA_MODE0);
>
> Please add a define instead of using a magic number.  Morever the code
> should read the content of MODE0 register first and then set bit1 (in
> the documentation that I have bits 2-31 are marked as Reserved, which
> means that they are not necessarily hard-wired to zero).
Ok.
>
> Also:
>
> This code sets PHY# speed mode to 6.0 Gb/s.  Does this setting need to
> be updated when 3.0 Gb/s or 1.5 Gb/s devices are used instead?  Do such
> devices work fine with the current code?
No,ahci driver will do that.If it could not able to detect the device
with 6.0Gb/s
it tries for the lower speed and detect the device.
>
> [ There is a patch adding set_speed method to the generic PHY framework:
>
>         http://permalink.gmane.org/gmane.linux.scsi/86660
>
>   but AHCI platform driver would still need to be updated to use it. ]
>
>> +     ret = i2c_master_send(phy_i2c_client, buf, sizeof(buf));
>> +     if (ret < 0)
>> +             return -ENXIO;
>> +
>> +     /* release cmu reset */
>> +     val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> +     val &= ~RESET_CMN_RST_N;
>> +     writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> +     val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> +     val |= RESET_CMN_RST_N;
>> +     writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> +     return (wait_for_reg_status(sata_phy->regs, EXYNOS5_SATA_PHSATA_STATM,
>> +             PHSTATM_PLL_LOCKED, 1)) ? 0 : -EINVAL;
>> +
>> +}
>> +
>> +static struct phy_ops exynos_sata_phy_ops = {
>> +     .init           = exynos_sata_phy_init,
>> +     .power_on       = exynos_sata_phy_power_on,
>> +     .power_off      = exynos_sata_phy_power_off,
>> +     .owner          = THIS_MODULE,
>> +};
>> +
>> +static int exynos_sata_phy_probe(struct platform_device *pdev)
>> +{
>> +     struct exynos_sata_phy *sata;
>
> Why not name it sata_phy like in other functions?
>
>> +     struct device *dev = &pdev->dev;
>> +     struct resource *res;
>> +     struct phy_provider *phy_provider;
>> +     int ret = 0;
>> +
>> +     sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
>> +     if (!sata)
>> +             return -ENOMEM;
>> +
>> +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +
>> +     sata->regs = devm_ioremap_resource(dev, res);
>> +     if (IS_ERR(sata->regs))
>> +             return PTR_ERR(sata->regs);
>> +
>> +     sata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
>> +                                     "samsung,syscon-phandle");
>> +     if (!sata->pmureg) {
>> +             dev_err(dev, "syscon regmap lookup failed.\n");
>> +             return PTR_ERR(sata->pmureg);
>> +     }
>> +     dev_set_drvdata(dev, sata);
>> +
>> +     if (i2c_add_driver(&sataphy_i2c_driver)) {
>> +             dev_err(dev, "failed to register sataphy i2c driver\n");
>> +             return -ENOENT;
>> +     }
>> +
>> +     sata->phyclk = devm_clk_get(dev, "sata_phyctrl");
>> +     if (IS_ERR(sata->phyclk)) {
>
> Don't we need to also unregister i2c driver on failure?
Yes needed.Will change.
>
>> +             dev_err(dev, "failed to get clk for PHY\n");
>> +             return PTR_ERR(sata->phyclk);
>> +     }
>> +
>> +     ret = clk_prepare_enable(sata->phyclk);
>> +     if (ret < 0) {
>
> ditto
Ok
>
>> +             dev_err(dev, "failed to enable source clk\n");
>> +             return ret;
>> +     }
>> +
>> +     sata->phy = devm_phy_create(dev, &exynos_sata_phy_ops, NULL);
>> +     if (IS_ERR(sata->phy)) {
>
> ditto + clk_disable_unprepare(sata->phyclk)
Ok
>
>> +             dev_err(dev, "failed to create PHY\n");
>> +             return PTR_ERR(sata->phy);
>> +     }
>> +
>> +     phy_provider = devm_of_phy_provider_register(dev,
>> +                                     of_phy_simple_xlate);
>> +     if (IS_ERR(phy_provider))
>
> ditto
Ok
>
>> +             return PTR_ERR(phy_provider);
>> +
>> +     phy_set_drvdata(sata->phy, sata);
>> +     return 0;
>> +}
>> +
>> +static const struct of_device_id exynos_sata_phy_of_match[] = {
>> +     { .compatible = "samsung,exynos5250-sata-phy" },
>> +     { },
>> +};
>> +MODULE_DEVICE_TABLE(of, exynos_sata_phy_of_match);
>> +
>> +static struct platform_driver exynos_sata_phy_driver = {
>> +     .probe  = exynos_sata_phy_probe,
>> +     .driver = {
>> +             .of_match_table = exynos_sata_phy_of_match,
>> +             .name  = "samsung,sata-phy",
>> +             .owner = THIS_MODULE,
>> +     }
>> +};
>> +module_platform_driver(exynos_sata_phy_driver);
>> +
>> +MODULE_DESCRIPTION("Samsung SerDes PHY driver");
>> +MODULE_LICENSE("GPL");
>> +MODULE_AUTHOR("ks.giri <ks.giri@samsung.com>");
>> +MODULE_AUTHOR("Yuvaraj C D <yuvaraj.cd@samsung.com>");
>> diff --git a/drivers/phy/sata_phy_exynos5250.h b/drivers/phy/sata_phy_exynos5250.h
>> new file mode 100644
>> index 0000000..3e2089d
>> --- /dev/null
>> +++ b/drivers/phy/sata_phy_exynos5250.h
>> @@ -0,0 +1,35 @@
>> +/*
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * Author:
>> + *   Yuvaraj Kumar C D<yuvaraj.cd@samsung.com>
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + */
>> +
>> +#define EXYNOS5_SATA_RESET           0x4
>> +#define EXYNOS5_SATA_MODE0           0x10
>> +#define EXYNOS5_SATA_CTRL0           0x14
>> +#define EXYNOS5_SATA_STAT0           0x18
>
> This one seems to be unused and can be removed.
Ok
>
>> +#define EXYNOS5_SATA_PHSATA_CTRLM    0xE0
>> +#define EXYNOS5_SATA_PHSATA_CTRL0    0xE4
>
> ditto
Ok
>
>> +#define EXYNOS5_SATA_PHSATA_STATM    0xF0
>> +#define EXYNOS5_SATA_PHSTAT0         0xF4
>
> ditto
Ok
>
>> +#define RESET_CMN_RST_N                      (1 << 1)
>> +#define LINK_RESET                   0xF0000
>> +#define CTRL0_P0_PHY_CALIBRATED_SEL  (1 << 9)
>> +#define CTRL0_P0_PHY_CALIBRATED              (1 << 8)
>> +#define PHCTRLM_REF_RATE             (1 << 1)
>> +#define PHCTRLM_HIGH_SPEED           (1 << 0)
>> +#define PHSTATM_PLL_LOCKED           (1 << 0)
>> +#define SATA_PHY_CON_RESET           (LINK_RESET | 3F)
>
> ditto (LINK_RESET can also be removed)
SATA_PHY_CON_RESET can be removed.But LINK_RESET required.
>
>> +#define EXYNOS_SATA_PHY_EN           (1 << 0)
>> +#define SATAPHY_CONTROL_OFFSET               0x0724
>> +#define EXYNOS5_SATAPHY_PMU_ENABLE   (1 << 0)
>
> All above defines can be moved into the SATA PHY driver as they are
> not intended to be shared with other code.
Ok
>
> To make the code easier to read you can also group the defines for
> specific register below this register offset define, i.e.:
>
> #define EXYNOS5_SATA_RESET              0x4
> #define RESET_CMN_RST_N                 (1 << 1)
> #define LINK_RESET                      0xF0000
> #define EXYNOS5_SATA_MODE0              0x10
Ok
> ...
>
>> +int sataphy_attach_i2c_client(struct i2c_client *sata_phy);
>> +extern struct i2c_driver sataphy_i2c_driver;
>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>

Re: [PATCH V4 1/2] Phy: Exynos: Add Exynos5250 sata phy driver

[Yuvaraj Kumar]

On Tue, Dec 31, 2013 at 4:18 PM, Kishon Vijay Abraham I <kishon@ti.com> wrote:
> Hi Yuvaraj,
>
>
> On Monday 30 December 2013 06:37 PM, Yuvaraj Kumar C D wrote:
>>
>> This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
>> phy comprises of CMU and TRSV blocks which are of I2C register Map.
>> So this patch also adds a i2c client driver, which is used configure
>> the CMU and TRSV block of exynos5250 SATA PHY.
>>
>> This patch incorporates the generic phy framework to deal with sata
>> phy.
>>
>> This patch depends on the below patches
>>         [1].drivers: phy: add generic PHY framework
>>                 by Kishon Vijay Abraham I<kishon@ti.com>
>>         [2].ata: ahci_platform: Manage SATA PHY
>>                 by Roger Quadros <rogerq@ti.com>
>>
>> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> Signed-off-by: Girish K S <ks.giri@samsung.com>
>> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
>> ---
>> Changes from V3:
>>         1.Moved devm_phy_create before to devm_phy_provider_register.
>>
>> Changes from V2:
>>         1.Removed of_match_table
>>         2.Moved to syscon interface for PMU handling.
>>
>> Changes from V1:
>>         1.Adapted to latest version of Generic PHY framework
>>         2.Removed exynos_sata_i2c_remove function.
>>
>>
>>   drivers/phy/Kconfig               |   11 ++
>>   drivers/phy/Makefile              |    1 +
>>   drivers/phy/exynos5250_phy_i2c.c  |   44 ++++++++
>>   drivers/phy/sata_phy_exynos5250.c |  220
>> +++++++++++++++++++++++++++++++++++++
>>   drivers/phy/sata_phy_exynos5250.h |   35 ++++++
>>   5 files changed, 311 insertions(+)
>>   create mode 100644 drivers/phy/exynos5250_phy_i2c.c
>>   create mode 100644 drivers/phy/sata_phy_exynos5250.c
>>   create mode 100644 drivers/phy/sata_phy_exynos5250.h
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index d0611b8..6ea124d 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -57,4 +57,15 @@ config PHY_EXYNOS_DP_VIDEO
>>         help
>>           Support for Display Port PHY found on Samsung EXYNOS SoCs.
>>
>> +config EXYNOS5250_SATA_PHY
>> +       tristate "Exynos5250 Sata SerDes/PHY driver"
>> +       depends on SOC_EXYNOS5250
>> +       select GENERIC_PHY
>> +       select MFD_SYSCON if ARCH_EXYNOS5
>> +       help
>> +         Enable this to support SATA SerDes/Phy found on Samsung's
>> +         Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
>> +         SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.It supports one SATA host
>> +         port to accept one SATA device.
>> +
>>   endmenu
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 4e4adc9..b73eb73 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)     +=
>> phy-exynos-mipi-video.o
>>   obj-$(CONFIG_PHY_MVEBU_SATA)          += phy-mvebu-sata.o
>>   obj-$(CONFIG_OMAP_USB2)                       += phy-omap-usb2.o
>>   obj-$(CONFIG_TWL4030_USB)             += phy-twl4030-usb.o
>> +obj-$(CONFIG_EXYNOS5250_SATA_PHY)      += sata_phy_exynos5250.o
>> exynos5250_phy_i2c.o
>> diff --git a/drivers/phy/exynos5250_phy_i2c.c
>> b/drivers/phy/exynos5250_phy_i2c.c
>> new file mode 100644
>> index 0000000..c0c1150
>> --- /dev/null
>> +++ b/drivers/phy/exynos5250_phy_i2c.c
>> @@ -0,0 +1,44 @@
>> +/*
>> + * Copyright (C) 2013 Samsung Electronics Co.Ltd
>> + * Author:
>> + *     Yuvaraj C D <yuvaraj.cd@samsung.com>
>> + *
>> + * This program is free software; you can redistribute  it and/or modify
>> it
>> + * under  the terms of  the GNU General  Public License as published by
>> the
>> + * Free Software Foundation;  either version 2 of the  License, or (at
>> your
>> + * option) any later version.
>> + *
>> + */
>> +
>> +#include <linux/i2c.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include "sata_phy_exynos5250.h"
>> +
>> +static int exynos_sata_i2c_probe(struct i2c_client *client,
>> +               const struct i2c_device_id *i2c_id)
>> +{
>> +       int ret = 0;
>> +       ret = sataphy_attach_i2c_client(client);
>> +       if (ret < 0)
>> +               return ret;
>> +
>> +       dev_info(&client->adapter->dev,
>> +               "attached %s into sataphy i2c adapter successfully\n",
>> +               client->name);
>> +
>> +       return ret;
>> +}
>> +
>> +static const struct i2c_device_id sataphy_i2c_device_match[] = {
>> +       { "exynos-sataphy-i2c", 0 },
>> +};
>> +
>> +struct i2c_driver sataphy_i2c_driver = {
>> +       .probe          = exynos_sata_i2c_probe,
>> +       .id_table       = sataphy_i2c_device_match,
>> +       .driver   = {
>> +               .name = "exynos-sataphy-i2c",
>> +               .owner = THIS_MODULE,
>> +               },
>> +};
>> diff --git a/drivers/phy/sata_phy_exynos5250.c
>> b/drivers/phy/sata_phy_exynos5250.c
>> new file mode 100644
>> index 0000000..0765863
>> --- /dev/null
>> +++ b/drivers/phy/sata_phy_exynos5250.c
>> @@ -0,0 +1,220 @@
>> +/*
>> + * Samsung SATA SerDes(PHY) driver
>> + *
>> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>> + * Authors: Girish K S <ks.giri@samsung.com>
>> + *         Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/i2c.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/mfd/syscon.h>
>> +#include "sata_phy_exynos5250.h"
>> +
>> +static struct i2c_client *phy_i2c_client;
>> +
>> +struct exynos_sata_phy {
>> +       struct phy *phy;
>> +       struct clk *phyclk;
>> +       void __iomem *regs;
>> +       void __iomem *pmureg;
>> +};
>> +
>> +static bool wait_for_reg_status(void __iomem *base, u32 reg, u32
>> checkbit,
>> +                               u32 status)
>> +{
>> +       unsigned long timeout = jiffies + usecs_to_jiffies(1000);
>> +       while (time_before(jiffies, timeout)) {
>> +               if ((readl(base + reg) & checkbit) == status)
>> +                       return true;
>> +       }
>> +       return false;
>> +}
>> +
>> +int sataphy_attach_i2c_client(struct i2c_client *sata_phy)
>> +{
>> +       if (!sata_phy)
>> +               return -EPROBE_DEFER;
>> +       else
>> +               phy_i2c_client = sata_phy;
>> +
>> +       return 0;
>> +}
>> +
>> +static int exynos_sata_phy_power_on(struct phy *phy)
>> +{
>> +       struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>> +
>> +       if (sata_phy->pmureg)
>> +               regmap_update_bits(sata_phy->pmureg,
>> SATAPHY_CONTROL_OFFSET,
>> +                       EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
>> +
>> +       return 0;
>> +}
>> +
>> +static int exynos_sata_phy_power_off(struct phy *phy)
>> +{
>> +       struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>> +
>> +       if (sata_phy->pmureg)
>> +               regmap_update_bits(sata_phy->pmureg,
>> SATAPHY_CONTROL_OFFSET,
>> +                       EXYNOS5_SATAPHY_PMU_ENABLE, ~EXYNOS_SATA_PHY_EN);
>> +
>> +       return 0;
>> +}
>> +
>> +static int exynos_sata_phy_init(struct phy *phy)
>> +{
>> +       u32 val = 0;
>> +       int ret = 0;
>> +       u8 buf[] = { 0x3A, 0x0B };
>> +       struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>> +
>> +       if (sata_phy->pmureg)
>> +               regmap_update_bits(sata_phy->pmureg,
>> SATAPHY_CONTROL_OFFSET,
>> +                       EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
>> +
>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> +       val |= 0xFF;
>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> +       val |= LINK_RESET;
>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> +       val |= RESET_CMN_RST_N;
>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> +       val &= ~PHCTRLM_REF_RATE;
>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> +
>> +       /* High speed enable for Gen3 */
>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> +       val |= PHCTRLM_HIGH_SPEED;
>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> +
>> +       val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
>> +
>> +       writel(0x2, sata_phy->regs + EXYNOS5_SATA_MODE0);
>> +
>> +       ret = i2c_master_send(phy_i2c_client, buf, sizeof(buf));
>> +       if (ret < 0)
>> +               return -ENXIO;
>> +
>> +       /* release cmu reset */
>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> +       val &= ~RESET_CMN_RST_N;
>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> +       val |= RESET_CMN_RST_N;
>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> +       return (wait_for_reg_status(sata_phy->regs,
>> EXYNOS5_SATA_PHSATA_STATM,
>> +               PHSTATM_PLL_LOCKED, 1)) ? 0 : -EINVAL;
>> +
>> +}
>> +
>> +static struct phy_ops exynos_sata_phy_ops = {
>> +       .init           = exynos_sata_phy_init,
>> +       .power_on       = exynos_sata_phy_power_on,
>> +       .power_off      = exynos_sata_phy_power_off,
>> +       .owner          = THIS_MODULE,
>> +};
>> +
>> +static int exynos_sata_phy_probe(struct platform_device *pdev)
>> +{
>> +       struct exynos_sata_phy *sata;
>> +       struct device *dev = &pdev->dev;
>> +       struct resource *res;
>> +       struct phy_provider *phy_provider;
>> +       int ret = 0;
>> +
>> +       sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
>> +       if (!sata)
>> +               return -ENOMEM;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +
>> +       sata->regs = devm_ioremap_resource(dev, res);
>> +       if (IS_ERR(sata->regs))
>> +               return PTR_ERR(sata->regs);
>> +
>> +       sata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
>> +                                       "samsung,syscon-phandle");
>> +       if (!sata->pmureg) {
>> +               dev_err(dev, "syscon regmap lookup failed.\n");
>> +               return PTR_ERR(sata->pmureg);
>> +       }
>> +       dev_set_drvdata(dev, sata);
>> +
>> +       if (i2c_add_driver(&sataphy_i2c_driver)) {
>> +               dev_err(dev, "failed to register sataphy i2c driver\n");
>> +               return -ENOENT;
>> +       }
>> +
>> +       sata->phyclk = devm_clk_get(dev, "sata_phyctrl");
>> +       if (IS_ERR(sata->phyclk)) {
>> +               dev_err(dev, "failed to get clk for PHY\n");
>> +               return PTR_ERR(sata->phyclk);
>> +       }
>> +
>> +       ret = clk_prepare_enable(sata->phyclk);
>> +       if (ret < 0) {
>> +               dev_err(dev, "failed to enable source clk\n");
>> +               return ret;
>> +       }
>> +
>> +       sata->phy = devm_phy_create(dev, &exynos_sata_phy_ops, NULL);
>> +       if (IS_ERR(sata->phy)) {
>> +               dev_err(dev, "failed to create PHY\n");
>> +               return PTR_ERR(sata->phy);
>> +       }
>> +
>> +       phy_provider = devm_of_phy_provider_register(dev,
>> +                                       of_phy_simple_xlate);
>> +       if (IS_ERR(phy_provider))
>> +               return PTR_ERR(phy_provider);
>> +
>> +       phy_set_drvdata(sata->phy, sata);
>
>
> huh.. phy_provider_register should be after phy_set_drvdata.
Sorry, I misunderstood.I will address this with the Bartlomiej
Zolnierkiewicz comments in the next version.
>
> Cheers
> Kishon

Re: [PATCH V4 1/2] Phy: Exynos: Add Exynos5250 sata phy driver

[Kishon Vijay Abraham I]

On Thursday 02 January 2014 07:13 PM, Yuvaraj Kumar wrote:
> On Tue, Dec 31, 2013 at 4:18 PM, Kishon Vijay Abraham I <kishon@ti.com> wrote:
>> Hi Yuvaraj,
>>
>>
>> On Monday 30 December 2013 06:37 PM, Yuvaraj Kumar C D wrote:
>>>
>>> This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
>>> phy comprises of CMU and TRSV blocks which are of I2C register Map.
>>> So this patch also adds a i2c client driver, which is used configure
>>> the CMU and TRSV block of exynos5250 SATA PHY.
>>>
>>> This patch incorporates the generic phy framework to deal with sata
>>> phy.
>>>
>>> This patch depends on the below patches
>>>         [1].drivers: phy: add generic PHY framework
>>>                 by Kishon Vijay Abraham I<kishon@ti.com>
>>>         [2].ata: ahci_platform: Manage SATA PHY
>>>                 by Roger Quadros <rogerq@ti.com>
>>>
>>> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>>> Signed-off-by: Girish K S <ks.giri@samsung.com>
>>> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
>>> ---
>>> Changes from V3:
>>>         1.Moved devm_phy_create before to devm_phy_provider_register.
>>>
>>> Changes from V2:
>>>         1.Removed of_match_table
>>>         2.Moved to syscon interface for PMU handling.
>>>
>>> Changes from V1:
>>>         1.Adapted to latest version of Generic PHY framework
>>>         2.Removed exynos_sata_i2c_remove function.
>>>
>>>
>>>   drivers/phy/Kconfig               |   11 ++
>>>   drivers/phy/Makefile              |    1 +
>>>   drivers/phy/exynos5250_phy_i2c.c  |   44 ++++++++
>>>   drivers/phy/sata_phy_exynos5250.c |  220
>>> +++++++++++++++++++++++++++++++++++++
>>>   drivers/phy/sata_phy_exynos5250.h |   35 ++++++
>>>   5 files changed, 311 insertions(+)
>>>   create mode 100644 drivers/phy/exynos5250_phy_i2c.c
>>>   create mode 100644 drivers/phy/sata_phy_exynos5250.c
>>>   create mode 100644 drivers/phy/sata_phy_exynos5250.h
>>>
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index d0611b8..6ea124d 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -57,4 +57,15 @@ config PHY_EXYNOS_DP_VIDEO
>>>         help
>>>           Support for Display Port PHY found on Samsung EXYNOS SoCs.
>>>
>>> +config EXYNOS5250_SATA_PHY
>>> +       tristate "Exynos5250 Sata SerDes/PHY driver"
>>> +       depends on SOC_EXYNOS5250
>>> +       select GENERIC_PHY
>>> +       select MFD_SYSCON if ARCH_EXYNOS5
>>> +       help
>>> +         Enable this to support SATA SerDes/Phy found on Samsung's
>>> +         Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
>>> +         SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.It supports one SATA host
>>> +         port to accept one SATA device.
>>> +
>>>   endmenu
>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>>> index 4e4adc9..b73eb73 100644
>>> --- a/drivers/phy/Makefile
>>> +++ b/drivers/phy/Makefile
>>> @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)     +=
>>> phy-exynos-mipi-video.o
>>>   obj-$(CONFIG_PHY_MVEBU_SATA)          += phy-mvebu-sata.o
>>>   obj-$(CONFIG_OMAP_USB2)                       += phy-omap-usb2.o
>>>   obj-$(CONFIG_TWL4030_USB)             += phy-twl4030-usb.o
>>> +obj-$(CONFIG_EXYNOS5250_SATA_PHY)      += sata_phy_exynos5250.o
>>> exynos5250_phy_i2c.o
>>> diff --git a/drivers/phy/exynos5250_phy_i2c.c
>>> b/drivers/phy/exynos5250_phy_i2c.c
>>> new file mode 100644
>>> index 0000000..c0c1150
>>> --- /dev/null
>>> +++ b/drivers/phy/exynos5250_phy_i2c.c
>>> @@ -0,0 +1,44 @@
>>> +/*
>>> + * Copyright (C) 2013 Samsung Electronics Co.Ltd
>>> + * Author:
>>> + *     Yuvaraj C D <yuvaraj.cd@samsung.com>
>>> + *
>>> + * This program is free software; you can redistribute  it and/or modify
>>> it
>>> + * under  the terms of  the GNU General  Public License as published by
>>> the
>>> + * Free Software Foundation;  either version 2 of the  License, or (at
>>> your
>>> + * option) any later version.
>>> + *
>>> + */
>>> +
>>> +#include <linux/i2c.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/module.h>
>>> +#include "sata_phy_exynos5250.h"
>>> +
>>> +static int exynos_sata_i2c_probe(struct i2c_client *client,
>>> +               const struct i2c_device_id *i2c_id)
>>> +{
>>> +       int ret = 0;
>>> +       ret = sataphy_attach_i2c_client(client);
>>> +       if (ret < 0)
>>> +               return ret;
>>> +
>>> +       dev_info(&client->adapter->dev,
>>> +               "attached %s into sataphy i2c adapter successfully\n",
>>> +               client->name);
>>> +
>>> +       return ret;
>>> +}
>>> +
>>> +static const struct i2c_device_id sataphy_i2c_device_match[] = {
>>> +       { "exynos-sataphy-i2c", 0 },
>>> +};
>>> +
>>> +struct i2c_driver sataphy_i2c_driver = {
>>> +       .probe          = exynos_sata_i2c_probe,
>>> +       .id_table       = sataphy_i2c_device_match,
>>> +       .driver   = {
>>> +               .name = "exynos-sataphy-i2c",
>>> +               .owner = THIS_MODULE,
>>> +               },
>>> +};
>>> diff --git a/drivers/phy/sata_phy_exynos5250.c
>>> b/drivers/phy/sata_phy_exynos5250.c
>>> new file mode 100644
>>> index 0000000..0765863
>>> --- /dev/null
>>> +++ b/drivers/phy/sata_phy_exynos5250.c
>>> @@ -0,0 +1,220 @@
>>> +/*
>>> + * Samsung SATA SerDes(PHY) driver
>>> + *
>>> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>>> + * Authors: Girish K S <ks.giri@samsung.com>
>>> + *         Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/io.h>
>>> +#include <linux/i2c.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/phy/phy.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/spinlock.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include "sata_phy_exynos5250.h"
>>> +
>>> +static struct i2c_client *phy_i2c_client;
>>> +
>>> +struct exynos_sata_phy {
>>> +       struct phy *phy;
>>> +       struct clk *phyclk;
>>> +       void __iomem *regs;
>>> +       void __iomem *pmureg;
>>> +};
>>> +
>>> +static bool wait_for_reg_status(void __iomem *base, u32 reg, u32
>>> checkbit,
>>> +                               u32 status)
>>> +{
>>> +       unsigned long timeout = jiffies + usecs_to_jiffies(1000);
>>> +       while (time_before(jiffies, timeout)) {
>>> +               if ((readl(base + reg) & checkbit) == status)
>>> +                       return true;
>>> +       }
>>> +       return false;
>>> +}
>>> +
>>> +int sataphy_attach_i2c_client(struct i2c_client *sata_phy)
>>> +{
>>> +       if (!sata_phy)
>>> +               return -EPROBE_DEFER;
>>> +       else
>>> +               phy_i2c_client = sata_phy;
>>> +
>>> +       return 0;
>>> +}
>>> +
>>> +static int exynos_sata_phy_power_on(struct phy *phy)
>>> +{
>>> +       struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>>> +
>>> +       if (sata_phy->pmureg)
>>> +               regmap_update_bits(sata_phy->pmureg,
>>> SATAPHY_CONTROL_OFFSET,
>>> +                       EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
>>> +
>>> +       return 0;
>>> +}
>>> +
>>> +static int exynos_sata_phy_power_off(struct phy *phy)
>>> +{
>>> +       struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>>> +
>>> +       if (sata_phy->pmureg)
>>> +               regmap_update_bits(sata_phy->pmureg,
>>> SATAPHY_CONTROL_OFFSET,
>>> +                       EXYNOS5_SATAPHY_PMU_ENABLE, ~EXYNOS_SATA_PHY_EN);
>>> +
>>> +       return 0;
>>> +}
>>> +
>>> +static int exynos_sata_phy_init(struct phy *phy)
>>> +{
>>> +       u32 val = 0;
>>> +       int ret = 0;
>>> +       u8 buf[] = { 0x3A, 0x0B };
>>> +       struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>>> +
>>> +       if (sata_phy->pmureg)
>>> +               regmap_update_bits(sata_phy->pmureg,
>>> SATAPHY_CONTROL_OFFSET,
>>> +                       EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
>>> +
>>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +
>>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +       val |= 0xFF;
>>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +
>>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +       val |= LINK_RESET;
>>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +
>>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +       val |= RESET_CMN_RST_N;
>>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>>> +       val &= ~PHCTRLM_REF_RATE;
>>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>>> +
>>> +       /* High speed enable for Gen3 */
>>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>>> +       val |= PHCTRLM_HIGH_SPEED;
>>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>>> +
>>> +       val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
>>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
>>> +
>>> +       writel(0x2, sata_phy->regs + EXYNOS5_SATA_MODE0);
>>> +
>>> +       ret = i2c_master_send(phy_i2c_client, buf, sizeof(buf));
>>> +       if (ret < 0)
>>> +               return -ENXIO;
>>> +
>>> +       /* release cmu reset */
>>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +       val &= ~RESET_CMN_RST_N;
>>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +
>>> +       val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +       val |= RESET_CMN_RST_N;
>>> +       writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>>> +
>>> +       return (wait_for_reg_status(sata_phy->regs,
>>> EXYNOS5_SATA_PHSATA_STATM,
>>> +               PHSTATM_PLL_LOCKED, 1)) ? 0 : -EINVAL;
>>> +
>>> +}
>>> +
>>> +static struct phy_ops exynos_sata_phy_ops = {
>>> +       .init           = exynos_sata_phy_init,
>>> +       .power_on       = exynos_sata_phy_power_on,
>>> +       .power_off      = exynos_sata_phy_power_off,
>>> +       .owner          = THIS_MODULE,
>>> +};
>>> +
>>> +static int exynos_sata_phy_probe(struct platform_device *pdev)
>>> +{
>>> +       struct exynos_sata_phy *sata;
>>> +       struct device *dev = &pdev->dev;
>>> +       struct resource *res;
>>> +       struct phy_provider *phy_provider;
>>> +       int ret = 0;
>>> +
>>> +       sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
>>> +       if (!sata)
>>> +               return -ENOMEM;
>>> +
>>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +
>>> +       sata->regs = devm_ioremap_resource(dev, res);
>>> +       if (IS_ERR(sata->regs))
>>> +               return PTR_ERR(sata->regs);
>>> +
>>> +       sata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
>>> +                                       "samsung,syscon-phandle");
>>> +       if (!sata->pmureg) {
>>> +               dev_err(dev, "syscon regmap lookup failed.\n");
>>> +               return PTR_ERR(sata->pmureg);
>>> +       }
>>> +       dev_set_drvdata(dev, sata);
>>> +
>>> +       if (i2c_add_driver(&sataphy_i2c_driver)) {
>>> +               dev_err(dev, "failed to register sataphy i2c driver\n");
>>> +               return -ENOENT;
>>> +       }
>>> +
>>> +       sata->phyclk = devm_clk_get(dev, "sata_phyctrl");
>>> +       if (IS_ERR(sata->phyclk)) {
>>> +               dev_err(dev, "failed to get clk for PHY\n");
>>> +               return PTR_ERR(sata->phyclk);
>>> +       }
>>> +
>>> +       ret = clk_prepare_enable(sata->phyclk);
>>> +       if (ret < 0) {
>>> +               dev_err(dev, "failed to enable source clk\n");
>>> +               return ret;
>>> +       }
>>> +
>>> +       sata->phy = devm_phy_create(dev, &exynos_sata_phy_ops, NULL);
>>> +       if (IS_ERR(sata->phy)) {
>>> +               dev_err(dev, "failed to create PHY\n");
>>> +               return PTR_ERR(sata->phy);
>>> +       }
>>> +
>>> +       phy_provider = devm_of_phy_provider_register(dev,
>>> +                                       of_phy_simple_xlate);
>>> +       if (IS_ERR(phy_provider))
>>> +               return PTR_ERR(phy_provider);
>>> +
>>> +       phy_set_drvdata(sata->phy, sata);
>>
>>
>> huh.. phy_provider_register should be after phy_set_drvdata.
> Sorry, I misunderstood.I will address this with the Bartlomiej
> Zolnierkiewicz comments in the next version.

cool.. thanks.

-Kishon
>>
>> Cheers
>> Kishon

Re: [PATCH V4 1/2] Phy: Exynos: Add Exynos5250 sata phy driver

[Bartlomiej Zolnierkiewicz]

Hi,

On Thursday, January 02, 2014 07:03:23 PM Yuvaraj Kumar wrote:
> On Tue, Dec 31, 2013 at 9:00 PM, Bartlomiej Zolnierkiewicz
> <b.zolnierkie@samsung.com> wrote:

> >> @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)   += phy-exynos-mipi-video.o
> >>  obj-$(CONFIG_PHY_MVEBU_SATA)         += phy-mvebu-sata.o
> >>  obj-$(CONFIG_OMAP_USB2)                      += phy-omap-usb2.o
> >>  obj-$(CONFIG_TWL4030_USB)            += phy-twl4030-usb.o
> >> +obj-$(CONFIG_EXYNOS5250_SATA_PHY)    += sata_phy_exynos5250.o exynos5250_phy_i2c.o
> >
> > Will this compile/work without I2C support?
> No.I missed this.It will not compile without I2C support.
> How about  below change in drivers/phy/Kconfig ?
> config EXYNOS5250_SATA_PHY
> select I2C
> select I2C_S3C2410

Fine with me.

> > CONFIG_EXYNOS5250_SATA_PHY doesn't require it currently.
> I didnt get this. what it doesn't require?

It doesn't require I2C.  If you add above I2C selects it will be OK.

> >> +struct i2c_driver sataphy_i2c_driver = {
> >
> > Keeping it global together with sataphy_attach_i2c_client() is not very
> > nice.  I've talked with our local device tree guru (a.k.a. Tomasz Figa)
> > about this and it may be that this i2c driver is not even necessary.
> Can you elaborate more on this?

The usage of the global i2c driver is not a proper solution.

i2c driver should register itself in the driver init function
(which is not present currently) instead of being registered by
the SATA PHY driver.

The SATA PHY driver should find i2c client device using DT.

sataphy_attach_i2c_client() should then be removed.

> > If you manage to extract i2c adapter and address data from the device
> > tree (using proper of_* methods) they can be used instead of i2c client
> > data in the SATA PHY driver.
> I think the above is true, if the complete SATA PHY controller sits on
> the i2c adapter.
> But in Exynos5250 case,only the few configurations ( CMU and TRSV
> blocks ) SATA PHY
> are done through I2C(channel 9). Correct me if i am wrong.

Well, it shouldn't matter if all or only some of the configuration of
the SATA PHY controller is done through i2c.

Anyway, how about another idea -> adding a new phandle of i2c client
device to SATA PHY DT entry and using DT in the SATA PHY driver to
find i2c client device?

i.e. "samsung,exynos-sataphy-i2c-phandle" property in SATA PHY
controller DT entry can point at existing "sata-phy@38" sataphy i2c
client DT entry (by adding new label to it, i.e. "sata_phy_i2c").

Such new phandle can be used first to find the DT device node of i2c
device (by using of_parse_phandle(), if it returns NULL the error
should be returned) and then later to find proper i2c client device
(by using of_find_i2c_device_by_node(), if it returns NULL deferred
probing should be requested by returning -EPROBE_DEFER).

i2c@121D0000 {
	...
	sata_phy_i2c: sata-phy@38 {
		...
	};
	...
};

sata_phy: sata-phy@12170000 {
	...
	samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
	...
};

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH V4 1/2] Phy: Exynos: Add Exynos5250 sata phy driver

[Yuvaraj Kumar]

On Tue, Jan 7, 2014 at 7:52 PM, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
>
> Hi,
>
> On Thursday, January 02, 2014 07:03:23 PM Yuvaraj Kumar wrote:
>> On Tue, Dec 31, 2013 at 9:00 PM, Bartlomiej Zolnierkiewicz
>> <b.zolnierkie@samsung.com> wrote:
>
>> >> @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)   += phy-exynos-mipi-video.o
>> >>  obj-$(CONFIG_PHY_MVEBU_SATA)         += phy-mvebu-sata.o
>> >>  obj-$(CONFIG_OMAP_USB2)                      += phy-omap-usb2.o
>> >>  obj-$(CONFIG_TWL4030_USB)            += phy-twl4030-usb.o
>> >> +obj-$(CONFIG_EXYNOS5250_SATA_PHY)    += sata_phy_exynos5250.o exynos5250_phy_i2c.o
>> >
>> > Will this compile/work without I2C support?
>> No.I missed this.It will not compile without I2C support.
>> How about  below change in drivers/phy/Kconfig ?
>> config EXYNOS5250_SATA_PHY
>> select I2C
>> select I2C_S3C2410
>
> Fine with me.
>
>> > CONFIG_EXYNOS5250_SATA_PHY doesn't require it currently.
>> I didnt get this. what it doesn't require?
>
> It doesn't require I2C.  If you add above I2C selects it will be OK.
>
>> >> +struct i2c_driver sataphy_i2c_driver = {
>> >
>> > Keeping it global together with sataphy_attach_i2c_client() is not very
>> > nice.  I've talked with our local device tree guru (a.k.a. Tomasz Figa)
>> > about this and it may be that this i2c driver is not even necessary.
>> Can you elaborate more on this?
>
> The usage of the global i2c driver is not a proper solution.
>
> i2c driver should register itself in the driver init function
do you mean i2c-s3c2410.c driver?
> (which is not present currently) instead of being registered by
> the SATA PHY driver.
>
> The SATA PHY driver should find i2c client device using DT.
>
> sataphy_attach_i2c_client() should then be removed.
>
>> > If you manage to extract i2c adapter and address data from the device
>> > tree (using proper of_* methods) they can be used instead of i2c client
>> > data in the SATA PHY driver.
>> I think the above is true, if the complete SATA PHY controller sits on
>> the i2c adapter.
>> But in Exynos5250 case,only the few configurations ( CMU and TRSV
>> blocks ) SATA PHY
>> are done through I2C(channel 9). Correct me if i am wrong.
>
> Well, it shouldn't matter if all or only some of the configuration of
> the SATA PHY controller is done through i2c.
>
> Anyway, how about another idea -> adding a new phandle of i2c client
> device to SATA PHY DT entry and using DT in the SATA PHY driver to
> find i2c client device?
>
> i.e. "samsung,exynos-sataphy-i2c-phandle" property in SATA PHY
> controller DT entry can point at existing "sata-phy@38" sataphy i2c
> client DT entry (by adding new label to it, i.e. "sata_phy_i2c").
>
> Such new phandle can be used first to find the DT device node of i2c
> device (by using of_parse_phandle(), if it returns NULL the error
> should be returned) and then later to find proper i2c client device
> (by using of_find_i2c_device_by_node(), if it returns NULL deferred
> probing should be requested by returning -EPROBE_DEFER).
I can get the i2c_client structure,but how the client driver binding
happens to registered device?
Currently with this approach i2c client device is being registered but
cleint driver could not able to bind with the device.
[    0.082680] i2c i2c-9: adapter [s3c2410-i2c] registered
[    0.082691] i2c i2c-9: of_i2c: walking child nodes
[    0.082696] i2c i2c-9: of_i2c: register /i2c@121D0000/sata-phy@38
[    0.082794] i2c 9-0038: uevent
[    0.082845] i2c i2c-9: client [exynos-sataphy-i2c] registered with
bus id 9-0038
[    0.082851] s3c-i2c 121d0000.i2c: i2c-9: S3C I2C adapter
>
> i2c@121D0000 {
>         ...
>         sata_phy_i2c: sata-phy@38 {
>                 ...
>         };
>         ...
> };
>
> sata_phy: sata-phy@12170000 {
>         ...
>         samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
>         ...
> };
>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>

Re: [PATCH V4 1/2] Phy: Exynos: Add Exynos5250 sata phy driver

[Bartlomiej Zolnierkiewicz]

On Wednesday, January 08, 2014 06:39:52 PM Yuvaraj Kumar wrote:
> On Tue, Jan 7, 2014 at 7:52 PM, Bartlomiej Zolnierkiewicz
> <b.zolnierkie@samsung.com> wrote:
> >
> > Hi,
> >
> > On Thursday, January 02, 2014 07:03:23 PM Yuvaraj Kumar wrote:
> >> On Tue, Dec 31, 2013 at 9:00 PM, Bartlomiej Zolnierkiewicz
> >> <b.zolnierkie@samsung.com> wrote:
> >
> >> >> @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)   += phy-exynos-mipi-video.o
> >> >>  obj-$(CONFIG_PHY_MVEBU_SATA)         += phy-mvebu-sata.o
> >> >>  obj-$(CONFIG_OMAP_USB2)                      += phy-omap-usb2.o
> >> >>  obj-$(CONFIG_TWL4030_USB)            += phy-twl4030-usb.o
> >> >> +obj-$(CONFIG_EXYNOS5250_SATA_PHY)    += sata_phy_exynos5250.o exynos5250_phy_i2c.o
> >> >
> >> > Will this compile/work without I2C support?
> >> No.I missed this.It will not compile without I2C support.
> >> How about  below change in drivers/phy/Kconfig ?
> >> config EXYNOS5250_SATA_PHY
> >> select I2C
> >> select I2C_S3C2410
> >
> > Fine with me.
> >
> >> > CONFIG_EXYNOS5250_SATA_PHY doesn't require it currently.
> >> I didnt get this. what it doesn't require?
> >
> > It doesn't require I2C.  If you add above I2C selects it will be OK.
> >
> >> >> +struct i2c_driver sataphy_i2c_driver = {
> >> >
> >> > Keeping it global together with sataphy_attach_i2c_client() is not very
> >> > nice.  I've talked with our local device tree guru (a.k.a. Tomasz Figa)
> >> > about this and it may be that this i2c driver is not even necessary.
> >> Can you elaborate more on this?
> >
> > The usage of the global i2c driver is not a proper solution.
> >
> > i2c driver should register itself in the driver init function
> do you mean i2c-s3c2410.c driver?

No, I mean that drivers/phy/exynos5250_phy_i2c.c should do

	i2c_add_driver(&sataphy_i2c_driver)

instead of drivers/phy/sata_phy_exynos5250.c.

i.e.:

...
static int exynos_sata_i2c_probe(struct i2c_client *client,
				const struct i2c_device_id *i2c_id)
{
	return 0;
}
...
static struct i2c_driver sataphy_i2c_driver = {
...
};
...
static int __init exynos5250_phy_i2c_init(void)
{
	return i2c_add_driver(&sataphy_i2c_driver);
}
...
module_init(exynos5250_phy_i2c_init);
...

BTW For consistency with the new naming it would be good to rename
exynos5250_phy_i2c.c to phy-exynos5250-sata-i2c.c.

> > (which is not present currently) instead of being registered by
> > the SATA PHY driver.
> >
> > The SATA PHY driver should find i2c client device using DT.
> >
> > sataphy_attach_i2c_client() should then be removed.
> >
> >> > If you manage to extract i2c adapter and address data from the device
> >> > tree (using proper of_* methods) they can be used instead of i2c client
> >> > data in the SATA PHY driver.
> >> I think the above is true, if the complete SATA PHY controller sits on
> >> the i2c adapter.
> >> But in Exynos5250 case,only the few configurations ( CMU and TRSV
> >> blocks ) SATA PHY
> >> are done through I2C(channel 9). Correct me if i am wrong.
> >
> > Well, it shouldn't matter if all or only some of the configuration of
> > the SATA PHY controller is done through i2c.
> >
> > Anyway, how about another idea -> adding a new phandle of i2c client
> > device to SATA PHY DT entry and using DT in the SATA PHY driver to
> > find i2c client device?
> >
> > i.e. "samsung,exynos-sataphy-i2c-phandle" property in SATA PHY
> > controller DT entry can point at existing "sata-phy@38" sataphy i2c
> > client DT entry (by adding new label to it, i.e. "sata_phy_i2c").
> >
> > Such new phandle can be used first to find the DT device node of i2c
> > device (by using of_parse_phandle(), if it returns NULL the error
> > should be returned) and then later to find proper i2c client device
> > (by using of_find_i2c_device_by_node(), if it returns NULL deferred
> > probing should be requested by returning -EPROBE_DEFER).
> I can get the i2c_client structure,but how the client driver binding
> happens to registered device?
> Currently with this approach i2c client device is being registered but
> cleint driver could not able to bind with the device.

Could you please explain more what the problem is?  What is the new
code exacly and what is the difference in the kernel logs?

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

> [    0.082680] i2c i2c-9: adapter [s3c2410-i2c] registered
> [    0.082691] i2c i2c-9: of_i2c: walking child nodes
> [    0.082696] i2c i2c-9: of_i2c: register /i2c@121D0000/sata-phy@38
> [    0.082794] i2c 9-0038: uevent
> [    0.082845] i2c i2c-9: client [exynos-sataphy-i2c] registered with
> bus id 9-0038
> [    0.082851] s3c-i2c 121d0000.i2c: i2c-9: S3C I2C adapter
> >
> > i2c@121D0000 {
> >         ...
> >         sata_phy_i2c: sata-phy@38 {
> >                 ...
> >         };
> >         ...
> > };
> >
> > sata_phy: sata-phy@12170000 {
> >         ...
> >         samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
> >         ...
> > };
> >
> > Best regards,
> > --
> > Bartlomiej Zolnierkiewicz
> > Samsung R&D Institute Poland
> > Samsung Electronics

Re: [PATCH V4 1/2] Phy: Exynos: Add Exynos5250 sata phy driver

[Yuvaraj Kumar]

On Wed, Jan 8, 2014 at 9:16 PM, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
> On Wednesday, January 08, 2014 06:39:52 PM Yuvaraj Kumar wrote:
>> On Tue, Jan 7, 2014 at 7:52 PM, Bartlomiej Zolnierkiewicz
>> <b.zolnierkie@samsung.com> wrote:
>> >
>> > Hi,
>> >
>> > On Thursday, January 02, 2014 07:03:23 PM Yuvaraj Kumar wrote:
>> >> On Tue, Dec 31, 2013 at 9:00 PM, Bartlomiej Zolnierkiewicz
>> >> <b.zolnierkie@samsung.com> wrote:
>> >
>> >> >> @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)   += phy-exynos-mipi-video.o
>> >> >>  obj-$(CONFIG_PHY_MVEBU_SATA)         += phy-mvebu-sata.o
>> >> >>  obj-$(CONFIG_OMAP_USB2)                      += phy-omap-usb2.o
>> >> >>  obj-$(CONFIG_TWL4030_USB)            += phy-twl4030-usb.o
>> >> >> +obj-$(CONFIG_EXYNOS5250_SATA_PHY)    += sata_phy_exynos5250.o exynos5250_phy_i2c.o
>> >> >
>> >> > Will this compile/work without I2C support?
>> >> No.I missed this.It will not compile without I2C support.
>> >> How about  below change in drivers/phy/Kconfig ?
>> >> config EXYNOS5250_SATA_PHY
>> >> select I2C
>> >> select I2C_S3C2410
>> >
>> > Fine with me.
>> >
>> >> > CONFIG_EXYNOS5250_SATA_PHY doesn't require it currently.
>> >> I didnt get this. what it doesn't require?
>> >
>> > It doesn't require I2C.  If you add above I2C selects it will be OK.
>> >
>> >> >> +struct i2c_driver sataphy_i2c_driver = {
>> >> >
>> >> > Keeping it global together with sataphy_attach_i2c_client() is not very
>> >> > nice.  I've talked with our local device tree guru (a.k.a. Tomasz Figa)
>> >> > about this and it may be that this i2c driver is not even necessary.
>> >> Can you elaborate more on this?
>> >
>> > The usage of the global i2c driver is not a proper solution.
>> >
>> > i2c driver should register itself in the driver init function
>> do you mean i2c-s3c2410.c driver?
>
> No, I mean that drivers/phy/exynos5250_phy_i2c.c should do
>
>         i2c_add_driver(&sataphy_i2c_driver)
>
> instead of drivers/phy/sata_phy_exynos5250.c.
>
> i.e.:
>
> ...
> static int exynos_sata_i2c_probe(struct i2c_client *client,
>                                 const struct i2c_device_id *i2c_id)
> {
>         return 0;
> }
> ...
> static struct i2c_driver sataphy_i2c_driver = {
> ...
> };
> ...
> static int __init exynos5250_phy_i2c_init(void)
> {
>         return i2c_add_driver(&sataphy_i2c_driver);
> }
> ...
> module_init(exynos5250_phy_i2c_init);
> ...
Thanks for the explaination.Will change as above.
>
> BTW For consistency with the new naming it would be good to rename
> exynos5250_phy_i2c.c to phy-exynos5250-sata-i2c.c.
Sure,will rename it.
>
>> > (which is not present currently) instead of being registered by
>> > the SATA PHY driver.
>> >
>> > The SATA PHY driver should find i2c client device using DT.
>> >
>> > sataphy_attach_i2c_client() should then be removed.
>> >
>> >> > If you manage to extract i2c adapter and address data from the device
>> >> > tree (using proper of_* methods) they can be used instead of i2c client
>> >> > data in the SATA PHY driver.
>> >> I think the above is true, if the complete SATA PHY controller sits on
>> >> the i2c adapter.
>> >> But in Exynos5250 case,only the few configurations ( CMU and TRSV
>> >> blocks ) SATA PHY
>> >> are done through I2C(channel 9). Correct me if i am wrong.
>> >
>> > Well, it shouldn't matter if all or only some of the configuration of
>> > the SATA PHY controller is done through i2c.
>> >
>> > Anyway, how about another idea -> adding a new phandle of i2c client
>> > device to SATA PHY DT entry and using DT in the SATA PHY driver to
>> > find i2c client device?
>> >
>> > i.e. "samsung,exynos-sataphy-i2c-phandle" property in SATA PHY
>> > controller DT entry can point at existing "sata-phy@38" sataphy i2c
>> > client DT entry (by adding new label to it, i.e. "sata_phy_i2c").
>> >
>> > Such new phandle can be used first to find the DT device node of i2c
>> > device (by using of_parse_phandle(), if it returns NULL the error
>> > should be returned) and then later to find proper i2c client device
>> > (by using of_find_i2c_device_by_node(), if it returns NULL deferred
>> > probing should be requested by returning -EPROBE_DEFER).
>> I can get the i2c_client structure,but how the client driver binding
>> happens to registered device?
>> Currently with this approach i2c client device is being registered but
>> cleint driver could not able to bind with the device.
>
> Could you please explain more what the problem is?  What is the new
> code exacly and what is the difference in the kernel logs?
I misunderstood your previous comments.Now its clarified.
I have addressed these comments and posted V5.
>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>
>> [    0.082680] i2c i2c-9: adapter [s3c2410-i2c] registered
>> [    0.082691] i2c i2c-9: of_i2c: walking child nodes
>> [    0.082696] i2c i2c-9: of_i2c: register /i2c@121D0000/sata-phy@38
>> [    0.082794] i2c 9-0038: uevent
>> [    0.082845] i2c i2c-9: client [exynos-sataphy-i2c] registered with
>> bus id 9-0038
>> [    0.082851] s3c-i2c 121d0000.i2c: i2c-9: S3C I2C adapter
>> >
>> > i2c@121D0000 {
>> >         ...
>> >         sata_phy_i2c: sata-phy@38 {
>> >                 ...
>> >         };
>> >         ...
>> > };
>> >
>> > sata_phy: sata-phy@12170000 {
>> >         ...
>> >         samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
>> >         ...
>> > };
>> >
>> > Best regards,
>> > --
>> > Bartlomiej Zolnierkiewicz
>> > Samsung R&D Institute Poland
>> > Samsung Electronics
>