[PATCHv13 00/40] ARM: TI SoC clock DT conversion

[PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tero Kristo]

Hi,

So, bad luck number release for this, as v12 wasn't sufficient still.

Changes compared to previous version:
- Dropped any changes to generic clock drivers, as it seems impossible
  to agree anything in short term, this means the patch set shrank in
  size from 49 patches to 40 (first 9 patches were dropped).
- Copy pasted implementation for clk-divider and clk-mux from drivers/clk
  to drivers/clk/ti, and made the modifications needed to the TI version
  of the clock drivers only (based on discussions with Mike, this is fine)
- Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
  with any generic implementation we might have at some point, migrating
  this to the generic version should be easy enough also.
- Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
  versions and resulted into an orphan clock node
- Fixed compile problem for omap5 only build reported by Felipe
- Fixed a couple of sparse warnings
- changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
  instead of __raw_readl / __raw_writel

Testing done:
- omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
- omap4-panda-es: boot / suspend-resume (RET)
- omap5-uevm: boot
- am335x-bone: boot
- dra7-evm: boot

Maintainer friendly branches also available:

tree: https://github.com/t-kristo/linux-pm.git

clk driver only (Mike): clk-next-dt-clks-v13
DTS data only (Benoit): dts_for_3.14-dt-clks-v13
full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13

-Tero

[PATCHv13 01/40] CLK: TI: add DT alias clock registration mechanism

[Tero Kristo]

Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/Makefile    |    1 +
 drivers/clk/ti/Makefile |    3 +++
 drivers/clk/ti/clk.c    |   55 +++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h  |   42 ++++++++++++++++++++++++++++++++++++
 4 files changed, 101 insertions(+)
 create mode 100644 drivers/clk/ti/Makefile
 create mode 100644 drivers/clk/ti/clk.c
 create mode 100644 include/linux/clk/ti.h

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7a10bc9..c61f768 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
 obj-$(CONFIG_COMMON_CLK_XGENE)  += clk-xgene.o
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)	+= keystone/
+obj-$(CONFIG_ARCH_OMAP)		+= ti/
 
 obj-$(CONFIG_X86)		+= x86/
 
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
new file mode 100644
index 0000000..1825f7f
--- /dev/null
+++ b/drivers/clk/ti/Makefile
@@ -0,0 +1,3 @@
+ifneq ($(CONFIG_OF),)
+obj-y					+= clk.o
+endif
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
new file mode 100644
index 0000000..ef1a7cd
--- /dev/null
+++ b/drivers/clk/ti/clk.c
@@ -0,0 +1,55 @@
+/*
+ * TI clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+#include <linux/of.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+/**
+ * ti_dt_clocks_register - register DT alias clocks during boot
+ * @oclks: list of clocks to register
+ *
+ * Register alias or non-standard DT clock entries during boot. By
+ * default, DT clocks are found based on their node name. If any
+ * additional con-id / dev-id -> clock mapping is required, use this
+ * function to list these.
+ */
+void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
+{
+	struct ti_dt_clk *c;
+	struct device_node *node;
+	struct clk *clk;
+	struct of_phandle_args clkspec;
+
+	for (c = oclks; c->node_name != NULL; c++) {
+		node = of_find_node_by_name(NULL, c->node_name);
+		clkspec.np = node;
+		clk = of_clk_get_from_provider(&clkspec);
+
+		if (!IS_ERR(clk)) {
+			c->lk.clk = clk;
+			clkdev_add(&c->lk);
+		} else {
+			pr_warn("failed to lookup clock node %s\n",
+				c->node_name);
+		}
+	}
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
new file mode 100644
index 0000000..df94c24
--- /dev/null
+++ b/include/linux/clk/ti.h
@@ -0,0 +1,42 @@
+/*
+ * TI clock drivers support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __LINUX_CLK_TI_H__
+#define __LINUX_CLK_TI_H__
+
+#include <linux/clkdev.h>
+
+/**
+ * struct ti_dt_clk - OMAP DT clock alias declarations
+ * @lk: clock lookup definition
+ * @node_name: clock DT node to map to
+ */
+struct ti_dt_clk {
+	struct clk_lookup		lk;
+	char				*node_name;
+};
+
+#define DT_CLK(dev, con, name)		\
+	{				\
+		.lk = {			\
+			.dev_id = dev,	\
+			.con_id = con,	\
+		},			\
+		.node_name = name,	\
+	}
+
+
+void ti_dt_clocks_register(struct ti_dt_clk *oclks);
+
+#endif
-- 
1.7.9.5

[PATCHv13 02/40] CLK: ti: add init support for clock IP blocks

[Tero Kristo]

ti_dt_clk_init_provider() can now be used to initialize the contents of
a single clock IP block. This parses all the clocks under the IP block
and calls the corresponding init function for them.

This patch also introduces a helper function for the TI clock drivers
to get register info from DT and append the master IP info to this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk.c            |    4 +-
 drivers/clk/ti/clk.c         |  112 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h |    2 +
 include/linux/clk/ti.h       |   35 +++++++++++++
 4 files changed, 150 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 2cf2ea6..bbbe799 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2104,8 +2104,6 @@ struct of_clk_provider {
 	void *data;
 };
 
-extern struct of_device_id __clk_of_table[];
-
 static const struct of_device_id __clk_of_table_sentinel
 	__used __section(__clk_of_table_end);
 
@@ -2245,7 +2243,7 @@ void __init of_clk_init(const struct of_device_id *matches)
 	struct device_node *np;
 
 	if (!matches)
-		matches = __clk_of_table;
+		matches = &__clk_of_table;
 
 	for_each_matching_node_and_match(np, matches, &match) {
 		of_clk_init_cb_t clk_init_cb = match->data;
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index ef1a7cd..b1a6f71 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -19,10 +19,15 @@
 #include <linux/clkdev.h>
 #include <linux/clk/ti.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/list.h>
 
 #undef pr_fmt
 #define pr_fmt(fmt) "%s: " fmt, __func__
 
+static int ti_dt_clk_memmap_index;
+struct ti_clk_ll_ops *ti_clk_ll_ops;
+
 /**
  * ti_dt_clocks_register - register DT alias clocks during boot
  * @oclks: list of clocks to register
@@ -53,3 +58,110 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
 		}
 	}
 }
+
+struct clk_init_item {
+	struct device_node *node;
+	struct clk_hw *hw;
+	ti_of_clk_init_cb_t func;
+	struct list_head link;
+};
+
+static LIST_HEAD(retry_list);
+
+/**
+ * ti_clk_retry_init - retries a failed clock init at later phase
+ * @node: device not for the clock
+ * @hw: partially initialized clk_hw struct for the clock
+ * @func: init function to be called for the clock
+ *
+ * Adds a failed clock init to the retry list. The retry list is parsed
+ * once all the other clocks have been initialized.
+ */
+int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
+			      ti_of_clk_init_cb_t func)
+{
+	struct clk_init_item *retry;
+
+	pr_debug("%s: adding to retry list...\n", node->name);
+	retry = kzalloc(sizeof(*retry), GFP_KERNEL);
+	if (!retry)
+		return -ENOMEM;
+
+	retry->node = node;
+	retry->func = func;
+	retry->hw = hw;
+	list_add(&retry->link, &retry_list);
+
+	return 0;
+}
+
+/**
+ * ti_clk_get_reg_addr - get register address for a clock register
+ * @node: device node for the clock
+ * @index: register index from the clock node
+ *
+ * Builds clock register address from device tree information. This
+ * is a struct of type clk_omap_reg.
+ */
+void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
+{
+	struct clk_omap_reg *reg;
+	u32 val;
+	u32 tmp;
+
+	reg = (struct clk_omap_reg *)&tmp;
+	reg->index = ti_dt_clk_memmap_index;
+
+	if (of_property_read_u32_index(node, "reg", index, &val)) {
+		pr_err("%s must have reg[%d]!\n", node->name, index);
+		return NULL;
+	}
+
+	reg->offset = val;
+
+	return (void __iomem *)tmp;
+}
+
+/**
+ * ti_dt_clk_init_provider - init master clock provider
+ * @parent: master node
+ * @index: internal index for clk_reg_ops
+ *
+ * Initializes a master clock IP block and its child clock nodes.
+ * Regmap is provided for accessing the register space for the
+ * IP block and all the clocks under it.
+ */
+void ti_dt_clk_init_provider(struct device_node *parent, int index)
+{
+	const struct of_device_id *match;
+	struct device_node *np;
+	struct device_node *clocks;
+	of_clk_init_cb_t clk_init_cb;
+	struct clk_init_item *retry;
+	struct clk_init_item *tmp;
+
+	ti_dt_clk_memmap_index = index;
+
+	/* get clocks for this parent */
+	clocks = of_get_child_by_name(parent, "clocks");
+	if (!clocks) {
+		pr_err("%s missing 'clocks' child node.\n", parent->name);
+		return;
+	}
+
+	for_each_child_of_node(clocks, np) {
+		match = of_match_node(&__clk_of_table, np);
+		if (!match)
+			continue;
+		clk_init_cb = (of_clk_init_cb_t)match->data;
+		pr_debug("%s: initializing: %s\n", __func__, np->name);
+		clk_init_cb(np);
+	}
+
+	list_for_each_entry_safe(retry, tmp, &retry_list, link) {
+		pr_debug("retry-init: %s\n", retry->node->name);
+		retry->func(retry->hw, retry->node);
+		list_del(&retry->link);
+		kfree(retry);
+	}
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7e59253..5760dc8 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -458,6 +458,8 @@ struct clk_onecell_data {
 	unsigned int clk_num;
 };
 
+extern struct of_device_id __clk_of_table;
+
 #define CLK_OF_DECLARE(name, compat, fn)			\
 	static const struct of_device_id __clk_of_table_##name	\
 		__used __section(__clk_of_table)		\
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index df94c24..c6eded5 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -36,7 +36,42 @@ struct ti_dt_clk {
 		.node_name = name,	\
 	}
 
+/* Maximum number of clock memmaps */
+#define CLK_MAX_MEMMAPS			4
 
+typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
+
+/**
+ * struct clk_omap_reg - OMAP register declaration
+ * @offset: offset from the master IP module base address
+ * @index: index of the master IP module
+ */
+struct clk_omap_reg {
+	u16 offset;
+	u16 index;
+};
+
+/**
+ * struct ti_clk_ll_ops - low-level register access ops for a clock
+ * @clk_readl: pointer to register read function
+ * @clk_writel: pointer to register write function
+ *
+ * Low-level register access ops are generally used by the basic clock types
+ * (clk-gate, clk-mux, clk-divider etc.) to provide support for various
+ * low-level hardware interfaces (direct MMIO, regmap etc.), but can also be
+ * used by other hardware-specific clock drivers if needed.
+ */
+struct ti_clk_ll_ops {
+	u32	(*clk_readl)(void __iomem *reg);
+	void	(*clk_writel)(u32 val, void __iomem *reg);
+};
+
+extern struct ti_clk_ll_ops *ti_clk_ll_ops;
+
+void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
+void ti_dt_clk_init_provider(struct device_node *np, int index);
+int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
+		      ti_of_clk_init_cb_t func);
 
 #endif
-- 
1.7.9.5

[PATCHv13 03/40] CLK: TI: Add DPLL clock support

[Tero Kristo]

The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/dpll.txt          |   75 +++
 arch/arm/mach-omap2/clock.h                        |  164 +-----
 arch/arm/mach-omap2/clock3xxx.h                    |    2 -
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/dpll.c                              |  558 ++++++++++++++++++++
 include/linux/clk/ti.h                             |  172 ++++++
 6 files changed, 807 insertions(+), 166 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
 create mode 100644 drivers/clk/ti/dpll.c

diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
new file mode 100644
index 0000000..30bfdb7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
@@ -0,0 +1,75 @@
+Binding for Texas Instruments DPLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped DPLL with usually two selectable input clocks
+(reference clock and bypass clock), with digital phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) This binding has several
+sub-types, which effectively result in slightly different setup
+for the actual DPLL clock.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of:
+		"ti,omap3-dpll-clock",
+		"ti,omap3-dpll-core-clock",
+		"ti,omap3-dpll-per-clock",
+		"ti,omap3-dpll-per-j-type-clock",
+		"ti,omap4-dpll-clock",
+		"ti,omap4-dpll-x2-clock",
+		"ti,omap4-dpll-core-clock",
+		"ti,omap4-dpll-m4xen-clock",
+		"ti,omap4-dpll-j-type-clock",
+		"ti,am3-dpll-no-gate-clock",
+		"ti,am3-dpll-j-type-clock",
+		"ti,am3-dpll-no-gate-j-type-clock",
+		"ti,am3-dpll-clock",
+		"ti,am3-dpll-core-clock",
+		"ti,am3-dpll-x2-clock",
+
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks, first entry lists reference clock
+  and second entry bypass clock
+- reg : offsets for the register set for controlling the DPLL.
+  Registers are listed in following order:
+	"control" - contains the control register base address
+	"idlest" - contains the idle status register base address
+	"mult-div1" - contains the multiplier / divider register base address
+	"autoidle" - contains the autoidle register base address (optional)
+  ti,am3-* dpll types do not have autoidle register
+
+Optional properties:
+- DPLL mode setting - defining any one or more of the following overrides
+  default setting.
+	- ti,low-power-stop : DPLL supports low power stop mode, gating output
+	- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
+	- ti,lock : DPLL locks in programmed rate
+
+Examples:
+	dpll_core_ck: dpll_core_ck@44e00490 {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-core-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x490>, <0x45c>, <0x488>, <0x468>;
+	};
+
+	dpll2_ck: dpll2_ck@48004004 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-dpll-clock";
+		clocks = <&sys_ck>, <&dpll2_fck>;
+		ti,low-power-stop;
+		ti,low-power-bypass;
+		ti,lock;
+		reg = <0x4>, <0x24>, <0x34>, <0x40>;
+	};
+
+	dpll_core_ck: dpll_core_ck@44e00490 {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-core-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x90>, <0x5c>, <0x68>;
+	};
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 82916cc..b345f3e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
 
 struct omap_clk {
 	u16				cpu;
@@ -37,7 +38,6 @@ struct omap_clk {
 	}
 
 struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name)	\
 	static struct clk _name = {				\
@@ -178,141 +178,6 @@ struct clksel {
 	const struct clksel_rate *rates;
 };
 
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @last_rounded_m4xen: cache of the last M4X result of
- *			omap4_dpll_regm4xen_round_rate()
- * @last_rounded_lpmode: cache of the last lpmode result of
- *			 omap4_dpll_lpmode_recalc()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
-	void __iomem		*mult_div1_reg;
-	u32			mult_mask;
-	u32			div1_mask;
-	struct clk		*clk_bypass;
-	struct clk		*clk_ref;
-	void __iomem		*control_reg;
-	u32			enable_mask;
-	unsigned long		last_rounded_rate;
-	u16			last_rounded_m;
-	u8			last_rounded_m4xen;
-	u8			last_rounded_lpmode;
-	u16			max_multiplier;
-	u8			last_rounded_n;
-	u8			min_divider;
-	u16			max_divider;
-	u8			modes;
-	void __iomem		*autoidle_reg;
-	void __iomem		*idlest_reg;
-	u32			autoidle_mask;
-	u32			freqsel_mask;
-	u32			idlest_mask;
-	u32			dco_mask;
-	u32			sddiv_mask;
-	u32			lpmode_mask;
-	u32			m4xen_mask;
-	u8			auto_recal_bit;
-	u8			recal_en_bit;
-	u8			recal_st_bit;
-	u8			flags;
-};
-
-/*
- * struct clk.flags possibilities
- *
- * XXX document the rest of the clock flags here
- *
- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- *     bits share the same register.  This flag allows the
- *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
- *     should be used.  This is a temporary solution - a better approach
- *     would be to associate clock type-specific data with the clock,
- *     similar to the struct dpll_data approach.
- */
-#define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL	(1 << 1)
-#define CLOCK_NO_IDLE_PARENT	(1 << 2)
-#define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
-#define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
-#define CLOCK_CLKOUTX2		(1 << 5)
-
-/**
- * struct clk_hw_omap - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- */
-
-struct clk_hw_omap_ops;
-
-struct clk_hw_omap {
-	struct clk_hw		hw;
-	struct list_head	node;
-	unsigned long		fixed_rate;
-	u8			fixed_div;
-	void __iomem		*enable_reg;
-	u8			enable_bit;
-	u8			flags;
-	void __iomem		*clksel_reg;
-	u32			clksel_mask;
-	const struct clksel	*clksel;
-	struct dpll_data	*dpll_data;
-	const char		*clkdm_name;
-	struct clockdomain	*clkdm;
-	const struct clk_hw_omap_ops	*ops;
-};
-
 struct clk_hw_omap_ops {
 	void			(*find_idlest)(struct clk_hw_omap *oclk,
 					void __iomem **idlest_reg,
@@ -348,36 +213,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 #define OMAP4XXX_EN_DPLL_FRBYPASS		0x6
 #define OMAP4XXX_EN_DPLL_LOCKED			0x7
 
-/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
-#define DPLL_LOW_POWER_STOP	0x1
-#define DPLL_LOW_POWER_BYPASS	0x5
-#define DPLL_LOCKED		0x7
-
-/* DPLL Type and DCO Selection Flags */
-#define DPLL_J_TYPE		0x1
-
-long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
-			unsigned long *parent_rate);
-unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk_hw *hw);
-void omap3_noncore_dpll_disable(struct clk_hw *hw);
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
-				unsigned long parent_rate);
 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
-				    unsigned long parent_rate);
 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
-				unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
-				    unsigned long target_rate,
-				    unsigned long *parent_rate);
 
-void omap2_init_clk_clkdm(struct clk_hw *clk);
 void __init omap2_clk_disable_clkdm_control(void);
 
 /* clkt_clksel.c public functions */
@@ -396,7 +238,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
-u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
 int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -408,7 +249,6 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 				void __iomem **idlest_reg,
 				u8 *idlest_bit, u8 *idlest_val);
-void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap2_clk_enable_autoidle_all(void);
 int omap2_clk_disable_autoidle_all(void);
 int omap2_clk_allow_idle(struct clk *clk);
@@ -433,10 +273,8 @@ extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
-extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 8cd4b0a..dab90e2 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,8 +9,6 @@
 #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
 
 int omap3xxx_clk_init(void);
-int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
-					unsigned long parent_rate);
 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
 					unsigned long parent_rate);
 void omap3_clk_lock_dpll5(void);
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 1825f7f..05af5d8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
 ifneq ($(CONFIG_OF),)
-obj-y					+= clk.o
+obj-y					+= clk.o dpll.o
 endif
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
new file mode 100644
index 0000000..7e498a4
--- /dev/null
+++ b/drivers/clk/ti/dpll.c
@@ -0,0 +1,558 @@
+/*
+ * OMAP DPLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#define DPLL_HAS_AUTOIDLE	0x1
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+	defined(CONFIG_SOC_DRA7XX)
+static const struct clk_ops dpll_m4xen_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
+	.round_rate	= &omap4_dpll_regm4xen_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+#endif
+
+static const struct clk_ops dpll_core_ck_ops = {
+	.recalc_rate	= &omap3_dpll_recalc,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+
+#ifdef CONFIG_ARCH_OMAP3
+static const struct clk_ops omap3_dpll_core_ck_ops = {
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+#endif
+
+static const struct clk_ops dpll_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_no_gate_ck_ops = {
+	.recalc_rate	= &omap3_dpll_recalc,
+	.get_parent	= &omap2_init_dpll_parent,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+};
+
+#ifdef CONFIG_ARCH_OMAP3
+static const struct clk_ops omap3_dpll_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops omap3_dpll_per_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.set_rate	= &omap3_dpll4_set_rate,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+#endif
+
+static const struct clk_ops dpll_x2_ck_ops = {
+	.recalc_rate	= &omap3_clkoutx2_recalc,
+};
+
+/**
+ * ti_clk_register_dpll - low level registration of a DPLL clock
+ * @hw: hardware clock definition for the clock
+ * @node: device node for the clock
+ *
+ * Finalizes DPLL registration process. In case a failure (clk-ref or
+ * clk-bypass is missing), the clock is added to retry list and
+ * the initialization is retried on later stage.
+ */
+static void __init ti_clk_register_dpll(struct clk_hw *hw,
+					struct device_node *node)
+{
+	struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
+	struct dpll_data *dd = clk_hw->dpll_data;
+	struct clk *clk;
+
+	dd->clk_ref = of_clk_get(node, 0);
+	dd->clk_bypass = of_clk_get(node, 1);
+
+	if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
+		pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
+			 node->name);
+		if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll))
+			return;
+
+		goto cleanup;
+	}
+
+	/* register the clock */
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (!IS_ERR(clk)) {
+		omap2_init_clk_hw_omap_clocks(clk);
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		kfree(clk_hw->hw.init->parent_names);
+		kfree(clk_hw->hw.init);
+		return;
+	}
+
+cleanup:
+	kfree(clk_hw->dpll_data);
+	kfree(clk_hw->hw.init->parent_names);
+	kfree(clk_hw->hw.init);
+	kfree(clk_hw);
+}
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+	defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX)
+/**
+ * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
+ * @node: device node for this clock
+ * @ops: clk_ops for this clock
+ * @hw_ops: clk_hw_ops for this clock
+ *
+ * Initializes a DPLL x 2 clock from device tree data.
+ */
+static void ti_clk_register_dpll_x2(struct device_node *node,
+				    const struct clk_ops *ops,
+				    const struct clk_hw_omap_ops *hw_ops)
+{
+	struct clk *clk;
+	struct clk_init_data init = { NULL };
+	struct clk_hw_omap *clk_hw;
+	const char *name = node->name;
+	const char *parent_name;
+
+	parent_name = of_clk_get_parent_name(node, 0);
+	if (!parent_name) {
+		pr_err("%s must have parent\n", node->name);
+		return;
+	}
+
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw)
+		return;
+
+	clk_hw->ops = hw_ops;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	/* register the clock */
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (IS_ERR(clk)) {
+		kfree(clk_hw);
+	} else {
+		omap2_init_clk_hw_omap_clocks(clk);
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	}
+}
+#endif
+
+/**
+ * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
+ * @node: device node containing the DPLL info
+ * @ops: ops for the DPLL
+ * @ddt: DPLL data template to use
+ * @init_flags: flags for controlling init types
+ *
+ * Initializes a DPLL clock from device tree data.
+ */
+static void __init of_ti_dpll_setup(struct device_node *node,
+				    const struct clk_ops *ops,
+				    const struct dpll_data *ddt,
+				    u8 init_flags)
+{
+	struct clk_hw_omap *clk_hw = NULL;
+	struct clk_init_data *init = NULL;
+	const char **parent_names = NULL;
+	struct dpll_data *dd = NULL;
+	int i;
+	u8 dpll_mode = 0;
+
+	dd = kzalloc(sizeof(*dd), GFP_KERNEL);
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	init = kzalloc(sizeof(*init), GFP_KERNEL);
+	if (!dd || !clk_hw || !init)
+		goto cleanup;
+
+	memcpy(dd, ddt, sizeof(*dd));
+
+	clk_hw->dpll_data = dd;
+	clk_hw->ops = &clkhwops_omap3_dpll;
+	clk_hw->hw.init = init;
+	clk_hw->flags = MEMMAP_ADDRESSING;
+
+	init->name = node->name;
+	init->ops = ops;
+
+	init->num_parents = of_clk_get_parent_count(node);
+	if (init->num_parents < 1) {
+		pr_err("%s must have parent(s)\n", node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
+	if (!parent_names)
+		goto cleanup;
+
+	for (i = 0; i < init->num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	init->parent_names = parent_names;
+
+	dd->control_reg = ti_clk_get_reg_addr(node, 0);
+	dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
+	dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
+
+	if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg)
+		goto cleanup;
+
+	if (init_flags & DPLL_HAS_AUTOIDLE) {
+		dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
+		if (!dd->autoidle_reg)
+			goto cleanup;
+	}
+
+	if (of_property_read_bool(node, "ti,low-power-stop"))
+		dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
+
+	if (of_property_read_bool(node, "ti,low-power-bypass"))
+		dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
+
+	if (of_property_read_bool(node, "ti,lock"))
+		dpll_mode |= 1 << DPLL_LOCKED;
+
+	if (dpll_mode)
+		dd->modes = dpll_mode;
+
+	ti_clk_register_dpll(&clk_hw->hw, node);
+	return;
+
+cleanup:
+	kfree(dd);
+	kfree(parent_names);
+	kfree(init);
+	kfree(clk_hw);
+}
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+	defined(CONFIG_SOC_DRA7XX)
+static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
+{
+	ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
+}
+CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
+	       of_ti_omap4_dpll_x2_setup);
+#endif
+
+#ifdef CONFIG_SOC_AM33XX
+static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
+{
+	ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
+}
+CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
+	       of_ti_am3_dpll_x2_setup);
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+static void __init of_ti_omap3_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.freqsel_mask = 0xf0,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
+	       of_ti_omap3_dpll_setup);
+
+static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 16,
+		.div1_mask = 0x7f << 8,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.freqsel_mask = 0xf0,
+	};
+
+	of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
+	       of_ti_omap3_core_dpll_setup);
+
+static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1 << 1,
+		.enable_mask = 0x7 << 16,
+		.autoidle_mask = 0x7 << 3,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.freqsel_mask = 0xf00000,
+		.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
+	       of_ti_omap3_per_dpll_setup);
+
+static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1 << 1,
+		.enable_mask = 0x7 << 16,
+		.autoidle_mask = 0x7 << 3,
+		.mult_mask = 0xfff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 4095,
+		.max_divider = 128,
+		.min_divider = 1,
+		.sddiv_mask = 0xff << 24,
+		.dco_mask = 0xe << 20,
+		.flags = DPLL_J_TYPE,
+		.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
+	       of_ti_omap3_per_jtype_dpll_setup);
+#endif
+
+static void __init of_ti_omap4_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
+	       of_ti_omap4_dpll_setup);
+
+static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
+	       of_ti_omap4_core_dpll_setup);
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+	defined(CONFIG_SOC_DRA7XX)
+static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.m4xen_mask = 0x800,
+		.lpmode_mask = 1 << 10,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
+	       of_ti_omap4_m4xen_dpll_setup);
+
+static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0xfff << 8,
+		.div1_mask = 0xff,
+		.max_multiplier = 4095,
+		.max_divider = 256,
+		.min_divider = 1,
+		.sddiv_mask = 0xff << 24,
+		.flags = DPLL_J_TYPE,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+}
+CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
+	       of_ti_omap4_jtype_dpll_setup);
+#endif
+
+static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
+	       of_ti_am3_no_gate_dpll_setup);
+
+static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 4095,
+		.max_divider = 256,
+		.min_divider = 2,
+		.flags = DPLL_J_TYPE,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
+	       of_ti_am3_jtype_dpll_setup);
+
+static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.flags = DPLL_J_TYPE,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
+	       "ti,am3-dpll-no-gate-j-type-clock",
+	       of_ti_am3_no_gate_jtype_dpll_setup);
+
+static void __init of_ti_am3_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
+
+static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, 0);
+}
+CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
+	       of_ti_am3_core_dpll_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index c6eded5..3f9de39 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -18,6 +18,153 @@
 #include <linux/clkdev.h>
 
 /**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @last_rounded_m4xen: cache of the last M4X result of
+ *			omap4_dpll_regm4xen_round_rate()
+ * @last_rounded_lpmode: cache of the last lpmode result of
+ *			 omap4_dpll_lpmode_recalc()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
+ * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ *
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+	void __iomem		*mult_div1_reg;
+	u32			mult_mask;
+	u32			div1_mask;
+	struct clk		*clk_bypass;
+	struct clk		*clk_ref;
+	void __iomem		*control_reg;
+	u32			enable_mask;
+	unsigned long		last_rounded_rate;
+	u16			last_rounded_m;
+	u8			last_rounded_m4xen;
+	u8			last_rounded_lpmode;
+	u16			max_multiplier;
+	u8			last_rounded_n;
+	u8			min_divider;
+	u16			max_divider;
+	u8			modes;
+	void __iomem		*autoidle_reg;
+	void __iomem		*idlest_reg;
+	u32			autoidle_mask;
+	u32			freqsel_mask;
+	u32			idlest_mask;
+	u32			dco_mask;
+	u32			sddiv_mask;
+	u32			lpmode_mask;
+	u32			m4xen_mask;
+	u8			auto_recal_bit;
+	u8			recal_en_bit;
+	u8			recal_st_bit;
+	u8			flags;
+};
+
+struct clk_hw_omap_ops;
+
+/**
+ * struct clk_hw_omap - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
+ * @ops: clock ops for this clock
+ */
+struct clk_hw_omap {
+	struct clk_hw		hw;
+	struct list_head	node;
+	unsigned long		fixed_rate;
+	u8			fixed_div;
+	void __iomem		*enable_reg;
+	u8			enable_bit;
+	u8			flags;
+	void __iomem		*clksel_reg;
+	u32			clksel_mask;
+	const struct clksel	*clksel;
+	struct dpll_data	*dpll_data;
+	const char		*clkdm_name;
+	struct clockdomain	*clkdm;
+	const struct clk_hw_omap_ops	*ops;
+};
+
+/*
+ * struct clk_hw_omap.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
+ *     with 32bit ops, by default OMAP1 uses 16bit ops.
+ * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
+ * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
+ *     clock is put to no-idle mode.
+ * ENABLE_ON_INIT: Clock is enabled on init.
+ * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
+ *     disable. This inverts the behavior making '0' enable and '1' disable.
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ *     bits share the same register.  This flag allows the
+ *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ *     should be used.  This is a temporary solution - a better approach
+ *     would be to associate clock type-specific data with the clock,
+ *     similar to the struct dpll_data approach.
+ * MEMMAP_ADDRESSING: Use memmap addressing to access clock registers.
+ */
+#define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL	(1 << 1)
+#define CLOCK_NO_IDLE_PARENT	(1 << 2)
+#define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
+#define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2		(1 << 5)
+#define MEMMAP_ADDRESSING	(1 << 6)
+
+/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+#define DPLL_LOW_POWER_STOP	0x1
+#define DPLL_LOW_POWER_BYPASS	0x5
+#define DPLL_LOCKED		0x7
+
+/* DPLL Type and DCO Selection Flags */
+#define DPLL_J_TYPE		0x1
+
+/**
  * struct ti_dt_clk - OMAP DT clock alias declarations
  * @lk: clock lookup definition
  * @node_name: clock DT node to map to
@@ -68,10 +215,35 @@ struct ti_clk_ll_ops {
 
 extern struct ti_clk_ll_ops *ti_clk_ll_ops;
 
+#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
+
+void omap2_init_clk_hw_omap_clocks(struct clk *clk);
+int omap3_noncore_dpll_enable(struct clk_hw *hw);
+void omap3_noncore_dpll_disable(struct clk_hw *hw);
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate);
+unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
+					 unsigned long parent_rate);
+long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
+				    unsigned long target_rate,
+				    unsigned long *parent_rate);
+u8 omap2_init_dpll_parent(struct clk_hw *hw);
+unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+			   unsigned long *parent_rate);
+void omap2_init_clk_clkdm(struct clk_hw *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
+				    unsigned long parent_rate);
+int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
+			 unsigned long parent_rate);
+
 void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
 void ti_dt_clk_init_provider(struct device_node *np, int index);
 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
 		      ti_of_clk_init_cb_t func);
 
+extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
+extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+
 #endif
-- 
1.7.9.5

[PATCHv13 04/40] CLK: TI: add autoidle support

[Tero Kristo]

TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/autoidle.txt      |   39 ++++++
 arch/arm/mach-omap2/clock.c                        |    6 +
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/autoidle.c                          |  133 ++++++++++++++++++++
 include/linux/clk/ti.h                             |    9 ++
 5 files changed, 188 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/autoidle.txt
 create mode 100644 drivers/clk/ti/autoidle.c

diff --git a/Documentation/devicetree/bindings/clock/ti/autoidle.txt b/Documentation/devicetree/bindings/clock/ti/autoidle.txt
new file mode 100644
index 0000000..7c735dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/autoidle.txt
@@ -0,0 +1,39 @@
+Binding for Texas Instruments autoidle clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a register mapped
+clock which can be put to idle automatically by hardware based on the usage
+and a configuration bit setting. Autoidle clock is never an individual
+clock, it is always a derivative of some basic clock like a gate, divider,
+or fixed-factor.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- reg : offset for the register controlling the autoidle
+- ti,autoidle-shift : bit shift of the autoidle enable bit
+- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
+
+Examples:
+	dpll_core_m4_ck: dpll_core_m4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2d38>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+		#clock-cells = <0>;
+		compatible = "ti,fixed-factor-clock";
+		clocks = <&dpll_usb_ck>;
+		ti,clock-div = <1>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01b4>;
+		ti,clock-mult = <1>;
+		ti,invert-autoidle-bit;
+	};
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index c7c5d31..238be3f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
 		if (c->ops && c->ops->allow_idle)
 			c->ops->allow_idle(c);
+
+	of_ti_clk_allow_autoidle_all();
+
 	return 0;
 }
 
@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
 		if (c->ops && c->ops->deny_idle)
 			c->ops->deny_idle(c);
+
+	of_ti_clk_deny_autoidle_all();
+
 	return 0;
 }
 
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 05af5d8..533efb4 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
 ifneq ($(CONFIG_OF),)
-obj-y					+= clk.o dpll.o
+obj-y					+= clk.o dpll.o autoidle.o
 endif
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
new file mode 100644
index 0000000..8912ff8
--- /dev/null
+++ b/drivers/clk/ti/autoidle.c
@@ -0,0 +1,133 @@
+/*
+ * TI clock autoidle support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+struct clk_ti_autoidle {
+	void __iomem		*reg;
+	u8			shift;
+	u8			flags;
+	const char		*name;
+	struct list_head	node;
+};
+
+#define AUTOIDLE_LOW		0x1
+
+static LIST_HEAD(autoidle_clks);
+
+static void ti_allow_autoidle(struct clk_ti_autoidle *clk)
+{
+	u32 val;
+
+	val = ti_clk_ll_ops->clk_readl(clk->reg);
+
+	if (clk->flags & AUTOIDLE_LOW)
+		val &= ~(1 << clk->shift);
+	else
+		val |= (1 << clk->shift);
+
+	ti_clk_ll_ops->clk_writel(val, clk->reg);
+}
+
+static void ti_deny_autoidle(struct clk_ti_autoidle *clk)
+{
+	u32 val;
+
+	val = ti_clk_ll_ops->clk_readl(clk->reg);
+
+	if (clk->flags & AUTOIDLE_LOW)
+		val |= (1 << clk->shift);
+	else
+		val &= ~(1 << clk->shift);
+
+	ti_clk_ll_ops->clk_writel(val, clk->reg);
+}
+
+/**
+ * of_ti_clk_allow_autoidle_all - enable autoidle for all clocks
+ *
+ * Enables hardware autoidle for all registered DT clocks, which have
+ * the feature.
+ */
+void of_ti_clk_allow_autoidle_all(void)
+{
+	struct clk_ti_autoidle *c;
+
+	list_for_each_entry(c, &autoidle_clks, node)
+		ti_allow_autoidle(c);
+}
+
+/**
+ * of_ti_clk_deny_autoidle_all - disable autoidle for all clocks
+ *
+ * Disables hardware autoidle for all registered DT clocks, which have
+ * the feature.
+ */
+void of_ti_clk_deny_autoidle_all(void)
+{
+	struct clk_ti_autoidle *c;
+
+	list_for_each_entry(c, &autoidle_clks, node)
+		ti_deny_autoidle(c);
+}
+
+/**
+ * of_ti_clk_autoidle_setup - sets up hardware autoidle for a clock
+ * @node: pointer to the clock device node
+ *
+ * Checks if a clock has hardware autoidle support or not (check
+ * for presence of 'ti,autoidle-shift' property in the device tree
+ * node) and sets up the hardware autoidle feature for the clock
+ * if available. If autoidle is available, the clock is also added
+ * to the autoidle list for later processing. Returns 0 on success,
+ * negative error value on failure.
+ */
+int __init of_ti_clk_autoidle_setup(struct device_node *node)
+{
+	u32 shift;
+	struct clk_ti_autoidle *clk;
+
+	/* Check if this clock has autoidle support or not */
+	if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
+		return 0;
+
+	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+
+	if (!clk)
+		return -ENOMEM;
+
+	clk->shift = shift;
+	clk->name = node->name;
+	clk->reg = ti_clk_get_reg_addr(node, 0);
+
+	if (!clk->reg) {
+		kfree(clk);
+		return -EINVAL;
+	}
+
+	if (of_property_read_bool(node, "ti,invert-autoidle-bit"))
+		clk->flags |= AUTOIDLE_LOW;
+
+	list_add(&clk->node, &autoidle_clks);
+
+	return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 3f9de39..ca38ee3 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -242,6 +242,15 @@ void ti_dt_clocks_register(struct ti_dt_clk *oclks);
 void ti_dt_clk_init_provider(struct device_node *np, int index);
 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
 		      ti_of_clk_init_cb_t func);
+int of_ti_clk_autoidle_setup(struct device_node *node);
+
+#ifdef CONFIG_OF
+void of_ti_clk_allow_autoidle_all(void);
+void of_ti_clk_deny_autoidle_all(void);
+#else
+static inline void of_ti_clk_allow_autoidle_all(void) { }
+static inline void of_ti_clk_deny_autoidle_all(void) { }
+#endif
 
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
-- 
1.7.9.5

[PATCHv13 05/40] clk: ti: add composite clock support

[Tero Kristo]

This is a multipurpose clock node, which contains support for multiple
sub-clocks. Uses basic composite clock type to implement the actual
functionality, and TI specific gate, mux and divider clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/composite.txt     |   54 ++++
 arch/arm/mach-omap2/clock.h                        |    3 -
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/composite.c                         |  269 ++++++++++++++++++++
 include/linux/clk/ti.h                             |   12 +
 5 files changed, 336 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/composite.txt
 create mode 100644 drivers/clk/ti/composite.c

diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt b/Documentation/devicetree/bindings/clock/ti/composite.txt
new file mode 100644
index 0000000..5f43c47
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/composite.txt
@@ -0,0 +1,54 @@
+Binding for TI composite clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped composite clock with multiple different sub-types;
+
+a multiplexer clock with multiple input clock signals or parents, one
+of which can be selected as output, this behaves exactly as [2]
+
+an adjustable clock rate divider, this behaves exactly as [3]
+
+a gating function which can be used to enable and disable the output
+clock, this behaves exactly as [4]
+
+The binding must provide a list of the component clocks that shall be
+merged to this clock. The component clocks shall be of one of the
+"ti,*composite*-clock" types.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/mux.txt
+[3] Documentation/devicetree/bindings/clock/ti/divider.txt
+[4] Documentation/devicetree/bindings/clock/ti/gate.txt
+
+Required properties:
+- compatible : shall be: "ti,composite-clock"
+- clocks : link phandles of component clocks
+- #clock-cells : from common clock binding; shall be set to 0.
+
+Examples:
+
+usb_l4_gate_ick: usb_l4_gate_ick {
+	#clock-cells = <0>;
+	compatible = "ti,composite-interface-clock";
+	clocks = <&l4_ick>;
+	ti,bit-shift = <5>;
+	reg = <0x0a10>;
+};
+
+usb_l4_div_ick: usb_l4_div_ick {
+	#clock-cells = <0>;
+	compatible = "ti,composite-divider-clock";
+	clocks = <&l4_ick>;
+	ti,bit-shift = <4>;
+	ti,max-div = <1>;
+	reg = <0x0a40>;
+	ti,index-starts-at-one;
+};
+
+usb_l4_ick: usb_l4_ick {
+	#clock-cells = <0>;
+	compatible = "ti,composite-clock";
+	clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
+};
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b345f3e..6bd72b5 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -240,9 +240,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
 				   void __iomem **other_reg,
 				   u8 *other_bit);
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 533efb4..a4a7595 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
 ifneq ($(CONFIG_OF),)
-obj-y					+= clk.o dpll.o autoidle.o
+obj-y					+= clk.o dpll.o autoidle.o composite.o
 endif
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
new file mode 100644
index 0000000..6539b65
--- /dev/null
+++ b/drivers/clk/ti/composite.c
@@ -0,0 +1,269 @@
+/*
+ * TI composite clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+#include <linux/list.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
+					      unsigned long parent_rate)
+{
+	return clk_divider_ops.recalc_rate(hw, parent_rate);
+}
+
+static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+				    unsigned long *prate)
+{
+	return -EINVAL;
+}
+
+static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+				 unsigned long parent_rate)
+{
+	return -EINVAL;
+}
+
+static const struct clk_ops ti_composite_divider_ops = {
+	.recalc_rate	= &ti_composite_recalc_rate,
+	.round_rate	= &ti_composite_round_rate,
+	.set_rate	= &ti_composite_set_rate,
+};
+
+static const struct clk_ops ti_composite_gate_ops = {
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+struct component_clk {
+	int num_parents;
+	const char **parent_names;
+	struct device_node *node;
+	int type;
+	struct clk_hw *hw;
+	struct list_head link;
+};
+
+static const char * __initconst component_clk_types[] = {
+	"gate", "divider", "mux"
+};
+
+static LIST_HEAD(component_clks);
+
+static struct device_node *_get_component_node(struct device_node *node, int i)
+{
+	int rc;
+	struct of_phandle_args clkspec;
+
+	rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i,
+					&clkspec);
+	if (rc)
+		return NULL;
+
+	return clkspec.np;
+}
+
+static struct component_clk *_lookup_component(struct device_node *node)
+{
+	struct component_clk *comp;
+
+	list_for_each_entry(comp, &component_clks, link) {
+		if (comp->node == node)
+			return comp;
+	}
+	return NULL;
+}
+
+struct clk_hw_omap_comp {
+	struct clk_hw hw;
+	struct device_node *comp_nodes[CLK_COMPONENT_TYPE_MAX];
+	struct component_clk *comp_clks[CLK_COMPONENT_TYPE_MAX];
+};
+
+static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
+{
+	if (!clk)
+		return NULL;
+
+	if (!clk->comp_clks[idx])
+		return NULL;
+
+	return clk->comp_clks[idx]->hw;
+}
+
+#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
+
+static void __init ti_clk_register_composite(struct clk_hw *hw,
+					     struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
+	struct component_clk *comp;
+	int num_parents = 0;
+	const char **parent_names = NULL;
+	int i;
+
+	/* Check for presence of each component clock */
+	for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
+		if (!cclk->comp_nodes[i])
+			continue;
+
+		comp = _lookup_component(cclk->comp_nodes[i]);
+		if (!comp) {
+			pr_debug("component %s not ready for %s, retry\n",
+				 cclk->comp_nodes[i]->name, node->name);
+			if (!ti_clk_retry_init(node, hw,
+					       ti_clk_register_composite))
+				return;
+
+			goto cleanup;
+		}
+		if (cclk->comp_clks[comp->type] != NULL) {
+			pr_err("duplicate component types for %s (%s)!\n",
+			       node->name, component_clk_types[comp->type]);
+			goto cleanup;
+		}
+
+		cclk->comp_clks[comp->type] = comp;
+
+		/* Mark this node as found */
+		cclk->comp_nodes[i] = NULL;
+	}
+
+	/* All components exists, proceed with registration */
+	for (i = CLK_COMPONENT_TYPE_MAX - 1; i >= 0; i--) {
+		comp = cclk->comp_clks[i];
+		if (!comp)
+			continue;
+		if (comp->num_parents) {
+			num_parents = comp->num_parents;
+			parent_names = comp->parent_names;
+			break;
+		}
+	}
+
+	if (!num_parents) {
+		pr_err("%s: no parents found for %s!\n", __func__, node->name);
+		goto cleanup;
+	}
+
+	clk = clk_register_composite(NULL, node->name,
+				     parent_names, num_parents,
+				     _get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
+				     &clk_mux_ops,
+				     _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER),
+				     &ti_composite_divider_ops,
+				     _get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
+				     &ti_composite_gate_ops, 0);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+cleanup:
+	/* Free component clock list entries */
+	for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
+		if (!cclk->comp_clks[i])
+			continue;
+		list_del(&cclk->comp_clks[i]->link);
+		kfree(cclk->comp_clks[i]);
+	}
+
+	kfree(cclk);
+}
+
+static void __init of_ti_composite_clk_setup(struct device_node *node)
+{
+	int num_clks;
+	int i;
+	struct clk_hw_omap_comp *cclk;
+
+	/* Number of component clocks to be put inside this clock */
+	num_clks = of_clk_get_parent_count(node);
+
+	if (num_clks < 1) {
+		pr_err("composite clk %s must have component(s)\n", node->name);
+		return;
+	}
+
+	cclk = kzalloc(sizeof(*cclk), GFP_KERNEL);
+	if (!cclk)
+		return;
+
+	/* Get device node pointers for each component clock */
+	for (i = 0; i < num_clks; i++)
+		cclk->comp_nodes[i] = _get_component_node(node, i);
+
+	ti_clk_register_composite(&cclk->hw, node);
+}
+CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
+	       of_ti_composite_clk_setup);
+
+/**
+ * ti_clk_add_component - add a component clock to the pool
+ * @node: device node of the component clock
+ * @hw: hardware clock definition for the component clock
+ * @type: type of the component clock
+ *
+ * Adds a component clock to the list of available components, so that
+ * it can be registered by a composite clock.
+ */
+int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw,
+				int type)
+{
+	int num_parents;
+	const char **parent_names;
+	struct component_clk *clk;
+	int i;
+
+	num_parents = of_clk_get_parent_count(node);
+
+	if (num_parents < 1) {
+		pr_err("component-clock %s must have parent(s)\n", node->name);
+		return -EINVAL;
+	}
+
+	parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
+	if (!parent_names)
+		return -ENOMEM;
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+	if (!clk) {
+		kfree(parent_names);
+		return -ENOMEM;
+	}
+
+	clk->num_parents = num_parents;
+	clk->parent_names = parent_names;
+	clk->hw = hw;
+	clk->node = node;
+	clk->type = type;
+	list_add(&clk->link, &component_clks);
+
+	return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index ca38ee3..c8c591d 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -164,6 +164,14 @@ struct clk_hw_omap {
 /* DPLL Type and DCO Selection Flags */
 #define DPLL_J_TYPE		0x1
 
+/* Composite clock component types */
+enum {
+	CLK_COMPONENT_TYPE_GATE = 0,
+	CLK_COMPONENT_TYPE_DIVIDER,
+	CLK_COMPONENT_TYPE_MUX,
+	CLK_COMPONENT_TYPE_MAX,
+};
+
 /**
  * struct ti_dt_clk - OMAP DT clock alias declarations
  * @lk: clock lookup definition
@@ -236,6 +244,9 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 				    unsigned long parent_rate);
 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 			 unsigned long parent_rate);
+int omap2_dflt_clk_enable(struct clk_hw *hw);
+void omap2_dflt_clk_disable(struct clk_hw *hw);
+int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
 
 void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
@@ -243,6 +254,7 @@ void ti_dt_clk_init_provider(struct device_node *np, int index);
 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
 		      ti_of_clk_init_cb_t func);
 int of_ti_clk_autoidle_setup(struct device_node *node);
+int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
 
 #ifdef CONFIG_OF
 void of_ti_clk_allow_autoidle_all(void);
-- 
1.7.9.5

[PATCHv13 06/40] CLK: ti: add support for ti divider-clock

[Tero Kristo]

This patch adds support for TI divider clock binding, which simply uses
the basic clock divider to provide the features needed.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/divider.txt       |  114 +++++
 drivers/clk/ti/Makefile                            |    3 +-
 drivers/clk/ti/composite.c                         |    2 +-
 drivers/clk/ti/divider.c                           |  487 ++++++++++++++++++++
 include/linux/clk/ti.h                             |    2 +
 5 files changed, 606 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/divider.txt
 create mode 100644 drivers/clk/ti/divider.c

diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt b/Documentation/devicetree/bindings/clock/ti/divider.txt
new file mode 100644
index 0000000..35a6f5c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/divider.txt
@@ -0,0 +1,114 @@
+Binding for TI divider clock
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped adjustable clock rate divider that does not gate and has
+only one input clock or parent.  By default the value programmed into
+the register is one less than the actual divisor value.  E.g:
+
+register value		actual divisor value
+0			1
+1			2
+2			3
+
+This assumption may be modified by the following optional properties:
+
+ti,index-starts-at-one - valid divisor values start at 1, not the default
+of 0.  E.g:
+register value		actual divisor value
+1			1
+2			2
+3			3
+
+ti,index-power-of-two - valid divisor values are powers of two.  E.g:
+register value		actual divisor value
+0			1
+1			2
+2			4
+
+Additionally an array of valid dividers may be supplied like so:
+
+	ti,dividers = <4>, <8>, <0>, <16>;
+
+Which will map the resulting values to a divisor table by their index:
+register value		actual divisor value
+0			4
+1			8
+2			<invalid divisor, skipped>
+3			16
+
+Any zero value in this array means the corresponding bit-value is invalid
+and must not be used.
+
+The binding must also provide the register to control the divider and
+unless the divider array is provided, min and max dividers. Optionally
+the number of bits to shift that mask, if necessary. If the shift value
+is missing it is the same as supplying a zero shift.
+
+This binding can also optionally provide support to the hardware autoidle
+feature, see [2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
+
+Required properties:
+- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link to phandle of parent clock
+- reg : offset for register controlling adjustable divider
+
+Optional properties:
+- clock-output-names : from common clock binding.
+- ti,dividers : array of integers defining divisors
+- ti,bit-shift : number of bits to shift the divider value, defaults to 0
+- ti,min-div : min divisor for dividing the input clock rate, only
+  needed if the first divisor is offset from the default value (1)
+- ti,max-div : max divisor for dividing the input clock rate, only needed
+  if ti,dividers is not defined.
+- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
+  only valid if ti,dividers is not defined.
+- ti,index-power-of-two : valid divisor programming must be a power of two,
+  only valid if ti,dividers is not defined.
+- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
+  see [2]
+- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
+  see [2]
+- ti,set-rate-parent : clk_set_rate is propagated to parent
+
+Examples:
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,max-div = <127>;
+	reg = <0x190>;
+	ti,index-starts-at-one;
+};
+
+aess_fclk: aess_fclk@4a004528 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&abe_clk>;
+	ti,bit-shift = <24>;
+	reg = <0x528>;
+	ti,max-div = <2>;
+};
+
+dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
+	#clock-cells = <0>;
+	compatible = "ti,composite-divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,max-div = <31>;
+	reg = <0x0134>;
+	ti,index-starts-at-one;
+};
+
+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
+	#clock-cells = <0>;
+	compatible = "ti,composite-divider-clock";
+	clocks = <&corex2_fck>;
+	ti,bit-shift = <8>;
+	reg = <0x0a40>;
+	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index a4a7595..640ebf9 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,4 @@
 ifneq ($(CONFIG_OF),)
-obj-y					+= clk.o dpll.o autoidle.o composite.o
+obj-y					+= clk.o dpll.o autoidle.o divider.o \
+					   composite.o
 endif
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index 6539b65..ffb8db4 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -31,7 +31,7 @@
 static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
 					      unsigned long parent_rate)
 {
-	return clk_divider_ops.recalc_rate(hw, parent_rate);
+	return ti_clk_divider_ops.recalc_rate(hw, parent_rate);
 }
 
 static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
new file mode 100644
index 0000000..a15e445
--- /dev/null
+++ b/drivers/clk/ti/divider.c
@@ -0,0 +1,487 @@
+/*
+ * TI Divider Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+#define div_mask(d)	((1 << ((d)->width)) - 1)
+
+static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
+{
+	unsigned int maxdiv = 0;
+	const struct clk_div_table *clkt;
+
+	for (clkt = table; clkt->div; clkt++)
+		if (clkt->div > maxdiv)
+			maxdiv = clkt->div;
+	return maxdiv;
+}
+
+static unsigned int _get_maxdiv(struct clk_divider *divider)
+{
+	if (divider->flags & CLK_DIVIDER_ONE_BASED)
+		return div_mask(divider);
+	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+		return 1 << div_mask(divider);
+	if (divider->table)
+		return _get_table_maxdiv(divider->table);
+	return div_mask(divider) + 1;
+}
+
+static unsigned int _get_table_div(const struct clk_div_table *table,
+				   unsigned int val)
+{
+	const struct clk_div_table *clkt;
+
+	for (clkt = table; clkt->div; clkt++)
+		if (clkt->val == val)
+			return clkt->div;
+	return 0;
+}
+
+static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
+{
+	if (divider->flags & CLK_DIVIDER_ONE_BASED)
+		return val;
+	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+		return 1 << val;
+	if (divider->table)
+		return _get_table_div(divider->table, val);
+	return val + 1;
+}
+
+static unsigned int _get_table_val(const struct clk_div_table *table,
+				   unsigned int div)
+{
+	const struct clk_div_table *clkt;
+
+	for (clkt = table; clkt->div; clkt++)
+		if (clkt->div == div)
+			return clkt->val;
+	return 0;
+}
+
+static unsigned int _get_val(struct clk_divider *divider, u8 div)
+{
+	if (divider->flags & CLK_DIVIDER_ONE_BASED)
+		return div;
+	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+		return __ffs(div);
+	if (divider->table)
+		return  _get_table_val(divider->table, div);
+	return div - 1;
+}
+
+static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
+						unsigned long parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	unsigned int div, val;
+
+	val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
+	val &= div_mask(divider);
+
+	div = _get_div(divider, val);
+	if (!div) {
+		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
+		     "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
+		     __clk_get_name(hw->clk));
+		return parent_rate;
+	}
+
+	return parent_rate / div;
+}
+
+/*
+ * The reverse of DIV_ROUND_UP: The maximum number which
+ * divided by m is r
+ */
+#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
+
+static bool _is_valid_table_div(const struct clk_div_table *table,
+				unsigned int div)
+{
+	const struct clk_div_table *clkt;
+
+	for (clkt = table; clkt->div; clkt++)
+		if (clkt->div == div)
+			return true;
+	return false;
+}
+
+static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
+{
+	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+		return is_power_of_2(div);
+	if (divider->table)
+		return _is_valid_table_div(divider->table, div);
+	return true;
+}
+
+static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+				  unsigned long *best_parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	int i, bestdiv = 0;
+	unsigned long parent_rate, best = 0, now, maxdiv;
+	unsigned long parent_rate_saved = *best_parent_rate;
+
+	if (!rate)
+		rate = 1;
+
+	maxdiv = _get_maxdiv(divider);
+
+	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
+		parent_rate = *best_parent_rate;
+		bestdiv = DIV_ROUND_UP(parent_rate, rate);
+		bestdiv = bestdiv == 0 ? 1 : bestdiv;
+		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+		return bestdiv;
+	}
+
+	/*
+	 * The maximum divider we can use without overflowing
+	 * unsigned long in rate * i below
+	 */
+	maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+	for (i = 1; i <= maxdiv; i++) {
+		if (!_is_valid_div(divider, i))
+			continue;
+		if (rate * i == parent_rate_saved) {
+			/*
+			 * It's the most ideal case if the requested rate can be
+			 * divided from parent clock without needing to change
+			 * parent rate, so return the divider immediately.
+			 */
+			*best_parent_rate = parent_rate_saved;
+			return i;
+		}
+		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+				MULT_ROUND_UP(rate, i));
+		now = parent_rate / i;
+		if (now <= rate && now > best) {
+			bestdiv = i;
+			best = now;
+			*best_parent_rate = parent_rate;
+		}
+	}
+
+	if (!bestdiv) {
+		bestdiv = _get_maxdiv(divider);
+		*best_parent_rate =
+			__clk_round_rate(__clk_get_parent(hw->clk), 1);
+	}
+
+	return bestdiv;
+}
+
+static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+				      unsigned long *prate)
+{
+	int div;
+	div = ti_clk_divider_bestdiv(hw, rate, prate);
+
+	return *prate / div;
+}
+
+static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+				   unsigned long parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	unsigned int div, value;
+	unsigned long flags = 0;
+	u32 val;
+
+	div = parent_rate / rate;
+	value = _get_val(divider, div);
+
+	if (value > div_mask(divider))
+		value = div_mask(divider);
+
+	if (divider->lock)
+		spin_lock_irqsave(divider->lock, flags);
+
+	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+		val = div_mask(divider) << (divider->shift + 16);
+	} else {
+		val = ti_clk_ll_ops->clk_readl(divider->reg);
+		val &= ~(div_mask(divider) << divider->shift);
+	}
+	val |= value << divider->shift;
+	ti_clk_ll_ops->clk_writel(val, divider->reg);
+
+	if (divider->lock)
+		spin_unlock_irqrestore(divider->lock, flags);
+
+	return 0;
+}
+
+const struct clk_ops ti_clk_divider_ops = {
+	.recalc_rate = ti_clk_divider_recalc_rate,
+	.round_rate = ti_clk_divider_round_rate,
+	.set_rate = ti_clk_divider_set_rate,
+};
+
+static struct clk *_register_divider(struct device *dev, const char *name,
+				     const char *parent_name,
+				     unsigned long flags, void __iomem *reg,
+				     u8 shift, u8 width, u8 clk_divider_flags,
+				     const struct clk_div_table *table,
+				     spinlock_t *lock)
+{
+	struct clk_divider *div;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
+		if (width + shift > 16) {
+			pr_warn("divider value exceeds LOWORD field\n");
+			return ERR_PTR(-EINVAL);
+		}
+	}
+
+	/* allocate the divider */
+	div = kzalloc(sizeof(*div), GFP_KERNEL);
+	if (!div) {
+		pr_err("%s: could not allocate divider clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &ti_clk_divider_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	/* struct clk_divider assignments */
+	div->reg = reg;
+	div->shift = shift;
+	div->width = width;
+	div->flags = clk_divider_flags;
+	div->lock = lock;
+	div->hw.init = &init;
+	div->table = table;
+
+	/* register the clock */
+	clk = clk_register(dev, &div->hw);
+
+	if (IS_ERR(clk))
+		kfree(div);
+
+	return clk;
+}
+
+static struct clk_div_table
+__init *ti_clk_get_div_table(struct device_node *node)
+{
+	struct clk_div_table *table;
+	const __be32 *divspec;
+	u32 val;
+	u32 num_div;
+	u32 valid_div;
+	int i;
+
+	divspec = of_get_property(node, "ti,dividers", &num_div);
+
+	if (!divspec)
+		return NULL;
+
+	num_div /= 4;
+
+	valid_div = 0;
+
+	/* Determine required size for divider table */
+	for (i = 0; i < num_div; i++) {
+		of_property_read_u32_index(node, "ti,dividers", i, &val);
+		if (val)
+			valid_div++;
+	}
+
+	if (!valid_div) {
+		pr_err("no valid dividers for %s table\n", node->name);
+		return ERR_PTR(-EINVAL);
+	}
+
+	table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
+
+	if (!table)
+		return ERR_PTR(-ENOMEM);
+
+	valid_div = 0;
+
+	for (i = 0; i < num_div; i++) {
+		of_property_read_u32_index(node, "ti,dividers", i, &val);
+		if (val) {
+			table[valid_div].div = val;
+			table[valid_div].val = i;
+			valid_div++;
+		}
+	}
+
+	return table;
+}
+
+static int _get_divider_width(struct device_node *node,
+			      const struct clk_div_table *table,
+			      u8 flags)
+{
+	u32 min_div;
+	u32 max_div;
+	u32 val = 0;
+	u32 div;
+
+	if (!table) {
+		/* Clk divider table not provided, determine min/max divs */
+		if (of_property_read_u32(node, "ti,min-div", &min_div))
+			min_div = 1;
+
+		if (of_property_read_u32(node, "ti,max-div", &max_div)) {
+			pr_err("no max-div for %s!\n", node->name);
+			return -EINVAL;
+		}
+
+		/* Determine bit width for the field */
+		if (flags & CLK_DIVIDER_ONE_BASED)
+			val = 1;
+
+		div = min_div;
+
+		while (div < max_div) {
+			if (flags & CLK_DIVIDER_POWER_OF_TWO)
+				div <<= 1;
+			else
+				div++;
+			val++;
+		}
+	} else {
+		div = 0;
+
+		while (table[div].div) {
+			val = table[div].val;
+			div++;
+		}
+	}
+
+	return fls(val);
+}
+
+static int __init ti_clk_divider_populate(struct device_node *node,
+	void __iomem **reg, const struct clk_div_table **table,
+	u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
+{
+	u32 val;
+
+	*reg = ti_clk_get_reg_addr(node, 0);
+	if (!*reg)
+		return -EINVAL;
+
+	if (!of_property_read_u32(node, "ti,bit-shift", &val))
+		*shift = val;
+	else
+		*shift = 0;
+
+	*flags = 0;
+	*div_flags = 0;
+
+	if (of_property_read_bool(node, "ti,index-starts-at-one"))
+		*div_flags |= CLK_DIVIDER_ONE_BASED;
+
+	if (of_property_read_bool(node, "ti,index-power-of-two"))
+		*div_flags |= CLK_DIVIDER_POWER_OF_TWO;
+
+	if (of_property_read_bool(node, "ti,set-rate-parent"))
+		*flags |= CLK_SET_RATE_PARENT;
+
+	*table = ti_clk_get_div_table(node);
+
+	if (IS_ERR(*table))
+		return PTR_ERR(*table);
+
+	*width = _get_divider_width(node, *table, *div_flags);
+
+	return 0;
+}
+
+/**
+ * of_ti_divider_clk_setup - Setup function for simple div rate clock
+ * @node: device node for this clock
+ *
+ * Sets up a basic divider clock.
+ */
+static void __init of_ti_divider_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *parent_name;
+	void __iomem *reg;
+	u8 clk_divider_flags = 0;
+	u8 width = 0;
+	u8 shift = 0;
+	const struct clk_div_table *table = NULL;
+	u32 flags = 0;
+
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	if (ti_clk_divider_populate(node, &reg, &table, &flags,
+				    &clk_divider_flags, &width, &shift))
+		goto cleanup;
+
+	clk = _register_divider(NULL, node->name, parent_name, flags, reg,
+				shift, width, clk_divider_flags, table, NULL);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		of_ti_clk_autoidle_setup(node);
+		return;
+	}
+
+cleanup:
+	kfree(table);
+}
+CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
+
+static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
+{
+	struct clk_divider *div;
+	u32 val;
+
+	div = kzalloc(sizeof(*div), GFP_KERNEL);
+	if (!div)
+		return;
+
+	if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
+				    &div->flags, &div->width, &div->shift) < 0)
+		goto cleanup;
+
+	if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
+		return;
+
+cleanup:
+	kfree(div->table);
+	kfree(div);
+}
+CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
+	       of_ti_composite_divider_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index c8c591d..17fb49e 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -223,6 +223,8 @@ struct ti_clk_ll_ops {
 
 extern struct ti_clk_ll_ops *ti_clk_ll_ops;
 
+extern const struct clk_ops ti_clk_divider_ops;
+
 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
-- 
1.7.9.5

[PATCHv13 07/40] clk: ti: add support for TI fixed factor clock

[Tero Kristo]

This behaves exactly in similar manner to basic fixed-factor-clock, but
adds a few properties on top for handling clock hardware autoidling.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../bindings/clock/ti/fixed-factor-clock.txt       |   43 +++++++++++++
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/fixed-factor.c                      |   66 ++++++++++++++++++++
 3 files changed, 110 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
 create mode 100644 drivers/clk/ti/fixed-factor.c

diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
new file mode 100644
index 0000000..662b36d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
@@ -0,0 +1,43 @@
+Binding for TI fixed factor rate clock sources.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1], and also uses the autoidle
+support from TI autoidle clock [2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
+
+Required properties:
+- compatible : shall be "ti,fixed-factor-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- ti,clock-div: fixed divider.
+- ti,clock-mult: fixed multiplier.
+- clocks: parent clock.
+
+Optional properties:
+- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
+  see [2]
+- reg: offset for the autoidle register of this clock, see [2]
+- ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2]
+- ti,set-rate-parent: clk_set_rate is propagated to parent
+
+Example:
+	clock {
+		compatible = "ti,fixed-factor-clock";
+		clocks = <&parentclk>;
+		#clock-cells = <0>;
+		ti,clock-div = <2>;
+		ti,clock-mult = <1>;
+	};
+
+	dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+		#clock-cells = <0>;
+		compatible = "ti,fixed-factor-clock";
+		clocks = <&dpll_usb_ck>;
+		ti,clock-div = <1>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01b4>;
+		ti,clock-mult = <1>;
+		ti,invert-autoidle-bit;
+	};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 640ebf9..f57fc4b 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o divider.o \
-					   composite.o
+					   fixed-factor.o composite.o
 endif
diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c
new file mode 100644
index 0000000..c2c8a28
--- /dev/null
+++ b/drivers/clk/ti/fixed-factor.c
@@ -0,0 +1,66 @@
+/*
+ * TI Fixed Factor Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+/**
+ * of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock
+ * @node: device node for this clock
+ *
+ * Sets up a simple fixed factor clock based on device tree info.
+ */
+static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	u32 div, mult;
+	u32 flags = 0;
+
+	if (of_property_read_u32(node, "ti,clock-div", &div)) {
+		pr_err("%s must have a clock-div property\n", node->name);
+		return;
+	}
+
+	if (of_property_read_u32(node, "ti,clock-mult", &mult)) {
+		pr_err("%s must have a clock-mult property\n", node->name);
+		return;
+	}
+
+	if (of_property_read_bool(node, "ti,set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
+					mult, div);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		of_ti_clk_autoidle_setup(node);
+	}
+}
+CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock",
+	       of_ti_fixed_factor_clk_setup);
-- 
1.7.9.5

[PATCHv13 09/40] CLK: TI: add support for clockdomain binding

[Tero Kristo]

Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks. Clockdomain
itself is rather misleading name for the hardware functionality, as at
least on OMAP4 / OMAP5 / DRA7 the clockdomains can be collections of either
clocks and/or IP blocks, thus idle-domain or such might be more appropriate.
For most cases on these SoCs, the kernel doesn't even need the information
and the mappings can be ignored.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/clockdomain.txt   |   24 +++++++
 drivers/clk/ti/Makefile                            |    3 +-
 drivers/clk/ti/clockdomain.c                       |   70 ++++++++++++++++++++
 include/linux/clk/ti.h                             |    1 +
 4 files changed, 97 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/clockdomain.txt
 create mode 100644 drivers/clk/ti/clockdomain.c

diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
new file mode 100644
index 0000000..cb76b3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
@@ -0,0 +1,24 @@
+Binding for Texas Instruments clockdomain.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1] in consumer role.
+Every clock on TI SoC belongs to one clockdomain, but software
+only needs this information for specific clocks which require
+their parent clockdomain to be controlled when the clock is
+enabled/disabled. This binding doesn't define a new clock
+binding type, it is used to group existing clock nodes under
+hardware hierarchy.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,clockdomain"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of clocks within this domain
+
+Examples:
+	dss_clkdm: dss_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+	};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 7cba389..67056fb 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,5 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o divider.o \
-					   fixed-factor.o gate.o composite.o
+					   fixed-factor.o gate.o clockdomain.o \
+					   composite.o
 endif
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
new file mode 100644
index 0000000..f1e0038
--- /dev/null
+++ b/drivers/clk/ti/clockdomain.c
@@ -0,0 +1,70 @@
+/*
+ * OMAP clockdomain support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+static void __init of_ti_clockdomain_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_hw *clk_hw;
+	const char *clkdm_name = node->name;
+	int i;
+	int num_clks;
+
+	num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells");
+
+	for (i = 0; i < num_clks; i++) {
+		clk = of_clk_get(node, i);
+		if (__clk_get_flags(clk) & CLK_IS_BASIC) {
+			pr_warn("can't setup clkdm for basic clk %s\n",
+				__clk_get_name(clk));
+			continue;
+		}
+		clk_hw = __clk_get_hw(clk);
+		to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
+		omap2_init_clk_clkdm(clk_hw);
+	}
+}
+
+static struct of_device_id ti_clkdm_match_table[] __initdata = {
+	{ .compatible = "ti,clockdomain" },
+	{ }
+};
+
+/**
+ * ti_dt_clockdomains_setup - setup device tree clockdomains
+ *
+ * Initializes clockdomain nodes for a SoC. This parses through all the
+ * nodes with compatible = "ti,clockdomain", and add the clockdomain
+ * info for all the clocks listed under these. This function shall be
+ * called after rest of the DT clock init has completed and all
+ * clock nodes have been registered.
+ */
+void __init ti_dt_clockdomains_setup(void)
+{
+	struct device_node *np;
+	for_each_matching_node(np, ti_clkdm_match_table) {
+		of_ti_clockdomain_setup(np);
+	}
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index d94feb3..a3f89a6 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -255,6 +255,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
 void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
 void ti_dt_clk_init_provider(struct device_node *np, int index);
+void ti_dt_clockdomains_setup(void);
 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
 		      ti_of_clk_init_cb_t func);
 int of_ti_clk_autoidle_setup(struct device_node *node);
-- 
1.7.9.5

[PATCHv13 10/40] clk: ti: add support for basic mux clock

[Tero Kristo]

ti,mux-clock provides now a binding for basic mux support. This is just
using the basic clock type.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 Documentation/devicetree/bindings/clock/ti/mux.txt |   76 ++++++
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/composite.c                         |    2 +-
 drivers/clk/ti/mux.c                               |  246 ++++++++++++++++++++
 include/linux/clk/ti.h                             |    1 +
 5 files changed, 325 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/mux.txt
 create mode 100644 drivers/clk/ti/mux.c

diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt
new file mode 100644
index 0000000..2d0d170
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/mux.txt
@@ -0,0 +1,76 @@
+Binding for TI mux clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped multiplexer with multiple input clock signals or
+parents, one of which can be selected as output.  This clock does not
+gate or adjust the parent rate via a divider or multiplier.
+
+By default the "clocks" property lists the parents in the same order
+as they are programmed into the regster.  E.g:
+
+	clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
+
+results in programming the register as follows:
+
+register value		selected parent clock
+0			foo_clock
+1			bar_clock
+2			baz_clock
+
+Some clock controller IPs do not allow a value of zero to be programmed
+into the register, instead indexing begins at 1.  The optional property
+"index-starts-at-one" modified the scheme as follows:
+
+register value		selected clock parent
+1			foo_clock
+2			bar_clock
+3			baz_clock
+
+The binding must provide the register to control the mux. Optionally
+the number of bits to shift the control field in the register can be
+supplied. If the shift value is missing it is the same as supplying
+a zero shift.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks
+- reg : register offset for register controlling adjustable mux
+
+Optional properties:
+- ti,bit-shift : number of bits to shift the bit-mask, defaults to
+  0 if not present
+- ti,index-starts-at-one : valid input select programming starts at 1, not
+  zero
+- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
+  not supported by the composite-mux-clock subtype
+
+Examples:
+
+sys_clkin_ck: sys_clkin_ck@4a306110 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x0110>;
+	ti,index-starts-at-one;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x0108>;
+};
+
+mcbsp5_mux_fck: mcbsp5_mux_fck {
+	#clock-cells = <0>;
+	compatible = "ti,composite-mux-clock";
+	clocks = <&core_96m_fck>, <&mcbsp_clks>;
+	ti,bit-shift = <4>;
+	reg = <0x02d8>;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 67056fb..ef61d39 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,5 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o divider.o \
 					   fixed-factor.o gate.o clockdomain.o \
-					   composite.o
+					   composite.o mux.o
 endif
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index ffb8db4..19d8980 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -173,7 +173,7 @@ static void __init ti_clk_register_composite(struct clk_hw *hw,
 	clk = clk_register_composite(NULL, node->name,
 				     parent_names, num_parents,
 				     _get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
-				     &clk_mux_ops,
+				     &ti_clk_mux_ops,
 				     _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER),
 				     &ti_composite_divider_ops,
 				     _get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
new file mode 100644
index 0000000..0197a47
--- /dev/null
+++ b/drivers/clk/ti/mux.c
@@ -0,0 +1,246 @@
+/*
+ * TI Multiplexer Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
+
+static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	int num_parents = __clk_get_num_parents(hw->clk);
+	u32 val;
+
+	/*
+	 * FIXME need a mux-specific flag to determine if val is bitwise or
+	 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
+	 * from 0x1 to 0x7 (index starts at one)
+	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
+	 * val = 0x4 really means "bit 2, index starts at bit 0"
+	 */
+	val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift;
+	val &= mux->mask;
+
+	if (mux->table) {
+		int i;
+
+		for (i = 0; i < num_parents; i++)
+			if (mux->table[i] == val)
+				return i;
+		return -EINVAL;
+	}
+
+	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
+		val = ffs(val) - 1;
+
+	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
+		val--;
+
+	if (val >= num_parents)
+		return -EINVAL;
+
+	return val;
+}
+
+static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val;
+	unsigned long flags = 0;
+
+	if (mux->table) {
+		index = mux->table[index];
+	} else {
+		if (mux->flags & CLK_MUX_INDEX_BIT)
+			index = (1 << ffs(index));
+
+		if (mux->flags & CLK_MUX_INDEX_ONE)
+			index++;
+	}
+
+	if (mux->lock)
+		spin_lock_irqsave(mux->lock, flags);
+
+	if (mux->flags & CLK_MUX_HIWORD_MASK) {
+		val = mux->mask << (mux->shift + 16);
+	} else {
+		val = ti_clk_ll_ops->clk_readl(mux->reg);
+		val &= ~(mux->mask << mux->shift);
+	}
+	val |= index << mux->shift;
+	ti_clk_ll_ops->clk_writel(val, mux->reg);
+
+	if (mux->lock)
+		spin_unlock_irqrestore(mux->lock, flags);
+
+	return 0;
+}
+
+const struct clk_ops ti_clk_mux_ops = {
+	.get_parent = ti_clk_mux_get_parent,
+	.set_parent = ti_clk_mux_set_parent,
+	.determine_rate = __clk_mux_determine_rate,
+};
+
+static struct clk *_register_mux(struct device *dev, const char *name,
+				 const char **parent_names, u8 num_parents,
+				 unsigned long flags, void __iomem *reg,
+				 u8 shift, u32 mask, u8 clk_mux_flags,
+				 u32 *table, spinlock_t *lock)
+{
+	struct clk_mux *mux;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the mux */
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux) {
+		pr_err("%s: could not allocate mux clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &ti_clk_mux_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	/* struct clk_mux assignments */
+	mux->reg = reg;
+	mux->shift = shift;
+	mux->mask = mask;
+	mux->flags = clk_mux_flags;
+	mux->lock = lock;
+	mux->table = table;
+	mux->hw.init = &init;
+
+	clk = clk_register(dev, &mux->hw);
+
+	if (IS_ERR(clk))
+		kfree(mux);
+
+	return clk;
+}
+
+/**
+ * of_mux_clk_setup - Setup function for simple mux rate clock
+ * @node: DT node for the clock
+ *
+ * Sets up a basic clock multiplexer.
+ */
+static void of_mux_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	void __iomem *reg;
+	int num_parents;
+	const char **parent_names;
+	int i;
+	u8 clk_mux_flags = 0;
+	u32 mask = 0;
+	u32 shift = 0;
+	u32 flags = 0;
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 2) {
+		pr_err("mux-clock %s must have parents\n", node->name);
+		return;
+	}
+	parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
+	if (!parent_names)
+		goto cleanup;
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	reg = ti_clk_get_reg_addr(node, 0);
+
+	if (!reg)
+		goto cleanup;
+
+	of_property_read_u32(node, "ti,bit-shift", &shift);
+
+	if (of_property_read_bool(node, "ti,index-starts-at-one"))
+		clk_mux_flags |= CLK_MUX_INDEX_ONE;
+
+	if (of_property_read_bool(node, "ti,set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
+	/* Generate bit-mask based on parent info */
+	mask = num_parents;
+	if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
+		mask--;
+
+	mask = (1 << fls(mask)) - 1;
+
+	clk = _register_mux(NULL, node->name, parent_names, num_parents, flags,
+			    reg, shift, mask, clk_mux_flags, NULL, NULL);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+cleanup:
+	kfree(parent_names);
+}
+CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
+
+static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
+{
+	struct clk_mux *mux;
+	int num_parents;
+	u32 val;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		return;
+
+	mux->reg = ti_clk_get_reg_addr(node, 0);
+
+	if (!mux->reg)
+		goto cleanup;
+
+	if (!of_property_read_u32(node, "ti,bit-shift", &val))
+		mux->shift = val;
+
+	if (of_property_read_bool(node, "ti,index-starts-at-one"))
+		mux->flags |= CLK_MUX_INDEX_ONE;
+
+	num_parents = of_clk_get_parent_count(node);
+
+	if (num_parents < 2) {
+		pr_err("%s must have parents\n", node->name);
+		goto cleanup;
+	}
+
+	mux->mask = num_parents - 1;
+	mux->mask = (1 << fls(mux->mask)) - 1;
+
+	if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
+		return;
+
+cleanup:
+	kfree(mux);
+}
+CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
+	       of_ti_composite_mux_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index a3f89a6..6e205b1 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -224,6 +224,7 @@ struct ti_clk_ll_ops {
 extern struct ti_clk_ll_ops *ti_clk_ll_ops;
 
 extern const struct clk_ops ti_clk_divider_ops;
+extern const struct clk_ops ti_clk_mux_ops;
 
 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
-- 
1.7.9.5

[PATCHv13 11/40] CLK: TI: add omap4 clock init file

[Tero Kristo]

clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/clock.h |    1 -
 drivers/clk/ti/Makefile     |    1 +
 drivers/clk/ti/clk-44xx.c   |  316 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h      |    3 +
 4 files changed, 320 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk-44xx.c

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 6bd72b5..b83fca6 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 				void __iomem **idlest_reg,
 				u8 *idlest_bit, u8 *idlest_val);
 int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
 int omap2_clk_allow_idle(struct clk *clk);
 int omap2_clk_deny_idle(struct clk *clk);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index ef61d39..381f1f8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,4 +2,5 @@ ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o divider.o \
 					   fixed-factor.o gate.o clockdomain.o \
 					   composite.o mux.o
+obj-$(CONFIG_ARCH_OMAP4)		+= clk-44xx.o
 endif
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
new file mode 100644
index 0000000..ae00218
--- /dev/null
+++ b/drivers/clk/ti/clk-44xx.c
@@ -0,0 +1,316 @@
+/*
+ * OMAP4 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+/*
+ * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
+ * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
+ * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
+ * half of this value.
+ */
+#define OMAP4_DPLL_ABE_DEFFREQ				98304000
+
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ				960000000
+
+static struct ti_dt_clk omap44xx_clks[] = {
+	DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
+	DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
+	DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
+	DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
+	DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+	DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
+	DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
+	DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+	DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+	DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+	DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+	DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+	DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+	DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+	DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+	DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+	DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
+	DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
+	DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
+	DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
+	DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
+	DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"),
+	DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
+	DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+	DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+	DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+	DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+	DT_CLK(NULL, "abe_clk", "abe_clk"),
+	DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+	DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+	DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
+	DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+	DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+	DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
+	DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
+	DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+	DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"),
+	DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"),
+	DT_CLK(NULL, "div_core_ck", "div_core_ck"),
+	DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"),
+	DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"),
+	DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"),
+	DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"),
+	DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
+	DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
+	DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"),
+	DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"),
+	DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+	DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
+	DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"),
+	DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"),
+	DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+	DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+	DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"),
+	DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"),
+	DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+	DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+	DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+	DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+	DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
+	DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"),
+	DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"),
+	DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"),
+	DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"),
+	DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"),
+	DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+	DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"),
+	DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+	DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"),
+	DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+	DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+	DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"),
+	DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+	DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"),
+	DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"),
+	DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+	DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"),
+	DT_CLK(NULL, "l3_div_ck", "l3_div_ck"),
+	DT_CLK(NULL, "l4_div_ck", "l4_div_ck"),
+	DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"),
+	DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"),
+	DT_CLK("smp_twd", NULL, "mpu_periphclk"),
+	DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"),
+	DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"),
+	DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"),
+	DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"),
+	DT_CLK(NULL, "aes1_fck", "aes1_fck"),
+	DT_CLK(NULL, "aes2_fck", "aes2_fck"),
+	DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
+	DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"),
+	DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
+	DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"),
+	DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+	DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+	DT_CLK(NULL, "dss_fck", "dss_fck"),
+	DT_CLK("omapdss_dss", "ick", "dss_fck"),
+	DT_CLK(NULL, "fdif_fck", "fdif_fck"),
+	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+	DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+	DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+	DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+	DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+	DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+	DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"),
+	DT_CLK(NULL, "hsi_fck", "hsi_fck"),
+	DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
+	DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
+	DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"),
+	DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
+	DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"),
+	DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
+	DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"),
+	DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
+	DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"),
+	DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"),
+	DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"),
+	DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"),
+	DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"),
+	DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"),
+	DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"),
+	DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"),
+	DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"),
+	DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"),
+	DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
+	DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"),
+	DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"),
+	DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"),
+	DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
+	DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
+	DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
+	DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
+	DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
+	DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
+	DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
+	DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
+	DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
+	DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
+	DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
+	DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
+	DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
+	DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
+	DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
+	DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
+	DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
+	DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
+	DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
+	DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
+	DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
+	DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
+	DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"),
+	DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"),
+	DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
+	DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"),
+	DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"),
+	DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"),
+	DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
+	DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
+	DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"),
+	DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
+	DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
+	DT_CLK(NULL, "usim_ck", "usim_ck"),
+	DT_CLK(NULL, "usim_fclk", "usim_fclk"),
+	DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"),
+	DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"),
+	DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
+	DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
+	DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
+	DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
+	DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
+	DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
+	DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
+	DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
+	DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
+	DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
+	DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
+	DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
+	DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
+	DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
+	DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"),
+	DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"),
+	DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"),
+	DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"),
+	DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"),
+	DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"),
+	DT_CLK("50000000.gpmc", "fck", "dummy_ck"),
+	DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
+	DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
+	DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
+	DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
+	DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
+	DT_CLK(NULL, "uart1_ick", "dummy_ck"),
+	DT_CLK(NULL, "uart2_ick", "dummy_ck"),
+	DT_CLK(NULL, "uart3_ick", "dummy_ck"),
+	DT_CLK(NULL, "uart4_ick", "dummy_ck"),
+	DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
+	DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
+	DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
+	DT_CLK("omap_wdt", "ick", "dummy_ck"),
+	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+	DT_CLK("omap_timer.1", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("omap_timer.2", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("omap_timer.3", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("omap_timer.4", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("omap_timer.9", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("omap_timer.10", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("omap_timer.11", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("omap_timer.5", "timer_sys_ck", "syc_clk_div_ck"),
+	DT_CLK("omap_timer.6", "timer_sys_ck", "syc_clk_div_ck"),
+	DT_CLK("omap_timer.7", "timer_sys_ck", "syc_clk_div_ck"),
+	DT_CLK("omap_timer.8", "timer_sys_ck", "syc_clk_div_ck"),
+	DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+	DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+	DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+	DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+	DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
+	DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"),
+	DT_CLK(NULL, "div_ts_ck", "div_ts_ck"),
+	DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
+	{ .node_name = NULL },
+};
+
+int __init omap4xxx_dt_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
+
+	ti_dt_clocks_register(omap44xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	/*
+	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+	 * domain can transition to retention state when not in use.
+	 */
+	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+	rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+	/*
+	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
+	 * state when turning the ABE clock domain. Workaround this by
+	 * locking the ABE DPLL on boot.
+	 * Lock the ABE DPLL in any case to avoid issues with audio.
+	 */
+	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
+	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+	if (!rc)
+		rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 6e205b1..a56ff12 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -247,6 +247,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 				    unsigned long parent_rate);
 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+int omap2_clk_disable_autoidle_all(void);
 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 			 unsigned long parent_rate);
 int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -262,6 +263,8 @@ int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
 int of_ti_clk_autoidle_setup(struct device_node *node);
 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
 
+int omap4xxx_dt_clk_init(void);
+
 #ifdef CONFIG_OF
 void of_ti_clk_allow_autoidle_all(void);
 void of_ti_clk_deny_autoidle_all(void);
-- 
1.7.9.5

[PATCHv13 12/40] CLK: TI: add omap5 clock init file

[Tero Kristo]

clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/io.c  |    1 +
 drivers/clk/ti/Makefile   |    1 +
 drivers/clk/ti/clk-54xx.c |  239 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h    |    1 +
 4 files changed, 242 insertions(+)
 create mode 100644 drivers/clk/ti/clk-54xx.c

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index cd22262..3d9b3fc 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -666,6 +666,7 @@ void __init omap5_init_early(void)
 	omap54xx_clockdomains_init();
 	omap54xx_hwmod_init();
 	omap_hwmod_init_postsetup();
+	omap_clk_init = omap5xxx_dt_clk_init;
 }
 
 void __init omap5_init_late(void)
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 381f1f8..935e5d2 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,4 +3,5 @@ obj-y					+= clk.o dpll.o autoidle.o divider.o \
 					   fixed-factor.o gate.o clockdomain.o \
 					   composite.o mux.o
 obj-$(CONFIG_ARCH_OMAP4)		+= clk-44xx.o
+obj-$(CONFIG_SOC_OMAP5)			+= clk-54xx.o
 endif
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
new file mode 100644
index 0000000..c876e6e
--- /dev/null
+++ b/drivers/clk/ti/clk-54xx.c
@@ -0,0 +1,239 @@
+/*
+ * OMAP5 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/ti.h>
+
+#define OMAP5_DPLL_ABE_DEFFREQ				98304000
+
+static struct ti_dt_clk omap54xx_clks[] = {
+	DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
+	DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
+	DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+	DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
+	DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
+	DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+	DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+	DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+	DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+	DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+	DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+	DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+	DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+	DT_CLK(NULL, "sys_clkin", "sys_clkin"),
+	DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
+	DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
+	DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
+	DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
+	DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+	DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+	DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+	DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+	DT_CLK(NULL, "abe_clk", "abe_clk"),
+	DT_CLK(NULL, "abe_iclk", "abe_iclk"),
+	DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
+	DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+	DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+	DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+	DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"),
+	DT_CLK(NULL, "c2c_fclk", "c2c_fclk"),
+	DT_CLK(NULL, "c2c_iclk", "c2c_iclk"),
+	DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
+	DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"),
+	DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
+	DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
+	DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
+	DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
+	DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
+	DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
+	DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+	DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
+	DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
+	DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+	DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
+	DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"),
+	DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"),
+	DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
+	DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+	DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+	DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
+	DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+	DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+	DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
+	DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
+	DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
+	DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+	DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+	DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
+	DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"),
+	DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"),
+	DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"),
+	DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"),
+	DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"),
+	DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"),
+	DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
+	DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+	DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
+	DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+	DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"),
+	DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
+	DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+	DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+	DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+	DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+	DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
+	DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"),
+	DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
+	DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
+	DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
+	DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
+	DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
+	DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+	DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+	DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
+	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+	DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+	DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+	DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+	DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+	DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+	DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
+	DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
+	DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
+	DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"),
+	DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"),
+	DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"),
+	DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
+	DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
+	DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
+	DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
+	DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"),
+	DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
+	DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
+	DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
+	DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"),
+	DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
+	DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+	DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
+	DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"),
+	DT_CLK(NULL, "fdif_fclk", "fdif_fclk"),
+	DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
+	DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
+	DT_CLK(NULL, "hsi_fclk", "hsi_fclk"),
+	DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
+	DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"),
+	DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
+	DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"),
+	DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
+	DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"),
+	DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
+	DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"),
+	DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
+	DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"),
+	DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
+	DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"),
+	DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
+	DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
+	DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
+	DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
+	DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
+	DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
+	DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
+	DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
+	DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
+	DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
+	DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
+	DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
+	DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
+	DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
+	DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
+	DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
+	DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
+	DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
+	DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
+	DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
+	DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
+	DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
+	DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
+	DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
+	DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
+	DT_CLK(NULL, "gpmc_ck", "dummy_ck"),
+	DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
+	DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
+	DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
+	DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
+	DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
+	DT_CLK(NULL, "uart1_ick", "dummy_ck"),
+	DT_CLK(NULL, "uart2_ick", "dummy_ck"),
+	DT_CLK(NULL, "uart3_ick", "dummy_ck"),
+	DT_CLK(NULL, "uart4_ick", "dummy_ck"),
+	DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
+	DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
+	DT_CLK("omap_wdt", "ick", "dummy_ck"),
+	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+	DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"),
+	{ .node_name = NULL },
+};
+
+int __init omap5xxx_dt_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+
+	ti_dt_clocks_register(omap54xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
+	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+	if (!rc)
+		rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index a56ff12..6647f28 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -264,6 +264,7 @@ int of_ti_clk_autoidle_setup(struct device_node *node);
 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
 
 int omap4xxx_dt_clk_init(void);
+int omap5xxx_dt_clk_init(void);
 
 #ifdef CONFIG_OF
 void of_ti_clk_allow_autoidle_all(void);
-- 
1.7.9.5

[PATCHv13 15/40] CLK: TI: add dra7 clock init file

[Tero Kristo]

clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 drivers/clk/ti/Makefile  |    1 +
 drivers/clk/ti/clk-7xx.c |  332 ++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h   |    1 +
 3 files changed, 334 insertions(+)
 create mode 100644 drivers/clk/ti/clk-7xx.c

diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 3d71e1e..f8ae4b5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -4,4 +4,5 @@ obj-y					+= clk.o dpll.o autoidle.o divider.o \
 					   composite.o mux.o apll.o
 obj-$(CONFIG_ARCH_OMAP4)		+= clk-44xx.o
 obj-$(CONFIG_SOC_OMAP5)			+= clk-54xx.o
+obj-$(CONFIG_SOC_DRA7XX)		+= clk-7xx.o
 endif
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
new file mode 100644
index 0000000..9977653
--- /dev/null
+++ b/drivers/clk/ti/clk-7xx.c
@@ -0,0 +1,332 @@
+/*
+ * DRA7 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+#define DRA7_DPLL_ABE_DEFFREQ				361267200
+#define DRA7_DPLL_GMAC_DEFFREQ				1000000000
+
+
+static struct ti_dt_clk dra7xx_clks[] = {
+	DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
+	DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
+	DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"),
+	DT_CLK(NULL, "atlclkin3_ck", "atlclkin3_ck"),
+	DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"),
+	DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"),
+	DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"),
+	DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"),
+	DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"),
+	DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"),
+	DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"),
+	DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"),
+	DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"),
+	DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"),
+	DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+	DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+	DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+	DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+	DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+	DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+	DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"),
+	DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+	DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+	DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+	DT_CLK(NULL, "sys_clkin1", "sys_clkin1"),
+	DT_CLK(NULL, "sys_clkin2", "sys_clkin2"),
+	DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"),
+	DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"),
+	DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"),
+	DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"),
+	DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"),
+	DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"),
+	DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
+	DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
+	DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+	DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+	DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+	DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+	DT_CLK(NULL, "abe_clk", "abe_clk"),
+	DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+	DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"),
+	DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
+	DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"),
+	DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"),
+	DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"),
+	DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"),
+	DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"),
+	DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"),
+	DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"),
+	DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"),
+	DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"),
+	DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"),
+	DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
+	DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"),
+	DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+	DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+	DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+	DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
+	DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
+	DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+	DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+	DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"),
+	DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"),
+	DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"),
+	DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"),
+	DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"),
+	DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
+	DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+	DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"),
+	DT_CLK(NULL, "iva_dclk", "iva_dclk"),
+	DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"),
+	DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"),
+	DT_CLK(NULL, "gpu_dclk", "gpu_dclk"),
+	DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+	DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"),
+	DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+	DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+	DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"),
+	DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"),
+	DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"),
+	DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"),
+	DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"),
+	DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"),
+	DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"),
+	DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
+	DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+	DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+	DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"),
+	DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
+	DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+	DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+	DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"),
+	DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"),
+	DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"),
+	DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"),
+	DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"),
+	DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"),
+	DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"),
+	DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"),
+	DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"),
+	DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"),
+	DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"),
+	DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"),
+	DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"),
+	DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"),
+	DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"),
+	DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
+	DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
+	DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
+	DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
+	DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
+	DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
+	DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
+	DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"),
+	DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"),
+	DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"),
+	DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"),
+	DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"),
+	DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"),
+	DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"),
+	DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"),
+	DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+	DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
+	DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
+	DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"),
+	DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
+	DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+	DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
+	DT_CLK(NULL, "eve_clk", "eve_clk"),
+	DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
+	DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+	DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+	DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+	DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+	DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"),
+	DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"),
+	DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"),
+	DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"),
+	DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
+	DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
+	DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
+	DT_CLK(NULL, "mlb_clk", "mlb_clk"),
+	DT_CLK(NULL, "mlbp_clk", "mlbp_clk"),
+	DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"),
+	DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"),
+	DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"),
+	DT_CLK(NULL, "video1_div_clk", "video1_div_clk"),
+	DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"),
+	DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"),
+	DT_CLK(NULL, "video2_div_clk", "video2_div_clk"),
+	DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"),
+	DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
+	DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
+	DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+	DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+	DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
+	DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
+	DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
+	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+	DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+	DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+	DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+	DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+	DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+	DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
+	DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
+	DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"),
+	DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"),
+	DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"),
+	DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"),
+	DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
+	DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"),
+	DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"),
+	DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"),
+	DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"),
+	DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"),
+	DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"),
+	DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"),
+	DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"),
+	DT_CLK(NULL, "gmac_gmii_ref_clk_div", "gmac_gmii_ref_clk_div"),
+	DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"),
+	DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
+	DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
+	DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"),
+	DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
+	DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"),
+	DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"),
+	DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"),
+	DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"),
+	DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"),
+	DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"),
+	DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"),
+	DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"),
+	DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"),
+	DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"),
+	DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"),
+	DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"),
+	DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"),
+	DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
+	DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
+	DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
+	DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
+	DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
+	DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
+	DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
+	DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
+	DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"),
+	DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"),
+	DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"),
+	DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"),
+	DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"),
+	DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"),
+	DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"),
+	DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
+	DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
+	DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"),
+	DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"),
+	DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"),
+	DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"),
+	DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
+	DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
+	DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
+	DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
+	DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
+	DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
+	DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
+	DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
+	DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
+	DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"),
+	DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"),
+	DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"),
+	DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"),
+	DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"),
+	DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"),
+	DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"),
+	DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"),
+	DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"),
+	DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"),
+	DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"),
+	DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"),
+	DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"),
+	DT_CLK(NULL, "gpmc_ck", "dummy_ck"),
+	DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
+	DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
+	DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
+	DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
+	DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
+	DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
+	DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
+	DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
+	DT_CLK(NULL, "uart1_ick", "dummy_ck"),
+	DT_CLK(NULL, "uart2_ick", "dummy_ck"),
+	DT_CLK(NULL, "uart3_ick", "dummy_ck"),
+	DT_CLK(NULL, "uart4_ick", "dummy_ck"),
+	DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
+	DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
+	DT_CLK("omap_wdt", "ick", "dummy_ck"),
+	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+	DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
+	{ .node_name = NULL },
+};
+
+int __init dra7xx_dt_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+
+	ti_dt_clocks_register(dra7xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
+	sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
+	dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
+
+	rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
+	if (!rc)
+		rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
+	rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
+
+	return rc;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 6647f28..506155b 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -265,6 +265,7 @@ int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
 
 int omap4xxx_dt_clk_init(void);
 int omap5xxx_dt_clk_init(void);
+int dra7xx_dt_clk_init(void);
 
 #ifdef CONFIG_OF
 void of_ti_clk_allow_autoidle_all(void);
-- 
1.7.9.5

[PATCHv13 16/40] CLK: TI: add am33xx clock init file

[Tero Kristo]

clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.

This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/clock.h |    1 -
 drivers/clk/ti/Makefile     |    1 +
 drivers/clk/ti/clk-33xx.c   |  161 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h      |    2 +
 4 files changed, 164 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk-33xx.c

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b83fca6..1da9dc3 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -249,7 +249,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 int omap2_clk_enable_autoidle_all(void);
 int omap2_clk_allow_idle(struct clk *clk);
 int omap2_clk_deny_idle(struct clk *clk);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 			       const char *core_ck_name,
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index f8ae4b5..7eb6f2b 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,6 +2,7 @@ ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o divider.o \
 					   fixed-factor.o gate.o clockdomain.o \
 					   composite.o mux.o apll.o
+obj-$(CONFIG_SOC_AM33XX)		+= clk-33xx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= clk-44xx.o
 obj-$(CONFIG_SOC_OMAP5)			+= clk-54xx.o
 obj-$(CONFIG_SOC_DRA7XX)		+= clk-7xx.o
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
new file mode 100644
index 0000000..776ee45
--- /dev/null
+++ b/drivers/clk/ti/clk-33xx.c
@@ -0,0 +1,161 @@
+/*
+ * AM33XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ *     Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+static struct ti_dt_clk am33xx_clks[] = {
+	DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
+	DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
+	DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+	DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
+	DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
+	DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+	DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+	DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
+	DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+	DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+	DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
+	DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
+	DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
+	DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+	DT_CLK("cpu0", NULL, "dpll_mpu_ck"),
+	DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+	DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+	DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+	DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
+	DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
+	DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
+	DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+	DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+	DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
+	DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
+	DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
+	DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
+	DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
+	DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
+	DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
+	DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+	DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
+	DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
+	DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
+	DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
+	DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
+	DT_CLK(NULL, "mmu_fck", "mmu_fck"),
+	DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
+	DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
+	DT_CLK(NULL, "sha0_fck", "sha0_fck"),
+	DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+	DT_CLK(NULL, "rng_fck", "rng_fck"),
+	DT_CLK(NULL, "timer1_fck", "timer1_fck"),
+	DT_CLK(NULL, "timer2_fck", "timer2_fck"),
+	DT_CLK(NULL, "timer3_fck", "timer3_fck"),
+	DT_CLK(NULL, "timer4_fck", "timer4_fck"),
+	DT_CLK(NULL, "timer5_fck", "timer5_fck"),
+	DT_CLK(NULL, "timer6_fck", "timer6_fck"),
+	DT_CLK(NULL, "timer7_fck", "timer7_fck"),
+	DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
+	DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
+	DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+	DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
+	DT_CLK(NULL, "l3_gclk", "l3_gclk"),
+	DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
+	DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
+	DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
+	DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
+	DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
+	DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
+	DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
+	DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
+	DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
+	DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
+	DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
+	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+	DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+	DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+	DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
+	DT_CLK(NULL, "mmc_clk", "mmc_clk"),
+	DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
+	DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
+	DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
+	DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
+	DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
+	DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
+	DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
+	DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
+	DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
+	DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
+	DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
+	DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
+	DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
+	DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
+	{ .node_name = NULL },
+};
+
+static const char *enable_init_clks[] = {
+	"dpll_ddr_m2_ck",
+	"dpll_mpu_m2_ck",
+	"l3_gclk",
+	"l4hs_gclk",
+	"l4fw_gclk",
+	"l4ls_gclk",
+	/* Required for external peripherals like, Audio codecs */
+	"clkout2_ck",
+};
+
+int __init am33xx_dt_clk_init(void)
+{
+	struct clk *clk1, *clk2;
+
+	ti_dt_clocks_register(am33xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	omap2_clk_enable_init_clocks(enable_init_clks,
+				     ARRAY_SIZE(enable_init_clks));
+
+	/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+	 *    physically present, in such a case HWMOD enabling of
+	 *    clock would be failure with default parent. And timer
+	 *    probe thinks clock is already enabled, this leads to
+	 *    crash upon accessing timer 3 & 6 registers in probe.
+	 *    Fix by setting parent of both these timers to master
+	 *    oscillator clock.
+	 */
+
+	clk1 = clk_get_sys(NULL, "sys_clkin_ck");
+	clk2 = clk_get_sys(NULL, "timer3_fck");
+	clk_set_parent(clk2, clk1);
+
+	clk2 = clk_get_sys(NULL, "timer6_fck");
+	clk_set_parent(clk2, clk1);
+	/*
+	 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
+	 * the design/spec, so as a result, for example, timer which supposed
+	 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
+	 * not expected by any use-case, so change WDT1 clock source to PRCM
+	 * 32KHz clock.
+	 */
+	clk1 = clk_get_sys(NULL, "wdt1_fck");
+	clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
+	clk_set_parent(clk1, clk2);
+
+	return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 506155b..0e7c8d9 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -248,6 +248,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 int omap2_clk_disable_autoidle_all(void);
+void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 			 unsigned long parent_rate);
 int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -266,6 +267,7 @@ int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
 int omap4xxx_dt_clk_init(void);
 int omap5xxx_dt_clk_init(void);
 int dra7xx_dt_clk_init(void);
+int am33xx_dt_clk_init(void);
 
 #ifdef CONFIG_OF
 void of_ti_clk_allow_autoidle_all(void);
-- 
1.7.9.5

[PATCHv13 18/40] CLK: TI: add omap3 clock init file

[Tero Kristo]

clk-3xxx.c now contains the clock init functionality for omap3, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/clock3xxx.h |    1 -
 drivers/clk/ti/Makefile         |    2 +-
 drivers/clk/ti/clk-3xxx.c       |  401 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h          |    5 +
 4 files changed, 407 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/ti/clk-3xxx.c

diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index dab90e2..78d9f56 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -11,7 +11,6 @@
 int omap3xxx_clk_init(void);
 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
 					unsigned long parent_rate);
-void omap3_clk_lock_dpll5(void);
 
 extern struct clk *sdrc_ick_p;
 extern struct clk *arm_fck_p;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index e42a703..ab386c8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,7 +3,7 @@ obj-y					+= clk.o dpll.o autoidle.o divider.o \
 					   fixed-factor.o gate.o clockdomain.o \
 					   composite.o mux.o apll.o
 obj-$(CONFIG_SOC_AM33XX)		+= clk-33xx.o
-obj-$(CONFIG_ARCH_OMAP3)		+= interface.o
+obj-$(CONFIG_ARCH_OMAP3)		+= interface.o clk-3xxx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= clk-44xx.o
 obj-$(CONFIG_SOC_OMAP5)			+= clk-54xx.o
 obj-$(CONFIG_SOC_DRA7XX)		+= clk-7xx.o
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
new file mode 100644
index 0000000..d323023
--- /dev/null
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -0,0 +1,401 @@
+/*
+ * OMAP3 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ *     Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+
+static struct ti_dt_clk omap3xxx_clks[] = {
+	DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
+	DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
+	DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
+	DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
+	DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+	DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+	DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
+	DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
+	DT_CLK("twl", "fck", "osc_sys_ck"),
+	DT_CLK(NULL, "sys_ck", "sys_ck"),
+	DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
+	DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
+	DT_CLK(NULL, "sys_altclk", "sys_altclk"),
+	DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
+	DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
+	DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
+	DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
+	DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
+	DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
+	DT_CLK(NULL, "core_ck", "core_ck"),
+	DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
+	DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
+	DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
+	DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
+	DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
+	DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
+	DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
+	DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
+	DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
+	DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
+	DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
+	DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
+	DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
+	DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
+	DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
+	DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
+	DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
+	DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
+	DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
+	DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
+	DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
+	DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
+	DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
+	DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
+	DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
+	DT_CLK(NULL, "corex2_fck", "corex2_fck"),
+	DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
+	DT_CLK(NULL, "mpu_ck", "mpu_ck"),
+	DT_CLK(NULL, "arm_fck", "arm_fck"),
+	DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
+	DT_CLK(NULL, "l3_ick", "l3_ick"),
+	DT_CLK(NULL, "l4_ick", "l4_ick"),
+	DT_CLK(NULL, "rm_ick", "rm_ick"),
+	DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
+	DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
+	DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
+	DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
+	DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
+	DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
+	DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
+	DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
+	DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
+	DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
+	DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
+	DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
+	DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
+	DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
+	DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
+	DT_CLK(NULL, "uart2_fck", "uart2_fck"),
+	DT_CLK(NULL, "uart1_fck", "uart1_fck"),
+	DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
+	DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
+	DT_CLK(NULL, "hdq_fck", "hdq_fck"),
+	DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
+	DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
+	DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
+	DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
+	DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
+	DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
+	DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
+	DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
+	DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
+	DT_CLK(NULL, "hdq_ick", "hdq_ick"),
+	DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
+	DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
+	DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
+	DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
+	DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
+	DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
+	DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
+	DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
+	DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
+	DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
+	DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
+	DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
+	DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
+	DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
+	DT_CLK(NULL, "uart2_ick", "uart2_ick"),
+	DT_CLK(NULL, "uart1_ick", "uart1_ick"),
+	DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
+	DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
+	DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
+	DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
+	DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
+	DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
+	DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
+	DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
+	DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
+	DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
+	DT_CLK(NULL, "utmi_p1_gfclk", "dummy_ck"),
+	DT_CLK(NULL, "utmi_p2_gfclk", "dummy_ck"),
+	DT_CLK(NULL, "xclk60mhsp1_ck", "dummy_ck"),
+	DT_CLK(NULL, "xclk60mhsp2_ck", "dummy_ck"),
+	DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
+	DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
+	DT_CLK(NULL, "aes2_ick", "aes2_ick"),
+	DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
+	DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
+	DT_CLK(NULL, "sha12_ick", "sha12_ick"),
+	DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
+	DT_CLK("omap_wdt", "ick", "wdt2_ick"),
+	DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
+	DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
+	DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
+	DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
+	DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
+	DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
+	DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
+	DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
+	DT_CLK(NULL, "uart3_fck", "uart3_fck"),
+	DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
+	DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
+	DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
+	DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
+	DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
+	DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
+	DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
+	DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
+	DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
+	DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
+	DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
+	DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
+	DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
+	DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
+	DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
+	DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
+	DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
+	DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
+	DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
+	DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
+	DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
+	DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
+	DT_CLK(NULL, "uart3_ick", "uart3_ick"),
+	DT_CLK(NULL, "uart4_ick", "uart4_ick"),
+	DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
+	DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
+	DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
+	DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
+	DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
+	DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
+	DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
+	DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
+	DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
+	DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
+	DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
+	DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
+	DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
+	DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"),
+	DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
+	DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
+	DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
+	DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
+	DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
+	DT_CLK(NULL, "pclk_fck", "pclk_fck"),
+	DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
+	DT_CLK(NULL, "atclk_fck", "atclk_fck"),
+	DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
+	DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
+	DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
+	DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
+	DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+	DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
+	DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
+	DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
+	{ .node_name = NULL },
+};
+
+static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
+	DT_CLK(NULL, "aes1_ick", "aes1_ick"),
+	DT_CLK("omap_rng", "ick", "rng_ick"),
+	DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
+	DT_CLK(NULL, "sha11_ick", "sha11_ick"),
+	DT_CLK(NULL, "des1_ick", "des1_ick"),
+	DT_CLK(NULL, "cam_mclk", "cam_mclk"),
+	DT_CLK(NULL, "cam_ick", "cam_ick"),
+	DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
+	DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
+	DT_CLK(NULL, "pka_ick", "pka_ick"),
+	DT_CLK(NULL, "icr_ick", "icr_ick"),
+	DT_CLK("omap-aes", "ick", "aes2_ick"),
+	DT_CLK("omap-sham", "ick", "sha12_ick"),
+	DT_CLK(NULL, "des2_ick", "des2_ick"),
+	DT_CLK(NULL, "mspro_ick", "mspro_ick"),
+	DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
+	DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
+	DT_CLK(NULL, "sr1_fck", "sr1_fck"),
+	DT_CLK(NULL, "sr2_fck", "sr2_fck"),
+	DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
+	DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
+	DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
+	DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
+	DT_CLK(NULL, "iva2_ck", "iva2_ck"),
+	DT_CLK(NULL, "modem_fck", "modem_fck"),
+	DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
+	DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
+	DT_CLK(NULL, "mspro_fck", "mspro_fck"),
+	DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
+	DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
+	{ .node_name = NULL },
+};
+
+static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
+	DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
+	DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
+	DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
+	DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
+	DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
+	DT_CLK(NULL, "usim_fck", "usim_fck"),
+	DT_CLK(NULL, "usim_ick", "usim_ick"),
+	{ .node_name = NULL },
+};
+
+static struct ti_dt_clk omap3430es1_clks[] = {
+	DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
+	DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
+	DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
+	DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
+	DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
+	DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
+	DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
+	DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
+	DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
+	DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
+	DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
+	DT_CLK(NULL, "fac_ick", "fac_ick"),
+	DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
+	DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
+	DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
+	DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
+	DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
+	{ .node_name = NULL },
+};
+
+static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
+	DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
+	DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
+	DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
+	DT_CLK(NULL, "sgx_fck", "sgx_fck"),
+	DT_CLK(NULL, "sgx_ick", "sgx_ick"),
+	DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
+	DT_CLK(NULL, "ts_fck", "ts_fck"),
+	DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
+	DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
+	DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
+	DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
+	DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
+	DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
+	DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
+	DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
+	DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
+	DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
+	DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
+	{ .node_name = NULL },
+};
+
+static struct ti_dt_clk am35xx_clks[] = {
+	DT_CLK(NULL, "ipss_ick", "ipss_ick"),
+	DT_CLK(NULL, "rmii_ck", "rmii_ck"),
+	DT_CLK(NULL, "pclk_ck", "pclk_ck"),
+	DT_CLK(NULL, "emac_ick", "emac_ick"),
+	DT_CLK(NULL, "emac_fck", "emac_fck"),
+	DT_CLK("davinci_emac.0", NULL, "emac_ick"),
+	DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
+	DT_CLK("vpfe-capture", "master", "vpfe_ick"),
+	DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
+	DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
+	DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
+	DT_CLK(NULL, "hecc_ck", "hecc_ck"),
+	DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
+	DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
+	{ .node_name = NULL },
+};
+
+static struct ti_dt_clk omap36xx_clks[] = {
+	DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
+	DT_CLK(NULL, "uart4_fck", "uart4_fck"),
+	{ .node_name = NULL },
+};
+
+static const char *enable_init_clks[] = {
+	"sdrc_ick",
+	"gpmc_fck",
+	"omapctrl_ick",
+};
+
+enum {
+	OMAP3_SOC_AM35XX,
+	OMAP3_SOC_OMAP3430_ES1,
+	OMAP3_SOC_OMAP3430_ES2_PLUS,
+	OMAP3_SOC_OMAP3630,
+	OMAP3_SOC_TI81XX,
+};
+
+static int __init omap3xxx_dt_clk_init(int soc_type)
+{
+	if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
+	    soc_type == OMAP3_SOC_OMAP3430_ES1 ||
+	    soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
+		ti_dt_clocks_register(omap3xxx_clks);
+
+	if (soc_type == OMAP3_SOC_AM35XX)
+		ti_dt_clocks_register(am35xx_clks);
+
+	if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
+	    soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
+		ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
+
+	if (soc_type == OMAP3_SOC_OMAP3430_ES1)
+		ti_dt_clocks_register(omap3430es1_clks);
+
+	if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
+	    soc_type == OMAP3_SOC_OMAP3630)
+		ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
+
+	if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
+	    soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
+	    soc_type == OMAP3_SOC_OMAP3630)
+		ti_dt_clocks_register(omap34xx_omap36xx_clks);
+
+	if (soc_type == OMAP3_SOC_OMAP3630)
+		ti_dt_clocks_register(omap36xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	omap2_clk_enable_init_clocks(enable_init_clks,
+				     ARRAY_SIZE(enable_init_clks));
+
+	pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+		(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
+		(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
+		(clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
+		(clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
+
+	if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1)
+		omap3_clk_lock_dpll5();
+
+	return 0;
+}
+
+int __init omap3430_dt_clk_init(void)
+{
+	return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
+}
+
+int __init omap3630_dt_clk_init(void)
+{
+	return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630);
+}
+
+int __init am35xx_dt_clk_init(void)
+{
+	return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
+}
+
+int __init ti81xx_dt_clk_init(void)
+{
+	return omap3xxx_dt_clk_init(OMAP3_SOC_TI81XX);
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 17c034e..3d2ba57 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -254,6 +254,7 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 int omap2_dflt_clk_enable(struct clk_hw *hw);
 void omap2_dflt_clk_disable(struct clk_hw *hw);
 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
+void omap3_clk_lock_dpll5(void);
 
 void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
@@ -264,6 +265,10 @@ int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
 int of_ti_clk_autoidle_setup(struct device_node *node);
 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
 
+int omap3430_dt_clk_init(void);
+int omap3630_dt_clk_init(void);
+int am35xx_dt_clk_init(void);
+int ti81xx_dt_clk_init(void);
 int omap4xxx_dt_clk_init(void);
 int omap5xxx_dt_clk_init(void);
 int dra7xx_dt_clk_init(void);
-- 
1.7.9.5

[PATCHv13 20/40] ARM: dts: omap4 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi           |   54 ++
 arch/arm/boot/dts/omap443x-clocks.dtsi |   18 +
 arch/arm/boot/dts/omap443x.dtsi        |    2 +
 arch/arm/boot/dts/omap4460.dtsi        |    2 +
 arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 1651 ++++++++++++++++++++++++++++++++
 6 files changed, 1754 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index a1e0585..d3f8a6e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -107,6 +107,58 @@
 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+		cm1: cm1@4a004000 {
+			compatible = "ti,omap4-cm1";
+			reg = <0x4a004000 0x2000>;
+
+			cm1_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cm1_clockdomains: clockdomains {
+			};
+		};
+
+		prm: prm@4a306000 {
+			compatible = "ti,omap4-prm";
+			reg = <0x4a306000 0x3000>;
+
+			prm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			prm_clockdomains: clockdomains {
+			};
+		};
+
+		cm2: cm2@4a008000 {
+			compatible = "ti,omap4-cm2";
+			reg = <0x4a008000 0x3000>;
+
+			cm2_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cm2_clockdomains: clockdomains {
+			};
+		};
+
+		scrm: scrm@4a30a000 {
+			compatible = "ti,omap4-scrm";
+			reg = <0x4a30a000 0x2000>;
+
+			scrm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			scrm_clockdomains: clockdomains {
+			};
+		};
+
 		counter32k: counter@4a304000 {
 			compatible = "ti,omap-counter32k";
 			reg = <0x4a304000 0x20>;
@@ -707,3 +759,5 @@
 		};
 	};
 };
+
+/include/ "omap44xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 0000000..2bd2166
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+	bandgap_fclk: bandgap_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1888>;
+	};
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455e..f67e191 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -31,3 +31,5 @@
 		compatible = "ti,omap4430-bandgap";
 	};
 };
+
+/include/ "omap443x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39..1758601 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -39,3 +39,5 @@
 		gpios = <&gpio3 22 0>; /* tshut */
 	};
 };
+
+/include/ "omap446x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 0000000..be033e9
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+	div_ts_ck: div_ts_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&l4_wkup_clk_mux_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1888>;
+		ti,dividers = <8>, <16>, <32>;
+	};
+
+	bandgap_ts_fclk: bandgap_ts_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&div_ts_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1888>;
+	};
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 0000000..c821ff5
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1651 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm1_clocks {
+	extalt_clkin_ck: extalt_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <59000000>;
+	};
+
+	pad_clks_src_ck: pad_clks_src_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	pad_clks_ck: pad_clks_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&pad_clks_src_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0108>;
+	};
+
+	pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	slimbus_src_clk: slimbus_src_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	slimbus_clk: slimbus_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&slimbus_src_clk>;
+		ti,bit-shift = <10>;
+		reg = <0x0108>;
+	};
+
+	sys_32k_ck: sys_32k_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	virt_12000000_ck: virt_12000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	virt_13000000_ck: virt_13000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <13000000>;
+	};
+
+	virt_16800000_ck: virt_16800000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <16800000>;
+	};
+
+	virt_19200000_ck: virt_19200000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <19200000>;
+	};
+
+	virt_26000000_ck: virt_26000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+	};
+
+	virt_27000000_ck: virt_27000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <27000000>;
+	};
+
+	virt_38400000_ck: virt_38400000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <38400000>;
+	};
+
+	tie_low_clock_ck: tie_low_clock_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <60000000>;
+	};
+
+	xclk60mhsp1_ck: xclk60mhsp1_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <60000000>;
+	};
+
+	xclk60mhsp2_ck: xclk60mhsp2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <60000000>;
+	};
+
+	xclk60motg_ck: xclk60motg_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <60000000>;
+	};
+
+	dpll_abe_ck: dpll_abe_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-m4xen-clock";
+		clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+	};
+
+	dpll_abe_x2_ck: dpll_abe_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_abe_ck>;
+		reg = <0x01f0>;
+	};
+
+	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01f0>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	abe_24m_fclk: abe_24m_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <8>;
+	};
+
+	abe_clk: abe_clk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_m2x2_ck>;
+		ti,max-div = <4>;
+		reg = <0x0108>;
+		ti,index-power-of-two;
+	};
+
+	aess_fclk: aess_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&abe_clk>;
+		ti,bit-shift = <24>;
+		ti,max-div = <2>;
+		reg = <0x0528>;
+	};
+
+	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01f4>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x012c>;
+	};
+
+	dpll_core_ck: dpll_core_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-core-clock";
+		clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+	};
+
+	dpll_core_x2_ck: dpll_core_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_core_ck>;
+	};
+
+	dpll_core_m6x2_ck: dpll_core_m6x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0140>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_m2_ck: dpll_core_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0130>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	ddrphy_ck: ddrphy_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	dpll_core_m5x2_ck: dpll_core_m5x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x013c>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	div_core_ck: div_core_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_m5x2_ck>;
+		reg = <0x0100>;
+		ti,max-div = <2>;
+	};
+
+	div_iva_hs_clk: div_iva_hs_clk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_m5x2_ck>;
+		ti,max-div = <4>;
+		reg = <0x01dc>;
+		ti,index-power-of-two;
+	};
+
+	div_mpu_hs_clk: div_mpu_hs_clk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_m5x2_ck>;
+		ti,max-div = <4>;
+		reg = <0x019c>;
+		ti,index-power-of-two;
+	};
+
+	dpll_core_m4x2_ck: dpll_core_m4x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0138>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dll_clk_div_ck: dll_clk_div_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4x2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	dpll_abe_m2_ck: dpll_abe_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_ck>;
+		ti,max-div = <31>;
+		reg = <0x01f0>;
+		ti,index-starts-at-one;
+	};
+
+	dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0134>;
+	};
+
+	dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		reg = <0x0134>;
+		ti,index-starts-at-one;
+	};
+
+	dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
+	};
+
+	dpll_core_m7x2_ck: dpll_core_m7x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0144>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+		ti,bit-shift = <23>;
+		reg = <0x01ac>;
+	};
+
+	dpll_iva_ck: dpll_iva_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+	};
+
+	dpll_iva_x2_ck: dpll_iva_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_iva_ck>;
+	};
+
+	dpll_iva_m4x2_ck: dpll_iva_m4x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_iva_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01b8>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_iva_m5x2_ck: dpll_iva_m5x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_iva_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01bc>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_mpu_ck: dpll_mpu_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+	};
+
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_mpu_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0170>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	per_hs_clk_div_ck: per_hs_clk_div_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m3x2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m3x2_ck>;
+		clock-mult = <1>;
+		clock-div = <3>;
+	};
+
+	l3_div_ck: l3_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&div_core_ck>;
+		ti,bit-shift = <4>;
+		ti,max-div = <2>;
+		reg = <0x0100>;
+	};
+
+	l4_div_ck: l4_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&l3_div_ck>;
+		ti,bit-shift = <8>;
+		ti,max-div = <2>;
+		reg = <0x0100>;
+	};
+
+	lp_clk_div_ck: lp_clk_div_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <16>;
+	};
+
+	mpu_periphclk: mpu_periphclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_mpu_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	ocp_abe_iclk: ocp_abe_iclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&aess_fclk>;
+		ti,bit-shift = <24>;
+		reg = <0x0528>;
+		ti,dividers = <2>, <1>;
+	};
+
+	per_abe_24m_fclk: per_abe_24m_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	dmic_sync_mux_ck: dmic_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+		ti,bit-shift = <25>;
+		reg = <0x0538>;
+	};
+
+	func_dmic_abe_gfclk: func_dmic_abe_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0538>;
+	};
+
+	mcasp_sync_mux_ck: mcasp_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+		ti,bit-shift = <25>;
+		reg = <0x0540>;
+	};
+
+	func_mcasp_abe_gfclk: func_mcasp_abe_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0540>;
+	};
+
+	mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+		ti,bit-shift = <25>;
+		reg = <0x0548>;
+	};
+
+	func_mcbsp1_gfclk: func_mcbsp1_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0548>;
+	};
+
+	mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+		ti,bit-shift = <25>;
+		reg = <0x0550>;
+	};
+
+	func_mcbsp2_gfclk: func_mcbsp2_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0550>;
+	};
+
+	mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+		ti,bit-shift = <25>;
+		reg = <0x0558>;
+	};
+
+	func_mcbsp3_gfclk: func_mcbsp3_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0558>;
+	};
+
+	slimbus1_fclk_1: slimbus1_fclk_1 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&func_24m_clk>;
+		ti,bit-shift = <9>;
+		reg = <0x0560>;
+	};
+
+	slimbus1_fclk_0: slimbus1_fclk_0 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&abe_24m_fclk>;
+		ti,bit-shift = <8>;
+		reg = <0x0560>;
+	};
+
+	slimbus1_fclk_2: slimbus1_fclk_2 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&pad_clks_ck>;
+		ti,bit-shift = <10>;
+		reg = <0x0560>;
+	};
+
+	slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&slimbus_clk>;
+		ti,bit-shift = <11>;
+		reg = <0x0560>;
+	};
+
+	timer5_sync_mux: timer5_sync_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0568>;
+	};
+
+	timer6_sync_mux: timer6_sync_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0570>;
+	};
+
+	timer7_sync_mux: timer7_sync_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0578>;
+	};
+
+	timer8_sync_mux: timer8_sync_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0580>;
+	};
+
+	dummy_ck: dummy_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+};
+&prm_clocks {
+	sys_clkin_ck: sys_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+		reg = <0x0110>;
+		ti,index-starts-at-one;
+	};
+
+	abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0108>;
+	};
+
+	abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+		reg = <0x010c>;
+	};
+
+	dbgclk_mux_ck: dbgclk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+		reg = <0x0108>;
+	};
+
+	syc_clk_div_ck: syc_clk_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin_ck>;
+		reg = <0x0100>;
+		ti,max-div = <2>;
+	};
+
+	gpio1_dbclk: gpio1_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1838>;
+	};
+
+	dmt1_clk_mux: dmt1_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1840>;
+	};
+
+	usim_ck: usim_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_m4x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1858>;
+		ti,dividers = <14>, <18>;
+	};
+
+	usim_fclk: usim_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&usim_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1858>;
+	};
+
+	pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+		ti,bit-shift = <20>;
+		reg = <0x1a20>;
+	};
+
+	pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+		ti,bit-shift = <22>;
+		reg = <0x1a20>;
+	};
+
+	stm_clk_div_ck: stm_clk_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&pmd_stm_clock_mux_ck>;
+		ti,bit-shift = <27>;
+		ti,max-div = <64>;
+		reg = <0x1a20>;
+		ti,index-power-of-two;
+	};
+
+	trace_clk_div_div_ck: trace_clk_div_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&pmd_trace_clk_mux_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1a20>;
+		ti,dividers = <0>, <1>, <2>, <0>, <4>;
+	};
+
+	trace_clk_div_ck: trace_clk_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,clkdm-gate-clock";
+		clocks = <&trace_clk_div_div_ck>;
+	};
+};
+
+&prm_clockdomains {
+	emu_sys_clkdm: emu_sys_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&trace_clk_div_ck>;
+	};
+};
+
+&cm2_clocks {
+	per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x014c>;
+	};
+
+	dpll_per_ck: dpll_per_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+	};
+
+	dpll_per_m2_ck: dpll_per_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_ck>;
+		ti,max-div = <31>;
+		reg = <0x0150>;
+		ti,index-starts-at-one;
+	};
+
+	dpll_per_x2_ck: dpll_per_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_per_ck>;
+		reg = <0x0150>;
+	};
+
+	dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0150>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0154>;
+	};
+
+	dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <31>;
+		reg = <0x0154>;
+		ti,index-starts-at-one;
+	};
+
+	dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
+	};
+
+	dpll_per_m4x2_ck: dpll_per_m4x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0158>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_m5x2_ck: dpll_per_m5x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x015c>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_m6x2_ck: dpll_per_m6x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0160>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_m7x2_ck: dpll_per_m7x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0164>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_usb_ck: dpll_usb_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-j-type-clock";
+		clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+	};
+
+	dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+		#clock-cells = <0>;
+		compatible = "ti,fixed-factor-clock";
+		clocks = <&dpll_usb_ck>;
+		ti,clock-div = <1>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01b4>;
+		ti,clock-mult = <1>;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_usb_m2_ck: dpll_usb_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_usb_ck>;
+		ti,max-div = <127>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0190>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	ducati_clk_mux_ck: ducati_clk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+		reg = <0x0100>;
+	};
+
+	func_12m_fclk: func_12m_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <16>;
+	};
+
+	func_24m_clk: func_24m_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	func_24mc_fclk: func_24mc_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <8>;
+	};
+
+	func_48m_fclk: func_48m_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		reg = <0x0108>;
+		ti,dividers = <4>, <8>;
+	};
+
+	func_48mc_fclk: func_48mc_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	func_64m_fclk: func_64m_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_m4x2_ck>;
+		reg = <0x0108>;
+		ti,dividers = <2>, <4>;
+	};
+
+	func_96m_fclk: func_96m_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		reg = <0x0108>;
+		ti,dividers = <2>, <4>;
+	};
+
+	init_60m_fclk: init_60m_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_usb_m2_ck>;
+		reg = <0x0104>;
+		ti,dividers = <1>, <8>;
+	};
+
+	per_abe_nc_fclk: per_abe_nc_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_m2_ck>;
+		reg = <0x0108>;
+		ti,max-div = <2>;
+	};
+
+	aes1_fck: aes1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3_div_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x15a0>;
+	};
+
+	aes2_fck: aes2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3_div_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x15a8>;
+	};
+
+	dss_sys_clk: dss_sys_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&syc_clk_div_ck>;
+		ti,bit-shift = <10>;
+		reg = <0x1120>;
+	};
+
+	dss_tv_clk: dss_tv_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&extalt_clkin_ck>;
+		ti,bit-shift = <11>;
+		reg = <0x1120>;
+	};
+
+	dss_dss_clk: dss_dss_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_per_m5x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1120>;
+		ti,set-rate-parent;
+	};
+
+	dss_48mhz_clk: dss_48mhz_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&func_48mc_fclk>;
+		ti,bit-shift = <9>;
+		reg = <0x1120>;
+	};
+
+	dss_fck: dss_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3_div_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x1120>;
+	};
+
+	fdif_fck: fdif_fck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_m4x2_ck>;
+		ti,bit-shift = <24>;
+		ti,max-div = <4>;
+		reg = <0x1028>;
+		ti,index-power-of-two;
+	};
+
+	gpio2_dbclk: gpio2_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1460>;
+	};
+
+	gpio3_dbclk: gpio3_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1468>;
+	};
+
+	gpio4_dbclk: gpio4_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1470>;
+	};
+
+	gpio5_dbclk: gpio5_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1478>;
+	};
+
+	gpio6_dbclk: gpio6_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1480>;
+	};
+
+	sgx_clk_mux: sgx_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1220>;
+	};
+
+	hsi_fck: hsi_fck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		ti,max-div = <4>;
+		reg = <0x1338>;
+		ti,index-power-of-two;
+	};
+
+	iss_ctrlclk: iss_ctrlclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&func_96m_fclk>;
+		ti,bit-shift = <8>;
+		reg = <0x1020>;
+	};
+
+	mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+		ti,bit-shift = <25>;
+		reg = <0x14e0>;
+	};
+
+	per_mcbsp4_gfclk: per_mcbsp4_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x14e0>;
+	};
+
+	hsmmc1_fclk: hsmmc1_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+		ti,bit-shift = <24>;
+		reg = <0x1328>;
+	};
+
+	hsmmc2_fclk: hsmmc2_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+		ti,bit-shift = <24>;
+		reg = <0x1330>;
+	};
+
+	ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&func_48m_fclk>;
+		ti,bit-shift = <8>;
+		reg = <0x13e0>;
+	};
+
+	sha2md5_fck: sha2md5_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3_div_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x15c8>;
+	};
+
+	slimbus2_fclk_1: slimbus2_fclk_1 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&per_abe_24m_fclk>;
+		ti,bit-shift = <9>;
+		reg = <0x1538>;
+	};
+
+	slimbus2_fclk_0: slimbus2_fclk_0 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&func_24mc_fclk>;
+		ti,bit-shift = <8>;
+		reg = <0x1538>;
+	};
+
+	slimbus2_slimbus_clk: slimbus2_slimbus_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&pad_slimbus_core_clks_ck>;
+		ti,bit-shift = <10>;
+		reg = <0x1538>;
+	};
+
+	smartreflex_core_fck: smartreflex_core_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l4_wkup_clk_mux_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0638>;
+	};
+
+	smartreflex_iva_fck: smartreflex_iva_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l4_wkup_clk_mux_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0630>;
+	};
+
+	smartreflex_mpu_fck: smartreflex_mpu_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l4_wkup_clk_mux_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0628>;
+	};
+
+	cm2_dm10_mux: cm2_dm10_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1428>;
+	};
+
+	cm2_dm11_mux: cm2_dm11_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1430>;
+	};
+
+	cm2_dm2_mux: cm2_dm2_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1438>;
+	};
+
+	cm2_dm3_mux: cm2_dm3_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1440>;
+	};
+
+	cm2_dm4_mux: cm2_dm4_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1448>;
+	};
+
+	cm2_dm9_mux: cm2_dm9_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1450>;
+	};
+
+	usb_host_fs_fck: usb_host_fs_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&func_48mc_fclk>;
+		ti,bit-shift = <1>;
+		reg = <0x13d0>;
+	};
+
+	utmi_p1_gfclk: utmi_p1_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1358>;
+	};
+
+	usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&utmi_p1_gfclk>;
+		ti,bit-shift = <8>;
+		reg = <0x1358>;
+	};
+
+	utmi_p2_gfclk: utmi_p2_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+		ti,bit-shift = <25>;
+		reg = <0x1358>;
+	};
+
+	usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&utmi_p2_gfclk>;
+		ti,bit-shift = <9>;
+		reg = <0x1358>;
+	};
+
+	usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&init_60m_fclk>;
+		ti,bit-shift = <10>;
+		reg = <0x1358>;
+	};
+
+	usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_m2_ck>;
+		ti,bit-shift = <13>;
+		reg = <0x1358>;
+	};
+
+	usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&init_60m_fclk>;
+		ti,bit-shift = <11>;
+		reg = <0x1358>;
+	};
+
+	usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&init_60m_fclk>;
+		ti,bit-shift = <12>;
+		reg = <0x1358>;
+	};
+
+	usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_m2_ck>;
+		ti,bit-shift = <14>;
+		reg = <0x1358>;
+	};
+
+	usb_host_hs_func48mclk: usb_host_hs_func48mclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&func_48mc_fclk>;
+		ti,bit-shift = <15>;
+		reg = <0x1358>;
+	};
+
+	usb_host_hs_fck: usb_host_hs_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&init_60m_fclk>;
+		ti,bit-shift = <1>;
+		reg = <0x1358>;
+	};
+
+	otg_60m_gfclk: otg_60m_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1360>;
+	};
+
+	usb_otg_hs_xclk: usb_otg_hs_xclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&otg_60m_gfclk>;
+		ti,bit-shift = <8>;
+		reg = <0x1360>;
+	};
+
+	usb_otg_hs_ick: usb_otg_hs_ick {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3_div_ck>;
+		ti,bit-shift = <0>;
+		reg = <0x1360>;
+	};
+
+	usb_phy_cm_clk32k: usb_phy_cm_clk32k {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0640>;
+	};
+
+	usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&init_60m_fclk>;
+		ti,bit-shift = <10>;
+		reg = <0x1368>;
+	};
+
+	usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&init_60m_fclk>;
+		ti,bit-shift = <8>;
+		reg = <0x1368>;
+	};
+
+	usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&init_60m_fclk>;
+		ti,bit-shift = <9>;
+		reg = <0x1368>;
+	};
+
+	usb_tll_hs_ick: usb_tll_hs_ick {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l4_div_ck>;
+		ti,bit-shift = <0>;
+		reg = <0x1368>;
+	};
+};
+
+&cm2_clockdomains {
+	l3_init_clkdm: l3_init_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
+	};
+};
+
+&scrm_clocks {
+	auxclk0_src_gate_ck: auxclk0_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0310>;
+	};
+
+	auxclk0_src_mux_ck: auxclk0_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0310>;
+	};
+
+	auxclk0_src_ck: auxclk0_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+	};
+
+	auxclk0_ck: auxclk0_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk0_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x0310>;
+	};
+
+	auxclk1_src_gate_ck: auxclk1_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0314>;
+	};
+
+	auxclk1_src_mux_ck: auxclk1_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0314>;
+	};
+
+	auxclk1_src_ck: auxclk1_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+	};
+
+	auxclk1_ck: auxclk1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk1_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x0314>;
+	};
+
+	auxclk2_src_gate_ck: auxclk2_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0318>;
+	};
+
+	auxclk2_src_mux_ck: auxclk2_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0318>;
+	};
+
+	auxclk2_src_ck: auxclk2_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+	};
+
+	auxclk2_ck: auxclk2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk2_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x0318>;
+	};
+
+	auxclk3_src_gate_ck: auxclk3_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x031c>;
+	};
+
+	auxclk3_src_mux_ck: auxclk3_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x031c>;
+	};
+
+	auxclk3_src_ck: auxclk3_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+	};
+
+	auxclk3_ck: auxclk3_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk3_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x031c>;
+	};
+
+	auxclk4_src_gate_ck: auxclk4_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0320>;
+	};
+
+	auxclk4_src_mux_ck: auxclk4_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0320>;
+	};
+
+	auxclk4_src_ck: auxclk4_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+	};
+
+	auxclk4_ck: auxclk4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk4_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x0320>;
+	};
+
+	auxclk5_src_gate_ck: auxclk5_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0324>;
+	};
+
+	auxclk5_src_mux_ck: auxclk5_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0324>;
+	};
+
+	auxclk5_src_ck: auxclk5_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
+	};
+
+	auxclk5_ck: auxclk5_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk5_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x0324>;
+	};
+
+	auxclkreq0_ck: auxclkreq0_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x0210>;
+	};
+
+	auxclkreq1_ck: auxclkreq1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x0214>;
+	};
+
+	auxclkreq2_ck: auxclkreq2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x0218>;
+	};
+
+	auxclkreq3_ck: auxclkreq3_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x021c>;
+	};
+
+	auxclkreq4_ck: auxclkreq4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x0220>;
+	};
+
+	auxclkreq5_ck: auxclkreq5_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x0224>;
+	};
+};
-- 
1.7.9.5

[PATCHv13 22/40] ARM: dts: dra7 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).

TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi          |   41 +
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 1985 ++++++++++++++++++++++++++++++++++
 2 files changed, 2026 insertions(+)
 create mode 100644 arch/arm/boot/dts/dra7xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d0df4c4..1fd75aa 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -104,6 +104,45 @@
 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+		prm: prm@4ae06000 {
+			compatible = "ti,dra7-prm";
+			reg = <0x4ae06000 0x3000>;
+
+			prm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			prm_clockdomains: clockdomains {
+			};
+		};
+
+		cm_core_aon: cm_core_aon@4a005000 {
+			compatible = "ti,dra7-cm-core-aon";
+			reg = <0x4a005000 0x2000>;
+
+			cm_core_aon_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cm_core_aon_clockdomains: clockdomains {
+			};
+		};
+
+		cm_core: cm_core@4a008000 {
+			compatible = "ti,dra7-cm-core";
+			reg = <0x4a008000 0x3000>;
+
+			cm_core_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cm_core_clockdomains: clockdomains {
+			};
+		};
+
 		counter32k: counter@4ae04000 {
 			compatible = "ti,omap-counter32k";
 			reg = <0x4ae04000 0x40>;
@@ -584,3 +623,5 @@
 		};
 	};
 };
+
+/include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 0000000..32df847
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,1985 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+	atl_clkin0_ck: atl_clkin0_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	atl_clkin1_ck: atl_clkin1_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	atl_clkin2_ck: atl_clkin2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	atlclkin3_ck: atlclkin3_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	hdmi_clkin_ck: hdmi_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	mlb_clkin_ck: mlb_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	mlbp_clkin_ck: mlbp_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <100000000>;
+	};
+
+	ref_clkin0_ck: ref_clkin0_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	ref_clkin1_ck: ref_clkin1_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	ref_clkin2_ck: ref_clkin2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	ref_clkin3_ck: ref_clkin3_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	rmii_clk_ck: rmii_clk_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	sdvenc_clkin_ck: sdvenc_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	sys_32k_ck: sys_32k_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	virt_12000000_ck: virt_12000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	virt_13000000_ck: virt_13000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <13000000>;
+	};
+
+	virt_16800000_ck: virt_16800000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <16800000>;
+	};
+
+	virt_19200000_ck: virt_19200000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <19200000>;
+	};
+
+	virt_20000000_ck: virt_20000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <20000000>;
+	};
+
+	virt_26000000_ck: virt_26000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+	};
+
+	virt_27000000_ck: virt_27000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <27000000>;
+	};
+
+	virt_38400000_ck: virt_38400000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <38400000>;
+	};
+
+	sys_clkin2: sys_clkin2 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <22579200>;
+	};
+
+	usb_otg_clkin_ck: usb_otg_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	video1_clkin_ck: video1_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	video1_m2_clkin_ck: video1_m2_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	video2_clkin_ck: video2_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	video2_m2_clkin_ck: video2_m2_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	dpll_abe_ck: dpll_abe_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-m4xen-clock";
+		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+	};
+
+	dpll_abe_x2_ck: dpll_abe_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_abe_ck>;
+	};
+
+	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01f0>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	abe_clk: abe_clk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_m2x2_ck>;
+		ti,max-div = <4>;
+		reg = <0x0108>;
+		ti,index-power-of-two;
+	};
+
+	dpll_abe_m2_ck: dpll_abe_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01f0>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01f4>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_ck: dpll_core_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-core-clock";
+		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+	};
+
+	dpll_core_x2_ck: dpll_core_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_core_ck>;
+	};
+
+	dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x013c>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_h12x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_mpu_ck: dpll_mpu_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+	};
+
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_mpu_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0170>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	mpu_dclk_div: mpu_dclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_mpu_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_h12x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_dsp_ck: dpll_dsp_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+		reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
+	};
+
+	dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_dsp_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0244>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_h12x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_iva_ck: dpll_iva_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+	};
+
+	dpll_iva_m2_ck: dpll_iva_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_iva_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01b0>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	iva_dclk: iva_dclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_iva_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_gpu_ck: dpll_gpu_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
+	};
+
+	dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_gpu_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x02e8>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_m2_ck: dpll_core_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0130>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_ddr_ck: dpll_ddr_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
+	};
+
+	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_ddr_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0220>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_gmac_ck: dpll_gmac_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
+	};
+
+	dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_gmac_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x02b8>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	video2_dclk_div: video2_dclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&video2_m2_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	video1_dclk_div: video1_dclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&video1_m2_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	hdmi_dclk_div: hdmi_dclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&hdmi_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m3x2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m3x2_ck>;
+		clock-mult = <1>;
+		clock-div = <3>;
+	};
+
+	eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_h12x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_eve_ck: dpll_eve_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+		reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
+	};
+
+	dpll_eve_m2_ck: dpll_eve_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_eve_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0294>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	eve_dclk_div: eve_dclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_eve_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0140>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0144>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0154>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0158>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x015c>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_ddr_ck>;
+	};
+
+	dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_ddr_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0228>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_dsp_ck>;
+	};
+
+	dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_dsp_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0248>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_gmac_ck>;
+	};
+
+	dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_gmac_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x02c0>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_gmac_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x02c4>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_gmac_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x02c8>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_gmac_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x02bc>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	gmii_m_clk_div: gmii_m_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_gmac_h11x2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	hdmi_clk2_div: hdmi_clk2_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&hdmi_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	hdmi_div_clk: hdmi_div_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&hdmi_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	l3_iclk_div: l3_iclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_h12x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	l4_root_clk_div: l4_root_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l3_iclk_div>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	video1_clk2_div: video1_clk2_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&video1_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	video1_div_clk: video1_div_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&video1_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	video2_clk2_div: video2_clk2_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&video2_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	video2_div_clk: video2_div_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&video2_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	ipu1_gfclk_mux: ipu1_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0520>;
+	};
+
+	mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+		ti,bit-shift = <28>;
+		reg = <0x0550>;
+	};
+
+	mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0550>;
+	};
+
+	mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+		ti,bit-shift = <22>;
+		reg = <0x0550>;
+	};
+
+	timer5_gfclk_mux: timer5_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+		ti,bit-shift = <24>;
+		reg = <0x0558>;
+	};
+
+	timer6_gfclk_mux: timer6_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+		ti,bit-shift = <24>;
+		reg = <0x0560>;
+	};
+
+	timer7_gfclk_mux: timer7_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+		ti,bit-shift = <24>;
+		reg = <0x0568>;
+	};
+
+	timer8_gfclk_mux: timer8_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+		ti,bit-shift = <24>;
+		reg = <0x0570>;
+	};
+
+	uart6_gfclk_mux: uart6_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0580>;
+	};
+
+	dummy_ck: dummy_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+};
+&prm_clocks {
+	sys_clkin1: sys_clkin1 {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+		reg = <0x0110>;
+		ti,index-starts-at-one;
+	};
+
+	abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&sys_clkin2>;
+		reg = <0x0118>;
+	};
+
+	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+		reg = <0x0114>;
+	};
+
+	abe_dpll_clk_mux: abe_dpll_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+		reg = <0x010c>;
+	};
+
+	abe_24m_fclk: abe_24m_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_m2x2_ck>;
+		reg = <0x011c>;
+		ti,dividers = <8>, <16>;
+	};
+
+	aess_fclk: aess_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&abe_clk>;
+		reg = <0x0178>;
+		ti,max-div = <2>;
+	};
+
+	abe_giclk_div: abe_giclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&aess_fclk>;
+		reg = <0x0174>;
+		ti,max-div = <2>;
+	};
+
+	abe_lp_clk_div: abe_lp_clk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_m2x2_ck>;
+		reg = <0x01d8>;
+		ti,dividers = <16>, <32>;
+	};
+
+	abe_sys_clk_div: abe_sys_clk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin1>;
+		reg = <0x0120>;
+		ti,max-div = <2>;
+	};
+
+	adc_gfclk_mux: adc_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+		reg = <0x01dc>;
+	};
+
+	sys_clk1_dclk_div: sys_clk1_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin1>;
+		ti,max-div = <64>;
+		reg = <0x01c8>;
+		ti,index-power-of-two;
+	};
+
+	sys_clk2_dclk_div: sys_clk2_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin2>;
+		ti,max-div = <64>;
+		reg = <0x01cc>;
+		ti,index-power-of-two;
+	};
+
+	per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_m2_ck>;
+		ti,max-div = <64>;
+		reg = <0x01bc>;
+		ti,index-power-of-two;
+	};
+
+	dsp_gclk_div: dsp_gclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_dsp_m2_ck>;
+		ti,max-div = <64>;
+		reg = <0x018c>;
+		ti,index-power-of-two;
+	};
+
+	gpu_dclk: gpu_dclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_gpu_m2_ck>;
+		ti,max-div = <64>;
+		reg = <0x01a0>;
+		ti,index-power-of-two;
+	};
+
+	emif_phy_dclk_div: emif_phy_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_ddr_m2_ck>;
+		ti,max-div = <64>;
+		reg = <0x0190>;
+		ti,index-power-of-two;
+	};
+
+	gmac_250m_dclk_div: gmac_250m_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_gmac_m2_ck>;
+		ti,max-div = <64>;
+		reg = <0x019c>;
+		ti,index-power-of-two;
+	};
+
+	l3init_480m_dclk_div: l3init_480m_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_usb_m2_ck>;
+		ti,max-div = <64>;
+		reg = <0x01ac>;
+		ti,index-power-of-two;
+	};
+
+	usb_otg_dclk_div: usb_otg_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&usb_otg_clkin_ck>;
+		ti,max-div = <64>;
+		reg = <0x0184>;
+		ti,index-power-of-two;
+	};
+
+	sata_dclk_div: sata_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin1>;
+		ti,max-div = <64>;
+		reg = <0x01c0>;
+		ti,index-power-of-two;
+	};
+
+	pcie2_dclk_div: pcie2_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_pcie_ref_m2_ck>;
+		ti,max-div = <64>;
+		reg = <0x01b8>;
+		ti,index-power-of-two;
+	};
+
+	pcie_dclk_div: pcie_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&apll_pcie_m2_ck>;
+		ti,max-div = <64>;
+		reg = <0x01b4>;
+		ti,index-power-of-two;
+	};
+
+	emu_dclk_div: emu_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin1>;
+		ti,max-div = <64>;
+		reg = <0x0194>;
+		ti,index-power-of-two;
+	};
+
+	secure_32k_dclk_div: secure_32k_dclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&secure_32k_clk_src_ck>;
+		ti,max-div = <64>;
+		reg = <0x01c4>;
+		ti,index-power-of-two;
+	};
+
+	clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+		reg = <0x0158>;
+	};
+
+	clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+		reg = <0x015c>;
+	};
+
+	clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+		reg = <0x0160>;
+	};
+
+	custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin1>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	eve_clk: eve_clk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+		reg = <0x0180>;
+	};
+
+	hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&sys_clkin2>;
+		reg = <0x01a4>;
+	};
+
+	mlb_clk: mlb_clk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&mlb_clkin_ck>;
+		ti,max-div = <64>;
+		reg = <0x0134>;
+		ti,index-power-of-two;
+	};
+
+	mlbp_clk: mlbp_clk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&mlbp_clkin_ck>;
+		ti,max-div = <64>;
+		reg = <0x0130>;
+		ti,index-power-of-two;
+	};
+
+	per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_m2_ck>;
+		ti,max-div = <64>;
+		reg = <0x0138>;
+		ti,index-power-of-two;
+	};
+
+	timer_sys_clk_div: timer_sys_clk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin1>;
+		reg = <0x0144>;
+		ti,max-div = <2>;
+	};
+
+	video1_dpll_clk_mux: video1_dpll_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&sys_clkin2>;
+		reg = <0x01d0>;
+	};
+
+	video2_dpll_clk_mux: video2_dpll_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&sys_clkin2>;
+		reg = <0x01d4>;
+	};
+
+	wkupaon_iclk_mux: wkupaon_iclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+		reg = <0x0108>;
+	};
+
+	gpio1_dbclk: gpio1_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1838>;
+	};
+
+	dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&sys_clkin2>;
+		ti,bit-shift = <24>;
+		reg = <0x1888>;
+	};
+
+	timer1_gfclk_mux: timer1_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1840>;
+	};
+
+	uart10_gfclk_mux: uart10_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1880>;
+	};
+};
+&cm_core_clocks {
+	dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin1>, <&sys_clkin1>;
+		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+	};
+
+	dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_pcie_ref_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0210>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	apll_pcie_ck: apll_pcie_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
+		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+	};
+
+	apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&apll_pcie_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&apll_pcie_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	apll_pcie_m2_ck: apll_pcie_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&apll_pcie_ck>;
+		ti,max-div = <127>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0224>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_ck: dpll_per_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+	};
+
+	dpll_per_m2_ck: dpll_per_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0150>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_usb_ck: dpll_usb_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-j-type-clock";
+		clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+	};
+
+	dpll_usb_m2_ck: dpll_usb_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_usb_ck>;
+		ti,max-div = <127>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0190>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_pcie_ref_ck>;
+		ti,max-div = <127>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0210>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_x2_ck: dpll_per_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_per_ck>;
+	};
+
+	dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0158>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x015c>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0160>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0164>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0150>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_usb_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	func_128m_clk: func_128m_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_h11x2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	func_12m_fclk: func_12m_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <16>;
+	};
+
+	func_24m_clk: func_24m_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	func_48m_fclk: func_48m_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	func_96m_fclk: func_96m_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	l3init_60m_fclk: l3init_60m_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_usb_m2_ck>;
+		reg = <0x0104>;
+		ti,dividers = <1>, <8>;
+	};
+
+	dss_32khz_clk: dss_32khz_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <11>;
+		reg = <0x1120>;
+	};
+
+	dss_48mhz_clk: dss_48mhz_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&func_48m_fclk>;
+		ti,bit-shift = <9>;
+		reg = <0x1120>;
+	};
+
+	dss_dss_clk: dss_dss_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_per_h12x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1120>;
+	};
+
+	dss_hdmi_clk: dss_hdmi_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&hdmi_dpll_clk_mux>;
+		ti,bit-shift = <10>;
+		reg = <0x1120>;
+	};
+
+	dss_video1_clk: dss_video1_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&video1_dpll_clk_mux>;
+		ti,bit-shift = <12>;
+		reg = <0x1120>;
+	};
+
+	dss_video2_clk: dss_video2_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&video2_dpll_clk_mux>;
+		ti,bit-shift = <13>;
+		reg = <0x1120>;
+	};
+
+	gpio2_dbclk: gpio2_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1760>;
+	};
+
+	gpio3_dbclk: gpio3_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1768>;
+	};
+
+	gpio4_dbclk: gpio4_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1770>;
+	};
+
+	gpio5_dbclk: gpio5_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1778>;
+	};
+
+	gpio6_dbclk: gpio6_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1780>;
+	};
+
+	gpio7_dbclk: gpio7_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1810>;
+	};
+
+	gpio8_dbclk: gpio8_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1818>;
+	};
+
+	mmc1_clk32k: mmc1_clk32k {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1328>;
+	};
+
+	mmc2_clk32k: mmc2_clk32k {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1330>;
+	};
+
+	mmc3_clk32k: mmc3_clk32k {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1820>;
+	};
+
+	mmc4_clk32k: mmc4_clk32k {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1828>;
+	};
+
+	sata_ref_clk: sata_ref_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_clkin1>;
+		ti,bit-shift = <8>;
+		reg = <0x1388>;
+	};
+
+	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_clkdcoldo>;
+		ti,bit-shift = <8>;
+		reg = <0x13f0>;
+	};
+
+	usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_clkdcoldo>;
+		ti,bit-shift = <8>;
+		reg = <0x1340>;
+	};
+
+	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0640>;
+	};
+
+	usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0688>;
+	};
+
+	usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0698>;
+	};
+
+	atl_dpll_clk_mux: atl_dpll_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0c00>;
+	};
+
+	atl_gfclk_mux: atl_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+		ti,bit-shift = <26>;
+		reg = <0x0c00>;
+	};
+
+	gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_gmac_m2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x13d0>;
+		ti,dividers = <2>;
+	};
+
+	gmac_rft_clk_mux: gmac_rft_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+		ti,bit-shift = <25>;
+		reg = <0x13d0>;
+	};
+
+	gpu_core_gclk_mux: gpu_core_gclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1220>;
+	};
+
+	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+		ti,bit-shift = <26>;
+		reg = <0x1220>;
+	};
+
+	l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&wkupaon_iclk_mux>;
+		ti,bit-shift = <24>;
+		reg = <0x0e50>;
+		ti,dividers = <8>, <16>, <32>;
+	};
+
+	mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+		ti,bit-shift = <28>;
+		reg = <0x1860>;
+	};
+
+	mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+		ti,bit-shift = <28>;
+		reg = <0x1860>;
+	};
+
+	mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+		ti,bit-shift = <22>;
+		reg = <0x1860>;
+	};
+
+	mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1868>;
+	};
+
+	mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+		ti,bit-shift = <22>;
+		reg = <0x1868>;
+	};
+
+	mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1898>;
+	};
+
+	mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+		ti,bit-shift = <22>;
+		reg = <0x1898>;
+	};
+
+	mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1878>;
+	};
+
+	mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+		ti,bit-shift = <22>;
+		reg = <0x1878>;
+	};
+
+	mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1904>;
+	};
+
+	mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+		ti,bit-shift = <22>;
+		reg = <0x1904>;
+	};
+
+	mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1908>;
+	};
+
+	mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+		ti,bit-shift = <22>;
+		reg = <0x1908>;
+	};
+
+	mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+		ti,bit-shift = <22>;
+		reg = <0x1890>;
+	};
+
+	mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+		ti,bit-shift = <24>;
+		reg = <0x1890>;
+	};
+
+	mmc1_fclk_mux: mmc1_fclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1328>;
+	};
+
+	mmc1_fclk_div: mmc1_fclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&mmc1_fclk_mux>;
+		ti,bit-shift = <25>;
+		ti,max-div = <4>;
+		reg = <0x1328>;
+		ti,index-power-of-two;
+	};
+
+	mmc2_fclk_mux: mmc2_fclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1330>;
+	};
+
+	mmc2_fclk_div: mmc2_fclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&mmc2_fclk_mux>;
+		ti,bit-shift = <25>;
+		ti,max-div = <4>;
+		reg = <0x1330>;
+		ti,index-power-of-two;
+	};
+
+	mmc3_gfclk_mux: mmc3_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1820>;
+	};
+
+	mmc3_gfclk_div: mmc3_gfclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&mmc3_gfclk_mux>;
+		ti,bit-shift = <25>;
+		ti,max-div = <4>;
+		reg = <0x1820>;
+		ti,index-power-of-two;
+	};
+
+	mmc4_gfclk_mux: mmc4_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1828>;
+	};
+
+	mmc4_gfclk_div: mmc4_gfclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&mmc4_gfclk_mux>;
+		ti,bit-shift = <25>;
+		ti,max-div = <4>;
+		reg = <0x1828>;
+		ti,index-power-of-two;
+	};
+
+	qspi_gfclk_mux: qspi_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1838>;
+	};
+
+	qspi_gfclk_div: qspi_gfclk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&qspi_gfclk_mux>;
+		ti,bit-shift = <25>;
+		ti,max-div = <4>;
+		reg = <0x1838>;
+		ti,index-power-of-two;
+	};
+
+	timer10_gfclk_mux: timer10_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1728>;
+	};
+
+	timer11_gfclk_mux: timer11_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1730>;
+	};
+
+	timer13_gfclk_mux: timer13_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x17c8>;
+	};
+
+	timer14_gfclk_mux: timer14_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x17d0>;
+	};
+
+	timer15_gfclk_mux: timer15_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x17d8>;
+	};
+
+	timer16_gfclk_mux: timer16_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1830>;
+	};
+
+	timer2_gfclk_mux: timer2_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1738>;
+	};
+
+	timer3_gfclk_mux: timer3_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1740>;
+	};
+
+	timer4_gfclk_mux: timer4_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1748>;
+	};
+
+	timer9_gfclk_mux: timer9_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x1750>;
+	};
+
+	uart1_gfclk_mux: uart1_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1840>;
+	};
+
+	uart2_gfclk_mux: uart2_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1848>;
+	};
+
+	uart3_gfclk_mux: uart3_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1850>;
+	};
+
+	uart4_gfclk_mux: uart4_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1858>;
+	};
+
+	uart5_gfclk_mux: uart5_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1870>;
+	};
+
+	uart7_gfclk_mux: uart7_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x18d0>;
+	};
+
+	uart8_gfclk_mux: uart8_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x18e0>;
+	};
+
+	uart9_gfclk_mux: uart9_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x18e8>;
+	};
+
+	vip1_gclk_mux: vip1_gclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1020>;
+	};
+
+	vip2_gclk_mux: vip2_gclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1028>;
+	};
+
+	vip3_gclk_mux: vip3_gclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1030>;
+	};
+};
+
+&cm_core_clockdomains {
+	coreaon_clkdm: coreaon_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dpll_usb_ck>;
+	};
+};
-- 
1.7.9.5

[PATCHv13 23/40] ARM: dts: clk: Add apll related clocks

[Tero Kristo]

From: J Keerthy <j-keerthy@ti.com>

The patch adds a mux node to choose the parent of apll_pcie_ck node.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 32df847..d4e7410 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1150,11 +1150,19 @@
 		ti,invert-autoidle-bit;
 	};
 
+	apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+		#clock-cells = <0>;
+		reg = <0x021c 0x4>;
+		ti,bit-shift = <7>;
+	};
+
 	apll_pcie_ck: apll_pcie_ck {
 		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-clock";
-		clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
-		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+		compatible = "ti,dra7-apll-clock";
+		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+		reg = <0x021c>, <0x0220>;
 	};
 
 	apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
-- 
1.7.9.5

[PATCHv13 24/40] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock

[Tero Kristo]

From: J Keerthy <j-keerthy@ti.com>

This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |    9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d4e7410..d616359 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1183,13 +1183,10 @@
 
 	apll_pcie_m2_ck: apll_pcie_m2_ck {
 		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
+		compatible = "fixed-factor-clock";
 		clocks = <&apll_pcie_ck>;
-		ti,max-div = <127>;
-		ti,autoidle-shift = <8>;
-		reg = <0x0224>;
-		ti,index-starts-at-one;
-		ti,invert-autoidle-bit;
+		clock-mult = <1>;
+		clock-div = <1>;
 	};
 
 	dpll_per_ck: dpll_per_ck {
-- 
1.7.9.5

[PATCHv13 25/40] ARM: dts: DRA7: Add PCIe related clock nodes

[Tero Kristo]

From: J Keerthy <j-keerthy@ti.com>

This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d616359..e96da9a 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,31 @@
 		reg = <0x021c>, <0x0220>;
 	};
 
+	optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+		compatible = "ti,divider-clock";
+		clocks = <&apll_pcie_ck>;
+		#clock-cells = <0>;
+		reg = <0x021c>;
+		ti,bit-shift = <8>;
+		ti,max-div = <2>;
+	};
+
+	optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+		compatible = "ti,gate-clock";
+		clocks = <&apll_pcie_ck>;
+		#clock-cells = <0>;
+		reg = <0x13b0>;
+		ti,bit-shift = <9>;
+	};
+
+	optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+		compatible = "ti,gate-clock";
+		clocks = <&optfclk_pciephy_div>;
+		#clock-cells = <0>;
+		reg = <0x13b0>;
+		ti,bit-shift = <10>;
+	};
+
 	apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
-- 
1.7.9.5

[PATCHv13 31/40] ARM: OMAP2+: clock: use driver API instead of direct memory read/write

[Tero Kristo]

Clock nodes shall use the services provided by underlying drivers to access
the hardware registers instead of direct memory read/write. Thus, change
all the code to use the new omap2_clk_readl / omap2_clk_writel APIs for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clkt_clksel.c |   10 +++++-----
 arch/arm/mach-omap2/clkt_dpll.c   |    6 +++---
 arch/arm/mach-omap2/clkt_iclk.c   |   20 ++++++++++++--------
 arch/arm/mach-omap2/clock.c       |   25 +++++++++++++------------
 arch/arm/mach-omap2/clock36xx.c   |    7 ++++---
 arch/arm/mach-omap2/dpll3xxx.c    |   37 ++++++++++++++++++++-----------------
 arch/arm/mach-omap2/dpll44xx.c    |   12 ++++++------
 7 files changed, 63 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 0ec9f6f..7ee2610 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
 {
 	u32 v;
 
-	v = __raw_readl(clk->clksel_reg);
+	v = omap2_clk_readl(clk, clk->clksel_reg);
 	v &= ~clk->clksel_mask;
 	v |= field_val << __ffs(clk->clksel_mask);
-	__raw_writel(v, clk->clksel_reg);
+	omap2_clk_writel(v, clk, clk->clksel_reg);
 
-	v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+	v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */
 }
 
 /**
@@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk)
 	if (!clk->clksel || !clk->clksel_mask)
 		return 0;
 
-	v = __raw_readl(clk->clksel_reg);
+	v = omap2_clk_readl(clk, clk->clksel_reg);
 	v &= clk->clksel_mask;
 	v >>= __ffs(clk->clksel_mask);
 
@@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
 	WARN((!clk->clksel || !clk->clksel_mask),
 	     "clock: %s: attempt to call on a non-clksel clock", clk_name);
 
-	r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+	r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask;
 	r >>= __ffs(clk->clksel_mask);
 
 	for (clks = clk->clksel; clks->parent && !found; clks++) {
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 924c230..47f9562 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
 	if (!dd)
 		return -EINVAL;
 
-	v = __raw_readl(dd->control_reg);
+	v = omap2_clk_readl(clk, dd->control_reg);
 	v &= dd->enable_mask;
 	v >>= __ffs(dd->enable_mask);
 
@@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
 		return 0;
 
 	/* Return bypass rate if DPLL is bypassed */
-	v = __raw_readl(dd->control_reg);
+	v = omap2_clk_readl(clk, dd->control_reg);
 	v &= dd->enable_mask;
 	v >>= __ffs(dd->enable_mask);
 
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
 			return __clk_get_rate(dd->clk_bypass);
 	}
 
-	v = __raw_readl(dd->mult_div1_reg);
+	v = omap2_clk_readl(clk, dd->mult_div1_reg);
 	dpll_mult = v & dd->mult_mask;
 	dpll_mult >>= __ffs(dd->mult_mask);
 	dpll_div = v & dd->div1_mask;
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index f10eb03..333f0a6 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -25,25 +25,29 @@
 /* XXX */
 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
 {
-	u32 v, r;
+	u32 v;
+	void __iomem *r;
 
-	r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+	r = (__force void __iomem *)
+		((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
 
-	v = __raw_readl((__force void __iomem *)r);
+	v = omap2_clk_readl(clk, r);
 	v |= (1 << clk->enable_bit);
-	__raw_writel(v, (__force void __iomem *)r);
+	omap2_clk_writel(v, clk, r);
 }
 
 /* XXX */
 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
 {
-	u32 v, r;
+	u32 v;
+	void __iomem *r;
 
-	r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+	r = (__force void __iomem *)
+		((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
 
-	v = __raw_readl((__force void __iomem *)r);
+	v = omap2_clk_readl(clk, r);
 	v &= ~(1 << clk->enable_bit);
-	__raw_writel(v, (__force void __iomem *)r);
+	omap2_clk_writel(v, clk, r);
 }
 
 /* Public data */
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index be53bb2..591581a 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -111,6 +111,7 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 
 /**
  * _wait_idlest_generic - wait for a module to leave the idle state
+ * @clk: module clock to wait for (needed for register offsets)
  * @reg: virtual address of module IDLEST register
  * @mask: value to mask against to determine if the module is active
  * @idlest: idle state indicator (0 or 1) for the clock
@@ -122,14 +123,14 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
  * elapsed.  XXX Deprecated - should be moved into drivers for the
  * individual IP block that the IDLEST register exists in.
  */
-static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
-				const char *name)
+static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg,
+				u32 mask, u8 idlest, const char *name)
 {
 	int i = 0, ena = 0;
 
 	ena = (idlest) ? 0 : mask;
 
-	omap_test_timeout(((__raw_readl(reg) & mask) == ena),
+	omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena),
 			  MAX_MODULE_ENABLE_WAIT, i);
 
 	if (i < MAX_MODULE_ENABLE_WAIT)
@@ -162,7 +163,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
 	/* Not all modules have multiple clocks that their IDLEST depends on */
 	if (clk->ops->find_companion) {
 		clk->ops->find_companion(clk, &companion_reg, &other_bit);
-		if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+		if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit)))
 			return;
 	}
 
@@ -170,8 +171,8 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
 	r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
 	if (r) {
 		/* IDLEST register not in the CM module */
-		_wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,
-				     __clk_get_name(clk->hw.clk));
+		_wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
+				     idlest_val, __clk_get_name(clk->hw.clk));
 	} else {
 		cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
 	};
@@ -333,13 +334,13 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
 	}
 
 	/* FIXME should not have INVERT_ENABLE bit here */
-	v = __raw_readl(clk->enable_reg);
+	v = omap2_clk_readl(clk, clk->enable_reg);
 	if (clk->flags & INVERT_ENABLE)
 		v &= ~(1 << clk->enable_bit);
 	else
 		v |= (1 << clk->enable_bit);
-	__raw_writel(v, clk->enable_reg);
-	v = __raw_readl(clk->enable_reg); /* OCP barrier */
+	omap2_clk_writel(v, clk, clk->enable_reg);
+	v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */
 
 	if (clk->ops && clk->ops->find_idlest)
 		_omap2_module_wait_ready(clk);
@@ -377,12 +378,12 @@ void omap2_dflt_clk_disable(struct clk_hw *hw)
 		return;
 	}
 
-	v = __raw_readl(clk->enable_reg);
+	v = omap2_clk_readl(clk, clk->enable_reg);
 	if (clk->flags & INVERT_ENABLE)
 		v |= (1 << clk->enable_bit);
 	else
 		v &= ~(1 << clk->enable_bit);
-	__raw_writel(v, clk->enable_reg);
+	omap2_clk_writel(v, clk, clk->enable_reg);
 	/* No OCP barrier needed here since it is a disable operation */
 
 	if (clkdm_control && clk->clkdm)
@@ -478,7 +479,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 	u32 v;
 
-	v = __raw_readl(clk->enable_reg);
+	v = omap2_clk_readl(clk, clk->enable_reg);
 
 	if (clk->flags & INVERT_ENABLE)
 		v ^= BIT(clk->enable_bit);
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index bbd6a3f..91ccb96 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -43,6 +43,7 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 	struct clk_divider *parent;
 	struct clk_hw *parent_hw;
 	u32 dummy_v, orig_v;
+	struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk);
 	int ret;
 
 	/* Clear PWRDN bit of HSDIVIDER */
@@ -53,15 +54,15 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 
 	/* Restore the dividers */
 	if (!ret) {
-		orig_v = __raw_readl(parent->reg);
+		orig_v = omap2_clk_readl(omap_clk, parent->reg);
 		dummy_v = orig_v;
 
 		/* Write any other value different from the Read value */
 		dummy_v ^= (1 << parent->shift);
-		__raw_writel(dummy_v, parent->reg);
+		omap2_clk_writel(dummy_v, omap_clk, parent->reg);
 
 		/* Write the original divider */
-		__raw_writel(orig_v, parent->reg);
+		omap2_clk_writel(orig_v, omap_clk, parent->reg);
 	}
 
 	return ret;
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3a0296c..3185ced 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -50,10 +50,10 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
 
 	dd = clk->dpll_data;
 
-	v = __raw_readl(dd->control_reg);
+	v = omap2_clk_readl(clk, dd->control_reg);
 	v &= ~dd->enable_mask;
 	v |= clken_bits << __ffs(dd->enable_mask);
-	__raw_writel(v, dd->control_reg);
+	omap2_clk_writel(v, clk, dd->control_reg);
 }
 
 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -69,8 +69,8 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
 
 	state <<= __ffs(dd->idlest_mask);
 
-	while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
-	       i < MAX_DPLL_WAIT_TRIES) {
+	while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask)
+		!= state) && i < MAX_DPLL_WAIT_TRIES) {
 		i++;
 		udelay(1);
 	}
@@ -147,7 +147,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
 	state <<= __ffs(dd->idlest_mask);
 
 	/* Check if already locked */
-	if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state)
+	if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state)
 		goto done;
 
 	ai = omap3_dpll_autoidle_read(clk);
@@ -311,14 +311,14 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
 	 * only since freqsel field is no longer present on other devices.
 	 */
 	if (cpu_is_omap343x()) {
-		v = __raw_readl(dd->control_reg);
+		v = omap2_clk_readl(clk, dd->control_reg);
 		v &= ~dd->freqsel_mask;
 		v |= freqsel << __ffs(dd->freqsel_mask);
-		__raw_writel(v, dd->control_reg);
+		omap2_clk_writel(v, clk, dd->control_reg);
 	}
 
 	/* Set DPLL multiplier, divider */
-	v = __raw_readl(dd->mult_div1_reg);
+	v = omap2_clk_readl(clk, dd->mult_div1_reg);
 	v &= ~(dd->mult_mask | dd->div1_mask);
 	v |= dd->last_rounded_m << __ffs(dd->mult_mask);
 	v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
@@ -336,11 +336,11 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
 		v |= sd_div << __ffs(dd->sddiv_mask);
 	}
 
-	__raw_writel(v, dd->mult_div1_reg);
+	omap2_clk_writel(v, clk, dd->mult_div1_reg);
 
 	/* Set 4X multiplier and low-power mode */
 	if (dd->m4xen_mask || dd->lpmode_mask) {
-		v = __raw_readl(dd->control_reg);
+		v = omap2_clk_readl(clk, dd->control_reg);
 
 		if (dd->m4xen_mask) {
 			if (dd->last_rounded_m4xen)
@@ -356,7 +356,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
 				v &= ~dd->lpmode_mask;
 		}
 
-		__raw_writel(v, dd->control_reg);
+		omap2_clk_writel(v, clk, dd->control_reg);
 	}
 
 	/* We let the clock framework set the other output dividers later */
@@ -554,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
 	if (!dd->autoidle_reg)
 		return -EINVAL;
 
-	v = __raw_readl(dd->autoidle_reg);
+	v = omap2_clk_readl(clk, dd->autoidle_reg);
 	v &= dd->autoidle_mask;
 	v >>= __ffs(dd->autoidle_mask);
 
@@ -588,10 +588,10 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
 	 * by writing 0x5 instead of 0x1.  Add some mechanism to
 	 * optionally enter this mode.
 	 */
-	v = __raw_readl(dd->autoidle_reg);
+	v = omap2_clk_readl(clk, dd->autoidle_reg);
 	v &= ~dd->autoidle_mask;
 	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
-	__raw_writel(v, dd->autoidle_reg);
+	omap2_clk_writel(v, clk, dd->autoidle_reg);
 
 }
 
@@ -614,10 +614,10 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
 	if (!dd->autoidle_reg)
 		return;
 
-	v = __raw_readl(dd->autoidle_reg);
+	v = omap2_clk_readl(clk, dd->autoidle_reg);
 	v &= ~dd->autoidle_mask;
 	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
-	__raw_writel(v, dd->autoidle_reg);
+	omap2_clk_writel(v, clk, dd->autoidle_reg);
 
 }
 
@@ -639,6 +639,9 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 	struct clk_hw_omap *pclk = NULL;
 	struct clk *parent;
 
+	if (!parent_rate)
+		return 0;
+
 	/* Walk up the parents of clk, looking for a DPLL */
 	do {
 		do {
@@ -660,7 +663,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 
 	WARN_ON(!dd->enable_mask);
 
-	v = __raw_readl(dd->control_reg) & dd->enable_mask;
+	v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
 	v >>= __ffs(dd->enable_mask);
 	if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
 		rate = parent_rate;
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index d28b0f7..52f9438 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -42,7 +42,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
 			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
 			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
 
-	v = __raw_readl(clk->clksel_reg);
+	v = omap2_clk_readl(clk, clk->clksel_reg);
 	v &= mask;
 	v >>= __ffs(mask);
 
@@ -61,10 +61,10 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
 			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
 			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
 
-	v = __raw_readl(clk->clksel_reg);
+	v = omap2_clk_readl(clk, clk->clksel_reg);
 	/* Clear the bit to allow gatectrl */
 	v &= ~mask;
-	__raw_writel(v, clk->clksel_reg);
+	omap2_clk_writel(v, clk, clk->clksel_reg);
 }
 
 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
@@ -79,10 +79,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
 			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
 			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
 
-	v = __raw_readl(clk->clksel_reg);
+	v = omap2_clk_readl(clk, clk->clksel_reg);
 	/* Set the bit to deny gatectrl */
 	v |= mask;
-	__raw_writel(v, clk->clksel_reg);
+	omap2_clk_writel(v, clk, clk->clksel_reg);
 }
 
 const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
@@ -140,7 +140,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
 	rate = omap2_get_dpll_rate(clk);
 
 	/* regm4xen adds a multiplier of 4 to DPLL calculations */
-	v = __raw_readl(dd->control_reg);
+	v = omap2_clk_readl(clk, dd->control_reg);
 	if (v & OMAP4430_DPLL_REGM4XEN_MASK)
 		rate *= OMAP4430_REGM4XEN_MULT;
 
-- 
1.7.9.5

[PATCHv13 32/40] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm

[Tero Kristo]

If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 8a1b5e0..cc24c95 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -686,6 +686,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
 	if (oh->clkdm) {
 		return oh->clkdm;
 	} else if (oh->_clk) {
+		if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+			return NULL;
 		clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
 		return  clk->clkdm;
 	}
-- 
1.7.9.5

[PATCHv13 34/40] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT

[Tero Kristo]

This patch provides top level functionality for the DT clock initialization.
Clock tree is initialized hierarchically starting from IP modules (CM/PRM/PRCM)
going down towards individual clock nodes, and finally initializing
clockdomains once all the clocks are ready.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm.h        |    1 +
 arch/arm/mach-omap2/prm_common.c |   66 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+)

diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ac25ae6..623db40 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,6 +18,7 @@
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
 extern void omap2_set_globals_prm(void __iomem *prm);
+int of_prcm_init(void);
 # endif
 
 
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index a2e1174..b4c4ab9 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -23,6 +23,10 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
 
 #include "soc.h"
 #include "prm2xxx_3xxx.h"
@@ -30,6 +34,7 @@
 #include "prm3xxx.h"
 #include "prm44xx.h"
 #include "common.h"
+#include "clock.h"
 
 /*
  * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld)
 
 	return 0;
 }
+
+static struct of_device_id omap_prcm_dt_match_table[] = {
+	{ .compatible = "ti,am3-prcm" },
+	{ .compatible = "ti,am3-scrm" },
+	{ .compatible = "ti,am4-prcm" },
+	{ .compatible = "ti,am4-scrm" },
+	{ .compatible = "ti,omap3-prm" },
+	{ .compatible = "ti,omap3-cm" },
+	{ .compatible = "ti,omap3-scrm" },
+	{ .compatible = "ti,omap4-cm1" },
+	{ .compatible = "ti,omap4-prm" },
+	{ .compatible = "ti,omap4-cm2" },
+	{ .compatible = "ti,omap4-scrm" },
+	{ .compatible = "ti,omap5-prm" },
+	{ .compatible = "ti,omap5-cm-core-aon" },
+	{ .compatible = "ti,omap5-scrm" },
+	{ .compatible = "ti,omap5-cm-core" },
+	{ .compatible = "ti,dra7-prm" },
+	{ .compatible = "ti,dra7-cm-core-aon" },
+	{ .compatible = "ti,dra7-cm-core" },
+	{ }
+};
+
+static struct clk_hw_omap memmap_dummy_ck = {
+	.flags = MEMMAP_ADDRESSING,
+};
+
+static u32 prm_clk_readl(void __iomem *reg)
+{
+	return omap2_clk_readl(&memmap_dummy_ck, reg);
+}
+
+static void prm_clk_writel(u32 val, void __iomem *reg)
+{
+	omap2_clk_writel(val, &memmap_dummy_ck, reg);
+}
+
+static struct ti_clk_ll_ops omap_clk_ll_ops = {
+	.clk_readl = prm_clk_readl,
+	.clk_writel = prm_clk_writel,
+};
+
+int __init of_prcm_init(void)
+{
+	struct device_node *np;
+	void __iomem *mem;
+	int memmap_index = 0;
+
+	ti_clk_ll_ops = &omap_clk_ll_ops;
+
+	for_each_matching_node(np, omap_prcm_dt_match_table) {
+		mem = of_iomap(np, 0);
+		clk_memmaps[memmap_index] = mem;
+		ti_dt_clk_init_provider(np, memmap_index);
+		memmap_index++;
+	}
+
+	ti_dt_clockdomains_setup();
+
+	return 0;
+}
-- 
1.7.9.5

[PATCHv13 08/40] CLK: TI: add support for gate clock

[Tero Kristo]

This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
- ti,clkdm-gate-clock: clockdomain level gate control
- ti,dss-gate-clock: gate clock with DSS specific hardware handling
- ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling
- ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 .../devicetree/bindings/clock/ti/gate.txt          |   85 +++++++
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/gate.c                              |  249 ++++++++++++++++++++
 include/linux/clk/ti.h                             |    6 +
 4 files changed, 341 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
 create mode 100644 drivers/clk/ti/gate.c

diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
new file mode 100644
index 0000000..125281a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
@@ -0,0 +1,85 @@
+Binding for Texas Instruments gate clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features. If no register
+is provided for this clock, the code assumes that a clockdomain
+will be controlled instead and the corresponding hw-ops for
+that is used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
+
+Required properties:
+- compatible : shall be one of:
+  "ti,gate-clock" - basic gate clock
+  "ti,wait-gate-clock" - gate clock which waits until clock is active before
+			 returning from clk_enable()
+  "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
+  "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
+  "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
+			  clock directly from a clockdomain, see [3] how
+			  to map clockdomains properly
+  "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
+			  required for a hardware errata
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : offset for register controlling adjustable gate, not needed for
+	ti,clkdm-gate-clock type
+
+Optional properties:
+- ti,bit-shift : bit shift for programming the clock gate, invalid for
+		 ti,clkdm-gate-clock type
+- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
+  gates the clock and clearing the bit ungates the clock.
+
+Examples:
+	mmchs2_fck: mmchs2_fck@48004a00 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&core_96m_fck>;
+		reg = <0x48004a00 0x4>;
+		ti,bit-shift = <25>;
+	};
+
+	uart4_fck_am35xx: uart4_fck_am35xx {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_48m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <23>;
+	};
+
+	dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
+		#clock-cells = <0>;
+		compatible = "ti,dss-gate-clock";
+		clocks = <&dpll4_m4x2_ck>;
+		reg = <0x48004e00 0x4>;
+		ti,bit-shift = <0>;
+	};
+
+	emac_ick: emac_ick@4800259c {
+		#clock-cells = <0>;
+		compatible = "ti,am35xx-gate-clock";
+		clocks = <&ipss_ick>;
+		reg = <0x4800259c 0x4>;
+		ti,bit-shift = <1>;
+	};
+
+	emu_src_ck: emu_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,clkdm-gate-clock";
+		clocks = <&emu_src_mux_ck>;
+	};
+
+	dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+		#clock-cells = <0>;
+		compatible = "ti,hsdiv-gate-clock";
+		clocks = <&dpll4_m2x2_mul_ck>;
+		ti,bit-shift = <0x1b>;
+		reg = <0x48004d00 0x4>;
+		ti,set-bit-to-disable;
+	};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index f57fc4b..7cba389 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o divider.o \
-					   fixed-factor.o composite.o
+					   fixed-factor.o gate.o composite.o
 endif
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
new file mode 100644
index 0000000..3e2999d
--- /dev/null
+++ b/drivers/clk/ti/gate.c
@@ -0,0 +1,249 @@
+/*
+ * OMAP gate clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
+
+static const struct clk_ops omap_gate_clkdm_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_clkops_enable_clkdm,
+	.disable	= &omap2_clkops_disable_clkdm,
+};
+
+static const struct clk_ops omap_gate_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap36xx_gate_clk_enable_with_hsdiv_restore,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+/**
+ * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
+ *         from HSDivider PWRDN problem Implements Errata ID: i556.
+ * @clk: DPLL output struct clk
+ *
+ * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
+ * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
+ * valueafter their respective PWRDN bits are set.  Any dummy write
+ * (Any other value different from the Read value) to the
+ * corresponding CM_CLKSEL register will refresh the dividers.
+ */
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
+{
+	struct clk_divider *parent;
+	struct clk_hw *parent_hw;
+	u32 dummy_v, orig_v;
+	int ret;
+
+	/* Clear PWRDN bit of HSDIVIDER */
+	ret = omap2_dflt_clk_enable(clk);
+
+	/* Parent is the x2 node, get parent of parent for the m2 div */
+	parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
+	parent = to_clk_divider(parent_hw);
+
+	/* Restore the dividers */
+	if (!ret) {
+		orig_v = ti_clk_ll_ops->clk_readl(parent->reg);
+		dummy_v = orig_v;
+
+		/* Write any other value different from the Read value */
+		dummy_v ^= (1 << parent->shift);
+		ti_clk_ll_ops->clk_writel(dummy_v, parent->reg);
+
+		/* Write the original divider */
+		ti_clk_ll_ops->clk_writel(orig_v, parent->reg);
+	}
+
+	return ret;
+}
+
+static void __init _of_ti_gate_clk_setup(struct device_node *node,
+					 const struct clk_ops *ops,
+					 const struct clk_hw_omap_ops *hw_ops)
+{
+	struct clk *clk;
+	struct clk_init_data init = { NULL };
+	struct clk_hw_omap *clk_hw;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	u32 val;
+
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw)
+		return;
+
+	clk_hw->hw.init = &init;
+
+	init.name = clk_name;
+	init.ops = ops;
+
+	if (ops != &omap_gate_clkdm_clk_ops) {
+		clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
+		if (!clk_hw->enable_reg)
+			goto cleanup;
+
+		if (!of_property_read_u32(node, "ti,bit-shift", &val))
+			clk_hw->enable_bit = val;
+	}
+
+	clk_hw->ops = hw_ops;
+
+	clk_hw->flags = MEMMAP_ADDRESSING;
+
+	if (of_clk_get_parent_count(node) != 1) {
+		pr_err("%s must have 1 parent\n", clk_name);
+		goto cleanup;
+	}
+
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	if (of_property_read_bool(node, "ti,set-rate-parent"))
+		init.flags |= CLK_SET_RATE_PARENT;
+
+	if (of_property_read_bool(node, "ti,set-bit-to-disable"))
+		clk_hw->flags |= INVERT_ENABLE;
+
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		return;
+	}
+
+cleanup:
+	kfree(clk_hw);
+}
+
+static void __init
+_of_ti_composite_gate_clk_setup(struct device_node *node,
+				const struct clk_hw_omap_ops *hw_ops)
+{
+	struct clk_hw_omap *gate;
+	u32 val = 0;
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		return;
+
+	gate->enable_reg = ti_clk_get_reg_addr(node, 0);
+	if (!gate->enable_reg)
+		goto cleanup;
+
+	of_property_read_u32(node, "ti,bit-shift", &val);
+
+	gate->enable_bit = val;
+	gate->ops = hw_ops;
+	gate->flags = MEMMAP_ADDRESSING;
+
+	if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
+		return;
+
+cleanup:
+	kfree(gate);
+}
+
+static void __init
+of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
+{
+	_of_ti_composite_gate_clk_setup(node, NULL);
+}
+CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
+	       of_ti_composite_no_wait_gate_clk_setup);
+
+#ifdef CONFIG_ARCH_OMAP3
+static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
+{
+	_of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
+}
+CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
+	       of_ti_composite_interface_clk_setup);
+#endif
+
+static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
+{
+	_of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
+}
+CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
+	       of_ti_composite_gate_clk_setup);
+
+
+static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
+{
+	_of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
+}
+CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
+	       of_ti_clkdm_gate_clk_setup);
+
+static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
+{
+	_of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
+			      &clkhwops_wait);
+}
+CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
+	       of_ti_hsdiv_gate_clk_setup);
+
+static void __init of_ti_gate_clk_setup(struct device_node *node)
+{
+	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
+}
+CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup)
+
+static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
+{
+	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
+}
+CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
+	       of_ti_wait_gate_clk_setup);
+
+#ifdef CONFIG_ARCH_OMAP3
+static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
+{
+	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
+			      &clkhwops_am35xx_ipss_module_wait);
+}
+CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
+	       of_ti_am35xx_gate_clk_setup);
+
+static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
+{
+	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
+			      &clkhwops_omap3430es2_dss_usbhost_wait);
+}
+CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
+	       of_ti_dss_gate_clk_setup);
+#endif
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 17fb49e..d94feb3 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -244,6 +244,8 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 void omap2_init_clk_clkdm(struct clk_hw *clk);
 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 				    unsigned long parent_rate);
+int omap2_clkops_enable_clkdm(struct clk_hw *hw);
+void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 			 unsigned long parent_rate);
 int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -268,5 +270,9 @@ static inline void of_ti_clk_deny_autoidle_all(void) { }
 
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+extern const struct clk_hw_omap_ops clkhwops_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 
 #endif
-- 
1.7.9.5

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[PATCHv13 13/40] CLK: TI: omap5: Initialize USB_DPLL at boot

[Tero Kristo]

From: Roger Quadros <rogerq-l0cyMroinI0@public.gmane.org>

USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Signed-off-by: Roger Quadros <rogerq-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Tested-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
Acked-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 drivers/clk/ti/clk-54xx.c |   18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index c876e6e..0ef9f58 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -19,6 +19,12 @@
 
 #define OMAP5_DPLL_ABE_DEFFREQ				98304000
 
+/*
+ * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
+ * states it must be at 960MHz
+ */
+#define OMAP5_DPLL_USB_DEFFREQ				960000000
+
 static struct ti_dt_clk omap54xx_clks[] = {
 	DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
 	DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
@@ -220,7 +226,7 @@ static struct ti_dt_clk omap54xx_clks[] = {
 int __init omap5xxx_dt_clk_init(void)
 {
 	int rc;
-	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
 
 	ti_dt_clocks_register(omap54xx_clks);
 
@@ -235,5 +241,15 @@ int __init omap5xxx_dt_clk_init(void)
 	if (rc)
 		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
+	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+	rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+	usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
+	rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
+	if (rc)
+		pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
+
 	return 0;
 }
-- 
1.7.9.5

--
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[PATCHv13 14/40] CLK: TI: DRA7: Add APLL support

[Tero Kristo]

From: J Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org>

The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.

APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.

Signed-off-by: J Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 .../devicetree/bindings/clock/ti/apll.txt          |   31 +++
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/apll.c                              |  223 ++++++++++++++++++++
 3 files changed, 255 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt
 create mode 100644 drivers/clk/ti/apll.c

diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt
new file mode 100644
index 0000000..7faf5a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
@@ -0,0 +1,31 @@
+Binding for Texas Instruments APLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped APLL with usually two selectable input clocks
+(reference clock and bypass clock), with analog phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) APLL mostly behaves like
+a subtype of a DPLL [2], although a simplified one at that.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
+
+Required properties:
+- compatible : shall be "ti,dra7-apll-clock"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : address and length of the register set for controlling the APLL.
+  It contains the information of registers in the following order:
+	"control" - contains the control register base address
+	"idlest" - contains the idlest register base address
+
+Examples:
+	apll_pcie_ck: apll_pcie_ck@4a008200 {
+		#clock-cells = <0>;
+		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+		reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
+		compatible = "ti,dra7-apll-clock";
+	};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 935e5d2..3d71e1e 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o divider.o \
 					   fixed-factor.o gate.o clockdomain.o \
-					   composite.o mux.o
+					   composite.o mux.o apll.o
 obj-$(CONFIG_ARCH_OMAP4)		+= clk-44xx.o
 obj-$(CONFIG_SOC_OMAP5)			+= clk-54xx.o
 endif
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
new file mode 100644
index 0000000..b986f61
--- /dev/null
+++ b/drivers/clk/ti/apll.c
@@ -0,0 +1,223 @@
+/*
+ * OMAP APLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * J Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+#include <linux/delay.h>
+
+#define APLL_FORCE_LOCK 0x1
+#define APLL_AUTO_IDLE	0x2
+#define MAX_APLL_WAIT_TRIES		1000000
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+static int dra7_apll_enable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	int r = 0, i = 0;
+	struct dpll_data *ad;
+	const char *clk_name;
+	u8 state = 1;
+	u32 v;
+
+	ad = clk->dpll_data;
+	if (!ad)
+		return -EINVAL;
+
+	clk_name = __clk_get_name(clk->hw.clk);
+
+	state <<= __ffs(ad->idlest_mask);
+
+	/* Check is already locked */
+	v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
+
+	if ((v & ad->idlest_mask) == state)
+		return r;
+
+	v = ti_clk_ll_ops->clk_readl(ad->control_reg);
+	v &= ~ad->enable_mask;
+	v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
+	ti_clk_ll_ops->clk_writel(v, ad->control_reg);
+
+	state <<= __ffs(ad->idlest_mask);
+
+	while (1) {
+		v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
+		if ((v & ad->idlest_mask) == state)
+			break;
+		if (i > MAX_APLL_WAIT_TRIES)
+			break;
+		i++;
+		udelay(1);
+	}
+
+	if (i == MAX_APLL_WAIT_TRIES) {
+		pr_warn("clock: %s failed transition to '%s'\n",
+			clk_name, (state) ? "locked" : "bypassed");
+	} else {
+		pr_debug("clock: %s transition to '%s' in %d loops\n",
+			 clk_name, (state) ? "locked" : "bypassed", i);
+
+		r = 0;
+	}
+
+	return r;
+}
+
+static void dra7_apll_disable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	struct dpll_data *ad;
+	u8 state = 1;
+	u32 v;
+
+	ad = clk->dpll_data;
+
+	state <<= __ffs(ad->idlest_mask);
+
+	v = ti_clk_ll_ops->clk_readl(ad->control_reg);
+	v &= ~ad->enable_mask;
+	v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
+	ti_clk_ll_ops->clk_writel(v, ad->control_reg);
+}
+
+static int dra7_apll_is_enabled(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	struct dpll_data *ad;
+	u32 v;
+
+	ad = clk->dpll_data;
+
+	v = ti_clk_ll_ops->clk_readl(ad->control_reg);
+	v &= ad->enable_mask;
+
+	v >>= __ffs(ad->enable_mask);
+
+	return v == APLL_AUTO_IDLE ? 0 : 1;
+}
+
+static u8 dra7_init_apll_parent(struct clk_hw *hw)
+{
+	return 0;
+}
+
+static const struct clk_ops apll_ck_ops = {
+	.enable		= &dra7_apll_enable,
+	.disable	= &dra7_apll_disable,
+	.is_enabled	= &dra7_apll_is_enabled,
+	.get_parent	= &dra7_init_apll_parent,
+};
+
+static void __init omap_clk_register_apll(struct clk_hw *hw,
+					  struct device_node *node)
+{
+	struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
+	struct dpll_data *ad = clk_hw->dpll_data;
+	struct clk *clk;
+
+	ad->clk_ref = of_clk_get(node, 0);
+	ad->clk_bypass = of_clk_get(node, 1);
+
+	if (IS_ERR(ad->clk_ref) || IS_ERR(ad->clk_bypass)) {
+		pr_debug("clk-ref or clk-bypass for %s not ready, retry\n",
+			 node->name);
+		if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
+			return;
+
+		goto cleanup;
+	}
+
+	clk = clk_register(NULL, &clk_hw->hw);
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		kfree(clk_hw->hw.init->parent_names);
+		kfree(clk_hw->hw.init);
+		return;
+	}
+
+cleanup:
+	kfree(clk_hw->dpll_data);
+	kfree(clk_hw->hw.init->parent_names);
+	kfree(clk_hw->hw.init);
+	kfree(clk_hw);
+}
+
+static void __init of_dra7_apll_setup(struct device_node *node)
+{
+	struct dpll_data *ad = NULL;
+	struct clk_hw_omap *clk_hw = NULL;
+	struct clk_init_data *init = NULL;
+	const char **parent_names = NULL;
+	int i;
+
+	ad = kzalloc(sizeof(*ad), GFP_KERNEL);
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	init = kzalloc(sizeof(*init), GFP_KERNEL);
+	if (!ad || !clk_hw || !init)
+		goto cleanup;
+
+	clk_hw->dpll_data = ad;
+	clk_hw->hw.init = init;
+	clk_hw->flags = MEMMAP_ADDRESSING;
+
+	init->name = node->name;
+	init->ops = &apll_ck_ops;
+
+	init->num_parents = of_clk_get_parent_count(node);
+	if (init->num_parents < 1) {
+		pr_err("dra7 apll %s must have parent(s)\n", node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
+	if (!parent_names)
+		goto cleanup;
+
+	for (i = 0; i < init->num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	init->parent_names = parent_names;
+
+	ad->control_reg = ti_clk_get_reg_addr(node, 0);
+	ad->idlest_reg = ti_clk_get_reg_addr(node, 1);
+
+	if (!ad->control_reg || !ad->idlest_reg)
+		goto cleanup;
+
+	ad->idlest_mask = 0x1;
+	ad->enable_mask = 0x3;
+
+	omap_clk_register_apll(&clk_hw->hw, node);
+	return;
+
+cleanup:
+	kfree(parent_names);
+	kfree(ad);
+	kfree(clk_hw);
+	kfree(init);
+}
+CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
-- 
1.7.9.5

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[PATCHv13 17/40] CLK: TI: add interface clock support for OMAP3

[Tero Kristo]

OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 .../devicetree/bindings/clock/ti/interface.txt     |   54 +++++++++
 arch/arm/mach-omap2/clock.h                        |    5 -
 drivers/clk/ti/Makefile                            |    1 +
 drivers/clk/ti/interface.c                         |  125 ++++++++++++++++++++
 include/linux/clk/ti.h                             |    5 +
 5 files changed, 185 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt
 create mode 100644 drivers/clk/ti/interface.c

diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt
new file mode 100644
index 0000000..064e8ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
@@ -0,0 +1,54 @@
+Binding for Texas Instruments interface clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features, including
+companion clock finding (match corresponding functional gate
+clock) and hardware autoidle enable / disable.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+
+Required properties:
+- compatible : shall be one of:
+  "ti,omap3-interface-clock" - basic OMAP3 interface clock
+  "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
+				       capability for waiting clock to be ready
+  "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
+					handling
+  "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
+  "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
+  "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : base address for the control register
+
+Optional properties:
+- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
+
+Examples:
+	aes1_ick: aes1_ick@48004a14 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&security_l4_ick2>;
+		reg = <0x48004a14 0x4>;
+		ti,bit-shift = <3>;
+	};
+
+	cam_ick: cam_ick@48004f10 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-no-wait-interface-clock";
+		clocks = <&l4_ick>;
+		reg = <0x48004f10 0x4>;
+		ti,bit-shift = <0>;
+	};
+
+	ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-ssi-interface-clock";
+		clocks = <&ssi_l4_ick>;
+		reg = <0x48004a10 0x4>;
+		ti,bit-shift = <0>;
+	};
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 1da9dc3..cbe5ff7 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -270,15 +270,10 @@ extern struct clk dummy_ck;
 
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
 extern const struct clk_hw_omap_ops clkhwops_apll54;
 extern const struct clk_hw_omap_ops clkhwops_apll96;
 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 7eb6f2b..e42a703 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,6 +3,7 @@ obj-y					+= clk.o dpll.o autoidle.o divider.o \
 					   fixed-factor.o gate.o clockdomain.o \
 					   composite.o mux.o apll.o
 obj-$(CONFIG_SOC_AM33XX)		+= clk-33xx.o
+obj-$(CONFIG_ARCH_OMAP3)		+= interface.o
 obj-$(CONFIG_ARCH_OMAP4)		+= clk-44xx.o
 obj-$(CONFIG_SOC_OMAP5)			+= clk-54xx.o
 obj-$(CONFIG_SOC_DRA7XX)		+= clk-7xx.o
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
new file mode 100644
index 0000000..320a2b1
--- /dev/null
+++ b/drivers/clk/ti/interface.c
@@ -0,0 +1,125 @@
+/*
+ * OMAP interface clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+static const struct clk_ops ti_interface_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+static void __init _of_ti_interface_clk_setup(struct device_node *node,
+					      const struct clk_hw_omap_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init = { NULL };
+	struct clk_hw_omap *clk_hw;
+	const char *parent_name;
+	u32 val;
+
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw)
+		return;
+
+	clk_hw->hw.init = &init;
+	clk_hw->ops = ops;
+	clk_hw->flags = MEMMAP_ADDRESSING;
+
+	clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
+	if (!clk_hw->enable_reg)
+		goto cleanup;
+
+	if (!of_property_read_u32(node, "ti,bit-shift", &val))
+		clk_hw->enable_bit = val;
+
+	init.name = node->name;
+	init.ops = &ti_interface_clk_ops;
+	init.flags = 0;
+
+	parent_name = of_clk_get_parent_name(node, 0);
+	if (!parent_name) {
+		pr_err("%s must have a parent\n", node->name);
+		goto cleanup;
+	}
+
+	init.num_parents = 1;
+	init.parent_names = &parent_name;
+
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		omap2_init_clk_hw_omap_clocks(clk);
+		return;
+	}
+
+cleanup:
+	kfree(clk_hw);
+}
+
+static void __init of_ti_interface_clk_setup(struct device_node *node)
+{
+	_of_ti_interface_clk_setup(node, &clkhwops_iclk_wait);
+}
+CLK_OF_DECLARE(ti_interface_clk, "ti,omap3-interface-clock",
+	       of_ti_interface_clk_setup);
+
+static void __init of_ti_no_wait_interface_clk_setup(struct device_node *node)
+{
+	_of_ti_interface_clk_setup(node, &clkhwops_iclk);
+}
+CLK_OF_DECLARE(ti_no_wait_interface_clk, "ti,omap3-no-wait-interface-clock",
+	       of_ti_no_wait_interface_clk_setup);
+
+static void __init of_ti_hsotgusb_interface_clk_setup(struct device_node *node)
+{
+	_of_ti_interface_clk_setup(node,
+				   &clkhwops_omap3430es2_iclk_hsotgusb_wait);
+}
+CLK_OF_DECLARE(ti_hsotgusb_interface_clk, "ti,omap3-hsotgusb-interface-clock",
+	       of_ti_hsotgusb_interface_clk_setup);
+
+static void __init of_ti_dss_interface_clk_setup(struct device_node *node)
+{
+	_of_ti_interface_clk_setup(node,
+				   &clkhwops_omap3430es2_iclk_dss_usbhost_wait);
+}
+CLK_OF_DECLARE(ti_dss_interface_clk, "ti,omap3-dss-interface-clock",
+	       of_ti_dss_interface_clk_setup);
+
+static void __init of_ti_ssi_interface_clk_setup(struct device_node *node)
+{
+	_of_ti_interface_clk_setup(node, &clkhwops_omap3430es2_iclk_ssi_wait);
+}
+CLK_OF_DECLARE(ti_ssi_interface_clk, "ti,omap3-ssi-interface-clock",
+	       of_ti_ssi_interface_clk_setup);
+
+static void __init of_ti_am35xx_interface_clk_setup(struct device_node *node)
+{
+	_of_ti_interface_clk_setup(node, &clkhwops_am35xx_ipss_wait);
+}
+CLK_OF_DECLARE(ti_am35xx_interface_clk, "ti,am35xx-interface-clock",
+	       of_ti_am35xx_interface_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 0e7c8d9..17c034e 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -282,6 +282,11 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 extern const struct clk_hw_omap_ops clkhwops_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 
 #endif
-- 
1.7.9.5

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[PATCHv13 19/40] CLK: TI: add am43xx clock init file

[Tero Kristo]

clk-43xx.c now contains the clock init functionality for am43xx, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Tested-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
Acked-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 drivers/clk/ti/Makefile   |    2 +-
 drivers/clk/ti/clk-43xx.c |  118 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h    |    1 +
 3 files changed, 120 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk-43xx.c

diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index ab386c8..007c3c2 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o divider.o \
 					   fixed-factor.o gate.o clockdomain.o \
-					   composite.o mux.o apll.o
+					   composite.o mux.o apll.o clk-43xx.o
 obj-$(CONFIG_SOC_AM33XX)		+= clk-33xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= interface.o clk-3xxx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= clk-44xx.o
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
new file mode 100644
index 0000000..67c8de5
--- /dev/null
+++ b/drivers/clk/ti/clk-43xx.c
@@ -0,0 +1,118 @@
+/*
+ * AM43XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ *     Tero Kristo (t-kristo-l0cyMroinI0@public.gmane.org)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+static struct ti_dt_clk am43xx_clks[] = {
+	DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
+	DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
+	DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+	DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
+	DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
+	DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+	DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+	DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
+	DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+	DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+	DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
+	DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
+	DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
+	DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+	DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+	DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+	DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+	DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
+	DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
+	DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+	DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+	DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
+	DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
+	DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
+	DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
+	DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
+	DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
+	DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
+	DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
+	DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
+	DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
+	DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
+	DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
+	DT_CLK(NULL, "sha0_fck", "sha0_fck"),
+	DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+	DT_CLK(NULL, "timer1_fck", "timer1_fck"),
+	DT_CLK(NULL, "timer2_fck", "timer2_fck"),
+	DT_CLK(NULL, "timer3_fck", "timer3_fck"),
+	DT_CLK(NULL, "timer4_fck", "timer4_fck"),
+	DT_CLK(NULL, "timer5_fck", "timer5_fck"),
+	DT_CLK(NULL, "timer6_fck", "timer6_fck"),
+	DT_CLK(NULL, "timer7_fck", "timer7_fck"),
+	DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+	DT_CLK(NULL, "l3_gclk", "l3_gclk"),
+	DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
+	DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
+	DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
+	DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
+	DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
+	DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
+	DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
+	DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
+	DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
+	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+	DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+	DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+	DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+	DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+	DT_CLK(NULL, "mmc_clk", "mmc_clk"),
+	DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
+	DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
+	DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK(NULL, "sysclk_div", "sysclk_div"),
+	DT_CLK(NULL, "disp_clk", "disp_clk"),
+	DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
+	DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
+	DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
+	DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
+	DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
+	DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
+	DT_CLK(NULL, "timer8_fck", "timer8_fck"),
+	DT_CLK(NULL, "timer9_fck", "timer9_fck"),
+	DT_CLK(NULL, "timer10_fck", "timer10_fck"),
+	DT_CLK(NULL, "timer11_fck", "timer11_fck"),
+	DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
+	DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
+	DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
+	DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
+	DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
+	DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
+	DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
+	DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
+	DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
+	DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
+	{ .node_name = NULL },
+};
+
+int __init am43xx_dt_clk_init(void)
+{
+	ti_dt_clocks_register(am43xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 3d2ba57..092b641 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -273,6 +273,7 @@ int omap4xxx_dt_clk_init(void);
 int omap5xxx_dt_clk_init(void);
 int dra7xx_dt_clk_init(void);
 int am33xx_dt_clk_init(void);
+int am43xx_dt_clk_init(void);
 
 #ifdef CONFIG_OF
 void of_ti_clk_allow_autoidle_all(void);
-- 
1.7.9.5

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[PATCHv13 21/40] ARM: dts: omap5 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/omap5.dtsi           |   54 ++
 arch/arm/boot/dts/omap54xx-clocks.dtsi | 1399 ++++++++++++++++++++++++++++++++
 2 files changed, 1453 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap54xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index fc3fad5..2f12a47 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -107,6 +107,58 @@
 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+		prm: prm@4ae06000 {
+			compatible = "ti,omap5-prm";
+			reg = <0x4ae06000 0x3000>;
+
+			prm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			prm_clockdomains: clockdomains {
+			};
+		};
+
+		cm_core_aon: cm_core_aon@4a004000 {
+			compatible = "ti,omap5-cm-core-aon";
+			reg = <0x4a004000 0x2000>;
+
+			cm_core_aon_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cm_core_aon_clockdomains: clockdomains {
+			};
+		};
+
+		scrm: scrm@4ae0a000 {
+			compatible = "ti,omap5-scrm";
+			reg = <0x4ae0a000 0x2000>;
+
+			scrm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			scrm_clockdomains: clockdomains {
+			};
+		};
+
+		cm_core: cm_core@4a008000 {
+			compatible = "ti,omap5-cm-core";
+			reg = <0x4a008000 0x3000>;
+
+			cm_core_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cm_core_clockdomains: clockdomains {
+			};
+		};
+
 		counter32k: counter@4ae04000 {
 			compatible = "ti,omap-counter32k";
 			reg = <0x4ae04000 0x40>;
@@ -739,3 +791,5 @@
 		};
 	};
 };
+
+/include/ "omap54xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 0000000..d487fda
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1399 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+	pad_clks_src_ck: pad_clks_src_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	pad_clks_ck: pad_clks_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&pad_clks_src_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0108>;
+	};
+
+	secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	slimbus_src_clk: slimbus_src_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	slimbus_clk: slimbus_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&slimbus_src_clk>;
+		ti,bit-shift = <10>;
+		reg = <0x0108>;
+	};
+
+	sys_32k_ck: sys_32k_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	virt_12000000_ck: virt_12000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	virt_13000000_ck: virt_13000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <13000000>;
+	};
+
+	virt_16800000_ck: virt_16800000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <16800000>;
+	};
+
+	virt_19200000_ck: virt_19200000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <19200000>;
+	};
+
+	virt_26000000_ck: virt_26000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+	};
+
+	virt_27000000_ck: virt_27000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <27000000>;
+	};
+
+	virt_38400000_ck: virt_38400000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <38400000>;
+	};
+
+	xclk60mhsp1_ck: xclk60mhsp1_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <60000000>;
+	};
+
+	xclk60mhsp2_ck: xclk60mhsp2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <60000000>;
+	};
+
+	dpll_abe_ck: dpll_abe_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-m4xen-clock";
+		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+	};
+
+	dpll_abe_x2_ck: dpll_abe_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_abe_ck>;
+	};
+
+	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01f0>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	abe_24m_fclk: abe_24m_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <8>;
+	};
+
+	abe_clk: abe_clk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_m2x2_ck>;
+		ti,max-div = <4>;
+		reg = <0x0108>;
+		ti,index-power-of-two;
+	};
+
+	abe_iclk: abe_iclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&abe_clk>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	abe_lp_clk_div: abe_lp_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <16>;
+	};
+
+	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01f4>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_ck: dpll_core_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-core-clock";
+		clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+	};
+
+	dpll_core_x2_ck: dpll_core_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_core_ck>;
+	};
+
+	dpll_core_h21x2_ck: dpll_core_h21x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0150>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	c2c_fclk: c2c_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_h21x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	c2c_iclk: c2c_iclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&c2c_fclk>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	dpll_core_h11x2_ck: dpll_core_h11x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0138>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x013c>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0140>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0144>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0154>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0158>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x015c>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_m2_ck: dpll_core_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0130>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0134>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_h12x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_iva_ck: dpll_iva_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+	};
+
+	dpll_iva_x2_ck: dpll_iva_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_iva_ck>;
+	};
+
+	dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_iva_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01b8>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_iva_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01bc>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_h12x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_mpu_ck: dpll_mpu_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+	};
+
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_mpu_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0170>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m3x2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_abe_m3x2_ck>;
+		clock-mult = <1>;
+		clock-div = <3>;
+	};
+
+	l3_iclk_div: l3_iclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_h12x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	gpu_l3_iclk: gpu_l3_iclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l3_iclk_div>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	l4_root_clk_div: l4_root_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l3_iclk_div>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&slimbus_clk>;
+		ti,bit-shift = <11>;
+		reg = <0x0560>;
+	};
+
+	aess_fclk: aess_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&abe_clk>;
+		ti,bit-shift = <24>;
+		ti,max-div = <2>;
+		reg = <0x0528>;
+	};
+
+	dmic_sync_mux_ck: dmic_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+		ti,bit-shift = <26>;
+		reg = <0x0538>;
+	};
+
+	dmic_gfclk: dmic_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0538>;
+	};
+
+	mcasp_sync_mux_ck: mcasp_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+		ti,bit-shift = <26>;
+		reg = <0x0540>;
+	};
+
+	mcasp_gfclk: mcasp_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0540>;
+	};
+
+	mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+		ti,bit-shift = <26>;
+		reg = <0x0548>;
+	};
+
+	mcbsp1_gfclk: mcbsp1_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0548>;
+	};
+
+	mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+		ti,bit-shift = <26>;
+		reg = <0x0550>;
+	};
+
+	mcbsp2_gfclk: mcbsp2_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0550>;
+	};
+
+	mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+		ti,bit-shift = <26>;
+		reg = <0x0558>;
+	};
+
+	mcbsp3_gfclk: mcbsp3_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+		ti,bit-shift = <24>;
+		reg = <0x0558>;
+	};
+
+	timer5_gfclk_mux: timer5_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0568>;
+	};
+
+	timer6_gfclk_mux: timer6_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0570>;
+	};
+
+	timer7_gfclk_mux: timer7_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0578>;
+	};
+
+	timer8_gfclk_mux: timer8_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x0580>;
+	};
+
+	dummy_ck: dummy_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+};
+&prm_clocks {
+	sys_clkin: sys_clkin {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+		reg = <0x0110>;
+		ti,index-starts-at-one;
+	};
+
+	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&sys_32k_ck>;
+		reg = <0x0108>;
+	};
+
+	abe_dpll_clk_mux: abe_dpll_clk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&sys_32k_ck>;
+		reg = <0x010c>;
+	};
+
+	custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	dss_syc_gfclk_div: dss_syc_gfclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	wkupaon_iclk_mux: wkupaon_iclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+		reg = <0x0108>;
+	};
+
+	l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&wkupaon_iclk_mux>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	gpio1_dbclk: gpio1_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1938>;
+	};
+
+	timer1_gfclk_mux: timer1_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1940>;
+	};
+};
+&cm_core_clocks {
+	dpll_per_ck: dpll_per_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+	};
+
+	dpll_per_x2_ck: dpll_per_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-x2-clock";
+		clocks = <&dpll_per_ck>;
+	};
+
+	dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0158>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x015c>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <63>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0164>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_m2_ck: dpll_per_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0150>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0150>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0154>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_unipro1_ck: dpll_unipro1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin>, <&sys_clkin>;
+		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+	};
+
+	dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_unipro1_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_unipro1_ck>;
+		ti,max-div = <127>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0210>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_unipro2_ck: dpll_unipro2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-clock";
+		clocks = <&sys_clkin>, <&sys_clkin>;
+		reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
+	};
+
+	dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_unipro2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_unipro2_ck>;
+		ti,max-div = <127>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01d0>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_usb_ck: dpll_usb_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-j-type-clock";
+		clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+	};
+
+	dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_usb_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_usb_m2_ck: dpll_usb_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_usb_ck>;
+		ti,max-div = <127>;
+		ti,autoidle-shift = <8>;
+		reg = <0x0190>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	func_128m_clk: func_128m_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_h11x2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	func_12m_fclk: func_12m_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <16>;
+	};
+
+	func_24m_clk: func_24m_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	func_48m_fclk: func_48m_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	func_96m_fclk: func_96m_fclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	l3init_60m_fclk: l3init_60m_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_usb_m2_ck>;
+		reg = <0x0104>;
+		ti,dividers = <1>, <8>;
+	};
+
+	dss_32khz_clk: dss_32khz_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <11>;
+		reg = <0x1420>;
+	};
+
+	dss_48mhz_clk: dss_48mhz_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&func_48m_fclk>;
+		ti,bit-shift = <9>;
+		reg = <0x1420>;
+	};
+
+	dss_dss_clk: dss_dss_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_per_h12x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1420>;
+	};
+
+	dss_sys_clk: dss_sys_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dss_syc_gfclk_div>;
+		ti,bit-shift = <10>;
+		reg = <0x1420>;
+	};
+
+	gpio2_dbclk: gpio2_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1060>;
+	};
+
+	gpio3_dbclk: gpio3_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1068>;
+	};
+
+	gpio4_dbclk: gpio4_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1070>;
+	};
+
+	gpio5_dbclk: gpio5_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1078>;
+	};
+
+	gpio6_dbclk: gpio6_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1080>;
+	};
+
+	gpio7_dbclk: gpio7_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1110>;
+	};
+
+	gpio8_dbclk: gpio8_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1118>;
+	};
+
+	iss_ctrlclk: iss_ctrlclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&func_96m_fclk>;
+		ti,bit-shift = <8>;
+		reg = <0x1320>;
+	};
+
+	lli_txphy_clk: lli_txphy_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_unipro1_clkdcoldo>;
+		ti,bit-shift = <8>;
+		reg = <0x0f20>;
+	};
+
+	lli_txphy_ls_clk: lli_txphy_ls_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_unipro1_m2_ck>;
+		ti,bit-shift = <9>;
+		reg = <0x0f20>;
+	};
+
+	mmc1_32khz_clk: mmc1_32khz_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1628>;
+	};
+
+	sata_ref_clk: sata_ref_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_clkin>;
+		ti,bit-shift = <8>;
+		reg = <0x1688>;
+	};
+
+	usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_m2_ck>;
+		ti,bit-shift = <13>;
+		reg = <0x1658>;
+	};
+
+	usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_m2_ck>;
+		ti,bit-shift = <14>;
+		reg = <0x1658>;
+	};
+
+	usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_m2_ck>;
+		ti,bit-shift = <7>;
+		reg = <0x1658>;
+	};
+
+	usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3init_60m_fclk>;
+		ti,bit-shift = <11>;
+		reg = <0x1658>;
+	};
+
+	usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3init_60m_fclk>;
+		ti,bit-shift = <12>;
+		reg = <0x1658>;
+	};
+
+	usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3init_60m_fclk>;
+		ti,bit-shift = <6>;
+		reg = <0x1658>;
+	};
+
+	utmi_p1_gfclk: utmi_p1_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1658>;
+	};
+
+	usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&utmi_p1_gfclk>;
+		ti,bit-shift = <8>;
+		reg = <0x1658>;
+	};
+
+	utmi_p2_gfclk: utmi_p2_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
+		ti,bit-shift = <25>;
+		reg = <0x1658>;
+	};
+
+	usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&utmi_p2_gfclk>;
+		ti,bit-shift = <9>;
+		reg = <0x1658>;
+	};
+
+	usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3init_60m_fclk>;
+		ti,bit-shift = <10>;
+		reg = <0x1658>;
+	};
+
+	usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_clkdcoldo>;
+		ti,bit-shift = <8>;
+		reg = <0x16f0>;
+	};
+
+	usb_phy_cm_clk32k: usb_phy_cm_clk32k {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0640>;
+	};
+
+	usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3init_60m_fclk>;
+		ti,bit-shift = <8>;
+		reg = <0x1668>;
+	};
+
+	usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3init_60m_fclk>;
+		ti,bit-shift = <9>;
+		reg = <0x1668>;
+	};
+
+	usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3init_60m_fclk>;
+		ti,bit-shift = <10>;
+		reg = <0x1668>;
+	};
+
+	fdif_fclk: fdif_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_h11x2_ck>;
+		ti,bit-shift = <24>;
+		ti,max-div = <2>;
+		reg = <0x1328>;
+	};
+
+	gpu_core_gclk_mux: gpu_core_gclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1520>;
+	};
+
+	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+		ti,bit-shift = <25>;
+		reg = <0x1520>;
+	};
+
+	hsi_fclk: hsi_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		ti,max-div = <2>;
+		reg = <0x1638>;
+	};
+
+	mmc1_fclk_mux: mmc1_fclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1628>;
+	};
+
+	mmc1_fclk: mmc1_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&mmc1_fclk_mux>;
+		ti,bit-shift = <25>;
+		ti,max-div = <2>;
+		reg = <0x1628>;
+	};
+
+	mmc2_fclk_mux: mmc2_fclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1630>;
+	};
+
+	mmc2_fclk: mmc2_fclk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&mmc2_fclk_mux>;
+		ti,bit-shift = <25>;
+		ti,max-div = <2>;
+		reg = <0x1630>;
+	};
+
+	timer10_gfclk_mux: timer10_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1028>;
+	};
+
+	timer11_gfclk_mux: timer11_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1030>;
+	};
+
+	timer2_gfclk_mux: timer2_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1038>;
+	};
+
+	timer3_gfclk_mux: timer3_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1040>;
+	};
+
+	timer4_gfclk_mux: timer4_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1048>;
+	};
+
+	timer9_gfclk_mux: timer9_gfclk_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&sys_32k_ck>;
+		ti,bit-shift = <24>;
+		reg = <0x1050>;
+	};
+};
+
+&cm_core_clockdomains {
+	l3init_clkdm: l3init_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dpll_usb_ck>;
+	};
+};
+
+&scrm_clocks {
+	auxclk0_src_gate_ck: auxclk0_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0310>;
+	};
+
+	auxclk0_src_mux_ck: auxclk0_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0310>;
+	};
+
+	auxclk0_src_ck: auxclk0_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+	};
+
+	auxclk0_ck: auxclk0_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk0_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x0310>;
+	};
+
+	auxclk1_src_gate_ck: auxclk1_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0314>;
+	};
+
+	auxclk1_src_mux_ck: auxclk1_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0314>;
+	};
+
+	auxclk1_src_ck: auxclk1_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+	};
+
+	auxclk1_ck: auxclk1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk1_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x0314>;
+	};
+
+	auxclk2_src_gate_ck: auxclk2_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0318>;
+	};
+
+	auxclk2_src_mux_ck: auxclk2_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0318>;
+	};
+
+	auxclk2_src_ck: auxclk2_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+	};
+
+	auxclk2_ck: auxclk2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk2_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x0318>;
+	};
+
+	auxclk3_src_gate_ck: auxclk3_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x031c>;
+	};
+
+	auxclk3_src_mux_ck: auxclk3_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x031c>;
+	};
+
+	auxclk3_src_ck: auxclk3_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+	};
+
+	auxclk3_ck: auxclk3_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk3_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x031c>;
+	};
+
+	auxclk4_src_gate_ck: auxclk4_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_core_m3x2_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x0320>;
+	};
+
+	auxclk4_src_mux_ck: auxclk4_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0320>;
+	};
+
+	auxclk4_src_ck: auxclk4_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+	};
+
+	auxclk4_ck: auxclk4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&auxclk4_src_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <16>;
+		reg = <0x0320>;
+	};
+
+	auxclkreq0_ck: auxclkreq0_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x0210>;
+	};
+
+	auxclkreq1_ck: auxclkreq1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x0214>;
+	};
+
+	auxclkreq2_ck: auxclkreq2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x0218>;
+	};
+
+	auxclkreq3_ck: auxclkreq3_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x021c>;
+	};
+};
-- 
1.7.9.5

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[PATCHv13 26/40] ARM: dts: am33xx clock data

[Tero Kristo]

This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/am33xx-clocks.dtsi |  664 ++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/am33xx.dtsi        |   28 ++
 2 files changed, 692 insertions(+)
 create mode 100644 arch/arm/boot/dts/am33xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 0000000..9ccfe50
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,664 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+	sys_clkin_ck: sys_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+		ti,bit-shift = <22>;
+		reg = <0x0040>;
+	};
+
+	adc_tsc_fck: adc_tsc_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dcan0_fck: dcan0_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dcan1_fck: dcan1_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	mcasp0_fck: mcasp0_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	mcasp1_fck: mcasp1_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	smartreflex0_fck: smartreflex0_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	smartreflex1_fck: smartreflex1_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	sha0_fck: sha0_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	aes0_fck: aes0_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	rng_fck: rng_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_per_m2_ck>;
+		ti,bit-shift = <0>;
+		reg = <0x0664>;
+	};
+
+	ehrpwm0_tbclk: ehrpwm0_tbclk {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&ehrpwm0_gate_tbclk>;
+	};
+
+	ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_per_m2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0664>;
+	};
+
+	ehrpwm1_tbclk: ehrpwm1_tbclk {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&ehrpwm1_gate_tbclk>;
+	};
+
+	ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&dpll_per_m2_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x0664>;
+	};
+
+	ehrpwm2_tbclk: ehrpwm2_tbclk {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&ehrpwm2_gate_tbclk>;
+	};
+};
+&prcm_clocks {
+	clk_32768_ck: clk_32768_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	clk_rc32k_ck: clk_rc32k_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32000>;
+	};
+
+	virt_19200000_ck: virt_19200000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <19200000>;
+	};
+
+	virt_24000000_ck: virt_24000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+	};
+
+	virt_25000000_ck: virt_25000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+	};
+
+	virt_26000000_ck: virt_26000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+	};
+
+	tclkin_ck: tclkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	dpll_core_ck: dpll_core_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-core-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x0490>, <0x045c>, <0x0468>;
+	};
+
+	dpll_core_x2_ck: dpll_core_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-x2-clock";
+		clocks = <&dpll_core_ck>;
+	};
+
+	dpll_core_m4_ck: dpll_core_m4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		reg = <0x0480>;
+		ti,index-starts-at-one;
+	};
+
+	dpll_core_m5_ck: dpll_core_m5_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		reg = <0x0484>;
+		ti,index-starts-at-one;
+	};
+
+	dpll_core_m6_ck: dpll_core_m6_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		reg = <0x04d8>;
+		ti,index-starts-at-one;
+	};
+
+	dpll_mpu_ck: dpll_mpu_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x0488>, <0x0420>, <0x042c>;
+	};
+
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_mpu_ck>;
+		ti,max-div = <31>;
+		reg = <0x04a8>;
+		ti,index-starts-at-one;
+	};
+
+	dpll_ddr_ck: dpll_ddr_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-no-gate-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x0494>, <0x0434>, <0x0440>;
+	};
+
+	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_ddr_ck>;
+		ti,max-div = <31>;
+		reg = <0x04a0>;
+		ti,index-starts-at-one;
+	};
+
+	dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_ddr_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	dpll_disp_ck: dpll_disp_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-no-gate-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x0498>, <0x0448>, <0x0454>;
+	};
+
+	dpll_disp_m2_ck: dpll_disp_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_disp_ck>;
+		ti,max-div = <31>;
+		reg = <0x04a4>;
+		ti,index-starts-at-one;
+		ti,set-rate-parent;
+	};
+
+	dpll_per_ck: dpll_per_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-no-gate-j-type-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x048c>, <0x0470>, <0x049c>;
+	};
+
+	dpll_per_m2_ck: dpll_per_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_ck>;
+		ti,max-div = <31>;
+		reg = <0x04ac>;
+		ti,index-starts-at-one;
+	};
+
+	dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	cefuse_fck: cefuse_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_clkin_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0a20>;
+	};
+
+	clk_24mhz: clk_24mhz {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <8>;
+	};
+
+	clkdiv32k_ck: clkdiv32k_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&clk_24mhz>;
+		clock-mult = <1>;
+		clock-div = <732>;
+	};
+
+	clkdiv32k_ick: clkdiv32k_ick {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkdiv32k_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x014c>;
+	};
+
+	l3_gclk: l3_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	pruss_ocp_gclk: pruss_ocp_gclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+		reg = <0x0530>;
+	};
+
+	mmu_fck: mmu_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_core_m4_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0914>;
+	};
+
+	timer1_fck: timer1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+		reg = <0x0528>;
+	};
+
+	timer2_fck: timer2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x0508>;
+	};
+
+	timer3_fck: timer3_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x050c>;
+	};
+
+	timer4_fck: timer4_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x0510>;
+	};
+
+	timer5_fck: timer5_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x0518>;
+	};
+
+	timer6_fck: timer6_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x051c>;
+	};
+
+	timer7_fck: timer7_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x0504>;
+	};
+
+	usbotg_fck: usbotg_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_per_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x047c>;
+	};
+
+	dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	ieee5000_fck: ieee5000_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_core_m4_div2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x00e4>;
+	};
+
+	wdt1_fck: wdt1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+		reg = <0x0538>;
+	};
+
+	l4_rtc_gclk: l4_rtc_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	l4hs_gclk: l4hs_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	l3s_gclk: l3s_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_div2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	l4fw_gclk: l4fw_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_div2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	l4ls_gclk: l4ls_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_div2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	sysclk_div_ck: sysclk_div_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m5_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+		reg = <0x0520>;
+	};
+
+	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+		reg = <0x053c>;
+	};
+
+	gpio0_dbclk: gpio0_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&gpio0_dbclk_mux_ck>;
+		ti,bit-shift = <18>;
+		reg = <0x0408>;
+	};
+
+	gpio1_dbclk: gpio1_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkdiv32k_ick>;
+		ti,bit-shift = <18>;
+		reg = <0x00ac>;
+	};
+
+	gpio2_dbclk: gpio2_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkdiv32k_ick>;
+		ti,bit-shift = <18>;
+		reg = <0x00b0>;
+	};
+
+	gpio3_dbclk: gpio3_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkdiv32k_ick>;
+		ti,bit-shift = <18>;
+		reg = <0x00b4>;
+	};
+
+	lcd_gclk: lcd_gclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+		reg = <0x0534>;
+		ti,set-rate-parent;
+	};
+
+	mmc_clk: mmc_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x052c>;
+	};
+
+	gfx_fck_div_ck: gfx_fck_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&gfx_fclk_clksel_ck>;
+		reg = <0x052c>;
+		ti,max-div = <2>;
+	};
+
+	sysclkout_pre_ck: sysclkout_pre_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+		reg = <0x0700>;
+	};
+
+	clkout2_div_ck: clkout2_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sysclkout_pre_ck>;
+		ti,bit-shift = <3>;
+		ti,max-div = <8>;
+		reg = <0x0700>;
+	};
+
+	dbg_sysclk_ck: dbg_sysclk_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_clkin_ck>;
+		ti,bit-shift = <19>;
+		reg = <0x0414>;
+	};
+
+	dbg_clka_ck: dbg_clka_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_core_m4_ck>;
+		ti,bit-shift = <30>;
+		reg = <0x0414>;
+	};
+
+	stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+		ti,bit-shift = <22>;
+		reg = <0x0414>;
+	};
+
+	trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+		ti,bit-shift = <20>;
+		reg = <0x0414>;
+	};
+
+	stm_clk_div_ck: stm_clk_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&stm_pmd_clock_mux_ck>;
+		ti,bit-shift = <27>;
+		ti,max-div = <64>;
+		reg = <0x0414>;
+		ti,index-power-of-two;
+	};
+
+	trace_clk_div_ck: trace_clk_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&trace_pmd_clk_mux_ck>;
+		ti,bit-shift = <24>;
+		ti,max-div = <64>;
+		reg = <0x0414>;
+		ti,index-power-of-two;
+	};
+
+	clkout2_ck: clkout2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkout2_div_ck>;
+		ti,bit-shift = <7>;
+		reg = <0x0700>;
+	};
+};
+
+&prcm_clockdomains {
+	clk_24mhz_clkdm: clk_24mhz_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&clkdiv32k_ick>;
+	};
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index f6d8ffe..6d95d3d 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -102,6 +102,32 @@
 		ranges;
 		ti,hwmods = "l3_main";
 
+		prcm: prcm@44e00000 {
+			compatible = "ti,am3-prcm";
+			reg = <0x44e00000 0x4000>;
+
+			prcm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			prcm_clockdomains: clockdomains {
+			};
+		};
+
+		scrm: scrm@44e10000 {
+			compatible = "ti,am3-scrm";
+			reg = <0x44e10000 0x2000>;
+
+			scrm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			scrm_clockdomains: clockdomains {
+			};
+		};
+
 		intc: interrupt-controller@48200000 {
 			compatible = "ti,omap2-intc";
 			interrupt-controller;
@@ -794,3 +820,5 @@
 		};
 	};
 };
+
+/include/ "am33xx-clocks.dtsi"
-- 
1.7.9.5

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[PATCHv13 27/40] ARM: dts: omap3 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/am35xx-clocks.dtsi               |  128 ++
 arch/arm/boot/dts/omap3.dtsi                       |   41 +
 arch/arm/boot/dts/omap3430es1-clocks.dtsi          |  208 +++
 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi    |  268 ++++
 arch/arm/boot/dts/omap34xx.dtsi                    |    4 +
 .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi    |  242 +++
 arch/arm/boot/dts/omap36xx-clocks.dtsi             |   90 ++
 .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi  |  198 +++
 arch/arm/boot/dts/omap36xx.dtsi                    |    5 +
 arch/arm/boot/dts/omap3xxx-clocks.dtsi             | 1660 ++++++++++++++++++++
 10 files changed, 2844 insertions(+)
 create mode 100644 arch/arm/boot/dts/am35xx-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap3430es1-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap3xxx-clocks.dtsi

diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
new file mode 100644
index 0000000..df489d3
--- /dev/null
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -0,0 +1,128 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+	emac_ick: emac_ick {
+		#clock-cells = <0>;
+		compatible = "ti,am35xx-gate-clock";
+		clocks = <&ipss_ick>;
+		reg = <0x059c>;
+		ti,bit-shift = <1>;
+	};
+
+	emac_fck: emac_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&rmii_ck>;
+		reg = <0x059c>;
+		ti,bit-shift = <9>;
+	};
+
+	vpfe_ick: vpfe_ick {
+		#clock-cells = <0>;
+		compatible = "ti,am35xx-gate-clock";
+		clocks = <&ipss_ick>;
+		reg = <0x059c>;
+		ti,bit-shift = <2>;
+	};
+
+	vpfe_fck: vpfe_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&pclk_ck>;
+		reg = <0x059c>;
+		ti,bit-shift = <10>;
+	};
+
+	hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
+		#clock-cells = <0>;
+		compatible = "ti,am35xx-gate-clock";
+		clocks = <&ipss_ick>;
+		reg = <0x059c>;
+		ti,bit-shift = <0>;
+	};
+
+	hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_ck>;
+		reg = <0x059c>;
+		ti,bit-shift = <8>;
+	};
+
+	hecc_ck: hecc_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am35xx-gate-clock";
+		clocks = <&sys_ck>;
+		reg = <0x059c>;
+		ti,bit-shift = <3>;
+	};
+};
+&cm_clocks {
+	ipss_ick: ipss_ick {
+		#clock-cells = <0>;
+		compatible = "ti,am35xx-interface-clock";
+		clocks = <&core_l3_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <4>;
+	};
+
+	rmii_ck: rmii_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+	};
+
+	pclk_ck: pclk_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <27000000>;
+	};
+
+	uart4_ick_am35xx: uart4_ick_am35xx {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <23>;
+	};
+
+	uart4_fck_am35xx: uart4_fck_am35xx {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_48m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <23>;
+	};
+};
+
+&cm_clockdomains {
+	core_l3_clkdm: core_l3_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
+			 <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
+			 <&hecc_ck>;
+	};
+
+	core_l4_clkdm: core_l4_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
+			 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+			 <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
+	};
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index daabf99..07c7341 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -89,6 +89,45 @@
 			interrupts = <0>;
 		};
 
+		prm: prm@48306000 {
+			compatible = "ti,omap3-prm";
+			reg = <0x48306000 0x4000>;
+
+			prm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			prm_clockdomains: clockdomains {
+			};
+		};
+
+		cm: cm@48004000 {
+			compatible = "ti,omap3-cm";
+			reg = <0x48004000 0x4000>;
+
+			cm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cm_clockdomains: clockdomains {
+			};
+		};
+
+		scrm: scrm@48002000 {
+			compatible = "ti,omap3-scrm";
+			reg = <0x48002000 0x2000>;
+
+			scrm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			scrm_clockdomains: clockdomains {
+			};
+		};
+
 		counter32k: counter@48320000 {
 			compatible = "ti,omap-counter32k";
 			reg = <0x48320000 0x20>;
@@ -632,3 +671,5 @@
 		};
 	};
 };
+
+/include/ "omap3xxx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
new file mode 100644
index 0000000..02f6c7f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -0,0 +1,208 @@
+/*
+ * Device Tree Source for OMAP3430 ES1 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+	gfx_l3_ck: gfx_l3_ck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&l3_ick>;
+		reg = <0x0b10>;
+		ti,bit-shift = <0>;
+	};
+
+	gfx_l3_fck: gfx_l3_fck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&l3_ick>;
+		ti,max-div = <7>;
+		reg = <0x0b40>;
+		ti,index-starts-at-one;
+	};
+
+	gfx_l3_ick: gfx_l3_ick {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&gfx_l3_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	gfx_cg1_ck: gfx_cg1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&gfx_l3_fck>;
+		reg = <0x0b00>;
+		ti,bit-shift = <1>;
+	};
+
+	gfx_cg2_ck: gfx_cg2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&gfx_l3_fck>;
+		reg = <0x0b00>;
+		ti,bit-shift = <2>;
+	};
+
+	d2d_26m_fck: d2d_26m_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&sys_ck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <3>;
+	};
+
+	fshostusb_fck: fshostusb_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_48m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <5>;
+	};
+
+	ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&corex2_fck>;
+		ti,bit-shift = <0>;
+		reg = <0x0a00>;
+	};
+
+	ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
+		#clock-cells = <0>;
+		compatible = "ti,composite-divider-clock";
+		clocks = <&corex2_fck>;
+		ti,bit-shift = <8>;
+		reg = <0x0a40>;
+		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+	};
+
+	ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
+	};
+
+	ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&ssi_ssr_fck_3430es1>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-no-wait-interface-clock";
+		clocks = <&core_l3_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <4>;
+	};
+
+	fac_ick: fac_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <8>;
+	};
+
+	ssi_l4_ick: ssi_l4_ick {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l4_ick>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	ssi_ick_3430es1: ssi_ick_3430es1 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-no-wait-interface-clock";
+		clocks = <&ssi_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <0>;
+	};
+
+	usb_l4_gate_ick: usb_l4_gate_ick {
+		#clock-cells = <0>;
+		compatible = "ti,composite-interface-clock";
+		clocks = <&l4_ick>;
+		ti,bit-shift = <5>;
+		reg = <0x0a10>;
+	};
+
+	usb_l4_div_ick: usb_l4_div_ick {
+		#clock-cells = <0>;
+		compatible = "ti,composite-divider-clock";
+		clocks = <&l4_ick>;
+		ti,bit-shift = <4>;
+		ti,max-div = <1>;
+		reg = <0x0a40>;
+		ti,index-starts-at-one;
+	};
+
+	usb_l4_ick: usb_l4_ick {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
+	};
+
+	dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll4_m4x2_ck>;
+		ti,bit-shift = <0>;
+		reg = <0x0e00>;
+		ti,set-rate-parent;
+	};
+
+	dss_ick_3430es1: dss_ick_3430es1 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-no-wait-interface-clock";
+		clocks = <&l4_ick>;
+		reg = <0x0e10>;
+		ti,bit-shift = <0>;
+	};
+};
+
+&cm_clockdomains {
+	core_l3_clkdm: core_l3_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
+	};
+
+	gfx_3430es1_clkdm: gfx_3430es1_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
+	};
+
+	dss_clkdm: dss_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
+			 <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
+	};
+
+	d2d_clkdm: d2d_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&d2d_26m_fck>;
+	};
+
+	core_l4_clkdm: core_l4_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+			 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
+	};
+};
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 0000000..b02017b
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,268 @@
+/*
+ * Device Tree Source for OMAP34XX/OMAP36XX clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+	security_l4_ick2: security_l4_ick2 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l4_ick>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	aes1_ick: aes1_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&security_l4_ick2>;
+		ti,bit-shift = <3>;
+		reg = <0x0a14>;
+	};
+
+	rng_ick: rng_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&security_l4_ick2>;
+		reg = <0x0a14>;
+		ti,bit-shift = <2>;
+	};
+
+	sha11_ick: sha11_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&security_l4_ick2>;
+		reg = <0x0a14>;
+		ti,bit-shift = <1>;
+	};
+
+	des1_ick: des1_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&security_l4_ick2>;
+		reg = <0x0a14>;
+		ti,bit-shift = <0>;
+	};
+
+	cam_mclk: cam_mclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll4_m5x2_ck>;
+		ti,bit-shift = <0>;
+		reg = <0x0f00>;
+		ti,set-rate-parent;
+	};
+
+	cam_ick: cam_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-no-wait-interface-clock";
+		clocks = <&l4_ick>;
+		reg = <0x0f10>;
+		ti,bit-shift = <0>;
+	};
+
+	csi2_96m_fck: csi2_96m_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&core_96m_fck>;
+		reg = <0x0f00>;
+		ti,bit-shift = <1>;
+	};
+
+	security_l3_ick: security_l3_ick {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l3_ick>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	pka_ick: pka_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&security_l3_ick>;
+		reg = <0x0a14>;
+		ti,bit-shift = <4>;
+	};
+
+	icr_ick: icr_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <29>;
+	};
+
+	des2_ick: des2_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <26>;
+	};
+
+	mspro_ick: mspro_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <23>;
+	};
+
+	mailboxes_ick: mailboxes_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <7>;
+	};
+
+	ssi_l4_ick: ssi_l4_ick {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l4_ick>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	sr1_fck: sr1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&sys_ck>;
+		reg = <0x0c00>;
+		ti,bit-shift = <6>;
+	};
+
+	sr2_fck: sr2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&sys_ck>;
+		reg = <0x0c00>;
+		ti,bit-shift = <7>;
+	};
+
+	sr_l4_ick: sr_l4_ick {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l4_ick>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll2_fck: dpll2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&core_ck>;
+		ti,bit-shift = <19>;
+		ti,max-div = <7>;
+		reg = <0x0040>;
+		ti,index-starts-at-one;
+	};
+
+	dpll2_ck: dpll2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-dpll-clock";
+		clocks = <&sys_ck>, <&dpll2_fck>;
+		reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
+		ti,low-power-stop;
+		ti,lock;
+		ti,low-power-bypass;
+	};
+
+	dpll2_m2_ck: dpll2_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll2_ck>;
+		ti,max-div = <31>;
+		reg = <0x0044>;
+		ti,index-starts-at-one;
+	};
+
+	iva2_ck: iva2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&dpll2_m2_ck>;
+		reg = <0x0000>;
+		ti,bit-shift = <0>;
+	};
+
+	modem_fck: modem_fck {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&sys_ck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <31>;
+	};
+
+	sad2d_ick: sad2d_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&l3_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <3>;
+	};
+
+	mad2d_ick: mad2d_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&l3_ick>;
+		reg = <0x0a18>;
+		ti,bit-shift = <3>;
+	};
+
+	mspro_fck: mspro_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_96m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <23>;
+	};
+};
+
+&cm_clockdomains {
+	cam_clkdm: cam_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&cam_ick>, <&csi2_96m_fck>;
+	};
+
+	iva2_clkdm: iva2_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&iva2_ck>;
+	};
+
+	dpll2_clkdm: dpll2_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dpll2_ck>;
+	};
+
+	wkup_clkdm: wkup_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+			 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+			 <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
+	};
+
+	d2d_clkdm: d2d_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
+	};
+
+	core_l4_clkdm: core_l4_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
+			 <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
+			 <&mspro_fck>;
+	};
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 5355d61..d531abf 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -26,3 +26,7 @@
 		};
 	};
 };
+
+/include/ "omap34xx-omap36xx-clocks.dtsi"
+/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
\ No newline at end of file
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..af9ae534
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,242 @@
+/*
+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+	corex2_d3_fck: corex2_d3_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&corex2_fck>;
+		clock-mult = <1>;
+		clock-div = <3>;
+	};
+
+	corex2_d5_fck: corex2_d5_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&corex2_fck>;
+		clock-mult = <1>;
+		clock-div = <5>;
+	};
+};
+&cm_clocks {
+	dpll5_ck: dpll5_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-dpll-clock";
+		clocks = <&sys_ck>, <&sys_ck>;
+		reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
+		ti,low-power-stop;
+		ti,lock;
+	};
+
+	dpll5_m2_ck: dpll5_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll5_ck>;
+		ti,max-div = <31>;
+		reg = <0x0d50>;
+		ti,index-starts-at-one;
+	};
+
+	sgx_gate_fck: sgx_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&core_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x0b00>;
+	};
+
+	core_d3_ck: core_d3_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&core_ck>;
+		clock-mult = <1>;
+		clock-div = <3>;
+	};
+
+	core_d4_ck: core_d4_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&core_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	core_d6_ck: core_d6_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&core_ck>;
+		clock-mult = <1>;
+		clock-div = <6>;
+	};
+
+	omap_192m_alwon_fck: omap_192m_alwon_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll4_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	core_d2_ck: core_d2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&core_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	sgx_mux_fck: sgx_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+		reg = <0x0b40>;
+	};
+
+	sgx_fck: sgx_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
+	};
+
+	sgx_ick: sgx_ick {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&l3_ick>;
+		reg = <0x0b10>;
+		ti,bit-shift = <0>;
+	};
+
+	cpefuse_fck: cpefuse_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_ck>;
+		reg = <0x0a08>;
+		ti,bit-shift = <0>;
+	};
+
+	ts_fck: ts_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&omap_32k_fck>;
+		reg = <0x0a08>;
+		ti,bit-shift = <1>;
+	};
+
+	usbtll_fck: usbtll_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&dpll5_m2_ck>;
+		reg = <0x0a08>;
+		ti,bit-shift = <2>;
+	};
+
+	usbtll_ick: usbtll_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a18>;
+		ti,bit-shift = <2>;
+	};
+
+	mmchs3_ick: mmchs3_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <30>;
+	};
+
+	mmchs3_fck: mmchs3_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_96m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <30>;
+	};
+
+	dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
+		#clock-cells = <0>;
+		compatible = "ti,dss-gate-clock";
+		clocks = <&dpll4_m4x2_ck>;
+		ti,bit-shift = <0>;
+		reg = <0x0e00>;
+		ti,set-rate-parent;
+	};
+
+	dss_ick_3430es2: dss_ick_3430es2 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-dss-interface-clock";
+		clocks = <&l4_ick>;
+		reg = <0x0e10>;
+		ti,bit-shift = <0>;
+	};
+
+	usbhost_120m_fck: usbhost_120m_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll5_m2_ck>;
+		reg = <0x1400>;
+		ti,bit-shift = <1>;
+	};
+
+	usbhost_48m_fck: usbhost_48m_fck {
+		#clock-cells = <0>;
+		compatible = "ti,dss-gate-clock";
+		clocks = <&omap_48m_fck>;
+		reg = <0x1400>;
+		ti,bit-shift = <0>;
+	};
+
+	usbhost_ick: usbhost_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-dss-interface-clock";
+		clocks = <&l4_ick>;
+		reg = <0x1410>;
+		ti,bit-shift = <0>;
+	};
+};
+
+&cm_clockdomains {
+	dpll5_clkdm: dpll5_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dpll5_ck>;
+	};
+
+	sgx_clkdm: sgx_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&sgx_ick>;
+	};
+
+	dss_clkdm: dss_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
+			 <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+	};
+
+	core_l4_clkdm: core_l4_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+			 <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
+	};
+
+	usbhost_clkdm: usbhost_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
+			 <&usbhost_ick>;
+	};
+};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
new file mode 100644
index 0000000..2fcf253
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -0,0 +1,90 @@
+/*
+ * Device Tree Source for OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+	dpll4_ck: dpll4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-dpll-per-j-type-clock";
+		clocks = <&sys_ck>, <&sys_ck>;
+		reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+	};
+
+	dpll4_m5x2_ck: dpll4_m5x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,hsdiv-gate-clock";
+		clocks = <&dpll4_m5x2_mul_ck>;
+		ti,bit-shift = <0x1e>;
+		reg = <0x0d00>;
+		ti,set-rate-parent;
+		ti,set-bit-to-disable;
+	};
+
+	dpll4_m2x2_ck: dpll4_m2x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,hsdiv-gate-clock";
+		clocks = <&dpll4_m2x2_mul_ck>;
+		ti,bit-shift = <0x1b>;
+		reg = <0x0d00>;
+		ti,set-bit-to-disable;
+	};
+
+	dpll3_m3x2_ck: dpll3_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,hsdiv-gate-clock";
+		clocks = <&dpll3_m3x2_mul_ck>;
+		ti,bit-shift = <0xc>;
+		reg = <0x0d00>;
+		ti,set-bit-to-disable;
+	};
+
+	dpll4_m3x2_ck: dpll4_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,hsdiv-gate-clock";
+		clocks = <&dpll4_m3x2_mul_ck>;
+		ti,bit-shift = <0x1c>;
+		reg = <0x0d00>;
+		ti,set-bit-to-disable;
+	};
+
+	dpll4_m6x2_ck: dpll4_m6x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,hsdiv-gate-clock";
+		clocks = <&dpll4_m6x2_mul_ck>;
+		ti,bit-shift = <0x1f>;
+		reg = <0x0d00>;
+		ti,set-bit-to-disable;
+	};
+
+	uart4_fck: uart4_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&per_48m_fck>;
+		reg = <0x1000>;
+		ti,bit-shift = <18>;
+	};
+};
+
+&cm_clockdomains {
+	dpll4_clkdm: dpll4_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dpll4_ck>;
+	};
+
+	per_clkdm: per_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+			 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+			 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+			 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+			 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+			 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+			 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+			 <&mcbsp4_ick>, <&uart4_fck>;
+	};
+};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..8ed475d
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,198 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+	ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&corex2_fck>;
+		ti,bit-shift = <0>;
+		reg = <0x0a00>;
+	};
+
+	ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
+		#clock-cells = <0>;
+		compatible = "ti,composite-divider-clock";
+		clocks = <&corex2_fck>;
+		ti,bit-shift = <8>;
+		reg = <0x0a40>;
+		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+	};
+
+	ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
+	};
+
+	ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&ssi_ssr_fck_3430es2>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-hsotgusb-interface-clock";
+		clocks = <&core_l3_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <4>;
+	};
+
+	ssi_l4_ick: ssi_l4_ick {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l4_ick>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	ssi_ick_3430es2: ssi_ick_3430es2 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-ssi-interface-clock";
+		clocks = <&ssi_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <0>;
+	};
+
+	usim_gate_fck: usim_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&omap_96m_fck>;
+		ti,bit-shift = <9>;
+		reg = <0x0c00>;
+	};
+
+	sys_d2_ck: sys_d2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	omap_96m_d2_fck: omap_96m_d2_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_96m_fck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	omap_96m_d4_fck: omap_96m_d4_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_96m_fck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	omap_96m_d8_fck: omap_96m_d8_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_96m_fck>;
+		clock-mult = <1>;
+		clock-div = <8>;
+	};
+
+	omap_96m_d10_fck: omap_96m_d10_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_96m_fck>;
+		clock-mult = <1>;
+		clock-div = <10>;
+	};
+
+	dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll5_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll5_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <8>;
+	};
+
+	dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll5_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <16>;
+	};
+
+	dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll5_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <20>;
+	};
+
+	usim_mux_fck: usim_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
+		ti,bit-shift = <3>;
+		reg = <0x0c40>;
+		ti,index-starts-at-one;
+	};
+
+	usim_fck: usim_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&usim_gate_fck>, <&usim_mux_fck>;
+	};
+
+	usim_ick: usim_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&wkup_l4_ick>;
+		reg = <0x0c10>;
+		ti,bit-shift = <9>;
+	};
+};
+
+&cm_clockdomains {
+	core_l3_clkdm: core_l3_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
+	};
+
+	wkup_clkdm: wkup_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+			 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+			 <&gpt1_ick>, <&usim_ick>;
+	};
+
+	core_l4_clkdm: core_l4_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
+			 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+			 <&ssi_ick_3430es2>;
+	};
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 380c22e..55ebaaa 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -40,3 +40,8 @@
 		};
 	};
 };
+
+/include/ "omap36xx-clocks.dtsi"
+/include/ "omap34xx-omap36xx-clocks.dtsi"
+/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
\ No newline at end of file
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
new file mode 100644
index 0000000..cb04d4b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -0,0 +1,1660 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+	virt_16_8m_ck: virt_16_8m_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <16800000>;
+	};
+
+	osc_sys_ck: osc_sys_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+		reg = <0x0d40>;
+	};
+
+	sys_ck: sys_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&osc_sys_ck>;
+		ti,bit-shift = <6>;
+		ti,max-div = <3>;
+		reg = <0x1270>;
+		ti,index-starts-at-one;
+	};
+
+	sys_clkout1: sys_clkout1 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&osc_sys_ck>;
+		reg = <0x0d70>;
+		ti,bit-shift = <7>;
+	};
+
+	dpll3_x2_ck: dpll3_x2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll3_ck>;
+		clock-mult = <2>;
+		clock-div = <1>;
+	};
+
+	dpll3_m2x2_ck: dpll3_m2x2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll3_m2_ck>;
+		clock-mult = <2>;
+		clock-div = <1>;
+	};
+
+	dpll4_x2_ck: dpll4_x2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll4_ck>;
+		clock-mult = <2>;
+		clock-div = <1>;
+	};
+
+	corex2_fck: corex2_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll3_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	wkup_l4_ick: wkup_l4_ick {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+};
+&scrm_clocks {
+	mcbsp5_mux_fck: mcbsp5_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&core_96m_fck>, <&mcbsp_clks>;
+		ti,bit-shift = <4>;
+		reg = <0x02d8>;
+	};
+
+	mcbsp5_fck: mcbsp5_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
+	};
+
+	mcbsp1_mux_fck: mcbsp1_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&core_96m_fck>, <&mcbsp_clks>;
+		ti,bit-shift = <2>;
+		reg = <0x0274>;
+	};
+
+	mcbsp1_fck: mcbsp1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
+	};
+
+	mcbsp2_mux_fck: mcbsp2_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&per_96m_fck>, <&mcbsp_clks>;
+		ti,bit-shift = <6>;
+		reg = <0x0274>;
+	};
+
+	mcbsp2_fck: mcbsp2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
+	};
+
+	mcbsp3_mux_fck: mcbsp3_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&per_96m_fck>, <&mcbsp_clks>;
+		reg = <0x02d8>;
+	};
+
+	mcbsp3_fck: mcbsp3_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
+	};
+
+	mcbsp4_mux_fck: mcbsp4_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&per_96m_fck>, <&mcbsp_clks>;
+		ti,bit-shift = <2>;
+		reg = <0x02d8>;
+	};
+
+	mcbsp4_fck: mcbsp4_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
+	};
+};
+&cm_clocks {
+	dummy_apb_pclk: dummy_apb_pclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0x0>;
+	};
+
+	omap_32k_fck: omap_32k_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	virt_12m_ck: virt_12m_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+	virt_13m_ck: virt_13m_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <13000000>;
+	};
+
+	virt_19200000_ck: virt_19200000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <19200000>;
+	};
+
+	virt_26000000_ck: virt_26000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+	};
+
+	virt_38_4m_ck: virt_38_4m_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <38400000>;
+	};
+
+	dpll4_ck: dpll4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-dpll-per-clock";
+		clocks = <&sys_ck>, <&sys_ck>;
+		reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+	};
+
+	dpll4_m2_ck: dpll4_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll4_ck>;
+		ti,max-div = <63>;
+		reg = <0x0d48>;
+		ti,index-starts-at-one;
+	};
+
+	dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll4_m2_ck>;
+		clock-mult = <2>;
+		clock-div = <1>;
+	};
+
+	dpll4_m2x2_ck: dpll4_m2x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll4_m2x2_mul_ck>;
+		ti,bit-shift = <0x1b>;
+		reg = <0x0d00>;
+		ti,set-bit-to-disable;
+	};
+
+	omap_96m_alwon_fck: omap_96m_alwon_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll4_m2x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll3_ck: dpll3_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-dpll-core-clock";
+		clocks = <&sys_ck>, <&sys_ck>;
+		reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
+	};
+
+	dpll3_m3_ck: dpll3_m3_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll3_ck>;
+		ti,bit-shift = <16>;
+		ti,max-div = <31>;
+		reg = <0x1140>;
+		ti,index-starts-at-one;
+	};
+
+	dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll3_m3_ck>;
+		clock-mult = <2>;
+		clock-div = <1>;
+	};
+
+	dpll3_m3x2_ck: dpll3_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll3_m3x2_mul_ck>;
+		ti,bit-shift = <0xc>;
+		reg = <0x0d00>;
+		ti,set-bit-to-disable;
+	};
+
+	emu_core_alwon_ck: emu_core_alwon_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll3_m3x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	sys_altclk: sys_altclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0x0>;
+	};
+
+	mcbsp_clks: mcbsp_clks {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0x0>;
+	};
+
+	dpll3_m2_ck: dpll3_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll3_ck>;
+		ti,bit-shift = <27>;
+		ti,max-div = <31>;
+		reg = <0x0d40>;
+		ti,index-starts-at-one;
+	};
+
+	core_ck: core_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll3_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll1_fck: dpll1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&core_ck>;
+		ti,bit-shift = <19>;
+		ti,max-div = <7>;
+		reg = <0x0940>;
+		ti,index-starts-at-one;
+	};
+
+	dpll1_ck: dpll1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-dpll-clock";
+		clocks = <&sys_ck>, <&dpll1_fck>;
+		reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
+	};
+
+	dpll1_x2_ck: dpll1_x2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll1_ck>;
+		clock-mult = <2>;
+		clock-div = <1>;
+	};
+
+	dpll1_x2m2_ck: dpll1_x2m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll1_x2_ck>;
+		ti,max-div = <31>;
+		reg = <0x0944>;
+		ti,index-starts-at-one;
+	};
+
+	cm_96m_fck: cm_96m_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_96m_alwon_fck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	omap_96m_fck: omap_96m_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&cm_96m_fck>, <&sys_ck>;
+		ti,bit-shift = <6>;
+		reg = <0x0d40>;
+	};
+
+	dpll4_m3_ck: dpll4_m3_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll4_ck>;
+		ti,bit-shift = <8>;
+		ti,max-div = <32>;
+		reg = <0x0e40>;
+		ti,index-starts-at-one;
+	};
+
+	dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll4_m3_ck>;
+		clock-mult = <2>;
+		clock-div = <1>;
+	};
+
+	dpll4_m3x2_ck: dpll4_m3x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll4_m3x2_mul_ck>;
+		ti,bit-shift = <0x1c>;
+		reg = <0x0d00>;
+		ti,set-bit-to-disable;
+	};
+
+	omap_54m_fck: omap_54m_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+		ti,bit-shift = <5>;
+		reg = <0x0d40>;
+	};
+
+	cm_96m_d2_fck: cm_96m_d2_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&cm_96m_fck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	omap_48m_fck: omap_48m_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+		ti,bit-shift = <3>;
+		reg = <0x0d40>;
+	};
+
+	omap_12m_fck: omap_12m_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_48m_fck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	dpll4_m4_ck: dpll4_m4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll4_ck>;
+		ti,max-div = <32>;
+		reg = <0x0e40>;
+		ti,index-starts-at-one;
+	};
+
+	dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll4_m4_ck>;
+		clock-mult = <2>;
+		clock-div = <1>;
+	};
+
+	dpll4_m4x2_ck: dpll4_m4x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll4_m4x2_mul_ck>;
+		ti,bit-shift = <0x1d>;
+		reg = <0x0d00>;
+		ti,set-bit-to-disable;
+	};
+
+	dpll4_m5_ck: dpll4_m5_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll4_ck>;
+		ti,max-div = <63>;
+		reg = <0x0f40>;
+		ti,index-starts-at-one;
+	};
+
+	dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll4_m5_ck>;
+		clock-mult = <2>;
+		clock-div = <1>;
+	};
+
+	dpll4_m5x2_ck: dpll4_m5x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll4_m5x2_mul_ck>;
+		ti,bit-shift = <0x1e>;
+		reg = <0x0d00>;
+		ti,set-bit-to-disable;
+	};
+
+	dpll4_m6_ck: dpll4_m6_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll4_ck>;
+		ti,bit-shift = <24>;
+		ti,max-div = <63>;
+		reg = <0x1140>;
+		ti,index-starts-at-one;
+	};
+
+	dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll4_m6_ck>;
+		clock-mult = <2>;
+		clock-div = <1>;
+	};
+
+	dpll4_m6x2_ck: dpll4_m6x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll4_m6x2_mul_ck>;
+		ti,bit-shift = <0x1f>;
+		reg = <0x0d00>;
+		ti,set-bit-to-disable;
+	};
+
+	emu_per_alwon_ck: emu_per_alwon_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll4_m6x2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	clkout2_src_gate_ck: clkout2_src_gate_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-no-wait-gate-clock";
+		clocks = <&core_ck>;
+		ti,bit-shift = <7>;
+		reg = <0x0d70>;
+	};
+
+	clkout2_src_mux_ck: clkout2_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+		reg = <0x0d70>;
+	};
+
+	clkout2_src_ck: clkout2_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
+	};
+
+	sys_clkout2: sys_clkout2 {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout2_src_ck>;
+		ti,bit-shift = <3>;
+		ti,max-div = <64>;
+		reg = <0x0d70>;
+		ti,index-power-of-two;
+	};
+
+	mpu_ck: mpu_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll1_x2m2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	arm_fck: arm_fck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&mpu_ck>;
+		reg = <0x0924>;
+		ti,max-div = <2>;
+	};
+
+	emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&mpu_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	l3_ick: l3_ick {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&core_ck>;
+		ti,max-div = <3>;
+		reg = <0x0a40>;
+		ti,index-starts-at-one;
+	};
+
+	l4_ick: l4_ick {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&l3_ick>;
+		ti,bit-shift = <2>;
+		ti,max-div = <3>;
+		reg = <0x0a40>;
+		ti,index-starts-at-one;
+	};
+
+	rm_ick: rm_ick {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&l4_ick>;
+		ti,bit-shift = <1>;
+		ti,max-div = <3>;
+		reg = <0x0c40>;
+		ti,index-starts-at-one;
+	};
+
+	gpt10_gate_fck: gpt10_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <11>;
+		reg = <0x0a00>;
+	};
+
+	gpt10_mux_fck: gpt10_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		ti,bit-shift = <6>;
+		reg = <0x0a40>;
+	};
+
+	gpt10_fck: gpt10_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
+	};
+
+	gpt11_gate_fck: gpt11_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <12>;
+		reg = <0x0a00>;
+	};
+
+	gpt11_mux_fck: gpt11_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		ti,bit-shift = <7>;
+		reg = <0x0a40>;
+	};
+
+	gpt11_fck: gpt11_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
+	};
+
+	core_96m_fck: core_96m_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_96m_fck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	mmchs2_fck: mmchs2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_96m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <25>;
+	};
+
+	mmchs1_fck: mmchs1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_96m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <24>;
+	};
+
+	i2c3_fck: i2c3_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_96m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <17>;
+	};
+
+	i2c2_fck: i2c2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_96m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <16>;
+	};
+
+	i2c1_fck: i2c1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_96m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <15>;
+	};
+
+	mcbsp5_gate_fck: mcbsp5_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&mcbsp_clks>;
+		ti,bit-shift = <10>;
+		reg = <0x0a00>;
+	};
+
+	mcbsp1_gate_fck: mcbsp1_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&mcbsp_clks>;
+		ti,bit-shift = <9>;
+		reg = <0x0a00>;
+	};
+
+	core_48m_fck: core_48m_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_48m_fck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	mcspi4_fck: mcspi4_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_48m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <21>;
+	};
+
+	mcspi3_fck: mcspi3_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_48m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <20>;
+	};
+
+	mcspi2_fck: mcspi2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_48m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <19>;
+	};
+
+	mcspi1_fck: mcspi1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_48m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <18>;
+	};
+
+	uart2_fck: uart2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_48m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <14>;
+	};
+
+	uart1_fck: uart1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_48m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <13>;
+	};
+
+	core_12m_fck: core_12m_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_12m_fck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	hdq_fck: hdq_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_12m_fck>;
+		reg = <0x0a00>;
+		ti,bit-shift = <22>;
+	};
+
+	core_l3_ick: core_l3_ick {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l3_ick>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	sdrc_ick: sdrc_ick {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&core_l3_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <1>;
+	};
+
+	gpmc_fck: gpmc_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&core_l3_ick>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	core_l4_ick: core_l4_ick {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l4_ick>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	mmchs2_ick: mmchs2_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <25>;
+	};
+
+	mmchs1_ick: mmchs1_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <24>;
+	};
+
+	hdq_ick: hdq_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <22>;
+	};
+
+	mcspi4_ick: mcspi4_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <21>;
+	};
+
+	mcspi3_ick: mcspi3_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <20>;
+	};
+
+	mcspi2_ick: mcspi2_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <19>;
+	};
+
+	mcspi1_ick: mcspi1_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <18>;
+	};
+
+	i2c3_ick: i2c3_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <17>;
+	};
+
+	i2c2_ick: i2c2_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <16>;
+	};
+
+	i2c1_ick: i2c1_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <15>;
+	};
+
+	uart2_ick: uart2_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <14>;
+	};
+
+	uart1_ick: uart1_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <13>;
+	};
+
+	gpt11_ick: gpt11_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <12>;
+	};
+
+	gpt10_ick: gpt10_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <11>;
+	};
+
+	mcbsp5_ick: mcbsp5_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <10>;
+	};
+
+	mcbsp1_ick: mcbsp1_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <9>;
+	};
+
+	omapctrl_ick: omapctrl_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <6>;
+	};
+
+	dss_tv_fck: dss_tv_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&omap_54m_fck>;
+		reg = <0x0e00>;
+		ti,bit-shift = <2>;
+	};
+
+	dss_96m_fck: dss_96m_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&omap_96m_fck>;
+		reg = <0x0e00>;
+		ti,bit-shift = <2>;
+	};
+
+	dss2_alwon_fck: dss2_alwon_fck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_ck>;
+		reg = <0x0e00>;
+		ti,bit-shift = <1>;
+	};
+
+	dummy_ck: dummy_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	gpt1_gate_fck: gpt1_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <0>;
+		reg = <0x0c00>;
+	};
+
+	gpt1_mux_fck: gpt1_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		reg = <0x0c40>;
+	};
+
+	gpt1_fck: gpt1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
+	};
+
+	aes2_ick: aes2_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		ti,bit-shift = <28>;
+		reg = <0x0a10>;
+	};
+
+	wkup_32k_fck: wkup_32k_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_32k_fck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	gpio1_dbck: gpio1_dbck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&wkup_32k_fck>;
+		reg = <0x0c00>;
+		ti,bit-shift = <3>;
+	};
+
+	sha12_ick: sha12_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&core_l4_ick>;
+		reg = <0x0a10>;
+		ti,bit-shift = <27>;
+	};
+
+	wdt2_fck: wdt2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&wkup_32k_fck>;
+		reg = <0x0c00>;
+		ti,bit-shift = <5>;
+	};
+
+	wdt2_ick: wdt2_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&wkup_l4_ick>;
+		reg = <0x0c10>;
+		ti,bit-shift = <5>;
+	};
+
+	wdt1_ick: wdt1_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&wkup_l4_ick>;
+		reg = <0x0c10>;
+		ti,bit-shift = <4>;
+	};
+
+	gpio1_ick: gpio1_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&wkup_l4_ick>;
+		reg = <0x0c10>;
+		ti,bit-shift = <3>;
+	};
+
+	omap_32ksync_ick: omap_32ksync_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&wkup_l4_ick>;
+		reg = <0x0c10>;
+		ti,bit-shift = <2>;
+	};
+
+	gpt12_ick: gpt12_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&wkup_l4_ick>;
+		reg = <0x0c10>;
+		ti,bit-shift = <1>;
+	};
+
+	gpt1_ick: gpt1_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&wkup_l4_ick>;
+		reg = <0x0c10>;
+		ti,bit-shift = <0>;
+	};
+
+	per_96m_fck: per_96m_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_96m_alwon_fck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	per_48m_fck: per_48m_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_48m_fck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	uart3_fck: uart3_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&per_48m_fck>;
+		reg = <0x1000>;
+		ti,bit-shift = <11>;
+	};
+
+	gpt2_gate_fck: gpt2_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <3>;
+		reg = <0x1000>;
+	};
+
+	gpt2_mux_fck: gpt2_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		reg = <0x1040>;
+	};
+
+	gpt2_fck: gpt2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
+	};
+
+	gpt3_gate_fck: gpt3_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <4>;
+		reg = <0x1000>;
+	};
+
+	gpt3_mux_fck: gpt3_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x1040>;
+	};
+
+	gpt3_fck: gpt3_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
+	};
+
+	gpt4_gate_fck: gpt4_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <5>;
+		reg = <0x1000>;
+	};
+
+	gpt4_mux_fck: gpt4_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x1040>;
+	};
+
+	gpt4_fck: gpt4_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
+	};
+
+	gpt5_gate_fck: gpt5_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <6>;
+		reg = <0x1000>;
+	};
+
+	gpt5_mux_fck: gpt5_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		ti,bit-shift = <3>;
+		reg = <0x1040>;
+	};
+
+	gpt5_fck: gpt5_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
+	};
+
+	gpt6_gate_fck: gpt6_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <7>;
+		reg = <0x1000>;
+	};
+
+	gpt6_mux_fck: gpt6_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		ti,bit-shift = <4>;
+		reg = <0x1040>;
+	};
+
+	gpt6_fck: gpt6_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
+	};
+
+	gpt7_gate_fck: gpt7_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x1000>;
+	};
+
+	gpt7_mux_fck: gpt7_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		ti,bit-shift = <5>;
+		reg = <0x1040>;
+	};
+
+	gpt7_fck: gpt7_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
+	};
+
+	gpt8_gate_fck: gpt8_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <9>;
+		reg = <0x1000>;
+	};
+
+	gpt8_mux_fck: gpt8_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		ti,bit-shift = <6>;
+		reg = <0x1040>;
+	};
+
+	gpt8_fck: gpt8_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
+	};
+
+	gpt9_gate_fck: gpt9_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&sys_ck>;
+		ti,bit-shift = <10>;
+		reg = <0x1000>;
+	};
+
+	gpt9_mux_fck: gpt9_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&omap_32k_fck>, <&sys_ck>;
+		ti,bit-shift = <7>;
+		reg = <0x1040>;
+	};
+
+	gpt9_fck: gpt9_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-clock";
+		clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
+	};
+
+	per_32k_alwon_fck: per_32k_alwon_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&omap_32k_fck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	gpio6_dbck: gpio6_dbck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&per_32k_alwon_fck>;
+		reg = <0x1000>;
+		ti,bit-shift = <17>;
+	};
+
+	gpio5_dbck: gpio5_dbck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&per_32k_alwon_fck>;
+		reg = <0x1000>;
+		ti,bit-shift = <16>;
+	};
+
+	gpio4_dbck: gpio4_dbck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&per_32k_alwon_fck>;
+		reg = <0x1000>;
+		ti,bit-shift = <15>;
+	};
+
+	gpio3_dbck: gpio3_dbck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&per_32k_alwon_fck>;
+		reg = <0x1000>;
+		ti,bit-shift = <14>;
+	};
+
+	gpio2_dbck: gpio2_dbck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&per_32k_alwon_fck>;
+		reg = <0x1000>;
+		ti,bit-shift = <13>;
+	};
+
+	wdt3_fck: wdt3_fck {
+		#clock-cells = <0>;
+		compatible = "ti,wait-gate-clock";
+		clocks = <&per_32k_alwon_fck>;
+		reg = <0x1000>;
+		ti,bit-shift = <12>;
+	};
+
+	per_l4_ick: per_l4_ick {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&l4_ick>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	gpio6_ick: gpio6_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <17>;
+	};
+
+	gpio5_ick: gpio5_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <16>;
+	};
+
+	gpio4_ick: gpio4_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <15>;
+	};
+
+	gpio3_ick: gpio3_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <14>;
+	};
+
+	gpio2_ick: gpio2_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <13>;
+	};
+
+	wdt3_ick: wdt3_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <12>;
+	};
+
+	uart3_ick: uart3_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <11>;
+	};
+
+	uart4_ick: uart4_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <18>;
+	};
+
+	gpt9_ick: gpt9_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <10>;
+	};
+
+	gpt8_ick: gpt8_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <9>;
+	};
+
+	gpt7_ick: gpt7_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <8>;
+	};
+
+	gpt6_ick: gpt6_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <7>;
+	};
+
+	gpt5_ick: gpt5_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <6>;
+	};
+
+	gpt4_ick: gpt4_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <5>;
+	};
+
+	gpt3_ick: gpt3_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <4>;
+	};
+
+	gpt2_ick: gpt2_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <3>;
+	};
+
+	mcbsp2_ick: mcbsp2_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <0>;
+	};
+
+	mcbsp3_ick: mcbsp3_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <1>;
+	};
+
+	mcbsp4_ick: mcbsp4_ick {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-interface-clock";
+		clocks = <&per_l4_ick>;
+		reg = <0x1010>;
+		ti,bit-shift = <2>;
+	};
+
+	mcbsp2_gate_fck: mcbsp2_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&mcbsp_clks>;
+		ti,bit-shift = <0>;
+		reg = <0x1000>;
+	};
+
+	mcbsp3_gate_fck: mcbsp3_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&mcbsp_clks>;
+		ti,bit-shift = <1>;
+		reg = <0x1000>;
+	};
+
+	mcbsp4_gate_fck: mcbsp4_gate_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-gate-clock";
+		clocks = <&mcbsp_clks>;
+		ti,bit-shift = <2>;
+		reg = <0x1000>;
+	};
+
+	emu_src_mux_ck: emu_src_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+		reg = <0x1140>;
+	};
+
+	emu_src_ck: emu_src_ck {
+		#clock-cells = <0>;
+		compatible = "ti,clkdm-gate-clock";
+		clocks = <&emu_src_mux_ck>;
+	};
+
+	pclk_fck: pclk_fck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&emu_src_ck>;
+		ti,bit-shift = <8>;
+		ti,max-div = <7>;
+		reg = <0x1140>;
+		ti,index-starts-at-one;
+	};
+
+	pclkx2_fck: pclkx2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&emu_src_ck>;
+		ti,bit-shift = <6>;
+		ti,max-div = <3>;
+		reg = <0x1140>;
+		ti,index-starts-at-one;
+	};
+
+	atclk_fck: atclk_fck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&emu_src_ck>;
+		ti,bit-shift = <4>;
+		ti,max-div = <3>;
+		reg = <0x1140>;
+		ti,index-starts-at-one;
+	};
+
+	traceclk_src_fck: traceclk_src_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+		ti,bit-shift = <2>;
+		reg = <0x1140>;
+	};
+
+	traceclk_fck: traceclk_fck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&traceclk_src_fck>;
+		ti,bit-shift = <11>;
+		ti,max-div = <7>;
+		reg = <0x1140>;
+		ti,index-starts-at-one;
+	};
+
+	secure_32k_fck: secure_32k_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	gpt12_fck: gpt12_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&secure_32k_fck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	wdt1_fck: wdt1_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&secure_32k_fck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+};
+
+&cm_clockdomains {
+	core_l3_clkdm: core_l3_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&sdrc_ick>;
+	};
+
+	dpll3_clkdm: dpll3_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dpll3_ck>;
+	};
+
+	dpll1_clkdm: dpll1_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dpll1_ck>;
+	};
+
+	per_clkdm: per_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+			 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+			 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+			 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+			 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+			 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+			 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+			 <&mcbsp4_ick>;
+	};
+
+	emu_clkdm: emu_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&emu_src_ck>;
+	};
+
+	dpll4_clkdm: dpll4_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dpll4_ck>;
+	};
+
+	wkup_clkdm: wkup_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+			 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+			 <&gpt1_ick>;
+	};
+
+	dss_clkdm: dss_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
+	};
+
+	core_l4_clkdm: core_l4_clkdm {
+		compatible = "ti,clockdomain";
+		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
+	};
+};
-- 
1.7.9.5

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Re: [PATCHv13 27/40] ARM: dts: omap3 clock data

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 597 bytes --]

Hi,

I just found some time to update my SSI driver adding DT clock
support. It works, but I wonder if the alias of the ssi clocks
can be changed to something like the following:

/* omap3430es1-clocks.dtsi */
ssi_ick: ssi_ick_3430es1 {};
ssi_ssr_fck: ssi_ssr_fck_3430es1 {};
ssi_sst_fck: ssi_sst_fck_3430es1 {};

/* omap36xx-omap3430es2plus-clocks.dtsi */
ssi_ick: ssi_ick_3430es2 {};
ssi_ssr_fck: ssi_ssr_fck_3430es2 {};
ssi_sst_fck: ssi_sst_fck_3430es2 {};

With this change I can reference the ssi clocks in omap3.dtsi
instead of creating files for omap3430es1 and omap3430es2+.

-- Sebastian

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

Re: [PATCHv13 27/40] ARM: dts: omap3 clock data

[Tero Kristo]

On 01/20/2014 08:00 PM, Sebastian Reichel wrote:
> Hi,
>
> I just found some time to update my SSI driver adding DT clock
> support. It works, but I wonder if the alias of the ssi clocks
> can be changed to something like the following:
>
> /* omap3430es1-clocks.dtsi */
> ssi_ick: ssi_ick_3430es1 {};
> ssi_ssr_fck: ssi_ssr_fck_3430es1 {};
> ssi_sst_fck: ssi_sst_fck_3430es1 {};
>
> /* omap36xx-omap3430es2plus-clocks.dtsi */
> ssi_ick: ssi_ick_3430es2 {};
> ssi_ssr_fck: ssi_ssr_fck_3430es2 {};
> ssi_sst_fck: ssi_sst_fck_3430es2 {};
>
> With this change I can reference the ssi clocks in omap3.dtsi
> instead of creating files for omap3430es1 and omap3430es2+.

Yea looks like a valid change to me. Feel free to send a patch for it.

-Tero

[PATCH] ARM: dts: omap3 clocks: simplify ssi aliases

[Sebastian Reichel]

update aliases for the ssi clocks ssi_ssr_fck, ssi_sst_fck and ssi_ick
to make them consistent for omap34xx and omap36xx. This makes it
possible to reference the clocks from generic omap3 dts files.

Signed-off-by: Sebastian Reichel <sre@debian.org>
---
 arch/arm/boot/dts/omap3430es1-clocks.dtsi              | 10 +++++-----
 arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
index 02f6c7f..6f31954 100644
--- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -82,16 +82,16 @@
 		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
 	};
 
-	ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
+	ssi_ssr_fck: ssi_ssr_fck_3430es1 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-clock";
 		clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
 	};
 
-	ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+	ssi_sst_fck: ssi_sst_fck_3430es1 {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
-		clocks = <&ssi_ssr_fck_3430es1>;
+		clocks = <&ssi_ssr_fck>;
 		clock-mult = <1>;
 		clock-div = <2>;
 	};
@@ -120,7 +120,7 @@
 		clock-div = <1>;
 	};
 
-	ssi_ick_3430es1: ssi_ick_3430es1 {
+	ssi_ick: ssi_ick_3430es1 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-no-wait-interface-clock";
 		clocks = <&ssi_l4_ick>;
@@ -203,6 +203,6 @@
 			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
 			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
 			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
-			 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
+			 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
index 8ed475d..877318c 100644
--- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -25,16 +25,16 @@
 		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
 	};
 
-	ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
+	ssi_ssr_fck: ssi_ssr_fck_3430es2 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-clock";
 		clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
 	};
 
-	ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+	ssi_sst_fck: ssi_sst_fck_3430es2 {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
-		clocks = <&ssi_ssr_fck_3430es2>;
+		clocks = <&ssi_ssr_fck>;
 		clock-mult = <1>;
 		clock-div = <2>;
 	};
@@ -55,7 +55,7 @@
 		clock-div = <1>;
 	};
 
-	ssi_ick_3430es2: ssi_ick_3430es2 {
+	ssi_ick: ssi_ick_3430es2 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-ssi-interface-clock";
 		clocks = <&ssi_l4_ick>;
@@ -193,6 +193,6 @@
 			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
 			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
 			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
-			 <&ssi_ick_3430es2>;
+			 <&ssi_ick>;
 	};
 };
-- 
1.8.5.2

Re: [PATCH] ARM: dts: omap3 clocks: simplify ssi aliases

[Tony Lindgren]

* Sebastian Reichel <sre@debian.org> [140121 06:39]:
> update aliases for the ssi clocks ssi_ssr_fck, ssi_sst_fck and ssi_ick
> to make them consistent for omap34xx and omap36xx. This makes it
> possible to reference the clocks from generic omap3 dts files.

Is this needed as a fix for v3.14-rc? If so, please let me know
and ack if you want me to take it.

Tony
 
> Signed-off-by: Sebastian Reichel <sre@debian.org>
> ---
>  arch/arm/boot/dts/omap3430es1-clocks.dtsi              | 10 +++++-----
>  arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | 10 +++++-----
>  2 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
> index 02f6c7f..6f31954 100644
> --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi
> +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
> @@ -82,16 +82,16 @@
>  		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
>  	};
>  
> -	ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
> +	ssi_ssr_fck: ssi_ssr_fck_3430es1 {
>  		#clock-cells = <0>;
>  		compatible = "ti,composite-clock";
>  		clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
>  	};
>  
> -	ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
> +	ssi_sst_fck: ssi_sst_fck_3430es1 {
>  		#clock-cells = <0>;
>  		compatible = "fixed-factor-clock";
> -		clocks = <&ssi_ssr_fck_3430es1>;
> +		clocks = <&ssi_ssr_fck>;
>  		clock-mult = <1>;
>  		clock-div = <2>;
>  	};
> @@ -120,7 +120,7 @@
>  		clock-div = <1>;
>  	};
>  
> -	ssi_ick_3430es1: ssi_ick_3430es1 {
> +	ssi_ick: ssi_ick_3430es1 {
>  		#clock-cells = <0>;
>  		compatible = "ti,omap3-no-wait-interface-clock";
>  		clocks = <&ssi_l4_ick>;
> @@ -203,6 +203,6 @@
>  			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
>  			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
>  			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
> -			 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
> +			 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
>  	};
>  };
> diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
> index 8ed475d..877318c 100644
> --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
> +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
> @@ -25,16 +25,16 @@
>  		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
>  	};
>  
> -	ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
> +	ssi_ssr_fck: ssi_ssr_fck_3430es2 {
>  		#clock-cells = <0>;
>  		compatible = "ti,composite-clock";
>  		clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
>  	};
>  
> -	ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
> +	ssi_sst_fck: ssi_sst_fck_3430es2 {
>  		#clock-cells = <0>;
>  		compatible = "fixed-factor-clock";
> -		clocks = <&ssi_ssr_fck_3430es2>;
> +		clocks = <&ssi_ssr_fck>;
>  		clock-mult = <1>;
>  		clock-div = <2>;
>  	};
> @@ -55,7 +55,7 @@
>  		clock-div = <1>;
>  	};
>  
> -	ssi_ick_3430es2: ssi_ick_3430es2 {
> +	ssi_ick: ssi_ick_3430es2 {
>  		#clock-cells = <0>;
>  		compatible = "ti,omap3-ssi-interface-clock";
>  		clocks = <&ssi_l4_ick>;
> @@ -193,6 +193,6 @@
>  			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
>  			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
>  			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
> -			 <&ssi_ick_3430es2>;
> +			 <&ssi_ick>;
>  	};
>  };
> -- 
> 1.8.5.2
> 

Re: [PATCH] ARM: dts: omap3 clocks: simplify ssi aliases

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 658 bytes --]

On Thu, Feb 13, 2014 at 02:49:14PM -0800, Tony Lindgren wrote:
> * Sebastian Reichel <sre@debian.org> [140121 06:39]:
> > update aliases for the ssi clocks ssi_ssr_fck, ssi_sst_fck and ssi_ick
> > to make them consistent for omap34xx and omap36xx. This makes it
> > possible to reference the clocks from generic omap3 dts files.
> 
> Is this needed as a fix for v3.14-rc? If so, please let me know
> and ack if you want me to take it.

The SSI driver will not arrive before 3.15 and 3.14 dts files do not
contain any SSI nodes.

Thus it should be enough to queue it for 3.15 if it goes via the
same tree as the SSI dts patches.

-- Sebastian

[-- Attachment #2: Digital signature --]
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Re: [PATCH] ARM: dts: omap3 clocks: simplify ssi aliases

[Tero Kristo]

On 02/14/2014 03:25 AM, Sebastian Reichel wrote:
> On Thu, Feb 13, 2014 at 02:49:14PM -0800, Tony Lindgren wrote:
>> * Sebastian Reichel <sre@debian.org> [140121 06:39]:
>>> update aliases for the ssi clocks ssi_ssr_fck, ssi_sst_fck and ssi_ick
>>> to make them consistent for omap34xx and omap36xx. This makes it
>>> possible to reference the clocks from generic omap3 dts files.
>>
>> Is this needed as a fix for v3.14-rc? If so, please let me know
>> and ack if you want me to take it.
>
> The SSI driver will not arrive before 3.15 and 3.14 dts files do not
> contain any SSI nodes.
>
> Thus it should be enough to queue it for 3.15 if it goes via the
> same tree as the SSI dts patches.
>
> -- Sebastian
>

The patch itself looks good to me, so acked.

-Tero

Re: [PATCH] ARM: dts: omap3 clocks: simplify ssi aliases

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [140214 05:50]:
> On 02/14/2014 03:25 AM, Sebastian Reichel wrote:
> >On Thu, Feb 13, 2014 at 02:49:14PM -0800, Tony Lindgren wrote:
> >>* Sebastian Reichel <sre@debian.org> [140121 06:39]:
> >>>update aliases for the ssi clocks ssi_ssr_fck, ssi_sst_fck and ssi_ick
> >>>to make them consistent for omap34xx and omap36xx. This makes it
> >>>possible to reference the clocks from generic omap3 dts files.
> >>
> >>Is this needed as a fix for v3.14-rc? If so, please let me know
> >>and ack if you want me to take it.
> >
> >The SSI driver will not arrive before 3.15 and 3.14 dts files do not
> >contain any SSI nodes.
> >
> >Thus it should be enough to queue it for 3.15 if it goes via the
> >same tree as the SSI dts patches.
> >
> >-- Sebastian
> >
> 
> The patch itself looks good to me, so acked.

Thanks applying into omap-for-v3.15/dt with Tero's ack.

Tony

[PATCHv13 28/40] ARM: dts: AM35xx: use DT clock data

[Tero Kristo]

AM35xx now uses the clock data from device tree. Most of the data is
shared with OMAP3xxx, but as there is some delta, a new base .dtsi
file is also created for the SoC.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/am3517.dtsi |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 2fbe02f..788391f 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -61,3 +61,6 @@
 		};
 	};
 };
+
+/include/ "am35xx-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
-- 
1.7.9.5

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[PATCHv13 29/40] ARM: dts: am43xx clock data

[Tero Kristo]

This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/am4372.dtsi        |   28 ++
 arch/arm/boot/dts/am43xx-clocks.dtsi |  656 ++++++++++++++++++++++++++++++++++
 2 files changed, 684 insertions(+)
 create mode 100644 arch/arm/boot/dts/am43xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 974d103..c6bd4d9 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -67,6 +67,32 @@
 		ranges;
 		ti,hwmods = "l3_main";
 
+		prcm: prcm@44df0000 {
+			compatible = "ti,am4-prcm";
+			reg = <0x44df0000 0x11000>;
+
+			prcm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			prcm_clockdomains: clockdomains {
+			};
+		};
+
+		scrm: scrm@44e10000 {
+			compatible = "ti,am4-scrm";
+			reg = <0x44e10000 0x2000>;
+
+			scrm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			scrm_clockdomains: clockdomains {
+			};
+		};
+
 		edma: edma@49000000 {
 			compatible = "ti,edma3";
 			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
@@ -665,3 +691,5 @@
 		};
 	};
 };
+
+/include/ "am43xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
new file mode 100644
index 0000000..142009c
--- /dev/null
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -0,0 +1,656 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+	sys_clkin_ck: sys_clkin_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+		ti,bit-shift = <22>;
+		reg = <0x0040>;
+	};
+
+	adc_tsc_fck: adc_tsc_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dcan0_fck: dcan0_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dcan1_fck: dcan1_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	mcasp0_fck: mcasp0_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	mcasp1_fck: mcasp1_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	smartreflex0_fck: smartreflex0_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	smartreflex1_fck: smartreflex1_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	sha0_fck: sha0_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	aes0_fck: aes0_fck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+};
+&prcm_clocks {
+	clk_32768_ck: clk_32768_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	clk_rc32k_ck: clk_rc32k_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	virt_19200000_ck: virt_19200000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <19200000>;
+	};
+
+	virt_24000000_ck: virt_24000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+	};
+
+	virt_25000000_ck: virt_25000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+	};
+
+	virt_26000000_ck: virt_26000000_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+	};
+
+	tclkin_ck: tclkin_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+	};
+
+	dpll_core_ck: dpll_core_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-core-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+	};
+
+	dpll_core_x2_ck: dpll_core_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-x2-clock";
+		clocks = <&dpll_core_ck>;
+	};
+
+	dpll_core_m4_ck: dpll_core_m4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2d38>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_m5_ck: dpll_core_m5_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2d3c>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_core_m6_ck: dpll_core_m6_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2d40>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_mpu_ck: dpll_mpu_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+	};
+
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_mpu_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2d70>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_ddr_ck: dpll_ddr_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x2da0>, <0x2da4>, <0x2dac>;
+	};
+
+	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_ddr_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2db0>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_disp_ck: dpll_disp_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+	};
+
+	dpll_disp_m2_ck: dpll_disp_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_disp_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2e30>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_ck: dpll_per_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-j-type-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x2de0>, <0x2de4>, <0x2dec>;
+	};
+
+	dpll_per_m2_ck: dpll_per_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_per_ck>;
+		ti,max-div = <127>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2df0>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <4>;
+	};
+
+	clk_24mhz: clk_24mhz {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <8>;
+	};
+
+	clkdiv32k_ck: clkdiv32k_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&clk_24mhz>;
+		clock-mult = <1>;
+		clock-div = <732>;
+	};
+
+	clkdiv32k_ick: clkdiv32k_ick {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkdiv32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x2a38>;
+	};
+
+	sysclk_div: sysclk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	pruss_ocp_gclk: pruss_ocp_gclk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
+		reg = <0x4248>;
+	};
+
+	clk_32k_tpm_ck: clk_32k_tpm_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	timer1_fck: timer1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+		reg = <0x4200>;
+	};
+
+	timer2_fck: timer2_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x4204>;
+	};
+
+	timer3_fck: timer3_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x4208>;
+	};
+
+	timer4_fck: timer4_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x420c>;
+	};
+
+	timer5_fck: timer5_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x4210>;
+	};
+
+	timer6_fck: timer6_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x4214>;
+	};
+
+	timer7_fck: timer7_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+		reg = <0x4218>;
+	};
+
+	wdt1_fck: wdt1_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+		reg = <0x422c>;
+	};
+
+	l3_gclk: l3_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sysclk_div>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	l4hs_gclk: l4hs_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	l3s_gclk: l3s_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_div2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	l4ls_gclk: l4ls_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m4_div2_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m5_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
+		reg = <0x4238>;
+	};
+
+	clk_32k_mosc_ck: clk_32k_mosc_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
+		reg = <0x4240>;
+	};
+
+	gpio0_dbclk: gpio0_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&gpio0_dbclk_mux_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x2b68>;
+	};
+
+	gpio1_dbclk: gpio1_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkdiv32k_ick>;
+		ti,bit-shift = <8>;
+		reg = <0x8c78>;
+	};
+
+	gpio2_dbclk: gpio2_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkdiv32k_ick>;
+		ti,bit-shift = <8>;
+		reg = <0x8c80>;
+	};
+
+	gpio3_dbclk: gpio3_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkdiv32k_ick>;
+		ti,bit-shift = <8>;
+		reg = <0x8c88>;
+	};
+
+	gpio4_dbclk: gpio4_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkdiv32k_ick>;
+		ti,bit-shift = <8>;
+		reg = <0x8c90>;
+	};
+
+	gpio5_dbclk: gpio5_dbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkdiv32k_ick>;
+		ti,bit-shift = <8>;
+		reg = <0x8c98>;
+	};
+
+	mmc_clk: mmc_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x423c>;
+	};
+
+	gfx_fck_div_ck: gfx_fck_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&gfx_fclk_clksel_ck>;
+		reg = <0x423c>;
+		ti,max-div = <2>;
+	};
+
+	disp_clk: disp_clk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+		reg = <0x4244>;
+	};
+
+	dpll_extdev_ck: dpll_extdev_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-clock";
+		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+		reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+	};
+
+	dpll_extdev_m2_ck: dpll_extdev_m2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_extdev_ck>;
+		ti,max-div = <127>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2e70>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	mux_synctimer32k_ck: mux_synctimer32k_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
+		reg = <0x4230>;
+	};
+
+	synctimer_32kclk: synctimer_32kclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&mux_synctimer32k_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x2a30>;
+	};
+
+	timer8_fck: timer8_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+		reg = <0x421c>;
+	};
+
+	timer9_fck: timer9_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+		reg = <0x4220>;
+	};
+
+	timer10_fck: timer10_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+		reg = <0x4224>;
+	};
+
+	timer11_fck: timer11_fck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+		reg = <0x4228>;
+	};
+
+	cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_core_m5_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&cpsw_50m_clkdiv>;
+		clock-mult = <1>;
+		clock-div = <10>;
+	};
+
+	dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+		#clock-cells = <0>;
+		compatible = "ti,am3-dpll-x2-clock";
+		clocks = <&dpll_ddr_ck>;
+	};
+
+	dpll_ddr_m4_ck: dpll_ddr_m4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_ddr_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2db8>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_ck>;
+		clock-mult = <1>;
+		clock-div = <1>;
+	};
+
+	dll_aging_clk_div: dll_aging_clk_div {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin_ck>;
+		reg = <0x4250>;
+		ti,dividers = <8>, <16>, <32>;
+	};
+
+	div_core_25m_ck: div_core_25m_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sysclk_div>;
+		clock-mult = <1>;
+		clock-div = <8>;
+	};
+
+	func_12m_clk: func_12m_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&dpll_per_m2_ck>;
+		clock-mult = <1>;
+		clock-div = <16>;
+	};
+
+	vtp_clk_div: vtp_clk_div {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin_ck>;
+		clock-mult = <1>;
+		clock-div = <2>;
+	};
+
+	usbphy_32khz_clkmux: usbphy_32khz_clkmux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+		reg = <0x4260>;
+	};
+};
-- 
1.7.9.5

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[PATCHv13 30/40] ARM: OMAP2+: clock: add support for indexed memmaps

[Tero Kristo]

Using indexed memmaps is required for isolating the actual memory access
from the clock code. Now, the driver providing the support for the clock IP
block provides the low level routines for reading/writing clock registers
also.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 arch/arm/mach-omap2/clock.c |   26 +++++++++++++++++++++++++-
 arch/arm/mach-omap2/clock.h |    5 +++++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 238be3f..be53bb2 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -26,7 +26,6 @@
 #include <linux/clk-private.h>
 #include <asm/cpu.h>
 
-
 #include <trace/events/power.h>
 
 #include "soc.h"
@@ -56,6 +55,31 @@ u16 cpu_mask;
 static bool clkdm_control = true;
 
 static LIST_HEAD(clk_hw_omap_clocks);
+void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
+{
+	if (clk->flags & MEMMAP_ADDRESSING) {
+		struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+		writel_relaxed(val, clk_memmaps[r->index] + r->offset);
+	} else {
+		writel_relaxed(val, reg);
+	}
+}
+
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
+{
+	u32 val;
+
+	if (clk->flags & MEMMAP_ADDRESSING) {
+		struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+		val = readl_relaxed(clk_memmaps[r->index] + r->offset);
+	} else {
+		val = readl_relaxed(reg);
+	}
+
+	return val;
+}
 
 /*
  * Used for clocks that have the same value as the parent clock,
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index cbe5ff7..bda767a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -254,6 +254,9 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 			       const char *core_ck_name,
 			       const char *mpu_ck_name);
 
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
+
 extern u16 cpu_mask;
 
 extern const struct clkops clkops_omap2_dflt_wait;
@@ -288,6 +291,8 @@ extern const struct clksel_rate div_1_3_rates[];
 extern const struct clksel_rate div_1_4_rates[];
 extern const struct clksel_rate div31_1to31_rates[];
 
+extern void __iomem *clk_memmaps[];
+
 extern int am33xx_clk_init(void);
 
 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
-- 
1.7.9.5

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[PATCHv13 33/40] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name

[Tero Kristo]

DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.

Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.

This patch also changes the return value for _init_clkdm to 0 for
incorrect clkdm_name, as this a warning, not a fatal error.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Tested-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
Acked-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/mach-omap2/omap_hwmod.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cc24c95..433fe2f 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1578,7 +1578,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
 	if (!oh->clkdm) {
 		pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
 			oh->name, oh->clkdm_name);
-		return -EINVAL;
+		return 0;
 	}
 
 	pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -4237,6 +4237,7 @@ void __init omap_hwmod_init(void)
 		soc_ops.assert_hardreset = _omap2_assert_hardreset;
 		soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
 		soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+		soc_ops.init_clkdm = _init_clkdm;
 	} else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
 		soc_ops.enable_module = _omap4_enable_module;
 		soc_ops.disable_module = _omap4_disable_module;
-- 
1.7.9.5

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[PATCHv13 35/40] ARM: OMAP2+: io: use new clock init API

[Tero Kristo]

clk_init is now separated to a common function which gets called for all
SoC:s, which initializes the DT clocks and calls the SoC specific clock init.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 arch/arm/mach-omap2/common.h |    2 +-
 arch/arm/mach-omap2/io.c     |   32 +++++++++++++++++++++++---------
 arch/arm/mach-omap2/timer.c  |    6 ++----
 3 files changed, 26 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index e30ef67..5ccf36d 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -305,7 +305,7 @@ struct omap_hwmod;
 extern int omap_dss_reset(struct omap_hwmod *);
 
 /* SoC specific clock initializer */
-extern int (*omap_clk_init)(void);
+int omap_clk_init(void);
 
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3d9b3fc..8517a62 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,10 +55,10 @@
 #include "prm44xx.h"
 
 /*
- * omap_clk_init: points to a function that does the SoC-specific
+ * omap_clk_soc_init: points to a function that does the SoC-specific
  * clock initializations
  */
-int (*omap_clk_init)(void);
+static int (*omap_clk_soc_init)(void);
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -419,7 +419,7 @@ void __init omap2420_init_early(void)
 	omap242x_clockdomains_init();
 	omap2420_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_init = omap2420_clk_init;
+	omap_clk_soc_init = omap2420_clk_init;
 }
 
 void __init omap2420_init_late(void)
@@ -448,7 +448,7 @@ void __init omap2430_init_early(void)
 	omap243x_clockdomains_init();
 	omap2430_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_init = omap2430_clk_init;
+	omap_clk_soc_init = omap2430_clk_init;
 }
 
 void __init omap2430_init_late(void)
@@ -482,7 +482,7 @@ void __init omap3_init_early(void)
 	omap3xxx_clockdomains_init();
 	omap3xxx_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_init = omap3xxx_clk_init;
+	omap_clk_soc_init = omap3xxx_clk_init;
 }
 
 void __init omap3430_init_early(void)
@@ -520,7 +520,7 @@ void __init ti81xx_init_early(void)
 	omap3xxx_clockdomains_init();
 	omap3xxx_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_init = omap3xxx_clk_init;
+	omap_clk_soc_init = omap3xxx_clk_init;
 }
 
 void __init omap3_init_late(void)
@@ -581,7 +581,7 @@ void __init am33xx_init_early(void)
 	am33xx_clockdomains_init();
 	am33xx_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_init = am33xx_clk_init;
+	omap_clk_soc_init = am33xx_clk_init;
 }
 
 void __init am33xx_init_late(void)
@@ -635,7 +635,7 @@ void __init omap4430_init_early(void)
 	omap44xx_clockdomains_init();
 	omap44xx_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_init = omap4xxx_clk_init;
+	omap_clk_soc_init = omap4xxx_clk_init;
 }
 
 void __init omap4430_init_late(void)
@@ -666,7 +666,7 @@ void __init omap5_init_early(void)
 	omap54xx_clockdomains_init();
 	omap54xx_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_init = omap5xxx_dt_clk_init;
+	omap_clk_soc_init = omap5xxx_dt_clk_init;
 }
 
 void __init omap5_init_late(void)
@@ -711,3 +711,17 @@ void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 		_omap2_init_reprogram_sdrc();
 	}
 }
+
+int __init omap_clk_init(void)
+{
+	int ret = 0;
+
+	if (!omap_clk_soc_init)
+		return 0;
+
+	ret = of_prcm_init();
+	if (!ret)
+		ret = omap_clk_soc_init();
+
+	return ret;
+}
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 3ca81e0..60e5fc9 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -570,8 +570,7 @@ static inline void __init realtime_counter_init(void)
 			       clksrc_nr, clksrc_src, clksrc_prop)	\
 void __init omap##name##_gptimer_timer_init(void)			\
 {									\
-	if (omap_clk_init)						\
-		omap_clk_init();					\
+	omap_clk_init();					\
 	omap_dmtimer_init();						\
 	omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);	\
 	omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,		\
@@ -582,8 +581,7 @@ void __init omap##name##_gptimer_timer_init(void)			\
 				clksrc_nr, clksrc_src, clksrc_prop)	\
 void __init omap##name##_sync32k_timer_init(void)		\
 {									\
-	if (omap_clk_init)						\
-		omap_clk_init();					\
+	omap_clk_init();					\
 	omap_dmtimer_init();						\
 	omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);	\
 	/* Enable the use of clocksource="gp_timer" kernel parameter */	\
-- 
1.7.9.5

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[PATCHv13 36/40] ARM: OMAP4: remove old clock data and link in new clock init code

[Tero Kristo]

OMAP4 clocks have now been moved to DT, thus remove the old data file
and use the new init code under drivers/clk/omap/clk-44xx.c.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Tested-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
Acked-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/mach-omap2/Makefile          |    2 +-
 arch/arm/mach-omap2/cclock44xx_data.c | 1735 ---------------------------------
 arch/arm/mach-omap2/io.c              |    2 +-
 3 files changed, 2 insertions(+), 1737 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cclock44xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index adcef40..e9d63ec 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -186,7 +186,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clock34xx.o clkt34xx_dpll3m2.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clock3517.o clock36xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= dpll3xxx.o cclock3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) cclock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o
 obj-$(CONFIG_SOC_AM33XX)		+= cclock33xx_data.o
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
deleted file mode 100644
index ec0dc0b..0000000
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ /dev/null
@@ -1,1735 +0,0 @@
-/*
- * OMAP4 Clock data
- *
- * Copyright (C) 2009-2012 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul-DWxLp4Yu+b8AvxtiuMwx3w@public.gmane.org)
- * Rajendra Nayak (rnayak-l0cyMroinI0@public.gmane.org)
- * Benoit Cousson (b-cousson-l0cyMroinI0@public.gmane.org)
- * Mike Turquette (mturquette-l0cyMroinI0@public.gmane.org)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX Some of the ES1 clocks have been removed/changed; once support
- * is added for discriminating clocks by ES level, these should be added back
- * in.
- *
- * XXX All of the remaining MODULEMODE clock nodes should be removed
- * once the drivers are updated to use pm_runtime or to use the appropriate
- * upstream clock node for rate/parent selection.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock44xx.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-#include "scrm44xx.h"
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL_SHIFT		0
-#define OMAP4430_MODULEMODE_SWCTRL_SHIFT		1
-
-/*
- * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
- * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
- * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
- * half of this value.
- */
-#define OMAP4_DPLL_ABE_DEFFREQ				98304000
-
-/*
- * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
- * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
- * locked frequency for the USB DPLL is 960MHz.
- */
-#define OMAP4_DPLL_USB_DEFFREQ				960000000
-
-/* Root clocks */
-
-DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
-		OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
-		OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
-
-static const char *sys_clkin_ck_parents[] = {
-	"virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
-	"virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
-	"virt_38400000_ck",
-};
-
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
-	       OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-
-DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
-
-DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
-	       NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
-	       OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_ABE,
-	.clk_bypass	= &abe_dpll_bypass_clk_mux_ck,
-	.clk_ref	= &abe_dpll_refclk_mux_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_ABE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_ABE,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_ABE,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.m4xen_mask	= OMAP4430_DPLL_REGM4XEN_MASK,
-	.lpmode_mask	= OMAP4430_DPLL_LPMODE_EN_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-
-static const char *dpll_abe_ck_parents[] = {
-	"abe_dpll_refclk_mux_ck",
-};
-
-static struct clk dpll_abe_ck;
-
-static const struct clk_ops dpll_abe_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
-	.round_rate	= &omap4_dpll_regm4xen_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_abe_ck_hw = {
-	.hw = {
-		.clk = &dpll_abe_ck,
-	},
-	.dpll_data	= &dpll_abe_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
-
-static const char *dpll_abe_x2_ck_parents[] = {
-	"dpll_abe_ck",
-};
-
-static struct clk dpll_abe_x2_ck;
-
-static const struct clk_ops dpll_abe_x2_ck_ops = {
-	.recalc_rate	= &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_abe_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_abe_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-static const struct clk_ops omap_hsdivider_ops = {
-	.set_rate	= &omap2_clksel_set_rate,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-};
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-			0x0, 1, 8);
-
-DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
-		   OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
-		   OMAP4430_CM1_ABE_AESS_CLKCTRL,
-		   OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-		   OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
-			  OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
-
-static const char *core_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "dpll_abe_m3x2_ck",
-};
-
-DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
-	       OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
-	       0x0, NULL);
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_CORE,
-	.clk_bypass	= &core_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_CORE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_CORE,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_CORE,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-
-static const char *dpll_core_ck_parents[] = {
-	"sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-	.hw = {
-		.clk = &dpll_core_ck,
-	},
-	.dpll_data	= &dpll_core_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-	"dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_core_x2_ck,
-	},
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_CORE,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
-			2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
-		   OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-		   0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
-		   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-		   0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
-		   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
-			0x0, 1, 2);
-
-DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
-		   OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-		   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const struct clk_ops dpll_hsd_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static const struct clk_ops func_dmic_abe_gfclk_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-};
-
-static const char *dpll_core_m3x2_ck_parents[] = {
-	"dpll_core_x2_ck",
-};
-
-static const struct clksel dpll_core_m3x2_div[] = {
-	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
-			 OMAP4430_CM_DIV_M3_DPLL_CORE,
-			 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-			 OMAP4430_CM_DIV_M3_DPLL_CORE,
-			 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-			 dpll_core_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "div_iva_hs_clk",
-};
-
-DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-	       OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_IVA,
-	.clk_bypass	= &iva_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_IVA,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_IVA,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_IVA,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_iva_ck_parents[] = {
-	"sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_iva_ck;
-
-static const struct clk_ops dpll_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_iva_ck_hw = {
-	.hw = {
-		.clk = &dpll_iva_ck,
-	},
-	.dpll_data	= &dpll_iva_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
-
-static const char *dpll_iva_x2_ck_parents[] = {
-	"dpll_iva_ck",
-};
-
-static struct clk dpll_iva_x2_ck;
-
-static struct clk_hw_omap dpll_iva_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_iva_x2_ck,
-	},
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,
-	.clk_bypass	= &div_mpu_hs_clk,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_MPU,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_MPU,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_MPU,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_mpu_ck_parents[] = {
-	"sys_clkin_ck", "div_mpu_hs_clk"
-};
-
-static struct clk dpll_mpu_ck;
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-	.hw = {
-		.clk = &dpll_mpu_ck,
-	},
-	.dpll_data	= &dpll_mpu_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_MPU,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-			&dpll_abe_m3x2_ck, 0x0, 1, 2);
-
-static const char *per_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "per_hs_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-	       OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_PER,
-	.clk_bypass	= &per_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_PER,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_PER,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_PER,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_per_ck_parents[] = {
-	"sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-	.hw = {
-		.clk = &dpll_per_ck,
-	},
-	.dpll_data	= &dpll_per_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		   OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-		   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const char *dpll_per_x2_ck_parents[] = {
-	"dpll_per_ck",
-};
-
-static struct clk dpll_per_x2_ck;
-
-static struct clk_hw_omap dpll_per_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_per_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-static const char *dpll_per_m3x2_ck_parents[] = {
-	"dpll_per_x2_ck",
-};
-
-static const struct clksel dpll_per_m3x2_div[] = {
-	{ .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
-			 OMAP4430_CM_DIV_M3_DPLL_PER,
-			 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-			 OMAP4430_CM_DIV_M3_DPLL_PER,
-			 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-			 dpll_per_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-			&dpll_abe_m3x2_ck, 0x0, 1, 3);
-
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_USB,
-	.clk_bypass	= &usb_hs_clk_div_ck,
-	.flags		= DPLL_J_TYPE,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_USB,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_USB,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_USB,
-	.mult_mask	= OMAP4430_DPLL_MULT_USB_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_0_7_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.sddiv_mask	= OMAP4430_DPLL_SD_DIV_MASK,
-	.max_multiplier	= 4095,
-	.max_divider	= 256,
-	.min_divider	= 1,
-};
-
-static const char *dpll_usb_ck_parents[] = {
-	"sys_clkin_ck", "usb_hs_clk_div_ck"
-};
-
-static struct clk dpll_usb_ck;
-
-static const struct clk_ops dpll_usb_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap dpll_usb_ck_hw = {
-	.hw = {
-		.clk = &dpll_usb_ck,
-	},
-	.dpll_data	= &dpll_usb_dd,
-	.clkdm_name	= "l3_init_clkdm",
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
-
-static const char *dpll_usb_clkdcoldo_ck_parents[] = {
-	"dpll_usb_ck",
-};
-
-static struct clk dpll_usb_clkdcoldo_ck;
-
-static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
-};
-
-static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
-	.hw = {
-		.clk = &dpll_usb_clkdcoldo_ck,
-	},
-	.clksel_reg	= OMAP4430_CM_CLKDCOLDO_DPLL_USB,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
-		  dpll_usb_clkdcoldo_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_USB,
-			  OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
-
-static const char *ducati_clk_mux_ck_parents[] = {
-	"div_core_ck", "dpll_per_m6x2_ck",
-};
-
-DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 16);
-
-DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
-			1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 8);
-
-static const struct clk_div_table func_48m_fclk_rates[] = {
-	{ .div = 4, .val = 0 },
-	{ .div = 8, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
-			 NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk,	"dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 4);
-
-static const struct clk_div_table func_64m_fclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 4, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
-			 NULL);
-
-static const struct clk_div_table func_96m_fclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 4, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
-			 NULL);
-
-static const struct clk_div_table init_60m_fclk_rates[] = {
-	{ .div = 1, .val = 0 },
-	{ .div = 8, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
-			 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
-			 OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
-			 0x0, init_60m_fclk_rates, NULL);
-
-DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
-		   OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
-		   OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-			0x0, 1, 16);
-
-static const char *l4_wkup_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "lp_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const struct clk_div_table ocp_abe_iclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 1, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
-			 OMAP4430_CM1_ABE_AESS_CLKCTRL,
-			 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-			 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-			 0x0, ocp_abe_iclk_rates, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
-			0x0, 1, 4);
-
-DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
-		   OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-		   OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-		   OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-		   OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const char *dbgclk_mux_ck_parents[] = {
-	"sys_clkin_ck"
-};
-
-static struct clk dbgclk_mux_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
-DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
-		  dpll_usb_clkdcoldo_ck_ops);
-
-/* Leaf clocks controlled by modules */
-
-DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-		OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table div_ts_ck_rates[] = {
-	{ .div = 8, .val = 0 },
-	{ .div = 16, .val = 1 },
-	{ .div = 32, .val = 2 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-			 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-			 OMAP4430_CLKSEL_24_25_SHIFT,
-			 OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
-			 NULL);
-
-DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
-		OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-		OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
-		0x0, NULL);
-
-static const char *dmic_sync_mux_ck_parents[] = {
-	"abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
-};
-
-DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-	{ .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_dmic_abe_gfclk_parents[] = {
-	"dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
-		    OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-		    func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
-		CLK_SET_RATE_PARENT,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-		   OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
-		   OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-		OMAP4430_OPTFCLKEN_DBCLK_SHIFT,	0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-		OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-static const struct clksel sgx_clk_mux_sel[] = {
-	{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *sgx_clk_mux_parents[] = {
-	"dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
-		    OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
-		    sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
-		   OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
-		   OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
-		OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
-	{ .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcasp_abe_gfclk_parents[] = {
-	"mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-		    func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
-	{ .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp1_gfclk_parents[] = {
-	"mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
-	{ .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp2_gfclk_parents[] = {
-	"mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
-	{ .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp3_gfclk_parents[] = {
-	"mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const char *mcbsp4_sync_mux_ck_parents[] = {
-	"func_96m_fclk", "per_abe_nc_fclk",
-};
-
-DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-	{ .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *per_mcbsp4_gfclk_parents[] = {
-	"mcbsp4_sync_mux_ck", "pad_clks_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
-		    OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const struct clksel hsmmc1_fclk_sel[] = {
-	{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
-	{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *hsmmc1_fclk_parents[] = {
-	"func_64m_fclk", "func_96m_fclk",
-};
-
-DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-		    OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-		    OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
-		&pad_slimbus_core_clks_ck, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clksel dmt1_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const struct clksel timer5_sync_mux_sel[] = {
-	{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer5_sync_mux_parents[] = {
-	"syc_clk_div_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static struct clk usb_host_fs_fck;
-
-static const char *usb_host_fs_fck_parent_names[] = {
-	"func_48mc_fclk",
-};
-
-static const struct clk_ops usb_host_fs_fck_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-};
-
-static struct clk_hw_omap usb_host_fs_fck_hw = {
-	.hw = {
-		.clk = &usb_host_fs_fck,
-	},
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-};
-
-DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
-		  usb_host_fs_fck_ops);
-
-static const char *utmi_p1_gfclk_parents[] = {
-	"init_60m_fclk", "xclk60mhsp1_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	       OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
-
-static const char *utmi_p2_gfclk_parents[] = {
-	"init_60m_fclk", "xclk60mhsp2_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	       OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
-		&dpll_usb_m2_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
-		&init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
-		&init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
-		&dpll_usb_m2_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const char *otg_60m_gfclk_parents[] = {
-	"utmi_phy_clkout_ck", "xclk60motg_ck",
-};
-
-DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
-	       OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-		OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-		OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-		OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table usim_ck_rates[] = {
-	{ .div = 14, .val = 0 },
-	{ .div = 18, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-			 OMAP4430_CM_WKUP_USIM_CLKCTRL,
-			 OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
-			 0x0, usim_ck_rates, NULL);
-
-DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
-		OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-		0x0, NULL);
-
-/* Remaining optional clocks */
-static const char *pmd_stm_clock_mux_ck_parents[] = {
-	"sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
-};
-
-DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
-	       OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	       OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
-	       OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
-		   &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-		   OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
-		   OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-static const char *trace_clk_div_ck_parents[] = {
-	"pmd_trace_clk_mux_ck",
-};
-
-static const struct clksel trace_clk_div_div[] = {
-	{ .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
-
-static struct clk trace_clk_div_ck;
-
-static const struct clk_ops trace_clk_div_ck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.set_rate	= &omap2_clksel_set_rate,
-	.round_rate	= &omap2_clksel_round_rate,
-	.init		= &omap2_init_clk_clkdm,
-	.enable		= &omap2_clkops_enable_clkdm,
-	.disable	= &omap2_clkops_disable_clkdm,
-};
-
-static struct clk_hw_omap trace_clk_div_ck_hw = {
-	.hw = {
-		.clk = &trace_clk_div_ck,
-	},
-	.clkdm_name	= "emu_sys_clkdm",
-	.clksel		= trace_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
-		  trace_clk_div_ck_ops);
-
-/* SCRM aux clk nodes */
-
-static const struct clksel auxclk_src_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *auxclk_src_ck_parents[] = {
-	"sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
-};
-
-static const struct clk_ops auxclk_src_ck_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-static const char *auxclkreq_ck_parents[] = {
-	"auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
-	"auxclk5_ck",
-};
-
-DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-/*
- * clocks specific to omap4460
- */
-static struct omap_clk omap446x_clks[] = {
-	CLK(NULL,	"div_ts_ck",			&div_ts_ck),
-	CLK(NULL,	"bandgap_ts_fclk",		&bandgap_ts_fclk),
-};
-
-/*
- * clocks specific to omap4430
- */
-static struct omap_clk omap443x_clks[] = {
-	CLK(NULL,	"bandgap_fclk",			&bandgap_fclk),
-};
-
-/*
- * clocks common to omap44xx
- */
-static struct omap_clk omap44xx_clks[] = {
-	CLK(NULL,	"extalt_clkin_ck",		&extalt_clkin_ck),
-	CLK(NULL,	"pad_clks_src_ck",		&pad_clks_src_ck),
-	CLK(NULL,	"pad_clks_ck",			&pad_clks_ck),
-	CLK(NULL,	"pad_slimbus_core_clks_ck",	&pad_slimbus_core_clks_ck),
-	CLK(NULL,	"secure_32k_clk_src_ck",	&secure_32k_clk_src_ck),
-	CLK(NULL,	"slimbus_src_clk",		&slimbus_src_clk),
-	CLK(NULL,	"slimbus_clk",			&slimbus_clk),
-	CLK(NULL,	"sys_32k_ck",			&sys_32k_ck),
-	CLK(NULL,	"virt_12000000_ck",		&virt_12000000_ck),
-	CLK(NULL,	"virt_13000000_ck",		&virt_13000000_ck),
-	CLK(NULL,	"virt_16800000_ck",		&virt_16800000_ck),
-	CLK(NULL,	"virt_19200000_ck",		&virt_19200000_ck),
-	CLK(NULL,	"virt_26000000_ck",		&virt_26000000_ck),
-	CLK(NULL,	"virt_27000000_ck",		&virt_27000000_ck),
-	CLK(NULL,	"virt_38400000_ck",		&virt_38400000_ck),
-	CLK(NULL,	"sys_clkin_ck",			&sys_clkin_ck),
-	CLK(NULL,	"tie_low_clock_ck",		&tie_low_clock_ck),
-	CLK(NULL,	"utmi_phy_clkout_ck",		&utmi_phy_clkout_ck),
-	CLK(NULL,	"xclk60mhsp1_ck",		&xclk60mhsp1_ck),
-	CLK(NULL,	"xclk60mhsp2_ck",		&xclk60mhsp2_ck),
-	CLK(NULL,	"xclk60motg_ck",		&xclk60motg_ck),
-	CLK(NULL,	"abe_dpll_bypass_clk_mux_ck",	&abe_dpll_bypass_clk_mux_ck),
-	CLK(NULL,	"abe_dpll_refclk_mux_ck",	&abe_dpll_refclk_mux_ck),
-	CLK(NULL,	"dpll_abe_ck",			&dpll_abe_ck),
-	CLK(NULL,	"dpll_abe_x2_ck",		&dpll_abe_x2_ck),
-	CLK(NULL,	"dpll_abe_m2x2_ck",		&dpll_abe_m2x2_ck),
-	CLK(NULL,	"abe_24m_fclk",			&abe_24m_fclk),
-	CLK(NULL,	"abe_clk",			&abe_clk),
-	CLK(NULL,	"aess_fclk",			&aess_fclk),
-	CLK(NULL,	"dpll_abe_m3x2_ck",		&dpll_abe_m3x2_ck),
-	CLK(NULL,	"core_hsd_byp_clk_mux_ck",	&core_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_core_ck",			&dpll_core_ck),
-	CLK(NULL,	"dpll_core_x2_ck",		&dpll_core_x2_ck),
-	CLK(NULL,	"dpll_core_m6x2_ck",		&dpll_core_m6x2_ck),
-	CLK(NULL,	"dbgclk_mux_ck",		&dbgclk_mux_ck),
-	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck),
-	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck),
-	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck),
-	CLK(NULL,	"div_core_ck",			&div_core_ck),
-	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk),
-	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk),
-	CLK(NULL,	"dpll_core_m4x2_ck",		&dpll_core_m4x2_ck),
-	CLK(NULL,	"dll_clk_div_ck",		&dll_clk_div_ck),
-	CLK(NULL,	"dpll_abe_m2_ck",		&dpll_abe_m2_ck),
-	CLK(NULL,	"dpll_core_m3x2_ck",		&dpll_core_m3x2_ck),
-	CLK(NULL,	"dpll_core_m7x2_ck",		&dpll_core_m7x2_ck),
-	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck),
-	CLK(NULL,	"dpll_iva_x2_ck",		&dpll_iva_x2_ck),
-	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck),
-	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck),
-	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck),
-	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck),
-	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck),
-	CLK(NULL,	"per_hsd_byp_clk_mux_ck",	&per_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_per_ck",			&dpll_per_ck),
-	CLK(NULL,	"dpll_per_m2_ck",		&dpll_per_m2_ck),
-	CLK(NULL,	"dpll_per_x2_ck",		&dpll_per_x2_ck),
-	CLK(NULL,	"dpll_per_m2x2_ck",		&dpll_per_m2x2_ck),
-	CLK(NULL,	"dpll_per_m3x2_ck",		&dpll_per_m3x2_ck),
-	CLK(NULL,	"dpll_per_m4x2_ck",		&dpll_per_m4x2_ck),
-	CLK(NULL,	"dpll_per_m5x2_ck",		&dpll_per_m5x2_ck),
-	CLK(NULL,	"dpll_per_m6x2_ck",		&dpll_per_m6x2_ck),
-	CLK(NULL,	"dpll_per_m7x2_ck",		&dpll_per_m7x2_ck),
-	CLK(NULL,	"usb_hs_clk_div_ck",		&usb_hs_clk_div_ck),
-	CLK(NULL,	"dpll_usb_ck",			&dpll_usb_ck),
-	CLK(NULL,	"dpll_usb_clkdcoldo_ck",	&dpll_usb_clkdcoldo_ck),
-	CLK(NULL,	"dpll_usb_m2_ck",		&dpll_usb_m2_ck),
-	CLK(NULL,	"ducati_clk_mux_ck",		&ducati_clk_mux_ck),
-	CLK(NULL,	"func_12m_fclk",		&func_12m_fclk),
-	CLK(NULL,	"func_24m_clk",			&func_24m_clk),
-	CLK(NULL,	"func_24mc_fclk",		&func_24mc_fclk),
-	CLK(NULL,	"func_48m_fclk",		&func_48m_fclk),
-	CLK(NULL,	"func_48mc_fclk",		&func_48mc_fclk),
-	CLK(NULL,	"func_64m_fclk",		&func_64m_fclk),
-	CLK(NULL,	"func_96m_fclk",		&func_96m_fclk),
-	CLK(NULL,	"init_60m_fclk",		&init_60m_fclk),
-	CLK(NULL,	"l3_div_ck",			&l3_div_ck),
-	CLK(NULL,	"l4_div_ck",			&l4_div_ck),
-	CLK(NULL,	"lp_clk_div_ck",		&lp_clk_div_ck),
-	CLK(NULL,	"l4_wkup_clk_mux_ck",		&l4_wkup_clk_mux_ck),
-	CLK("smp_twd",	NULL,				&mpu_periphclk),
-	CLK(NULL,	"ocp_abe_iclk",			&ocp_abe_iclk),
-	CLK(NULL,	"per_abe_24m_fclk",		&per_abe_24m_fclk),
-	CLK(NULL,	"per_abe_nc_fclk",		&per_abe_nc_fclk),
-	CLK(NULL,	"syc_clk_div_ck",		&syc_clk_div_ck),
-	CLK(NULL,	"aes1_fck",			&aes1_fck),
-	CLK(NULL,	"aes2_fck",			&aes2_fck),
-	CLK(NULL,	"dmic_sync_mux_ck",		&dmic_sync_mux_ck),
-	CLK(NULL,	"func_dmic_abe_gfclk",		&func_dmic_abe_gfclk),
-	CLK(NULL,	"dss_sys_clk",			&dss_sys_clk),
-	CLK(NULL,	"dss_tv_clk",			&dss_tv_clk),
-	CLK(NULL,	"dss_dss_clk",			&dss_dss_clk),
-	CLK(NULL,	"dss_48mhz_clk",		&dss_48mhz_clk),
-	CLK(NULL,	"dss_fck",			&dss_fck),
-	CLK("omapdss_dss",	"ick",			&dss_fck),
-	CLK(NULL,	"fdif_fck",			&fdif_fck),
-	CLK(NULL,	"gpio1_dbclk",			&gpio1_dbclk),
-	CLK(NULL,	"gpio2_dbclk",			&gpio2_dbclk),
-	CLK(NULL,	"gpio3_dbclk",			&gpio3_dbclk),
-	CLK(NULL,	"gpio4_dbclk",			&gpio4_dbclk),
-	CLK(NULL,	"gpio5_dbclk",			&gpio5_dbclk),
-	CLK(NULL,	"gpio6_dbclk",			&gpio6_dbclk),
-	CLK(NULL,	"sgx_clk_mux",			&sgx_clk_mux),
-	CLK(NULL,	"hsi_fck",			&hsi_fck),
-	CLK(NULL,	"iss_ctrlclk",			&iss_ctrlclk),
-	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck),
-	CLK(NULL,	"func_mcasp_abe_gfclk",		&func_mcasp_abe_gfclk),
-	CLK(NULL,	"mcbsp1_sync_mux_ck",		&mcbsp1_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp1_gfclk",		&func_mcbsp1_gfclk),
-	CLK(NULL,	"mcbsp2_sync_mux_ck",		&mcbsp2_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp2_gfclk",		&func_mcbsp2_gfclk),
-	CLK(NULL,	"mcbsp3_sync_mux_ck",		&mcbsp3_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp3_gfclk",		&func_mcbsp3_gfclk),
-	CLK(NULL,	"mcbsp4_sync_mux_ck",		&mcbsp4_sync_mux_ck),
-	CLK(NULL,	"per_mcbsp4_gfclk",		&per_mcbsp4_gfclk),
-	CLK(NULL,	"hsmmc1_fclk",			&hsmmc1_fclk),
-	CLK(NULL,	"hsmmc2_fclk",			&hsmmc2_fclk),
-	CLK(NULL,	"ocp2scp_usb_phy_phy_48m",	&ocp2scp_usb_phy_phy_48m),
-	CLK(NULL,	"sha2md5_fck",			&sha2md5_fck),
-	CLK(NULL,	"slimbus1_fclk_1",		&slimbus1_fclk_1),
-	CLK(NULL,	"slimbus1_fclk_0",		&slimbus1_fclk_0),
-	CLK(NULL,	"slimbus1_fclk_2",		&slimbus1_fclk_2),
-	CLK(NULL,	"slimbus1_slimbus_clk",		&slimbus1_slimbus_clk),
-	CLK(NULL,	"slimbus2_fclk_1",		&slimbus2_fclk_1),
-	CLK(NULL,	"slimbus2_fclk_0",		&slimbus2_fclk_0),
-	CLK(NULL,	"slimbus2_slimbus_clk",		&slimbus2_slimbus_clk),
-	CLK(NULL,	"smartreflex_core_fck",		&smartreflex_core_fck),
-	CLK(NULL,	"smartreflex_iva_fck",		&smartreflex_iva_fck),
-	CLK(NULL,	"smartreflex_mpu_fck",		&smartreflex_mpu_fck),
-	CLK(NULL,	"dmt1_clk_mux",			&dmt1_clk_mux),
-	CLK(NULL,	"cm2_dm10_mux",			&cm2_dm10_mux),
-	CLK(NULL,	"cm2_dm11_mux",			&cm2_dm11_mux),
-	CLK(NULL,	"cm2_dm2_mux",			&cm2_dm2_mux),
-	CLK(NULL,	"cm2_dm3_mux",			&cm2_dm3_mux),
-	CLK(NULL,	"cm2_dm4_mux",			&cm2_dm4_mux),
-	CLK(NULL,	"timer5_sync_mux",		&timer5_sync_mux),
-	CLK(NULL,	"timer6_sync_mux",		&timer6_sync_mux),
-	CLK(NULL,	"timer7_sync_mux",		&timer7_sync_mux),
-	CLK(NULL,	"timer8_sync_mux",		&timer8_sync_mux),
-	CLK(NULL,	"cm2_dm9_mux",			&cm2_dm9_mux),
-	CLK(NULL,	"usb_host_fs_fck",		&usb_host_fs_fck),
-	CLK("usbhs_omap",	"fs_fck",		&usb_host_fs_fck),
-	CLK(NULL,	"utmi_p1_gfclk",		&utmi_p1_gfclk),
-	CLK(NULL,	"usb_host_hs_utmi_p1_clk",	&usb_host_hs_utmi_p1_clk),
-	CLK(NULL,	"utmi_p2_gfclk",		&utmi_p2_gfclk),
-	CLK(NULL,	"usb_host_hs_utmi_p2_clk",	&usb_host_hs_utmi_p2_clk),
-	CLK(NULL,	"usb_host_hs_utmi_p3_clk",	&usb_host_hs_utmi_p3_clk),
-	CLK(NULL,	"usb_host_hs_hsic480m_p1_clk",	&usb_host_hs_hsic480m_p1_clk),
-	CLK(NULL,	"usb_host_hs_hsic60m_p1_clk",	&usb_host_hs_hsic60m_p1_clk),
-	CLK(NULL,	"usb_host_hs_hsic60m_p2_clk",	&usb_host_hs_hsic60m_p2_clk),
-	CLK(NULL,	"usb_host_hs_hsic480m_p2_clk",	&usb_host_hs_hsic480m_p2_clk),
-	CLK(NULL,	"usb_host_hs_func48mclk",	&usb_host_hs_func48mclk),
-	CLK(NULL,	"usb_host_hs_fck",		&usb_host_hs_fck),
-	CLK("usbhs_omap",	"hs_fck",		&usb_host_hs_fck),
-	CLK(NULL,	"otg_60m_gfclk",		&otg_60m_gfclk),
-	CLK(NULL,	"usb_otg_hs_xclk",		&usb_otg_hs_xclk),
-	CLK(NULL,	"usb_otg_hs_ick",		&usb_otg_hs_ick),
-	CLK("musb-omap2430",	"ick",			&usb_otg_hs_ick),
-	CLK(NULL,	"usb_phy_cm_clk32k",		&usb_phy_cm_clk32k),
-	CLK(NULL,	"usb_tll_hs_usb_ch2_clk",	&usb_tll_hs_usb_ch2_clk),
-	CLK(NULL,	"usb_tll_hs_usb_ch0_clk",	&usb_tll_hs_usb_ch0_clk),
-	CLK(NULL,	"usb_tll_hs_usb_ch1_clk",	&usb_tll_hs_usb_ch1_clk),
-	CLK(NULL,	"usb_tll_hs_ick",		&usb_tll_hs_ick),
-	CLK("usbhs_omap",	"usbtll_ick",		&usb_tll_hs_ick),
-	CLK("usbhs_tll",	"usbtll_ick",		&usb_tll_hs_ick),
-	CLK(NULL,	"usim_ck",			&usim_ck),
-	CLK(NULL,	"usim_fclk",			&usim_fclk),
-	CLK(NULL,	"pmd_stm_clock_mux_ck",		&pmd_stm_clock_mux_ck),
-	CLK(NULL,	"pmd_trace_clk_mux_ck",		&pmd_trace_clk_mux_ck),
-	CLK(NULL,	"stm_clk_div_ck",		&stm_clk_div_ck),
-	CLK(NULL,	"trace_clk_div_ck",		&trace_clk_div_ck),
-	CLK(NULL,	"auxclk0_src_ck",		&auxclk0_src_ck),
-	CLK(NULL,	"auxclk0_ck",			&auxclk0_ck),
-	CLK(NULL,	"auxclkreq0_ck",		&auxclkreq0_ck),
-	CLK(NULL,	"auxclk1_src_ck",		&auxclk1_src_ck),
-	CLK(NULL,	"auxclk1_ck",			&auxclk1_ck),
-	CLK(NULL,	"auxclkreq1_ck",		&auxclkreq1_ck),
-	CLK(NULL,	"auxclk2_src_ck",		&auxclk2_src_ck),
-	CLK(NULL,	"auxclk2_ck",			&auxclk2_ck),
-	CLK(NULL,	"auxclkreq2_ck",		&auxclkreq2_ck),
-	CLK(NULL,	"auxclk3_src_ck",		&auxclk3_src_ck),
-	CLK(NULL,	"auxclk3_ck",			&auxclk3_ck),
-	CLK(NULL,	"auxclkreq3_ck",		&auxclkreq3_ck),
-	CLK(NULL,	"auxclk4_src_ck",		&auxclk4_src_ck),
-	CLK(NULL,	"auxclk4_ck",			&auxclk4_ck),
-	CLK(NULL,	"auxclkreq4_ck",		&auxclkreq4_ck),
-	CLK(NULL,	"auxclk5_src_ck",		&auxclk5_src_ck),
-	CLK(NULL,	"auxclk5_ck",			&auxclk5_ck),
-	CLK(NULL,	"auxclkreq5_ck",		&auxclkreq5_ck),
-	CLK("50000000.gpmc",	"fck",			&dummy_ck),
-	CLK("omap_i2c.1",	"ick",			&dummy_ck),
-	CLK("omap_i2c.2",	"ick",			&dummy_ck),
-	CLK("omap_i2c.3",	"ick",			&dummy_ck),
-	CLK("omap_i2c.4",	"ick",			&dummy_ck),
-	CLK(NULL,	"mailboxes_ick",		&dummy_ck),
-	CLK("omap_hsmmc.0",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.1",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.2",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.3",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.4",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.1",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.2",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.3",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.4",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.1",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.2",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.3",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.4",	"ick",			&dummy_ck),
-	CLK(NULL,	"uart1_ick",			&dummy_ck),
-	CLK(NULL,	"uart2_ick",			&dummy_ck),
-	CLK(NULL,	"uart3_ick",			&dummy_ck),
-	CLK(NULL,	"uart4_ick",			&dummy_ck),
-	CLK("usbhs_omap",	"usbhost_ick",		&dummy_ck),
-	CLK("usbhs_omap",	"usbtll_fck",		&dummy_ck),
-	CLK("usbhs_tll",	"usbtll_fck",		&dummy_ck),
-	CLK("omap_wdt",	"ick",				&dummy_ck),
-	CLK(NULL,	"timer_32k_ck",	&sys_32k_ck),
-	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
-	CLK("omap_timer.1",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.2",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.3",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.4",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.9",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.10",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.11",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.5",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.6",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.7",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.8",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4a318000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48032000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48034000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48036000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("4803e000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48086000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48088000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("40138000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013a000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013c000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013e000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK(NULL,	"cpufreq_ck",	&dpll_mpu_ck),
-};
-
-int __init omap4xxx_clk_init(void)
-{
-	int rc;
-
-	if (cpu_is_omap443x()) {
-		cpu_mask = RATE_IN_4430;
-		omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
-	} else if (cpu_is_omap446x() || cpu_is_omap447x()) {
-		cpu_mask = RATE_IN_4460 | RATE_IN_4430;
-		omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
-		if (cpu_is_omap447x())
-			pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
-	} else {
-		return 0;
-	}
-
-	omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
-
-	omap2_clk_disable_autoidle_all();
-
-	/*
-	 * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
-	 * when its in bypass. So always lock USB before ABE DPLL.
-	 */
-	/*
-	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
-	 * domain can transition to retention state when not in use.
-	 */
-	rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
-	if (rc)
-		pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
-	/*
-	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
-	 * state when turning the ABE clock domain. Workaround this by
-	 * locking the ABE DPLL on boot.
-	 * Lock the ABE DPLL in any case to avoid issues with audio.
-	 */
-	rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
-	if (!rc)
-		rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
-	if (rc)
-		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
-
-	return 0;
-}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 8517a62..c95b836 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -635,7 +635,7 @@ void __init omap4430_init_early(void)
 	omap44xx_clockdomains_init();
 	omap44xx_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_soc_init = omap4xxx_clk_init;
+	omap_clk_soc_init = omap4xxx_dt_clk_init;
 }
 
 void __init omap4430_init_late(void)
-- 
1.7.9.5

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[PATCHv13 37/40] ARM: OMAP: DRA7: Enable clock init

[Tero Kristo]

Initializes clock data from device tree.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 arch/arm/mach-omap2/io.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c95b836..44fc8cd 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -692,6 +692,7 @@ void __init dra7xx_init_early(void)
 	dra7xx_clockdomains_init();
 	dra7xx_hwmod_init();
 	omap_hwmod_init_postsetup();
+	omap_clk_soc_init = dra7xx_dt_clk_init;
 }
 
 void __init dra7xx_init_late(void)
-- 
1.7.9.5

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[PATCHv13 38/40] ARM: AM43xx: Enable clock init

[Tero Kristo]

Initializes clock data from device tree.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
 arch/arm/mach-omap2/io.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 44fc8cd..bbd2959 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -606,6 +606,7 @@ void __init am43xx_init_early(void)
 	am43xx_clockdomains_init();
 	am43xx_hwmod_init();
 	omap_hwmod_init_postsetup();
+	omap_clk_soc_init = am43xx_dt_clk_init;
 }
 
 void __init am43xx_init_late(void)
-- 
1.7.9.5

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[PATCHv13 39/40] ARM: AM33xx: remove old clock data and link in new clock init code

[Tero Kristo]

AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Tested-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
Acked-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/mach-omap2/Makefile          |    1 -
 arch/arm/mach-omap2/cclock33xx_data.c | 1064 ---------------------------------
 arch/arm/mach-omap2/io.c              |    2 +-
 3 files changed, 1 insertion(+), 1066 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e9d63ec..088305f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -189,7 +189,6 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX)		+= cclock33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)			+= $(clock-common)
 obj-$(CONFIG_SOC_OMAP5)			+= dpll3xxx.o dpll44xx.o
 
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index 865d30e..0000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1064 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav-l0cyMroinI0@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "am33xx.h"
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "control.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT		0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT		1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
-	"virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
-	"virt_26000000_ck",
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-	       AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
-	       AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
-	       AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
-	       0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_CORE,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_CORE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_CORE,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
-	"sys_clkin_ck",
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_core_ck,
-	},
-	.dpll_data	= &dpll_core_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-	"dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static const struct clk_ops dpll_x2_ck_ops = {
-	.recalc_rate	= &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_core_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-		   NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_MPU,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_MPU,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_MPU,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_mpu_ck;
-
-static const struct clk_ops dpll_mpu_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-	.hw = {
-		.clk	= &dpll_mpu_ck,
-	},
-	.dpll_data	= &dpll_mpu_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
-		   0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-		   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_DDR */
-static struct dpll_data dpll_ddr_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DDR,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DDR,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DDR,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_ddr_ck;
-
-static const struct clk_ops dpll_ddr_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk_hw_omap dpll_ddr_ck_hw = {
-	.hw = {
-		.clk	= &dpll_ddr_ck,
-	},
-	.dpll_data	= &dpll_ddr_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
-		   0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
-		   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* emif_fck functional clock */
-DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
-			0x0, 1, 2);
-
-/* DPLL_DISP */
-static struct dpll_data dpll_disp_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DISP,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DISP,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DISP,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_disp_ck;
-
-static struct clk_hw_omap dpll_disp_ck_hw = {
-	.hw = {
-		.clk	= &dpll_disp_ck,
-	},
-	.dpll_data	= &dpll_disp_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
-		   CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
-		   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_PERIPH,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_PER,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_PER,
-	.mult_mask	= AM33XX_DPLL_MULT_PERIPH_MASK,
-	.div1_mask	= AM33XX_DPLL_PER_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-	.flags		= DPLL_J_TYPE,
-};
-
-/* CLKDCOLDO */
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_per_ck,
-	},
-	.dpll_data	= &dpll_per_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/* CLKOUT: fdpll/M2 */
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		   AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-		   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-		   NULL);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
-			&dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
-			&dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
-			&dpll_core_m4_ck, 0x0, 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-			1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
-			8);
-
-/*
- * Below clock nodes describes clockdomains derived out
- * of core clock.
- */
-static const struct clk_ops clk_ops_null = {
-};
-
-static const char *l3_gclk_parents[] = {
-	"dpll_core_m4_ck"
-};
-
-static struct clk l3_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
-DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
-
-static struct clk l4hs_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
-DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
-
-static const char *l3s_gclk_parents[] = {
-	"dpll_core_m4_div2_ck"
-};
-
-static struct clk l3s_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
-DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4fw_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
-DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4ls_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
-DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk sysclk_div_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
-DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
-
-/*
- * In order to match the clock domain with hwmod clockdomain entry,
- * separate clock nodes is required for the modules which are
- * directly getting their funtioncal clock from sys_clkin.
- */
-static struct clk adc_tsc_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
-DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
-DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
-DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk sha0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
-DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk aes0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
-DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk rng_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
-DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
-
-/*
- * Modules clock nodes
- *
- * The following clock leaf nodes are added for the moment because:
- *
- *  - hwmod data is not present for these modules, either hwmod
- *    control is not required or its not populated.
- *  - Driver code is not yet migrated to use hwmod/runtime pm
- *  - Modules outside kernel access (to disable them by default)
- *
- *     - mmu (gfx domain)
- *     - cefuse
- *     - usbotg_fck (its additional clock and not really a modulemode)
- *     - ieee5000
- */
-
-DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-		AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-		AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-/*
- * clkdiv32 is generated from fixed division of 732.4219
- */
-DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
-
-static struct clk clkdiv32k_ick;
-
-static const char *clkdiv32k_ick_parent_names[] = {
-	"clkdiv32k_ck",
-};
-
-static const struct clk_ops clkdiv32k_ick_ops = {
-	.enable         = &omap2_dflt_clk_enable,
-	.disable        = &omap2_dflt_clk_disable,
-	.is_enabled     = &omap2_dflt_clk_is_enabled,
-	.init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap clkdiv32k_ick_hw = {
-	.hw	= {
-		.clk	= &clkdiv32k_ick,
-	},
-	.enable_reg	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
-	.enable_bit	= AM33XX_MODULEMODE_SWCTRL_SHIFT,
-	.clkdm_name	= "clk_24mhz_clkdm",
-};
-
-DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
-
-/* "usbotg_fck" is an additional clock and not really a modulemode */
-DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
-		0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
-		AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-/* Timers */
-static const struct clksel timer1_clkmux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-	{ .parent = &tclkin_ck, .rates = div_1_2_rates },
-	{ .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
-	{ .parent = &clk_32768_ck, .rates = div_1_4_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer1_ck_parents[] = {
-	"sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
-	"clk_32768_ck",
-};
-
-static struct clk timer1_fck;
-
-static const struct clk_ops timer1_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap timer1_fck_hw = {
-	.hw	= {
-		.clk	= &timer1_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer1_clkmux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER1MS_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_2_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
-
-static const struct clksel timer2_to_7_clk_sel[] = {
-	{ .parent = &tclkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_clkin_ck, .rates = div_1_1_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer2_to_7_ck_parents[] = {
-	"tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
-};
-
-static struct clk timer2_fck;
-
-static struct clk_hw_omap timer2_fck_hw = {
-	.hw	= {
-		.clk	= &timer2_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER2_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer3_fck;
-
-static struct clk_hw_omap timer3_fck_hw = {
-	.hw	= {
-		.clk	= &timer3_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER3_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer4_fck;
-
-static struct clk_hw_omap timer4_fck_hw = {
-	.hw	= {
-		.clk	= &timer4_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER4_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer5_fck;
-
-static struct clk_hw_omap timer5_fck_hw = {
-	.hw	= {
-		.clk	= &timer5_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER5_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer6_fck;
-
-static struct clk_hw_omap timer6_fck_hw = {
-	.hw	= {
-		.clk	= &timer6_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER6_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer7_fck;
-
-static struct clk_hw_omap timer7_fck_hw = {
-	.hw	= {
-		.clk	= &timer7_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER7_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
-			"dpll_core_m5_ck",
-			&dpll_core_m5_ck,
-			0x0,
-			1, 2);
-
-static const struct clk_ops cpsw_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-};
-
-static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
-	{ .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *cpsw_cpts_rft_ck_parents[] = {
-	"dpll_core_m5_ck", "dpll_core_m4_ck",
-};
-
-static struct clk cpsw_cpts_rft_clk;
-
-static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
-	.hw	= {
-		.clk	= &cpsw_cpts_rft_clk,
-	},
-	.clkdm_name	= "cpsw_125mhz_clkdm",
-	.clksel		= cpsw_cpts_rft_clkmux_sel,
-	.clksel_reg	= AM33XX_CM_CPTS_RFT_CLKSEL,
-	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
-
-
-/* gpio */
-static const char *gpio0_ck_parents[] = {
-	"clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel gpio0_dbclk_mux_sel[] = {
-	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-	{ .parent = &clk_32768_ck, .rates = div_1_1_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const struct clk_ops gpio_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk gpio0_dbclk_mux_ck;
-
-static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
-	.hw	= {
-		.clk	= &gpio0_dbclk_mux_ck,
-	},
-	.clkdm_name	= "l4_wkup_clkdm",
-	.clksel		= gpio0_dbclk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_GPIO0_DBCLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
-
-DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
-		AM33XX_CM_WKUP_GPIO0_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO1_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO2_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO3_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
-
-
-static const char *pruss_ck_parents[] = {
-	"l3_gclk", "dpll_disp_m2_ck",
-};
-
-static const struct clksel pruss_ocp_clk_mux_sel[] = {
-	{ .parent = &l3_gclk, .rates = div_1_0_rates },
-	{ .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk pruss_ocp_gclk;
-
-static struct clk_hw_omap pruss_ocp_gclk_hw = {
-	.hw	= {
-		.clk	= &pruss_ocp_gclk,
-	},
-	.clkdm_name	= "pruss_ocp_clkdm",
-	.clksel		= pruss_ocp_clk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_PRUSS_OCP_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
-
-static const char *lcd_ck_parents[] = {
-	"dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel lcd_clk_mux_sel[] = {
-	{ .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static struct clk lcd_gclk;
-
-static struct clk_hw_omap lcd_gclk_hw = {
-	.hw	= {
-		.clk	= &lcd_gclk,
-	},
-	.clkdm_name	= "lcdc_clkdm",
-	.clksel		= lcd_clk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_LCDC_PIXEL_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
-			gpio_fck_ops, CLK_SET_RATE_PARENT);
-
-DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
-
-static const char *gfx_ck_parents[] = {
-	"dpll_core_m4_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel gfx_clksel_sel[] = {
-	{ .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk gfx_fclk_clksel_ck;
-
-static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
-	.hw	= {
-		.clk	= &gfx_fclk_clksel_ck,
-	},
-	.clksel		= gfx_clksel_sel,
-	.clksel_reg	= AM33XX_CLKSEL_GFX_FCLK,
-	.clksel_mask	= AM33XX_CLKSEL_GFX_FCLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
-
-static const struct clk_div_table div_1_0_2_1_rates[] = {
-	{ .div = 1, .val = 0, },
-	{ .div = 2, .val = 1, },
-	{ .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
-			 &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
-			 AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
-			 0x0, div_1_0_2_1_rates, NULL);
-
-static const char *sysclkout_ck_parents[] = {
-	"clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
-	"lcd_gclk",
-};
-
-static const struct clksel sysclkout_pre_sel[] = {
-	{ .parent = &clk_32768_ck, .rates = div_1_0_rates },
-	{ .parent = &l3_gclk, .rates = div_1_1_rates },
-	{ .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
-	{ .parent = &lcd_gclk, .rates = div_1_4_rates },
-	{ .parent = NULL },
-};
-
-static struct clk sysclkout_pre_ck;
-
-static struct clk_hw_omap sysclkout_pre_ck_hw = {
-	.hw	= {
-		.clk	= &sysclkout_pre_ck,
-	},
-	.clksel		= sysclkout_pre_sel,
-	.clksel_reg	= AM33XX_CM_CLKOUT_CTRL,
-	.clksel_mask	= AM33XX_CLKOUT2SOURCE_MASK,
-};
-
-DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
-
-/* Divide by 8 clock rates with default clock is 1/1*/
-static const struct clk_div_table div8_rates[] = {
-	{ .div = 1, .val = 0, },
-	{ .div = 2, .val = 1, },
-	{ .div = 3, .val = 2, },
-	{ .div = 4, .val = 3, },
-	{ .div = 5, .val = 4, },
-	{ .div = 6, .val = 5, },
-	{ .div = 7, .val = 6, },
-	{ .div = 8, .val = 7, },
-	{ .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
-			 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
-			 AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
-
-DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
-		AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
-
-static const char *wdt_ck_parents[] = {
-	"clk_rc32k_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel wdt_clkmux_sel[] = {
-	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk wdt1_fck;
-
-static struct clk_hw_omap wdt1_fck_hw = {
-	.hw	= {
-		.clk	= &wdt1_fck,
-	},
-	.clkdm_name	= "l4_wkup_clkdm",
-	.clksel		= wdt_clkmux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_WDT1_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
-
-static const char *pwmss_clk_parents[] = {
-	"dpll_per_m2_ck",
-};
-
-static const struct clk_ops ehrpwm_tbclk_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS0_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS1_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS2_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-/*
- * debugss optional clocks
- */
-DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
-		0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
-		0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
-
-static const char *stm_pmd_clock_mux_ck_parents[] = {
-	"dbg_sysclk_ck", "dbg_clka_ck",
-};
-
-DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-	       AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
-	       AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-	       AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-	       AM33XX_TRC_PMD_CLKSEL_SHIFT,
-	       AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
-		   &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		   AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
-		   AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
-		   &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		   AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
-		   AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-/*
- * clkdev
- */
-static struct omap_clk am33xx_clks[] = {
-	CLK(NULL,	"clk_32768_ck",		&clk_32768_ck),
-	CLK(NULL,	"clk_rc32k_ck",		&clk_rc32k_ck),
-	CLK(NULL,	"virt_19200000_ck",	&virt_19200000_ck),
-	CLK(NULL,	"virt_24000000_ck",	&virt_24000000_ck),
-	CLK(NULL,	"virt_25000000_ck",	&virt_25000000_ck),
-	CLK(NULL,	"virt_26000000_ck",	&virt_26000000_ck),
-	CLK(NULL,	"sys_clkin_ck",		&sys_clkin_ck),
-	CLK(NULL,	"tclkin_ck",		&tclkin_ck),
-	CLK(NULL,	"dpll_core_ck",		&dpll_core_ck),
-	CLK(NULL,	"dpll_core_x2_ck",	&dpll_core_x2_ck),
-	CLK(NULL,	"dpll_core_m4_ck",	&dpll_core_m4_ck),
-	CLK(NULL,	"dpll_core_m5_ck",	&dpll_core_m5_ck),
-	CLK(NULL,	"dpll_core_m6_ck",	&dpll_core_m6_ck),
-	CLK(NULL,	"dpll_mpu_ck",		&dpll_mpu_ck),
-	CLK("cpu0",	NULL,			&dpll_mpu_ck),
-	CLK(NULL,	"dpll_mpu_m2_ck",	&dpll_mpu_m2_ck),
-	CLK(NULL,	"dpll_ddr_ck",		&dpll_ddr_ck),
-	CLK(NULL,	"dpll_ddr_m2_ck",	&dpll_ddr_m2_ck),
-	CLK(NULL,	"dpll_ddr_m2_div2_ck",	&dpll_ddr_m2_div2_ck),
-	CLK(NULL,	"dpll_disp_ck",		&dpll_disp_ck),
-	CLK(NULL,	"dpll_disp_m2_ck",	&dpll_disp_m2_ck),
-	CLK(NULL,	"dpll_per_ck",		&dpll_per_ck),
-	CLK(NULL,	"dpll_per_m2_ck",	&dpll_per_m2_ck),
-	CLK(NULL,	"dpll_per_m2_div4_wkupdm_ck",	&dpll_per_m2_div4_wkupdm_ck),
-	CLK(NULL,	"dpll_per_m2_div4_ck",	&dpll_per_m2_div4_ck),
-	CLK(NULL,	"adc_tsc_fck",		&adc_tsc_fck),
-	CLK(NULL,	"cefuse_fck",		&cefuse_fck),
-	CLK(NULL,	"clkdiv32k_ck",		&clkdiv32k_ck),
-	CLK(NULL,	"clkdiv32k_ick",	&clkdiv32k_ick),
-	CLK(NULL,	"dcan0_fck",		&dcan0_fck),
-	CLK("481cc000.d_can",	NULL,		&dcan0_fck),
-	CLK(NULL,	"dcan1_fck",		&dcan1_fck),
-	CLK("481d0000.d_can",	NULL,		&dcan1_fck),
-	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk),
-	CLK(NULL,	"mcasp0_fck",		&mcasp0_fck),
-	CLK(NULL,	"mcasp1_fck",		&mcasp1_fck),
-	CLK(NULL,	"mmu_fck",		&mmu_fck),
-	CLK(NULL,	"smartreflex0_fck",	&smartreflex0_fck),
-	CLK(NULL,	"smartreflex1_fck",	&smartreflex1_fck),
-	CLK(NULL,	"sha0_fck",		&sha0_fck),
-	CLK(NULL,	"aes0_fck",		&aes0_fck),
-	CLK(NULL,	"rng_fck",		&rng_fck),
-	CLK(NULL,	"timer1_fck",		&timer1_fck),
-	CLK(NULL,	"timer2_fck",		&timer2_fck),
-	CLK(NULL,	"timer3_fck",		&timer3_fck),
-	CLK(NULL,	"timer4_fck",		&timer4_fck),
-	CLK(NULL,	"timer5_fck",		&timer5_fck),
-	CLK(NULL,	"timer6_fck",		&timer6_fck),
-	CLK(NULL,	"timer7_fck",		&timer7_fck),
-	CLK(NULL,	"usbotg_fck",		&usbotg_fck),
-	CLK(NULL,	"ieee5000_fck",		&ieee5000_fck),
-	CLK(NULL,	"wdt1_fck",		&wdt1_fck),
-	CLK(NULL,	"l4_rtc_gclk",		&l4_rtc_gclk),
-	CLK(NULL,	"l3_gclk",		&l3_gclk),
-	CLK(NULL,	"dpll_core_m4_div2_ck",	&dpll_core_m4_div2_ck),
-	CLK(NULL,	"l4hs_gclk",		&l4hs_gclk),
-	CLK(NULL,	"l3s_gclk",		&l3s_gclk),
-	CLK(NULL,	"l4fw_gclk",		&l4fw_gclk),
-	CLK(NULL,	"l4ls_gclk",		&l4ls_gclk),
-	CLK(NULL,	"clk_24mhz",		&clk_24mhz),
-	CLK(NULL,	"sysclk_div_ck",	&sysclk_div_ck),
-	CLK(NULL,	"cpsw_125mhz_gclk",	&cpsw_125mhz_gclk),
-	CLK(NULL,	"cpsw_cpts_rft_clk",	&cpsw_cpts_rft_clk),
-	CLK(NULL,	"gpio0_dbclk_mux_ck",	&gpio0_dbclk_mux_ck),
-	CLK(NULL,	"gpio0_dbclk",		&gpio0_dbclk),
-	CLK(NULL,	"gpio1_dbclk",		&gpio1_dbclk),
-	CLK(NULL,	"gpio2_dbclk",		&gpio2_dbclk),
-	CLK(NULL,	"gpio3_dbclk",		&gpio3_dbclk),
-	CLK(NULL,	"lcd_gclk",		&lcd_gclk),
-	CLK(NULL,	"mmc_clk",		&mmc_clk),
-	CLK(NULL,	"gfx_fclk_clksel_ck",	&gfx_fclk_clksel_ck),
-	CLK(NULL,	"gfx_fck_div_ck",	&gfx_fck_div_ck),
-	CLK(NULL,	"sysclkout_pre_ck",	&sysclkout_pre_ck),
-	CLK(NULL,	"clkout2_div_ck",	&clkout2_div_ck),
-	CLK(NULL,	"timer_32k_ck",		&clkdiv32k_ick),
-	CLK(NULL,	"timer_sys_ck",		&sys_clkin_ck),
-	CLK(NULL,	"dbg_sysclk_ck",	&dbg_sysclk_ck),
-	CLK(NULL,	"dbg_clka_ck",		&dbg_clka_ck),
-	CLK(NULL,	"stm_pmd_clock_mux_ck",	&stm_pmd_clock_mux_ck),
-	CLK(NULL,	"trace_pmd_clk_mux_ck",	&trace_pmd_clk_mux_ck),
-	CLK(NULL,	"stm_clk_div_ck",	&stm_clk_div_ck),
-	CLK(NULL,	"trace_clk_div_ck",	&trace_clk_div_ck),
-	CLK(NULL,	"clkout2_ck",		&clkout2_ck),
-	CLK("48300200.ehrpwm",	"tbclk",	&ehrpwm0_tbclk),
-	CLK("48302200.ehrpwm",	"tbclk",	&ehrpwm1_tbclk),
-	CLK("48304200.ehrpwm",	"tbclk",	&ehrpwm2_tbclk),
-};
-
-
-static const char *enable_init_clks[] = {
-	"dpll_ddr_m2_ck",
-	"dpll_mpu_m2_ck",
-	"l3_gclk",
-	"l4hs_gclk",
-	"l4fw_gclk",
-	"l4ls_gclk",
-	"clkout2_ck",	/* Required for external peripherals like, Audio codecs */
-};
-
-int __init am33xx_clk_init(void)
-{
-	if (soc_is_am33xx())
-		cpu_mask = RATE_IN_AM33XX;
-
-	omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
-
-	omap2_clk_disable_autoidle_all();
-
-	omap2_clk_enable_init_clocks(enable_init_clks,
-				     ARRAY_SIZE(enable_init_clks));
-
-	/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
-	 *    physically present, in such a case HWMOD enabling of
-	 *    clock would be failure with default parent. And timer
-	 *    probe thinks clock is already enabled, this leads to
-	 *    crash upon accessing timer 3 & 6 registers in probe.
-	 *    Fix by setting parent of both these timers to master
-	 *    oscillator clock.
-	 */
-
-	clk_set_parent(&timer3_fck, &sys_clkin_ck);
-	clk_set_parent(&timer6_fck, &sys_clkin_ck);
-	/*
-	 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
-	 * the design/spec, so as a result, for example, timer which supposed
-	 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
-	 * not expected by any use-case, so change WDT1 clock source to PRCM
-	 * 32KHz clock.
-	 */
-	clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
-
-	return 0;
-}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index bbd2959..f28399f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -581,7 +581,7 @@ void __init am33xx_init_early(void)
 	am33xx_clockdomains_init();
 	am33xx_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_soc_init = am33xx_clk_init;
+	omap_clk_soc_init = am33xx_dt_clk_init;
 }
 
 void __init am33xx_init_late(void)
-- 
1.7.9.5

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[PATCHv13 40/40] ARM: OMAP3: use DT clock init if DT data is available

[Tero Kristo]

OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Tested-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
Acked-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/mach-omap2/io.c |   13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f28399f..b8097fe 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -488,21 +488,29 @@ void __init omap3_init_early(void)
 void __init omap3430_init_early(void)
 {
 	omap3_init_early();
+	if (of_have_populated_dt())
+		omap_clk_soc_init = omap3430_dt_clk_init;
 }
 
 void __init omap35xx_init_early(void)
 {
 	omap3_init_early();
+	if (of_have_populated_dt())
+		omap_clk_soc_init = omap3430_dt_clk_init;
 }
 
 void __init omap3630_init_early(void)
 {
 	omap3_init_early();
+	if (of_have_populated_dt())
+		omap_clk_soc_init = omap3630_dt_clk_init;
 }
 
 void __init am35xx_init_early(void)
 {
 	omap3_init_early();
+	if (of_have_populated_dt())
+		omap_clk_soc_init = am35xx_dt_clk_init;
 }
 
 void __init ti81xx_init_early(void)
@@ -520,7 +528,10 @@ void __init ti81xx_init_early(void)
 	omap3xxx_clockdomains_init();
 	omap3xxx_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_soc_init = omap3xxx_clk_init;
+	if (of_have_populated_dt())
+		omap_clk_soc_init = ti81xx_dt_clk_init;
+	else
+		omap_clk_soc_init = omap3xxx_clk_init;
 }
 
 void __init omap3_init_late(void)
-- 
1.7.9.5

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Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Mike Turquette]

Quoting Tero Kristo (2014-01-09 06:00:11)
> Hi,
> 
> So, bad luck number release for this, as v12 wasn't sufficient still.
> 
> Changes compared to previous version:
> - Dropped any changes to generic clock drivers, as it seems impossible
>   to agree anything in short term, this means the patch set shrank in
>   size from 49 patches to 40 (first 9 patches were dropped).
> - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
>   to drivers/clk/ti, and made the modifications needed to the TI version
>   of the clock drivers only (based on discussions with Mike, this is fine)
> - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
>   with any generic implementation we might have at some point, migrating
>   this to the generic version should be easy enough also.
> - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
>   versions and resulted into an orphan clock node
> - Fixed compile problem for omap5 only build reported by Felipe
> - Fixed a couple of sparse warnings
> - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
>   instead of __raw_readl / __raw_writel

Hi Tero,

This approach takes care of all of my concerns with this series. Thanks
for your long suffering patience on it.

It seems some build errors are cropping up, so once those are fixed then
I'll be happy to merge clk-next-dt-clks-v13 into clk-next for 3.14.

Regards,
Mike

> 
> Testing done:
> - omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
> - omap4-panda-es: boot / suspend-resume (RET)
> - omap5-uevm: boot
> - am335x-bone: boot
> - dra7-evm: boot
> 
> Maintainer friendly branches also available:
> 
> tree: https://github.com/t-kristo/linux-pm.git
> 
> clk driver only (Mike): clk-next-dt-clks-v13
> DTS data only (Benoit): dts_for_3.14-dt-clks-v13
> full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13
> 
> -Tero
> 
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Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tony Lindgren]

* Mike Turquette <mturquette@linaro.org> [140109 14:25]:
> Quoting Tero Kristo (2014-01-09 06:00:11)
> > Hi,
> > 
> > So, bad luck number release for this, as v12 wasn't sufficient still.
> > 
> > Changes compared to previous version:
> > - Dropped any changes to generic clock drivers, as it seems impossible
> >   to agree anything in short term, this means the patch set shrank in
> >   size from 49 patches to 40 (first 9 patches were dropped).
> > - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
> >   to drivers/clk/ti, and made the modifications needed to the TI version
> >   of the clock drivers only (based on discussions with Mike, this is fine)
> > - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
> >   with any generic implementation we might have at some point, migrating
> >   this to the generic version should be easy enough also.
> > - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
> >   versions and resulted into an orphan clock node
> > - Fixed compile problem for omap5 only build reported by Felipe
> > - Fixed a couple of sparse warnings
> > - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
> >   instead of __raw_readl / __raw_writel
> 
> Hi Tero,
> 
> This approach takes care of all of my concerns with this series. Thanks
> for your long suffering patience on it.
> 
> It seems some build errors are cropping up, so once those are fixed then
> I'll be happy to merge clk-next-dt-clks-v13 into clk-next for 3.14.

I'm fine with Mike merging these all via the clock tree assuming no more
pending comments. For the patches changed from the last time around,
please feel free to add:

Acked-by: Tony Lindgren <tony@atomide.com>

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tero Kristo]

On 01/10/2014 08:53 PM, Tony Lindgren wrote:
> * Mike Turquette <mturquette@linaro.org> [140109 14:25]:
>> Quoting Tero Kristo (2014-01-09 06:00:11)
>>> Hi,
>>>
>>> So, bad luck number release for this, as v12 wasn't sufficient still.
>>>
>>> Changes compared to previous version:
>>> - Dropped any changes to generic clock drivers, as it seems impossible
>>>    to agree anything in short term, this means the patch set shrank in
>>>    size from 49 patches to 40 (first 9 patches were dropped).
>>> - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
>>>    to drivers/clk/ti, and made the modifications needed to the TI version
>>>    of the clock drivers only (based on discussions with Mike, this is fine)
>>> - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
>>>    with any generic implementation we might have at some point, migrating
>>>    this to the generic version should be easy enough also.
>>> - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
>>>    versions and resulted into an orphan clock node
>>> - Fixed compile problem for omap5 only build reported by Felipe
>>> - Fixed a couple of sparse warnings
>>> - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
>>>    instead of __raw_readl / __raw_writel
>>
>> Hi Tero,
>>
>> This approach takes care of all of my concerns with this series. Thanks
>> for your long suffering patience on it.
>>
>> It seems some build errors are cropping up, so once those are fixed then
>> I'll be happy to merge clk-next-dt-clks-v13 into clk-next for 3.14.
>
> I'm fine with Mike merging these all via the clock tree assuming no more
> pending comments. For the patches changed from the last time around,
> please feel free to add:
>
> Acked-by: Tony Lindgren <tony@atomide.com>

How about the dts data patches? Should these also go via Mike's tree? 
Otherwise we will have boot failures until the dts patches are merged.

-Tero

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [140111 01:56]:
> On 01/10/2014 08:53 PM, Tony Lindgren wrote:
> >* Mike Turquette <mturquette@linaro.org> [140109 14:25]:
> >>Quoting Tero Kristo (2014-01-09 06:00:11)
> >>>Hi,
> >>>
> >>>So, bad luck number release for this, as v12 wasn't sufficient still.
> >>>
> >>>Changes compared to previous version:
> >>>- Dropped any changes to generic clock drivers, as it seems impossible
> >>>   to agree anything in short term, this means the patch set shrank in
> >>>   size from 49 patches to 40 (first 9 patches were dropped).
> >>>- Copy pasted implementation for clk-divider and clk-mux from drivers/clk
> >>>   to drivers/clk/ti, and made the modifications needed to the TI version
> >>>   of the clock drivers only (based on discussions with Mike, this is fine)
> >>>- Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
> >>>   with any generic implementation we might have at some point, migrating
> >>>   this to the generic version should be easy enough also.
> >>>- Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
> >>>   versions and resulted into an orphan clock node
> >>>- Fixed compile problem for omap5 only build reported by Felipe
> >>>- Fixed a couple of sparse warnings
> >>>- changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
> >>>   instead of __raw_readl / __raw_writel
> >>
> >>Hi Tero,
> >>
> >>This approach takes care of all of my concerns with this series. Thanks
> >>for your long suffering patience on it.
> >>
> >>It seems some build errors are cropping up, so once those are fixed then
> >>I'll be happy to merge clk-next-dt-clks-v13 into clk-next for 3.14.
> >
> >I'm fine with Mike merging these all via the clock tree assuming no more
> >pending comments. For the patches changed from the last time around,
> >please feel free to add:
> >
> >Acked-by: Tony Lindgren <tony@atomide.com>
> 
> How about the dts data patches? Should these also go via Mike's
> tree? Otherwise we will have boot failures until the dts patches are
> merged.

Yes I think that's the way to go, they mostly add new files so there
should not be major conflicts.

Regards,

Tony

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Felipe Balbi]

[-- Attachment #1.1: Type: text/plain, Size: 1261 bytes --]

Hi,

On Thu, Jan 09, 2014 at 04:00:11PM +0200, Tero Kristo wrote:
> So, bad luck number release for this, as v12 wasn't sufficient still.
> 
> Changes compared to previous version:
> - Dropped any changes to generic clock drivers, as it seems impossible
>   to agree anything in short term, this means the patch set shrank in
>   size from 49 patches to 40 (first 9 patches were dropped).
> - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
>   to drivers/clk/ti, and made the modifications needed to the TI version
>   of the clock drivers only (based on discussions with Mike, this is fine)
> - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
>   with any generic implementation we might have at some point, migrating
>   this to the generic version should be easy enough also.
> - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
>   versions and resulted into an orphan clock node
> - Fixed compile problem for omap5 only build reported by Felipe
> - Fixed a couple of sparse warnings
> - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
>   instead of __raw_readl / __raw_writel

just caught a build breakage. .config attached

-- 
balbi

[-- Attachment #1.2: config-am43xx-only.config-10 --]
[-- Type: text/plain, Size: 71061 bytes --]

#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 3.13.0-rc7 Kernel Configuration
#
CONFIG_ARM=y
CONFIG_MIGHT_HAVE_PCI=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_HAVE_TCM=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_NO_IOPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_ARCH_HAS_CPUFREQ=y
CONFIG_ARCH_HAS_BANDGAP=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_FIQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y

#
# General setup
#
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
# CONFIG_COMPILE_TEST is not set
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
# CONFIG_KERNEL_LZ4 is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
# CONFIG_SYSVIPC is not set
# CONFIG_FHANDLE is not set

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_KTIME_SCALAR=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_BSD_PROCESS_ACCT is not set

#
# RCU Subsystem
#
CONFIG_TINY_RCU=y
# CONFIG_PREEMPT_RCU is not set
CONFIG_RCU_STALL_COMMON=y
# CONFIG_TREE_RCU_TRACE is not set
CONFIG_IKCONFIG=y
# CONFIG_IKCONFIG_PROC is not set
CONFIG_LOG_BUF_SHIFT=17
CONFIG_GENERIC_SCHED_CLOCK=y
# CONFIG_CGROUPS is not set
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_USER_NS=y
# CONFIG_PID_NS is not set
CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_RD_GZIP is not set
CONFIG_RD_BZIP2=y
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
CONFIG_RD_LZ4=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_HAVE_UID16=y
CONFIG_EXPERT=y
# CONFIG_UID16 is not set
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_PRINTK=y
# CONFIG_BUG is not set
# CONFIG_BASE_FULL is not set
# CONFIG_FUTEX is not set
CONFIG_EPOLL=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
CONFIG_EVENTFD=y
# CONFIG_SHMEM is not set
CONFIG_AIO=y
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y

#
# Kernel Performance Events And Counters
#
# CONFIG_PERF_EVENTS is not set
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_JUMP_LABEL=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y

#
# GCOV-based kernel profiling
#
CONFIG_GCOV_KERNEL=y
CONFIG_GCOV_FORMAT_AUTODETECT=y
# CONFIG_GCOV_FORMAT_3_4 is not set
# CONFIG_GCOV_FORMAT_4_7 is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=1
CONFIG_SYSTEM_TRUSTED_KEYRING=y
# CONFIG_MODULES is not set
# CONFIG_BLOCK is not set
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_FREEZER=y

#
# System Type
#
CONFIG_MMU=y
CONFIG_ARCH_MULTIPLATFORM=y
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_SHMOBILE is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C24XX is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5P64X0 is not set
# CONFIG_ARCH_S5PC100 is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP1 is not set

#
# Multiple platform selection
#

#
# CPU Core family selection
#
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_MULTI_V6_V7=y
# CONFIG_ARCH_MULTI_CPU_AUTO is not set
CONFIG_ARCH_MVEBU=y

#
# Marvell SOC with device tree
#
# CONFIG_MACH_ARMADA_370 is not set
# CONFIG_MACH_ARMADA_XP is not set
# CONFIG_ARCH_BCM is not set
CONFIG_ARCH_BCM2835=y
CONFIG_ARCH_CNS3XXX=y

#
# CNS3XXX platform type
#
CONFIG_GPIO_PCA953X=y
CONFIG_ARCH_HIGHBANK=y
# CONFIG_ARCH_KEYSTONE is not set
CONFIG_ARCH_MXC=y

#
# Freescale i.MX support
#
# CONFIG_MXC_IRQ_PRIOR is not set
CONFIG_MXC_AVIC=y
CONFIG_MXC_DEBUG_BOARD=y
CONFIG_HAVE_EPIT=y
CONFIG_MXC_USE_EPIT=y
CONFIG_ARCH_HAS_RNGA=y
CONFIG_ARCH_MXC_IOMUX_V3=y
CONFIG_SOC_IMX31=y
CONFIG_SOC_IMX35=y

#
# MX31 platforms:
#
CONFIG_MACH_MX31ADS=y
# CONFIG_MACH_MX31LILLY is not set
# CONFIG_MACH_MX31LITE is not set
CONFIG_MACH_PCM037=y
CONFIG_MACH_PCM037_EET=y
CONFIG_MACH_MX31_3DS=y
CONFIG_MACH_MX31MOBOARD=y
CONFIG_MACH_QONG=y
# CONFIG_MACH_ARMADILLO5X0 is not set
# CONFIG_MACH_KZM_ARM11_01 is not set
CONFIG_MACH_BUG=y
CONFIG_MACH_IMX31_DT=y

#
# MX35 platforms:
#
CONFIG_MACH_PCM043=y
CONFIG_MACH_MX35_3DS=y
# CONFIG_MACH_EUKREA_CPUIMX35SD is not set
# CONFIG_MACH_VPR200 is not set

#
# i.MX51 machines:
#
# CONFIG_MACH_IMX51_DT is not set
# CONFIG_MACH_MX51_BABBAGE is not set
# CONFIG_MACH_EUKREA_CPUIMX51SD is not set

#
# Device tree only
#
# CONFIG_SOC_IMX53 is not set
# CONFIG_SOC_IMX6Q is not set
# CONFIG_SOC_IMX6SL is not set
# CONFIG_SOC_VF610 is not set
CONFIG_IMX_HAVE_PLATFORM_FEC=y
CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS=y
CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
CONFIG_IMX_HAVE_PLATFORM_IMX_FB=y
CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD=y
CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
CONFIG_IMX_HAVE_PLATFORM_IPU_CORE=y
CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
CONFIG_IMX_HAVE_PLATFORM_MXC_MMC=y
CONFIG_IMX_HAVE_PLATFORM_MXC_NAND=y
CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA=y
CONFIG_IMX_HAVE_PLATFORM_MXC_RTC=y
CONFIG_IMX_HAVE_PLATFORM_MXC_W1=y
CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y

#
# TI OMAP Common Features
#

#
# OMAP Feature Selections
#
CONFIG_OMAP_RESET_CLOCKS=y
# CONFIG_OMAP_MUX is not set
# CONFIG_OMAP_32K_TIMER is not set
CONFIG_OMAP_DM_TIMER=y
CONFIG_OMAP_PM_NOOP=y
CONFIG_MACH_OMAP_GENERIC=y
CONFIG_ARCH_OMAP=y
# CONFIG_ARCH_OMAP2 is not set
# CONFIG_ARCH_OMAP3 is not set
# CONFIG_ARCH_OMAP4 is not set
# CONFIG_SOC_OMAP5 is not set
# CONFIG_SOC_AM33XX is not set
CONFIG_SOC_AM43XX=y
CONFIG_ARCH_OMAP2PLUS=y

#
# TI OMAP2/3/4 Specific Features
#
CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
# CONFIG_SOC_HAS_OMAP2_SDRC is not set
# CONFIG_SOC_DRA7XX is not set

#
# OMAP Legacy Platform Data Board Type
#
CONFIG_ARCH_PICOXCELL=y
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_SOCFPGA is not set
CONFIG_PLAT_SPEAR=y
# CONFIG_ARCH_SPEAR13XX is not set
# CONFIG_ARCH_SPEAR_AUTO is not set
# CONFIG_ARCH_STI is not set
# CONFIG_ARCH_SHMOBILE_MULTI is not set
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_SIRF=y

#
# CSR SiRF atlas6/primaII/Marco/Polo Specific Features
#
# CONFIG_ARCH_ATLAS6 is not set
# CONFIG_ARCH_PRIMA2 is not set
# CONFIG_ARCH_MARCO is not set
# CONFIG_ARCH_TEGRA is not set
CONFIG_ARCH_U8500=y
CONFIG_UX500_SOC_DB8500=y

#
# Ux500 target platform (boards)
#
CONFIG_MACH_MOP500=y
CONFIG_MACH_HREFV60=y
CONFIG_MACH_SNOWBALL=y
CONFIG_UX500_AUTO_PLATFORM=y
# CONFIG_MACH_UX500_DT is not set
CONFIG_UX500_DEBUG_UART=2
# CONFIG_ARCH_VEXPRESS is not set
CONFIG_ARCH_VIRT=y
CONFIG_ARCH_VT8500=y
CONFIG_ARCH_WM8750=y
# CONFIG_ARCH_WM8850 is not set
CONFIG_ARCH_ZYNQ=y
CONFIG_PLAT_ORION=y
CONFIG_ARM_TIMER_SP804=y

#
# Processor Type
#
CONFIG_CPU_V6=y
CONFIG_CPU_V6K=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v6=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV6=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_V6=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V6=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_USE_DOMAINS=y

#
# Processor Features
#
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
# CONFIG_ARM_THUMB is not set
# CONFIG_ARM_THUMBEE is not set
CONFIG_ARM_VIRT_EXT=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_ICACHE_DISABLE=y
CONFIG_CPU_DCACHE_DISABLE=y
# CONFIG_CPU_BPREDICT_DISABLE is not set
# CONFIG_KUSER_HELPERS is not set
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_CACHE_L2X0=y
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
CONFIG_ARM_NR_BANKS=8
CONFIG_MULTI_IRQ_HANDLER=y
CONFIG_ARM_ERRATA_326103=y
CONFIG_ARM_ERRATA_411920=y
CONFIG_ARM_ERRATA_430973=y
CONFIG_PL310_ERRATA_588369=y
# CONFIG_ARM_ERRATA_720789 is not set
# CONFIG_PL310_ERRATA_727915 is not set
CONFIG_ARM_ERRATA_754322=y
# CONFIG_ARM_ERRATA_364296 is not set
# CONFIG_PL310_ERRATA_769419 is not set
CONFIG_ARM_ERRATA_775420=y
# CONFIG_ARM_ERRATA_773022 is not set
CONFIG_ICST=y
CONFIG_TI_PRIV_EDMA=y

#
# Bus support
#
CONFIG_ARM_AMBA=y
# CONFIG_PCI is not set
# CONFIG_PCI_SYSCALL is not set
# CONFIG_PCCARD is not set

#
# Kernel Features
#
CONFIG_HAVE_SMP=y
# CONFIG_SMP is not set
CONFIG_HAVE_ARM_SCU=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_ARM_PSCI=y
CONFIG_ARCH_NR_GPIO=392
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_PREEMPT_COUNT=y
CONFIG_HZ_FIXED=0
CONFIG_HZ_100=y
# CONFIG_HZ_200 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_500 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_MIGRATION=y
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NEED_PER_CPU_KM=y
CONFIG_CLEANCACHE=y
CONFIG_CMA=y
CONFIG_CMA_DEBUG=y
# CONFIG_ZBUD is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
CONFIG_SECCOMP=y
# CONFIG_CC_STACKPROTECTOR is not set
CONFIG_SWIOTLB=y
CONFIG_IOMMU_HELPER=y

#
# Boot options
#
CONFIG_USE_OF=y
# CONFIG_ATAGS is not set
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
CONFIG_CMDLINE=""
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_AUTO_ZRELADDR=y

#
# CPU Power Management
#

#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set

#
# CPU Idle
#
# CONFIG_CPU_IDLE is not set
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set

#
# Floating point emulation
#

#
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
CONFIG_FPE_FASTFPE=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_NEON=y
# CONFIG_KERNEL_MODE_NEON is not set

#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_BINFMT_SCRIPT=y
# CONFIG_HAVE_AOUT is not set
CONFIG_BINFMT_MISC=y
# CONFIG_COREDUMP is not set

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_PM_SLEEP=y
CONFIG_PM_AUTOSLEEP=y
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM_RUNTIME=y
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_ADVANCED_DEBUG is not set
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_APM_EMULATION=y
CONFIG_ARCH_HAS_OPP=y
CONFIG_PM_OPP=y
CONFIG_PM_CLK=y
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
CONFIG_CPU_PM=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_NET is not set
CONFIG_HAVE_BPF_JIT=y

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH=""
# CONFIG_DEVTMPFS is not set
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_GENERIC_CPU_DEVICES is not set
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_CMA is not set

#
# Bus devices
#
# CONFIG_IMX_WEIM is not set
CONFIG_MVEBU_MBUS=y
# CONFIG_OMAP_OCP2SCP is not set
# CONFIG_OMAP_INTERCONNECT is not set
CONFIG_ARM_CCI=y
CONFIG_MTD=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_AFS_PARTS=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_AR7_PARTS=y

#
# User Modules And Translation Layers
#
# CONFIG_MTD_OOPS is not set

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_GEOMETRY is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_OTP is not set
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
# CONFIG_MTD_PHYSMAP_COMPAT is not set
# CONFIG_MTD_PHYSMAP_OF is not set
# CONFIG_MTD_PLATRAM is not set

#
# Self-contained MTD device drivers
#
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
CONFIG_MTD_DATAFLASH_OTP=y
# CONFIG_MTD_M25P80 is not set
CONFIG_MTD_SPEAR_SMI=y
CONFIG_MTD_SST25L=y
CONFIG_MTD_SLRAM=y
CONFIG_MTD_PHRAM=y
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=4096
CONFIG_MTDRAM_ERASE_SIZE=128
CONFIG_MTDRAM_ABS_POS=0

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# CONFIG_MTD_NAND is not set
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
# CONFIG_MTD_ONENAND_GENERIC is not set
# CONFIG_MTD_ONENAND_OTP is not set
# CONFIG_MTD_ONENAND_2X_PROGRAM is not set

#
# LPDDR flash memory drivers
#
# CONFIG_MTD_LPDDR is not set
# CONFIG_MTD_UBI is not set
CONFIG_DTC=y
CONFIG_OF=y

#
# Device Tree and Open Firmware support
#
CONFIG_PROC_DEVICETREE=y
# CONFIG_OF_SELFTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_MTD=y
CONFIG_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_PARPORT_PC is not set
# CONFIG_PARPORT_GSC is not set
# CONFIG_PARPORT_AX88796 is not set
# CONFIG_PARPORT_1284 is not set
CONFIG_PARPORT_NOT_PC=y

#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=y
CONFIG_AD525X_DPOT=y
CONFIG_AD525X_DPOT_I2C=y
CONFIG_AD525X_DPOT_SPI=y
CONFIG_ATMEL_PWM=y
CONFIG_DUMMY_IRQ=y
CONFIG_ICS932S401=y
CONFIG_ATMEL_SSC=y
CONFIG_ENCLOSURE_SERVICES=y
CONFIG_APDS9802ALS=y
CONFIG_ISL29003=y
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
CONFIG_SENSORS_BH1780=y
CONFIG_SENSORS_BH1770=y
CONFIG_SENSORS_APDS990X=y
CONFIG_HMC6352=y
CONFIG_DS1682=y
# CONFIG_TI_DAC7512 is not set
CONFIG_BMP085=y
CONFIG_BMP085_I2C=y
CONFIG_BMP085_SPI=y
CONFIG_USB_SWITCH_FSA9480=y
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
CONFIG_C2PORT=y

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
CONFIG_EEPROM_AT25=y
CONFIG_EEPROM_LEGACY=y
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=y
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_SUNXI_SID is not set

#
# Texas Instruments shared transport line discipline
#
CONFIG_SENSORS_LIS3_SPI=y
CONFIG_SENSORS_LIS3_I2C=y

#
# Altera FPGA firmware download module
#
CONFIG_ALTERA_STAPL=y

#
# Intel MIC Host Driver
#

#
# Intel MIC Card Driver
#

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_POLLDEV=y
CONFIG_INPUT_SPARSEKMAP=y
CONFIG_INPUT_MATRIXKMAP=y

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=y
# CONFIG_INPUT_EVDEV is not set
CONFIG_INPUT_EVBUG=y
CONFIG_INPUT_APMPOWER=y

#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_88PM860X=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_AD7877=y
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
CONFIG_TOUCHSCREEN_BU21013=y
CONFIG_TOUCHSCREEN_CY8CTMG110=y
CONFIG_TOUCHSCREEN_CYTTSP_CORE=y
CONFIG_TOUCHSCREEN_CYTTSP_I2C=y
CONFIG_TOUCHSCREEN_CYTTSP_SPI=y
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=y
# CONFIG_TOUCHSCREEN_CYTTSP4_I2C is not set
CONFIG_TOUCHSCREEN_CYTTSP4_SPI=y
CONFIG_TOUCHSCREEN_DA9052=y
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
CONFIG_TOUCHSCREEN_EETI=y
CONFIG_TOUCHSCREEN_EGALAX=y
# CONFIG_TOUCHSCREEN_FUJITSU is not set
CONFIG_TOUCHSCREEN_ILI210X=y
CONFIG_TOUCHSCREEN_GUNZE=y
CONFIG_TOUCHSCREEN_ELO=y
CONFIG_TOUCHSCREEN_WACOM_W8001=y
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
CONFIG_TOUCHSCREEN_MAX11801=y
# CONFIG_TOUCHSCREEN_MCS5000 is not set
CONFIG_TOUCHSCREEN_MMS114=y
CONFIG_TOUCHSCREEN_MTOUCH=y
CONFIG_TOUCHSCREEN_INEXIO=y
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
CONFIG_TOUCHSCREEN_TOUCHWIN=y
CONFIG_TOUCHSCREEN_PIXCIR=y
# CONFIG_TOUCHSCREEN_WM97XX is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
CONFIG_TOUCHSCREEN_MC13783=y
CONFIG_TOUCHSCREEN_TOUCHIT213=y
CONFIG_TOUCHSCREEN_TSC_SERIO=y
CONFIG_TOUCHSCREEN_TSC2005=y
CONFIG_TOUCHSCREEN_TSC2007=y
CONFIG_TOUCHSCREEN_W90X900=y
# CONFIG_TOUCHSCREEN_PCAP is not set
CONFIG_TOUCHSCREEN_ST1232=y
CONFIG_TOUCHSCREEN_STMPE=y
# CONFIG_TOUCHSCREEN_SUR40 is not set
CONFIG_TOUCHSCREEN_TPS6507X=y
CONFIG_TOUCHSCREEN_ZFORCE=y
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_88PM860X_ONKEY is not set
CONFIG_INPUT_88PM80X_ONKEY=y
CONFIG_INPUT_AB8500_PONKEY=y
CONFIG_INPUT_AD714X=y
# CONFIG_INPUT_AD714X_I2C is not set
CONFIG_INPUT_AD714X_SPI=y
CONFIG_INPUT_ARIZONA_HAPTICS=y
CONFIG_INPUT_BMA150=y
CONFIG_INPUT_MAX8925_ONKEY=y
CONFIG_INPUT_MC13783_PWRBUTTON=y
CONFIG_INPUT_MMA8450=y
CONFIG_INPUT_MPU3050=y
CONFIG_INPUT_GP2A=y
# CONFIG_INPUT_GPIO_TILT_POLLED is not set
CONFIG_INPUT_ATI_REMOTE2=y
CONFIG_INPUT_KEYSPAN_REMOTE=y
CONFIG_INPUT_KXTJ9=y
# CONFIG_INPUT_KXTJ9_POLLED_MODE is not set
CONFIG_INPUT_POWERMATE=y
# CONFIG_INPUT_YEALINK is not set
CONFIG_INPUT_CM109=y
CONFIG_INPUT_RETU_PWRBUTTON=y
CONFIG_INPUT_TWL6040_VIBRA=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
CONFIG_INPUT_DA9052_ONKEY=y
# CONFIG_INPUT_DA9055_ONKEY is not set
CONFIG_INPUT_PCAP=y
CONFIG_INPUT_ADXL34X=y
# CONFIG_INPUT_ADXL34X_I2C is not set
# CONFIG_INPUT_ADXL34X_SPI is not set
CONFIG_INPUT_IMS_PCU=y
CONFIG_INPUT_CMA3000=y
# CONFIG_INPUT_CMA3000_I2C is not set
# CONFIG_INPUT_SIRFSOC_ONKEY is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_PARKBD=y
CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=y
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
CONFIG_SERIO_ARC_PS2=y
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_OLPC_APSP is not set
CONFIG_GAMEPORT=y
# CONFIG_GAMEPORT_NS558 is not set
# CONFIG_GAMEPORT_L4 is not set

#
# Character devices
#
# CONFIG_TTY is not set
CONFIG_DEVKMEM=y
CONFIG_PRINTER=y
# CONFIG_LP_CONSOLE is not set
CONFIG_PPDEV=y
CONFIG_IPMI_HANDLER=y
# CONFIG_IPMI_PANIC_EVENT is not set
CONFIG_IPMI_DEVICE_INTERFACE=y
CONFIG_IPMI_SI=y
CONFIG_IPMI_WATCHDOG=y
# CONFIG_IPMI_POWEROFF is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
CONFIG_HW_RANDOM_ATMEL=y
# CONFIG_HW_RANDOM_BCM2835 is not set
CONFIG_HW_RANDOM_OMAP=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_HW_RANDOM_MXC_RNGA=y
CONFIG_HW_RANDOM_EXYNOS=y
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
# CONFIG_I2C_CHARDEV is not set
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
# CONFIG_I2C_MUX_GPIO is not set
CONFIG_I2C_MUX_PCA9541=y
# CONFIG_I2C_MUX_PCA954x is not set
# CONFIG_I2C_MUX_PINCTRL is not set
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_SMBUS=y

#
# I2C Algorithms
#
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_ALGOPCF=y
CONFIG_I2C_ALGOPCA=y

#
# I2C Hardware Bus support
#

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_BCM2835=y
CONFIG_I2C_CBUS_GPIO=y
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_IMX=y
CONFIG_I2C_MV64XXX=y
CONFIG_I2C_NOMADIK=y
CONFIG_I2C_OCORES=y
CONFIG_I2C_OMAP=y
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_PXA_PCI is not set
CONFIG_I2C_SH_MOBILE=y
CONFIG_I2C_SIMTEC=y
CONFIG_I2C_SIRF=y
CONFIG_I2C_WMT=y
# CONFIG_I2C_XILINX is not set
CONFIG_I2C_RCAR=y

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
CONFIG_I2C_PARPORT=y
# CONFIG_I2C_PARPORT_LIGHT is not set
CONFIG_I2C_TINY_USB=y
CONFIG_I2C_VIPERBOARD=y

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_BCM2835 is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_BUTTERFLY is not set
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_IMX=y
CONFIG_SPI_LM70_LLP=y
# CONFIG_SPI_FSL_SPI is not set
CONFIG_SPI_OC_TINY=y
CONFIG_SPI_OMAP24XX=y
# CONFIG_SPI_TI_QSPI is not set
# CONFIG_SPI_ORION is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_PXA2XX_PCI is not set
CONFIG_SPI_SC18IS602=y
CONFIG_SPI_SIRF=y
# CONFIG_SPI_XCOMM is not set
CONFIG_SPI_XILINX=y
CONFIG_SPI_DESIGNWARE=y
# CONFIG_SPI_DW_MMIO is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
CONFIG_SPI_TLE62X0=y
CONFIG_HSI=y
CONFIG_HSI_BOARDINFO=y

#
# HSI clients
#
CONFIG_HSI_CHAR=y

#
# PPS support
#
CONFIG_PPS=y
CONFIG_PPS_DEBUG=y
CONFIG_NTP_PPS=y

#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=y
CONFIG_PPS_CLIENT_PARPORT=y
CONFIG_PPS_CLIENT_GPIO=y

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PINCTRL=y

#
# Pin controllers
#
CONFIG_PINMUX=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
CONFIG_DEBUG_PINCTRL=y
CONFIG_PINCTRL_ABX500=y
CONFIG_PINCTRL_AB8500=y
CONFIG_PINCTRL_AB8540=y
CONFIG_PINCTRL_AB9540=y
CONFIG_PINCTRL_AB8505=y
CONFIG_PINCTRL_BCM2835=y
# CONFIG_PINCTRL_IMX35 is not set
CONFIG_PINCTRL_NOMADIK=y
CONFIG_PINCTRL_DB8500=y
CONFIG_PINCTRL_DB8540=y
CONFIG_PINCTRL_ROCKCHIP=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_SIRF=y
CONFIG_PINCTRL_SUNXI=y
# CONFIG_PINCTRL_WM8750 is not set
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_DEVRES=y
CONFIG_OF_GPIO=y
CONFIG_DEBUG_GPIO=y
# CONFIG_GPIO_SYSFS is not set
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_DA9052=y
# CONFIG_GPIO_DA9055 is not set
CONFIG_GPIO_MAX730X=y

#
# Memory mapped GPIO drivers:
#
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_EM=y
CONFIG_GPIO_MVEBU=y
CONFIG_GPIO_MXC=y
CONFIG_GPIO_PL061=y
CONFIG_GPIO_RCAR=y
# CONFIG_GPIO_SPEAR_SPICS is not set
CONFIG_GPIO_TS5500=y
CONFIG_GPIO_XILINX=y
CONFIG_GPIO_GRGPIO=y

#
# I2C GPIO expanders:
#
CONFIG_GPIO_ARIZONA=y
CONFIG_GPIO_MAX7300=y
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_MAX732X_IRQ=y
# CONFIG_GPIO_MC9S08DZ60 is not set
# CONFIG_GPIO_PCA953X_IRQ is not set
CONFIG_GPIO_PCF857X=y
# CONFIG_GPIO_SX150X is not set
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_TPS65912=y
# CONFIG_GPIO_TWL6040 is not set
CONFIG_GPIO_WM8994=y
# CONFIG_GPIO_ADP5588 is not set
# CONFIG_GPIO_ADNP is not set

#
# PCI GPIO expanders:
#

#
# SPI GPIO expanders:
#
CONFIG_GPIO_MAX7301=y
CONFIG_GPIO_MCP23S08=y
CONFIG_GPIO_MC33880=y
CONFIG_GPIO_74X164=y

#
# AC97 GPIO expanders:
#

#
# LPC GPIO expanders:
#

#
# MODULbus GPIO expanders:
#
# CONFIG_GPIO_TPS6586X is not set
CONFIG_GPIO_BCM_KONA=y

#
# USB GPIO expanders:
#
# CONFIG_GPIO_VIPERBOARD is not set
CONFIG_W1=y

#
# 1-wire Bus Masters
#
# CONFIG_W1_MASTER_DS2490 is not set
CONFIG_W1_MASTER_DS2482=y
CONFIG_W1_MASTER_MXC=y
# CONFIG_W1_MASTER_DS1WM is not set
# CONFIG_W1_MASTER_GPIO is not set
CONFIG_HDQ_MASTER_OMAP=y

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=y
CONFIG_W1_SLAVE_SMEM=y
CONFIG_W1_SLAVE_DS2408=y
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=y
CONFIG_W1_SLAVE_DS2423=y
CONFIG_W1_SLAVE_DS2431=y
# CONFIG_W1_SLAVE_DS2433 is not set
CONFIG_W1_SLAVE_DS2760=y
# CONFIG_W1_SLAVE_DS2780 is not set
CONFIG_W1_SLAVE_DS2781=y
CONFIG_W1_SLAVE_DS28E04=y
# CONFIG_W1_SLAVE_BQ27000 is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_PDA_POWER is not set
# CONFIG_APM_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_MAX8925_POWER is not set
CONFIG_TEST_POWER=y
CONFIG_BATTERY_88PM860X=y
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
CONFIG_BATTERY_DS2782=y
CONFIG_BATTERY_SBS=y
# CONFIG_BATTERY_BQ27x00 is not set
CONFIG_BATTERY_DA9052=y
CONFIG_BATTERY_MAX17040=y
CONFIG_BATTERY_MAX17042=y
CONFIG_CHARGER_88PM860X=y
CONFIG_CHARGER_ISP1704=y
CONFIG_CHARGER_MAX8903=y
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=y
CONFIG_CHARGER_MAX8997=y
# CONFIG_CHARGER_BQ2415X is not set
CONFIG_CHARGER_BQ24190=y
CONFIG_CHARGER_BQ24735=y
CONFIG_CHARGER_SMB347=y
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_GPIO is not set
# CONFIG_POWER_RESET_QNAP is not set
# CONFIG_POWER_RESET_RESTART is not set
# CONFIG_POWER_RESET_VEXPRESS is not set
# CONFIG_POWER_AVS is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
CONFIG_SENSORS_ADCXX=y
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
CONFIG_SENSORS_ADM1026=y
# CONFIG_SENSORS_ADM1029 is not set
CONFIG_SENSORS_ADM1031=y
CONFIG_SENSORS_ADM9240=y
CONFIG_SENSORS_ADT7X10=y
# CONFIG_SENSORS_ADT7310 is not set
CONFIG_SENSORS_ADT7410=y
CONFIG_SENSORS_ADT7411=y
# CONFIG_SENSORS_ADT7462 is not set
CONFIG_SENSORS_ADT7470=y
CONFIG_SENSORS_ADT7475=y
CONFIG_SENSORS_ASC7621=y
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
CONFIG_SENSORS_DS1621=y
CONFIG_SENSORS_DA9052_ADC=y
CONFIG_SENSORS_DA9055=y
CONFIG_SENSORS_F71805F=y
CONFIG_SENSORS_F71882FG=y
CONFIG_SENSORS_F75375S=y
CONFIG_SENSORS_G760A=y
CONFIG_SENSORS_G762=y
CONFIG_SENSORS_GL518SM=y
CONFIG_SENSORS_GL520SM=y
CONFIG_SENSORS_GPIO_FAN=y
# CONFIG_SENSORS_HIH6130 is not set
CONFIG_SENSORS_HTU21=y
CONFIG_SENSORS_IBMAEM=y
CONFIG_SENSORS_IBMPEX=y
CONFIG_SENSORS_IIO_HWMON=y
CONFIG_SENSORS_IT87=y
CONFIG_SENSORS_JC42=y
CONFIG_SENSORS_LINEAGE=y
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
CONFIG_SENSORS_LM73=y
# CONFIG_SENSORS_LM75 is not set
CONFIG_SENSORS_LM77=y
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
CONFIG_SENSORS_LM83=y
CONFIG_SENSORS_LM85=y
CONFIG_SENSORS_LM87=y
# CONFIG_SENSORS_LM90 is not set
CONFIG_SENSORS_LM92=y
# CONFIG_SENSORS_LM93 is not set
CONFIG_SENSORS_LTC4151=y
CONFIG_SENSORS_LTC4215=y
CONFIG_SENSORS_LTC4245=y
CONFIG_SENSORS_LTC4261=y
CONFIG_SENSORS_LM95234=y
CONFIG_SENSORS_LM95241=y
CONFIG_SENSORS_LM95245=y
CONFIG_SENSORS_MAX1111=y
CONFIG_SENSORS_MAX16065=y
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
CONFIG_SENSORS_MAX197=y
CONFIG_SENSORS_MAX6639=y
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
CONFIG_SENSORS_MAX6697=y
CONFIG_SENSORS_MCP3021=y
CONFIG_SENSORS_NCT6775=y
CONFIG_SENSORS_NTC_THERMISTOR=y
CONFIG_SENSORS_PC87360=y
CONFIG_SENSORS_PC87427=y
CONFIG_SENSORS_PCF8591=y
CONFIG_PMBUS=y
CONFIG_SENSORS_PMBUS=y
CONFIG_SENSORS_ADM1275=y
CONFIG_SENSORS_LM25066=y
CONFIG_SENSORS_LTC2978=y
# CONFIG_SENSORS_MAX16064 is not set
CONFIG_SENSORS_MAX34440=y
# CONFIG_SENSORS_MAX8688 is not set
# CONFIG_SENSORS_UCD9000 is not set
# CONFIG_SENSORS_UCD9200 is not set
# CONFIG_SENSORS_ZL6100 is not set
CONFIG_SENSORS_SHT15=y
CONFIG_SENSORS_SHT21=y
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
CONFIG_SENSORS_EMC2103=y
# CONFIG_SENSORS_EMC6W201 is not set
CONFIG_SENSORS_SMSC47M1=y
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH56XX_COMMON is not set
CONFIG_SENSORS_ADS1015=y
CONFIG_SENSORS_ADS7828=y
CONFIG_SENSORS_ADS7871=y
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
CONFIG_SENSORS_INA2XX=y
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
CONFIG_SENSORS_TMP401=y
CONFIG_SENSORS_TMP421=y
CONFIG_SENSORS_VEXPRESS=y
CONFIG_SENSORS_VT1211=y
# CONFIG_SENSORS_W83781D is not set
CONFIG_SENSORS_W83791D=y
CONFIG_SENSORS_W83792D=y
# CONFIG_SENSORS_W83793 is not set
CONFIG_SENSORS_W83795=y
CONFIG_SENSORS_W83795_FANCTRL=y
CONFIG_SENSORS_W83L785TS=y
CONFIG_SENSORS_W83L786NG=y
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_MC13783_ADC is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_HWMON is not set
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_USER_SPACE is not set
# CONFIG_THERMAL_EMULATION is not set
CONFIG_SPEAR_THERMAL=y
CONFIG_DB8500_THERMAL=y
CONFIG_ARMADA_THERMAL=y

#
# Texas Instruments thermal drivers
#
CONFIG_TI_SOC_THERMAL=y
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y

#
# Sonics Silicon Backplane
#
CONFIG_SSB=y
# CONFIG_SSB_SILENT is not set
CONFIG_SSB_DEBUG=y
CONFIG_SSB_DRIVER_GPIO=y
CONFIG_BCMA_POSSIBLE=y

#
# Broadcom specific AMBA
#
CONFIG_BCMA=y
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_GMAC_CMN=y
# CONFIG_BCMA_DRIVER_GPIO is not set
CONFIG_BCMA_DEBUG=y

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
CONFIG_MFD_AS3711=y
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
CONFIG_MFD_CROS_EC=y
CONFIG_MFD_CROS_EC_I2C=y
CONFIG_MFD_CROS_EC_SPI=y
CONFIG_MFD_ASIC3=y
# CONFIG_PMIC_DA903X is not set
CONFIG_PMIC_DA9052=y
CONFIG_MFD_DA9052_SPI=y
CONFIG_MFD_DA9052_I2C=y
CONFIG_MFD_DA9055=y
# CONFIG_MFD_DA9063 is not set
CONFIG_MFD_MC13783=y
CONFIG_MFD_MC13XXX=y
CONFIG_MFD_MC13XXX_SPI=y
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_HTC_EGPIO is not set
CONFIG_HTC_PASIC3=y
CONFIG_HTC_I2CPLD=y
# CONFIG_MFD_KEMPLD is not set
CONFIG_MFD_88PM800=y
# CONFIG_MFD_88PM805 is not set
CONFIG_MFD_88PM860X=y
CONFIG_MFD_MAX77686=y
CONFIG_MFD_MAX77693=y
# CONFIG_MFD_MAX8907 is not set
CONFIG_MFD_MAX8925=y
CONFIG_MFD_MAX8997=y
# CONFIG_MFD_MAX8998 is not set
CONFIG_EZX_PCAP=y
CONFIG_MFD_VIPERBOARD=y
CONFIG_MFD_RETU=y
# CONFIG_MFD_PCF50633 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_SEC_CORE=y
CONFIG_MFD_SI476X_CORE=y
CONFIG_MFD_SM501=y
CONFIG_MFD_SM501_GPIO=y
# CONFIG_MFD_SMSC is not set
CONFIG_ABX500_CORE=y
# CONFIG_AB3100_CORE is not set
CONFIG_AB8500_CORE=y
CONFIG_MFD_DB8500_PRCMU=y
CONFIG_MFD_STMPE=y

#
# STMicroelectronics STMPE Interface Drivers
#
# CONFIG_STMPE_I2C is not set
# CONFIG_STMPE_SPI is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
CONFIG_TPS65010=y
CONFIG_TPS6507X=y
# CONFIG_MFD_TPS65090 is not set
CONFIG_MFD_TPS65217=y
CONFIG_MFD_TPS6586X=y
# CONFIG_MFD_TPS65910 is not set
CONFIG_MFD_TPS65912=y
CONFIG_MFD_TPS65912_I2C=y
# CONFIG_MFD_TPS65912_SPI is not set
CONFIG_MFD_TPS80031=y
# CONFIG_TWL4030_CORE is not set
CONFIG_TWL6040_CORE=y
CONFIG_MFD_WL1273_CORE=y
CONFIG_MFD_LM3533=y
# CONFIG_MFD_TC3589X is not set
CONFIG_MFD_TMIO=y
CONFIG_MFD_T7L66XB=y
CONFIG_MFD_TC6387XB=y
# CONFIG_MFD_TC6393XB is not set
CONFIG_MFD_ARIZONA=y
CONFIG_MFD_ARIZONA_I2C=y
CONFIG_MFD_ARIZONA_SPI=y
CONFIG_MFD_WM5102=y
# CONFIG_MFD_WM5110 is not set
# CONFIG_MFD_WM8997 is not set
CONFIG_MFD_WM8400=y
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
CONFIG_MFD_WM8994=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
CONFIG_REGULATOR_USERSPACE_CONSUMER=y
CONFIG_REGULATOR_88PM800=y
CONFIG_REGULATOR_88PM8607=y
CONFIG_REGULATOR_AD5398=y
CONFIG_REGULATOR_ANATOP=y
# CONFIG_REGULATOR_AB8500 is not set
CONFIG_REGULATOR_ARIZONA=y
CONFIG_REGULATOR_AS3711=y
# CONFIG_REGULATOR_DA9052 is not set
CONFIG_REGULATOR_DA9055=y
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_DBX500_PRCMU=y
CONFIG_REGULATOR_DB8500_PRCMU=y
CONFIG_REGULATOR_FAN53555=y
# CONFIG_REGULATOR_GPIO is not set
CONFIG_REGULATOR_ISL6271A=y
CONFIG_REGULATOR_LP3971=y
# CONFIG_REGULATOR_LP3972 is not set
CONFIG_REGULATOR_LP872X=y
CONFIG_REGULATOR_LP8755=y
CONFIG_REGULATOR_MAX1586=y
CONFIG_REGULATOR_MAX8649=y
# CONFIG_REGULATOR_MAX8660 is not set
CONFIG_REGULATOR_MAX8925=y
CONFIG_REGULATOR_MAX8952=y
CONFIG_REGULATOR_MAX8973=y
CONFIG_REGULATOR_MAX8997=y
CONFIG_REGULATOR_MAX77686=y
# CONFIG_REGULATOR_MAX77693 is not set
CONFIG_REGULATOR_MC13XXX_CORE=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
# CONFIG_REGULATOR_PCAP is not set
CONFIG_REGULATOR_PFUZE100=y
# CONFIG_REGULATOR_S2MPS11 is not set
# CONFIG_REGULATOR_S5M8767 is not set
# CONFIG_REGULATOR_TI_ABB is not set
CONFIG_REGULATOR_TPS51632=y
# CONFIG_REGULATOR_TPS62360 is not set
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y
# CONFIG_REGULATOR_TPS65217 is not set
CONFIG_REGULATOR_TPS6524X=y
CONFIG_REGULATOR_TPS6586X=y
CONFIG_REGULATOR_TPS65912=y
# CONFIG_REGULATOR_TPS80031 is not set
# CONFIG_REGULATOR_VEXPRESS is not set
CONFIG_REGULATOR_WM8400=y
CONFIG_REGULATOR_WM8994=y
CONFIG_MEDIA_SUPPORT=y

#
# Multimedia core support
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_RC_SUPPORT is not set
# CONFIG_MEDIA_CONTROLLER is not set
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2=y
# CONFIG_VIDEO_ADV_DEBUG is not set
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_VIDEO_TUNER=y
CONFIG_V4L2_MEM2MEM_DEV=y
CONFIG_VIDEOBUF_GEN=y
CONFIG_VIDEOBUF_VMALLOC=y
CONFIG_VIDEOBUF_DMA_CONTIG=y
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEO_V4L2_INT_DEVICE=y
# CONFIG_TTPCI_EEPROM is not set

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=y
# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set
# CONFIG_USB_GSPCA is not set
CONFIG_USB_PWC=y
CONFIG_USB_PWC_DEBUG=y
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_VIDEO_CPIA2=y
# CONFIG_USB_ZR364XX is not set
CONFIG_USB_STKWEBCAM=y
CONFIG_USB_S2255=y
CONFIG_USB_SN9C102=y
CONFIG_VIDEO_USBTV=y

#
# Analog TV USB devices
#
CONFIG_VIDEO_PVRUSB2=y
CONFIG_VIDEO_PVRUSB2_SYSFS=y
# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
CONFIG_VIDEO_HDPVR=y
CONFIG_VIDEO_USBVISION=y
CONFIG_VIDEO_STK1160_COMMON=y
CONFIG_VIDEO_STK1160_AC97=y
CONFIG_VIDEO_STK1160=y

#
# Analog/digital TV USB devices
#

#
# Webcam, TV (analog/digital) USB devices
#
# CONFIG_VIDEO_EM28XX is not set
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_TIMBERDALE=y
# CONFIG_SOC_CAMERA is not set
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_CODA=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
CONFIG_VIDEO_SH_VEU=y
# CONFIG_V4L_TEST_DRIVERS is not set

#
# Supported MMC/SDIO adapters
#
# CONFIG_MEDIA_PARPORT_SUPPORT is not set
CONFIG_VIDEO_CX2341X=y
CONFIG_VIDEO_TVEEPROM=y
CONFIG_CYPRESS_FIRMWARE=y

#
# Media ancillary drivers (tuners, sensors, i2c, frontends)
#
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set

#
# Encoders, decoders, sensors and other helper chips
#

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_TVAUDIO=y
CONFIG_VIDEO_TDA7432=y
# CONFIG_VIDEO_TDA9840 is not set
# CONFIG_VIDEO_TEA6415C is not set
CONFIG_VIDEO_TEA6420=y
CONFIG_VIDEO_MSP3400=y
CONFIG_VIDEO_CS5345=y
CONFIG_VIDEO_CS53L32A=y
CONFIG_VIDEO_TLV320AIC23B=y
# CONFIG_VIDEO_UDA1342 is not set
CONFIG_VIDEO_WM8775=y
CONFIG_VIDEO_WM8739=y
# CONFIG_VIDEO_VP27SMPX is not set
CONFIG_VIDEO_SONY_BTF_MPX=y

#
# RDS decoders
#
# CONFIG_VIDEO_SAA6588 is not set

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=y
CONFIG_VIDEO_ADV7183=y
CONFIG_VIDEO_BT819=y
CONFIG_VIDEO_BT856=y
CONFIG_VIDEO_BT866=y
CONFIG_VIDEO_KS0127=y
CONFIG_VIDEO_ML86V7667=y
CONFIG_VIDEO_SAA7110=y
CONFIG_VIDEO_SAA711X=y
# CONFIG_VIDEO_SAA7191 is not set
CONFIG_VIDEO_TVP514X=y
CONFIG_VIDEO_TVP5150=y
# CONFIG_VIDEO_TVP7002 is not set
CONFIG_VIDEO_TW2804=y
# CONFIG_VIDEO_TW9903 is not set
CONFIG_VIDEO_TW9906=y
CONFIG_VIDEO_VPX3220=y

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=y
CONFIG_VIDEO_CX25840=y

#
# Video encoders
#
CONFIG_VIDEO_SAA7127=y
CONFIG_VIDEO_SAA7185=y
CONFIG_VIDEO_ADV7170=y
CONFIG_VIDEO_ADV7175=y
CONFIG_VIDEO_ADV7343=y
CONFIG_VIDEO_ADV7393=y
CONFIG_VIDEO_AK881X=y
# CONFIG_VIDEO_THS8200 is not set

#
# Camera sensor devices
#
# CONFIG_VIDEO_OV7640 is not set
CONFIG_VIDEO_OV7670=y
CONFIG_VIDEO_VS6624=y
CONFIG_VIDEO_MT9V011=y
# CONFIG_VIDEO_TCM825X is not set
CONFIG_VIDEO_SR030PC30=y

#
# Flash devices
#

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=y
# CONFIG_VIDEO_UPD64083 is not set

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_THS7303=y
CONFIG_VIDEO_M52790=y

#
# Sensors used on soc_camera driver
#
CONFIG_MEDIA_TUNER=y

#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_SIMPLE=y
CONFIG_MEDIA_TUNER_TDA8290=y
CONFIG_MEDIA_TUNER_TDA827X=y
CONFIG_MEDIA_TUNER_TDA18271=y
CONFIG_MEDIA_TUNER_TDA9887=y
# CONFIG_MEDIA_TUNER_TEA5761 is not set
# CONFIG_MEDIA_TUNER_TEA5767 is not set
CONFIG_MEDIA_TUNER_MT20XX=y
CONFIG_MEDIA_TUNER_MT2060=y
CONFIG_MEDIA_TUNER_MT2063=y
# CONFIG_MEDIA_TUNER_MT2266 is not set
# CONFIG_MEDIA_TUNER_MT2131 is not set
CONFIG_MEDIA_TUNER_QT1010=y
# CONFIG_MEDIA_TUNER_XC2028 is not set
CONFIG_MEDIA_TUNER_XC5000=y
CONFIG_MEDIA_TUNER_XC4000=y
CONFIG_MEDIA_TUNER_MXL5005S=y
CONFIG_MEDIA_TUNER_MXL5007T=y
# CONFIG_MEDIA_TUNER_MC44S803 is not set
CONFIG_MEDIA_TUNER_MAX2165=y
# CONFIG_MEDIA_TUNER_TDA18218 is not set
# CONFIG_MEDIA_TUNER_FC0011 is not set
# CONFIG_MEDIA_TUNER_FC0012 is not set
CONFIG_MEDIA_TUNER_FC0013=y
CONFIG_MEDIA_TUNER_TDA18212=y
CONFIG_MEDIA_TUNER_E4000=y
CONFIG_MEDIA_TUNER_FC2580=y
CONFIG_MEDIA_TUNER_TUA9001=y
# CONFIG_MEDIA_TUNER_IT913X is not set
# CONFIG_MEDIA_TUNER_R820T is not set

#
# Customise DVB Frontends
#
# CONFIG_DVB_AU8522_V4L is not set
CONFIG_DVB_TUNER_DIB0070=y
CONFIG_DVB_TUNER_DIB0090=y

#
# Tools to develop new frontends
#
# CONFIG_DVB_DUMMY_FE is not set

#
# Graphics support
#
CONFIG_TEGRA_HOST1X=y
# CONFIG_TEGRA_HOST1X_FIREWALL is not set
CONFIG_DRM=y
CONFIG_DRM_USB=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
CONFIG_DRM_EXYNOS=y
CONFIG_DRM_EXYNOS_DMABUF=y
CONFIG_DRM_EXYNOS_HDMI=y
# CONFIG_DRM_EXYNOS_VIDI is not set
# CONFIG_DRM_EXYNOS_G2D is not set
CONFIG_DRM_UDL=y
CONFIG_DRM_ARMADA=y
CONFIG_DRM_RCAR_DU=y
# CONFIG_DRM_RCAR_LVDS is not set
CONFIG_DRM_SHMOBILE=y
CONFIG_DRM_OMAP=y
CONFIG_DRM_OMAP_NUM_CRTCS=1
# CONFIG_DRM_TILCDC is not set
# CONFIG_DRM_TEGRA is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
CONFIG_FB_FOREIGN_ENDIAN=y
CONFIG_FB_BOTH_ENDIAN=y
# CONFIG_FB_BIG_ENDIAN is not set
# CONFIG_FB_LITTLE_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_IMX=y
CONFIG_FB_S1D13XXX=y
CONFIG_FB_VT8500=y
# CONFIG_FB_WM8505 is not set
CONFIG_FB_WMT_GE_ROPS=y
CONFIG_FB_TMIO=y
CONFIG_FB_TMIO_ACCELL=y
# CONFIG_FB_SM501 is not set
CONFIG_FB_SMSCUFX=y
CONFIG_FB_UDL=y
# CONFIG_FB_XILINX is not set
CONFIG_FB_GOLDFISH=y
CONFIG_FB_VIRTUAL=y
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MX3 is not set
CONFIG_FB_BROADSHEET=y
CONFIG_FB_AUO_K190X=y
# CONFIG_FB_AUO_K1900 is not set
CONFIG_FB_AUO_K1901=y
# CONFIG_FB_SIMPLE is not set
CONFIG_OMAP2_DSS=y
# CONFIG_OMAP2_DSS_DEBUG is not set
CONFIG_OMAP2_DSS_DEBUGFS=y
# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set
CONFIG_OMAP2_DSS_DPI=y
CONFIG_OMAP2_DSS_VENC=y
# CONFIG_OMAP4_DSS_HDMI is not set
# CONFIG_OMAP2_DSS_SDI is not set
# CONFIG_OMAP2_DSS_DSI is not set
CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
# CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET is not set

#
# OMAP Display Device Drivers (new device model)
#
# CONFIG_DISPLAY_ENCODER_TFP410 is not set
CONFIG_DISPLAY_ENCODER_TPD12S015=y
CONFIG_DISPLAY_CONNECTOR_DVI=y
CONFIG_DISPLAY_CONNECTOR_HDMI=y
CONFIG_DISPLAY_CONNECTOR_ANALOG_TV=y
# CONFIG_DISPLAY_PANEL_DPI is not set
# CONFIG_DISPLAY_PANEL_DSI_CM is not set
# CONFIG_DISPLAY_PANEL_SONY_ACX565AKM is not set
CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02=y
# CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01 is not set
CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1=y
CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1=y
CONFIG_DISPLAY_PANEL_NEC_NL8048HL11=y
# CONFIG_EXYNOS_VIDEO is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_LOGO is not set
CONFIG_FB_SSD1307=y
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_COMPRESS_OFFLOAD=y
CONFIG_SND_JACK=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_SEQ_DUMMY=y
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
# CONFIG_SND_PCM_OSS is not set
# CONFIG_SND_SEQUENCER_OSS is not set
# CONFIG_SND_HRTIMER is not set
# CONFIG_SND_DYNAMIC_MINORS is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
CONFIG_SND_DEBUG=y
CONFIG_SND_DEBUG_VERBOSE=y
CONFIG_SND_PCM_XRUN_DEBUG=y
CONFIG_SND_VMASTER=y
CONFIG_SND_RAWMIDI_SEQ=y
# CONFIG_SND_OPL3_LIB_SEQ is not set
# CONFIG_SND_OPL4_LIB_SEQ is not set
# CONFIG_SND_SBAWE_SEQ is not set
# CONFIG_SND_EMU10K1_SEQ is not set
CONFIG_SND_MPU401_UART=y
CONFIG_SND_AC97_CODEC=y
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=y
CONFIG_SND_ALOOP=y
CONFIG_SND_VIRMIDI=y
CONFIG_SND_MTPAV=y
CONFIG_SND_MTS64=y
CONFIG_SND_SERIAL_U16550=y
CONFIG_SND_MPU401=y
CONFIG_SND_PORTMAN2X4=y
CONFIG_SND_AC97_POWER_SAVE=y
CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
CONFIG_SND_ARM=y
# CONFIG_SND_ARMAACI is not set
CONFIG_SND_SPI=y
CONFIG_SND_AT73C213=y
CONFIG_SND_AT73C213_TARGET_BITRATE=48000
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_USB_UA101=y
# CONFIG_SND_USB_CAIAQ is not set
CONFIG_SND_USB_6FIRE=y
CONFIG_SND_USB_HIFACE=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_ATMEL_SOC=y
CONFIG_SND_DESIGNWARE_I2S=y
CONFIG_SND_SOC_FSL_SSI=y
CONFIG_SND_IMX_SOC=y
CONFIG_SND_SOC_IMX_SSI=y
CONFIG_SND_SOC_IMX_PCM_FIQ=y
CONFIG_SND_SOC_IMX_PCM_DMA=y
CONFIG_SND_SOC_IMX_AUDMUX=y
CONFIG_SND_SOC_PHYCORE_AC97=y
CONFIG_SND_SOC_IMX_WM8962=y
CONFIG_SND_SOC_IMX_SGTL5000=y
# CONFIG_SND_SOC_IMX_SPDIF is not set
CONFIG_SND_SOC_IMX_MC13783=y
CONFIG_SND_OMAP_SOC=y
# CONFIG_SND_SOC_UX500 is not set
CONFIG_SND_SOC_I2C_AND_SPI=y
CONFIG_SND_SOC_SGTL5000=y
CONFIG_SND_SOC_WM8962=y
CONFIG_SND_SOC_WM9712=y
CONFIG_SND_SOC_MC13783=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SOUND_PRIME=y
CONFIG_AC97_BUS=y

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=y
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=y
CONFIG_HID_ACRUX=y
# CONFIG_HID_ACRUX_FF is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_AUREAL is not set
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_PRODIKEYS=y
CONFIG_HID_CYPRESS=y
# CONFIG_HID_DRAGONRISE is not set
CONFIG_HID_EMS_FF=y
# CONFIG_HID_ELECOM is not set
CONFIG_HID_ELO=y
# CONFIG_HID_EZKEY is not set
CONFIG_HID_HOLTEK=y
CONFIG_HOLTEK_FF=y
# CONFIG_HID_HUION is not set
CONFIG_HID_KEYTOUCH=y
CONFIG_HID_KYE=y
CONFIG_HID_UCLOGIC=y
CONFIG_HID_WALTOP=y
CONFIG_HID_GYRATION=y
CONFIG_HID_ICADE=y
CONFIG_HID_TWINHAN=y
# CONFIG_HID_KENSINGTON is not set
CONFIG_HID_LCPOWER=y
CONFIG_HID_LENOVO_TPKBD=y
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MAGICMOUSE is not set
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_MULTITOUCH=y
# CONFIG_HID_NTRIG is not set
CONFIG_HID_ORTEK=y
CONFIG_HID_PANTHERLORD=y
# CONFIG_PANTHERLORD_FF is not set
# CONFIG_HID_PETALYNX is not set
CONFIG_HID_PICOLCD=y
CONFIG_HID_PICOLCD_FB=y
# CONFIG_HID_PICOLCD_BACKLIGHT is not set
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PRIMAX=y
CONFIG_HID_ROCCAT=y
CONFIG_HID_SAITEK=y
CONFIG_HID_SAMSUNG=y
# CONFIG_HID_SONY is not set
CONFIG_HID_SPEEDLINK=y
CONFIG_HID_STEELSERIES=y
CONFIG_HID_SUNPLUS=y
# CONFIG_HID_GREENASIA is not set
CONFIG_HID_SMARTJOYPLUS=y
CONFIG_SMARTJOYPLUS_FF=y
# CONFIG_HID_TIVO is not set
CONFIG_HID_TOPSEED=y
CONFIG_HID_THINGM=y
CONFIG_HID_THRUSTMASTER=y
# CONFIG_THRUSTMASTER_FF is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_WIIMOTE is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
CONFIG_HID_ZYDACRON=y
CONFIG_HID_SENSOR_HUB=y

#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
# CONFIG_USB_HIDDEV is not set

#
# I2C HID support
#
CONFIG_I2C_HID=y
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
CONFIG_USB_DYNAMIC_MINORS=y
CONFIG_USB_OTG=y
CONFIG_USB_OTG_WHITELIST=y
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_MON=y
CONFIG_USB_WUSB_CBAF=y
CONFIG_USB_WUSB_CBAF_DEBUG=y

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=y
# CONFIG_USB_XHCI_HCD is not set
# CONFIG_USB_EHCI_HCD is not set
CONFIG_USB_OXU210HP_HCD=y
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
CONFIG_USB_FUSBH200_HCD=y
CONFIG_USB_FOTG210_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_SPEAR=y
# CONFIG_USB_OHCI_HCD_SSB is not set
CONFIG_USB_CNS3XXX_OHCI=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC=y
CONFIG_USB_UHCI_PLATFORM=y
# CONFIG_USB_U132_HCD is not set
CONFIG_USB_SL811_HCD=y
CONFIG_USB_SL811_HCD_ISO=y
CONFIG_USB_R8A66597_HCD=y
# CONFIG_USB_IMX21_HCD is not set
CONFIG_USB_HCD_BCMA=y
CONFIG_USB_HCD_SSB=y
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
# CONFIG_USB_PRINTER is not set
CONFIG_USB_WDM=y
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#

#
# USB Imaging devices
#
CONFIG_USB_MDC800=y
# CONFIG_USB_DWC3 is not set

#
# USB port drivers
#
CONFIG_USB_USS720=y

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=y
# CONFIG_USB_EMI26 is not set
CONFIG_USB_ADUTUX=y
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
CONFIG_USB_LEGOTOWER=y
# CONFIG_USB_LCD is not set
CONFIG_USB_LED=y
CONFIG_USB_CYPRESS_CY7C63=y
CONFIG_USB_CYTHERM=y
# CONFIG_USB_IDMOUSE is not set
CONFIG_USB_FTDI_ELAN=y
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
CONFIG_USB_TRANCEVIBRATOR=y
CONFIG_USB_IOWARRIOR=y
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
CONFIG_USB_ISIGHTFW=y
CONFIG_USB_YUREX=y
CONFIG_USB_EZUSB_FX2=y
CONFIG_USB_HSIC_USB3503=y

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_AB8500_USB=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_OMAP_CONTROL_USB=y
CONFIG_OMAP_USB3=y
CONFIG_AM335X_CONTROL_USB=y
CONFIG_AM335X_PHY_USB=y
# CONFIG_SAMSUNG_USB2PHY is not set
# CONFIG_SAMSUNG_USB3PHY is not set
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_MXS_PHY is not set
CONFIG_USB_RCAR_PHY=y
# CONFIG_USB_ULPI is not set
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
CONFIG_MEMSTICK=y
CONFIG_MEMSTICK_DEBUG=y

#
# MemoryStick drivers
#
CONFIG_MEMSTICK_UNSAFE_RESUME=y

#
# MemoryStick Host Controller Drivers
#
CONFIG_LEDS_GPIO_REGISTER=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y

#
# LED drivers
#
CONFIG_LEDS_88PM860X=y
CONFIG_LEDS_ATMEL_PWM=y
CONFIG_LEDS_LM3530=y
# CONFIG_LEDS_LM3533 is not set
CONFIG_LEDS_LM3642=y
CONFIG_LEDS_PCA9532=y
# CONFIG_LEDS_PCA9532_GPIO is not set
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_LP5521=y
# CONFIG_LEDS_LP5523 is not set
CONFIG_LEDS_LP5562=y
CONFIG_LEDS_LP8501=y
# CONFIG_LEDS_PCA955X is not set
CONFIG_LEDS_PCA963X=y
CONFIG_LEDS_PCA9685=y
# CONFIG_LEDS_DA9052 is not set
CONFIG_LEDS_DAC124S085=y
CONFIG_LEDS_PWM=y
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
CONFIG_LEDS_LT3593=y
# CONFIG_LEDS_MC13783 is not set
CONFIG_LEDS_ASIC3=y
# CONFIG_LEDS_TCA6507 is not set
CONFIG_LEDS_MAX8997=y
CONFIG_LEDS_LM355x=y
# CONFIG_LEDS_OT200 is not set
# CONFIG_LEDS_BLINKM is not set

#
# LED Triggers
#
# CONFIG_LEDS_TRIGGERS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_EDAC is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
CONFIG_DMADEVICES=y
CONFIG_DMADEVICES_DEBUG=y
# CONFIG_DMADEVICES_VDEBUG is not set

#
# DMA Devices
#
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_AMBA_PL08X=y
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
CONFIG_MV_XOR=y
CONFIG_MX3_IPU=y
CONFIG_MX3_IPU_IRQS=4
# CONFIG_STE_DMA40 is not set
CONFIG_TIMB_DMA=y
CONFIG_SIRF_DMA=y
CONFIG_TI_EDMA=y
# CONFIG_PL330_DMA is not set
CONFIG_IMX_SDMA=y
# CONFIG_IMX_DMA is not set
CONFIG_DMA_OMAP=y
CONFIG_TI_CPPI41=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_OF=y

#
# DMA Clients
#
CONFIG_ASYNC_TX_DMA=y
CONFIG_DMATEST=y
CONFIG_DMA_ENGINE_RAID=y
# CONFIG_AUXDISPLAY is not set
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=y
# CONFIG_UIO_DMEM_GENIRQ is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO=y

#
# Virtio drivers
#
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_MMIO=y
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set

#
# Microsoft Hyper-V guest support
#
CONFIG_STAGING=y
CONFIG_ECHO=y
CONFIG_PANEL=y
CONFIG_PANEL_PARPORT=0
CONFIG_PANEL_PROFILE=5
CONFIG_PANEL_CHANGE_MESSAGE=y
CONFIG_PANEL_BOOT_MESSAGE=""
CONFIG_TRANZPORT=y
CONFIG_LINE6_USB=y
CONFIG_LINE6_USB_IMPULSE_RESPONSE=y

#
# IIO staging drivers
#

#
# Accelerometers
#
CONFIG_ADIS16201=y
CONFIG_ADIS16203=y
CONFIG_ADIS16204=y
# CONFIG_ADIS16209 is not set
CONFIG_ADIS16220=y
# CONFIG_ADIS16240 is not set
CONFIG_LIS3L02DQ=y
CONFIG_SCA3000=y

#
# Analog to digital converters
#
# CONFIG_AD7291 is not set
CONFIG_AD7606=y
CONFIG_AD7606_IFACE_PARALLEL=y
CONFIG_AD7606_IFACE_SPI=y
# CONFIG_AD799X is not set
CONFIG_AD7780=y
CONFIG_AD7816=y
# CONFIG_AD7192 is not set
# CONFIG_AD7280 is not set
CONFIG_SPEAR_ADC=y

#
# Analog digital bi-direction converters
#
CONFIG_ADT7316=y
CONFIG_ADT7316_SPI=y
CONFIG_ADT7316_I2C=y

#
# Capacitance to digital converters
#
CONFIG_AD7150=y
CONFIG_AD7152=y
# CONFIG_AD7746 is not set

#
# Direct Digital Synthesis
#
# CONFIG_AD5930 is not set
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
CONFIG_AD9850=y
CONFIG_AD9852=y
CONFIG_AD9910=y
CONFIG_AD9951=y

#
# Digital gyroscope sensors
#
CONFIG_ADIS16060=y

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set

#
# Light sensors
#
CONFIG_SENSORS_ISL29018=y
CONFIG_SENSORS_ISL29028=y
# CONFIG_TSL2583 is not set
CONFIG_TSL2x7x=y

#
# Magnetometer sensors
#
CONFIG_SENSORS_HMC5843=y

#
# Active energy metering IC
#
# CONFIG_ADE7753 is not set
# CONFIG_ADE7754 is not set
# CONFIG_ADE7758 is not set
# CONFIG_ADE7759 is not set
CONFIG_ADE7854=y
# CONFIG_ADE7854_I2C is not set
CONFIG_ADE7854_SPI=y

#
# Resolver to digital converters
#
CONFIG_AD2S90=y
CONFIG_AD2S1200=y
# CONFIG_AD2S1210 is not set

#
# Triggers - standalone
#
CONFIG_IIO_DUMMY_EVGEN=y
CONFIG_IIO_SIMPLE_DUMMY=y
CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y
CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y
# CONFIG_ZSMALLOC is not set
# CONFIG_FT1000 is not set

#
# Speakup console speech
#
# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
# CONFIG_STAGING_MEDIA is not set

#
# Android
#
# CONFIG_ANDROID is not set
CONFIG_CED1401=y
# CONFIG_DRM_IMX is not set
# CONFIG_USB_DWC2 is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Common Clock Framework
#
CONFIG_COMMON_CLK_DEBUG=y
CONFIG_COMMON_CLK_MAX77686=y
CONFIG_COMMON_CLK_SI5351=y
CONFIG_COMMON_CLK_S2MPS11=y
# CONFIG_CLK_TWL6040 is not set
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
CONFIG_HWSPINLOCK=y

#
# Hardware Spinlock drivers
#
CONFIG_HSEM_U8500=y
CONFIG_CLKSRC_OF=y
CONFIG_CLKSRC_MMIO=y
CONFIG_DW_APB_TIMER=y
CONFIG_DW_APB_TIMER_OF=y
CONFIG_SUN4I_TIMER=y
CONFIG_VT8500_TIMER=y
CONFIG_CADENCE_TTC_TIMER=y
CONFIG_CLKSRC_NOMADIK_MTU=y
# CONFIG_CLKSRC_DBX500_PRCMU is not set
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GLOBAL_TIMER=y
CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
CONFIG_MAILBOX=y
CONFIG_PL320_MBOX=y
# CONFIG_OMAP2PLUS_MBOX is not set
# CONFIG_IOMMU_SUPPORT is not set

#
# Remoteproc drivers
#
# CONFIG_STE_MODEM_RPROC is not set

#
# Rpmsg drivers
#
CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
# CONFIG_DEVFREQ_GOV_USERSPACE is not set

#
# DEVFREQ Drivers
#
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_OF_EXTCON=y
CONFIG_EXTCON_GPIO=y
# CONFIG_EXTCON_ADC_JACK is not set
CONFIG_EXTCON_MAX77693=y
CONFIG_EXTCON_MAX8997=y
CONFIG_EXTCON_ARIZONA=y
CONFIG_MEMORY=y
CONFIG_TI_EMIF=y
CONFIG_MVEBU_DEVBUS=y
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2

#
# Accelerometers
#
CONFIG_BMA180=y
CONFIG_HID_SENSOR_ACCEL_3D=y
CONFIG_IIO_ST_ACCEL_3AXIS=y
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=y
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=y
CONFIG_KXSD9=y

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=y
CONFIG_AD7266=y
CONFIG_AD7298=y
CONFIG_AD7476=y
CONFIG_AD7791=y
CONFIG_AD7793=y
CONFIG_AD7887=y
CONFIG_AD7923=y
# CONFIG_EXYNOS_ADC is not set
# CONFIG_MAX1363 is not set
CONFIG_MCP320X=y
CONFIG_MCP3422=y
CONFIG_NAU7802=y
CONFIG_TI_ADC081C=y
CONFIG_VIPERBOARD_ADC=y

#
# Amplifiers
#
CONFIG_AD8366=y

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=y
CONFIG_HID_SENSOR_IIO_TRIGGER=y
CONFIG_IIO_ST_SENSORS_I2C=y
CONFIG_IIO_ST_SENSORS_SPI=y
CONFIG_IIO_ST_SENSORS_CORE=y

#
# Digital to analog converters
#
CONFIG_AD5064=y
CONFIG_AD5360=y
CONFIG_AD5380=y
# CONFIG_AD5421 is not set
# CONFIG_AD5446 is not set
CONFIG_AD5449=y
CONFIG_AD5504=y
# CONFIG_AD5624R_SPI is not set
CONFIG_AD5686=y
# CONFIG_AD5755 is not set
CONFIG_AD5764=y
CONFIG_AD5791=y
CONFIG_AD7303=y
# CONFIG_MAX517 is not set
CONFIG_MCP4725=y

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=y

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=y

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=y
# CONFIG_ADIS16130 is not set
CONFIG_ADIS16136=y
# CONFIG_ADIS16260 is not set
CONFIG_ADXRS450=y
CONFIG_HID_SENSOR_GYRO_3D=y
# CONFIG_IIO_ST_GYRO_3AXIS is not set
# CONFIG_ITG3200 is not set

#
# Inertial measurement units
#
# CONFIG_ADIS16400 is not set
CONFIG_ADIS16480=y
CONFIG_IIO_ADIS_LIB=y
CONFIG_IIO_ADIS_LIB_BUFFER=y
# CONFIG_INV_MPU6050_IIO is not set

#
# Light sensors
#
# CONFIG_ADJD_S311 is not set
# CONFIG_APDS9300 is not set
# CONFIG_CM36651 is not set
CONFIG_GP2AP020A00F=y
CONFIG_HID_SENSOR_ALS=y
CONFIG_SENSORS_LM3533=y
# CONFIG_TCS3472 is not set
# CONFIG_SENSORS_TSL2563 is not set
CONFIG_TSL4531=y
CONFIG_VCNL4000=y

#
# Magnetometer sensors
#
# CONFIG_AK8975 is not set
# CONFIG_MAG3110 is not set
CONFIG_HID_SENSOR_MAGNETOMETER_3D=y
CONFIG_IIO_ST_MAGN_3AXIS=y
CONFIG_IIO_ST_MAGN_I2C_3AXIS=y
CONFIG_IIO_ST_MAGN_SPI_3AXIS=y

#
# Triggers - standalone
#
CONFIG_IIO_INTERRUPT_TRIGGER=y
# CONFIG_IIO_SYSFS_TRIGGER is not set

#
# Pressure sensors
#
CONFIG_IIO_ST_PRESS=y
CONFIG_IIO_ST_PRESS_I2C=y
CONFIG_IIO_ST_PRESS_SPI=y

#
# Temperature sensors
#
# CONFIG_TMP006 is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_PWM_AB8500=y
CONFIG_PWM_IMX=y
# CONFIG_PWM_PCA9685 is not set
# CONFIG_PWM_SPEAR is not set
CONFIG_PWM_VT8500=y
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_VIC=y
CONFIG_ARM_VIC_NR=2
CONFIG_IPACK_BUS=y
# CONFIG_RESET_CONTROLLER is not set
CONFIG_FMC=y
CONFIG_FMC_FAKEDEV=y
CONFIG_FMC_TRIVIAL=y
CONFIG_FMC_WRITE_EEPROM=y
CONFIG_FMC_CHARDEV=y

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
CONFIG_OMAP_USB2=y
CONFIG_PHY_EXYNOS_DP_VIDEO=y
CONFIG_POWERCAP=y

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_FILE_LOCKING is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
# CONFIG_INOTIFY_USER is not set
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_QUOTACTL is not set
# CONFIG_AUTOFS4_FS is not set
CONFIG_FUSE_FS=y
# CONFIG_CUSE is not set

#
# Caches
#
# CONFIG_FSCACHE is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
# CONFIG_HUGETLB_PAGE is not set
CONFIG_CONFIGFS_FS=y
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ECRYPT_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_LOGFS is not set
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_MTD=y
CONFIG_ROMFS_ON_MTD=y
# CONFIG_PSTORE is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
CONFIG_NLS_CODEPAGE_775=y
CONFIG_NLS_CODEPAGE_850=y
# CONFIG_NLS_CODEPAGE_852 is not set
CONFIG_NLS_CODEPAGE_855=y
# CONFIG_NLS_CODEPAGE_857 is not set
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
CONFIG_NLS_CODEPAGE_864=y
CONFIG_NLS_CODEPAGE_865=y
CONFIG_NLS_CODEPAGE_866=y
CONFIG_NLS_CODEPAGE_869=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_CODEPAGE_932=y
CONFIG_NLS_CODEPAGE_949=y
CONFIG_NLS_CODEPAGE_874=y
CONFIG_NLS_ISO8859_8=y
CONFIG_NLS_CODEPAGE_1250=y
CONFIG_NLS_CODEPAGE_1251=y
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
CONFIG_NLS_ISO8859_5=y
CONFIG_NLS_ISO8859_6=y
CONFIG_NLS_ISO8859_7=y
CONFIG_NLS_ISO8859_9=y
CONFIG_NLS_ISO8859_13=y
# CONFIG_NLS_ISO8859_14 is not set
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=y
# CONFIG_NLS_MAC_ROMAN is not set
CONFIG_NLS_MAC_CELTIC=y
# CONFIG_NLS_MAC_CENTEURO is not set
CONFIG_NLS_MAC_CROATIAN=y
CONFIG_NLS_MAC_CYRILLIC=y
# CONFIG_NLS_MAC_GAELIC is not set
CONFIG_NLS_MAC_GREEK=y
CONFIG_NLS_MAC_ICELAND=y
CONFIG_NLS_MAC_INUIT=y
# CONFIG_NLS_MAC_ROMANIAN is not set
CONFIG_NLS_MAC_TURKISH=y
CONFIG_NLS_UTF8=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
CONFIG_BOOT_PRINTK_DELAY=y
CONFIG_DYNAMIC_DEBUG=y

#
# Compile-time checks and compiler options
#
# CONFIG_DEBUG_INFO is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_READABLE_ASM=y
CONFIG_UNUSED_SYMBOLS=y
CONFIG_DEBUG_FS=y
CONFIG_HEADERS_CHECK=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_DEBUG_KERNEL=y

#
# Memory Debugging
#
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_DEBUG_OBJECTS=y
CONFIG_DEBUG_OBJECTS_SELFTEST=y
# CONFIG_DEBUG_OBJECTS_FREE is not set
CONFIG_DEBUG_OBJECTS_TIMERS=y
# CONFIG_DEBUG_OBJECTS_WORK is not set
CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y
CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
CONFIG_SLUB_STATS=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
CONFIG_DEBUG_STACK_USAGE=y
# CONFIG_DEBUG_VM is not set
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_HIGHMEM=y
# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Lockups and Hangs
#
# CONFIG_LOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_SCHED_DEBUG=y
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
CONFIG_LOCKDEP=y
CONFIG_LOCK_STAT=y
CONFIG_DEBUG_LOCKDEP=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_TRACE_IRQFLAGS=y
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_KOBJECT_RELEASE is not set
CONFIG_DEBUG_WRITECOUNT=y
# CONFIG_DEBUG_LIST is not set
CONFIG_DEBUG_SG=y
# CONFIG_DEBUG_NOTIFIERS is not set
CONFIG_DEBUG_CREDENTIALS=y

#
# RCU Debugging
#
# CONFIG_PROVE_RCU is not set
CONFIG_SPARSE_RCU_POINTER=y
CONFIG_RCU_TORTURE_TEST=y
# CONFIG_RCU_TORTURE_TEST_RUNNABLE is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_TRACE=y
CONFIG_NOTIFIER_ERROR_INJECTION=y
# CONFIG_PM_NOTIFIER_ERROR_INJECT is not set
CONFIG_FAULT_INJECTION=y
# CONFIG_FAILSLAB is not set
# CONFIG_FAIL_PAGE_ALLOC is not set
# CONFIG_FAULT_INJECTION_DEBUG_FS is not set
CONFIG_LATENCYTOP=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set

#
# Runtime Testing
#
CONFIG_TEST_LIST_SORT=y
CONFIG_BACKTRACE_SELF_TEST=y
# CONFIG_RBTREE_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_TEST_STRING_HELPERS is not set
CONFIG_TEST_KSTRTOX=y
CONFIG_BUILD_DOCSRC=y
CONFIG_DMA_API_DEBUG=y
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
# CONFIG_STRICT_DEVMEM is not set
CONFIG_ARM_UNWIND=y
# CONFIG_DEBUG_USER is not set
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_BCM2835=y
# CONFIG_DEBUG_CNS3XXX is not set
# CONFIG_DEBUG_ZYNQ_UART0 is not set
# CONFIG_DEBUG_ZYNQ_UART1 is not set
# CONFIG_DEBUG_HIGHBANK_UART is not set
# CONFIG_DEBUG_IMX31_UART is not set
# CONFIG_DEBUG_IMX35_UART is not set
# CONFIG_DEBUG_MVEBU_UART is not set
# CONFIG_DEBUG_MVEBU_UART_ALTERNATE is not set
# CONFIG_DEBUG_OMAP2UART1 is not set
# CONFIG_DEBUG_OMAP2UART2 is not set
# CONFIG_DEBUG_OMAP2UART3 is not set
# CONFIG_DEBUG_OMAP3UART3 is not set
# CONFIG_DEBUG_OMAP4UART3 is not set
# CONFIG_DEBUG_OMAP3UART4 is not set
# CONFIG_DEBUG_OMAP4UART4 is not set
# CONFIG_DEBUG_TI81XXUART1 is not set
# CONFIG_DEBUG_TI81XXUART2 is not set
# CONFIG_DEBUG_TI81XXUART3 is not set
# CONFIG_DEBUG_AM33XXUART1 is not set
# CONFIG_DEBUG_ZOOM_UART is not set
# CONFIG_DEBUG_PICOXCELL_UART is not set
# CONFIG_DEBUG_RK29_UART0 is not set
# CONFIG_DEBUG_RK29_UART1 is not set
# CONFIG_DEBUG_RK29_UART2 is not set
# CONFIG_DEBUG_RK3X_UART0 is not set
# CONFIG_DEBUG_RK3X_UART1 is not set
# CONFIG_DEBUG_RK3X_UART2 is not set
# CONFIG_DEBUG_RK3X_UART3 is not set
# CONFIG_DEBUG_SUNXI_UART0 is not set
# CONFIG_DEBUG_SUNXI_UART1 is not set
# CONFIG_DEBUG_UX500_UART is not set
# CONFIG_DEBUG_VT8500_UART0 is not set
# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_DEBUG_SEMIHOSTING is not set
# CONFIG_DEBUG_LL_UART_8250 is not set
# CONFIG_DEBUG_LL_UART_PL01X is not set
CONFIG_DEBUG_IMX_UART_PORT=1
CONFIG_DEBUG_LL_INCLUDE="debug/pl01x.S"
CONFIG_DEBUG_UART_PL01X=y
# CONFIG_DEBUG_UART_8250 is not set
CONFIG_DEBUG_UART_PHYS=0x20201000
CONFIG_DEBUG_UART_VIRT=0xf0201000
CONFIG_DEBUG_UNCOMPRESS=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_EARLY_PRINTK=y
CONFIG_OC_ETM=y
# CONFIG_PID_IN_CONTEXTIDR is not set

#
# Security options
#
CONFIG_KEYS=y
CONFIG_PERSISTENT_KEYRINGS=y
CONFIG_ENCRYPTED_KEYS=y
CONFIG_KEYS_DEBUG_PROC_KEYS=y
CONFIG_SECURITY_DMESG_RESTRICT=y
CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_PATH=y
# CONFIG_SECURITY_YAMA is not set
# CONFIG_IMA is not set
# CONFIG_EVM is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_PCOMP=y
CONFIG_CRYPTO_PCOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SEQIV=y

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=y

#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_VMAC=y

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRC32 is not set
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_GHASH=y
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_RMD128=y
CONFIG_CRYPTO_RMD160=y
# CONFIG_CRYPTO_RMD256 is not set
CONFIG_CRYPTO_RMD320=y
CONFIG_CRYPTO_SHA1=y
# CONFIG_CRYPTO_SHA1_ARM is not set
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_SHA512 is not set
CONFIG_CRYPTO_TGR192=y
CONFIG_CRYPTO_WP512=y

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_ANUBIS=y
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_BLOWFISH is not set
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST_COMMON=y
# CONFIG_CRYPTO_CAST5 is not set
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_SALSA20=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_ZLIB=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y

#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_MV_CESA is not set
# CONFIG_CRYPTO_DEV_OMAP_SHAM is not set
CONFIG_CRYPTO_DEV_OMAP_AES=y
CONFIG_CRYPTO_DEV_PICOXCELL=y
# CONFIG_CRYPTO_DEV_SAHARA is not set
# CONFIG_CRYPTO_DEV_UX500 is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_PUBLIC_KEY_ALGO_RSA=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_BINARY_PRINTF is not set

#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IO=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
# CONFIG_CRC_CCITT is not set
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
CONFIG_CRC32_SELFTEST=y
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC7=y
# CONFIG_LIBCRC32C is not set
CONFIG_CRC8=y
CONFIG_RANDOM32_SELFTEST=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
# CONFIG_XZ_DEC is not set
# CONFIG_XZ_DEC_BCJ is not set
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_DMA=y
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
# CONFIG_AVERAGE is not set
CONFIG_CLZ_TAB=y
CONFIG_CORDIC=y
CONFIG_DDR=y
CONFIG_MPILIB=y
CONFIG_OID_REGISTRY=y
CONFIG_VIRTUALIZATION=y

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Felipe Balbi]

[-- Attachment #1.1: Type: text/plain, Size: 1416 bytes --]

Hi,

On Thu, Jan 09, 2014 at 11:22:17AM -0600, Felipe Balbi wrote:
> > Changes compared to previous version:
> > - Dropped any changes to generic clock drivers, as it seems impossible
> >   to agree anything in short term, this means the patch set shrank in
> >   size from 49 patches to 40 (first 9 patches were dropped).
> > - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
> >   to drivers/clk/ti, and made the modifications needed to the TI version
> >   of the clock drivers only (based on discussions with Mike, this is fine)
> > - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
> >   with any generic implementation we might have at some point, migrating
> >   this to the generic version should be easy enough also.
> > - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
> >   versions and resulted into an orphan clock node
> > - Fixed compile problem for omap5 only build reported by Felipe
> > - Fixed a couple of sparse warnings
> > - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
> >   instead of __raw_readl / __raw_writel
> 
> just caught a build breakage. .config attached

forgot to give you build errors found, they're here:
http://hastebin.com/jibuyuyoto.vbs

Also, just caught another build breakage:

http://hastebin.com/reravalupe.vbs

.config attached

-- 
balbi

[-- Attachment #1.2: config-am33xx-only.config-2 --]
[-- Type: text/plain, Size: 87926 bytes --]

#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 3.13.0-rc7 Kernel Configuration
#
CONFIG_ARM=y
CONFIG_MIGHT_HAVE_PCI=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_NO_IOPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_ARCH_HAS_CPUFREQ=y
CONFIG_ARCH_HAS_BANDGAP=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_FIQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
CONFIG_COMPILE_TEST=y
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
# CONFIG_KERNEL_LZ4 is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
CONFIG_FHANDLE=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_KTIME_SCALAR=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_PREEMPT_RCU is not set
CONFIG_RCU_STALL_COMMON=y
# CONFIG_RCU_USER_QS is not set
CONFIG_RCU_FANOUT=32
CONFIG_RCU_FANOUT_LEAF=16
CONFIG_RCU_FANOUT_EXACT=y
# CONFIG_RCU_FAST_NO_HZ is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_RCU_NOCB_CPU is not set
CONFIG_IKCONFIG=y
# CONFIG_IKCONFIG_PROC is not set
CONFIG_LOG_BUF_SHIFT=17
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_CGROUPS=y
# CONFIG_CGROUP_DEBUG is not set
# CONFIG_CGROUP_FREEZER is not set
CONFIG_CGROUP_DEVICE=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_MEMCG is not set
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
CONFIG_CHECKPOINT_RESTORE=y
# CONFIG_NAMESPACES is not set
# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
CONFIG_SCHED_AUTOGROUP=y
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_SYSFS_DEPRECATED_V2 is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
CONFIG_RD_LZMA=y
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
CONFIG_RD_LZ4=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_ANON_INODES=y
CONFIG_HAVE_UID16=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_PRINTK is not set
# CONFIG_BUG is not set
CONFIG_ELF_CORE=y
# CONFIG_BASE_FULL is not set
CONFIG_FUTEX=y
# CONFIG_EPOLL is not set
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SHMEM is not set
CONFIG_AIO=y
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y

#
# Kernel Performance Events And Counters
#
# CONFIG_PERF_EVENTS is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
CONFIG_COMPAT_BRK=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLUB_CPU_PARTIAL=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# CONFIG_OPROFILE is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_JUMP_LABEL=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y

#
# GCOV-based kernel profiling
#
CONFIG_GCOV_KERNEL=y
CONFIG_GCOV_FORMAT_AUTODETECT=y
# CONFIG_GCOV_FORMAT_3_4 is not set
# CONFIG_GCOV_FORMAT_4_7 is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=1
# CONFIG_MODULES is not set
CONFIG_STOP_MACHINE=y
CONFIG_BLOCK=y
CONFIG_LBDAF=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
# CONFIG_BLK_DEV_INTEGRITY is not set
CONFIG_BLK_CMDLINE_PARSER=y

#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_EFI_PARTITION=y

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_PADATA=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_FREEZER=y

#
# System Type
#
CONFIG_MMU=y
CONFIG_ARCH_MULTIPLATFORM=y
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_SHMOBILE is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C24XX is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5P64X0 is not set
# CONFIG_ARCH_S5PC100 is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP1 is not set

#
# Multiple platform selection
#

#
# CPU Core family selection
#
# CONFIG_ARCH_MULTI_V6 is not set
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_MULTI_V6_V7=y
# CONFIG_ARCH_MULTI_CPU_AUTO is not set
CONFIG_ARCH_MVEBU=y

#
# Marvell SOC with device tree
#
CONFIG_MACH_ARMADA_370_XP=y
CONFIG_MACH_ARMADA_370=y
# CONFIG_MACH_ARMADA_XP is not set
# CONFIG_ARCH_BCM is not set
CONFIG_GPIO_PCA953X=y
CONFIG_KEYBOARD_GPIO_POLLED=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ARCH_MXC=y

#
# Freescale i.MX support
#
# CONFIG_MXC_IRQ_PRIOR is not set
CONFIG_MXC_TZIC=y
CONFIG_MXC_DEBUG_BOARD=y
CONFIG_HAVE_IMX_ANATOP=y
CONFIG_HAVE_IMX_GPC=y
CONFIG_HAVE_IMX_MMDC=y
CONFIG_HAVE_IMX_SRC=y
CONFIG_ARCH_MXC_IOMUX_V3=y
CONFIG_SOC_IMX5=y
CONFIG_SOC_IMX51=y

#
# i.MX51 machines:
#
# CONFIG_MACH_IMX51_DT is not set
CONFIG_MACH_MX51_BABBAGE=y
CONFIG_MACH_EUKREA_CPUIMX51SD=y
CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD=y

#
# Device tree only
#
# CONFIG_SOC_IMX53 is not set
CONFIG_SOC_IMX6Q=y
# CONFIG_SOC_IMX6SL is not set
CONFIG_SOC_VF610=y
CONFIG_IMX_HAVE_PLATFORM_FEC=y
CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS=y
CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
CONFIG_IMX_HAVE_PLATFORM_MXC_NAND=y
CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y

#
# TI OMAP Common Features
#

#
# OMAP Feature Selections
#
# CONFIG_OMAP_RESET_CLOCKS is not set
CONFIG_OMAP_MUX=y
CONFIG_OMAP_MUX_DEBUG=y
CONFIG_OMAP_MUX_WARNINGS=y
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP_DM_TIMER=y
CONFIG_OMAP_PM_NOOP=y
CONFIG_MACH_OMAP_GENERIC=y
CONFIG_ARCH_OMAP=y
# CONFIG_ARCH_OMAP3 is not set
# CONFIG_ARCH_OMAP4 is not set
# CONFIG_SOC_OMAP5 is not set
CONFIG_SOC_AM33XX=y
# CONFIG_SOC_AM43XX is not set
CONFIG_ARCH_OMAP2PLUS=y

#
# TI OMAP2/3/4 Specific Features
#
# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
# CONFIG_SOC_HAS_OMAP2_SDRC is not set
CONFIG_SOC_HAS_REALTIME_COUNTER=y
CONFIG_SOC_DRA7XX=y

#
# OMAP Legacy Platform Data Board Type
#
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SOCFPGA=y
# CONFIG_PLAT_SPEAR is not set
# CONFIG_ARCH_STI is not set
CONFIG_ARCH_SHMOBILE_MULTI=y

#
# SH-Mobile System Type
#
# CONFIG_ARCH_EMEV2 is not set

#
# SH-Mobile Board Type
#

#
# SH-Mobile System Configuration
#

#
# Timer and clock configuration
#
CONFIG_SHMOBILE_TIMER_HZ=128
CONFIG_SH_TIMER_CMT=y
CONFIG_SH_TIMER_TMU=y
# CONFIG_EM_TIMER_STI is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_SIRF is not set
CONFIG_ARCH_TEGRA=y

#
# NVIDIA Tegra options
#
# CONFIG_ARCH_TEGRA_2x_SOC is not set
CONFIG_ARCH_TEGRA_3x_SOC=y
# CONFIG_ARCH_TEGRA_114_SOC is not set
# CONFIG_ARCH_TEGRA_124_SOC is not set
# CONFIG_TEGRA_AHB is not set
# CONFIG_TEGRA_EMC_SCALING_ENABLE is not set
# CONFIG_ARCH_U8500 is not set
# CONFIG_ARCH_VEXPRESS is not set
CONFIG_ARCH_VIRT=y
CONFIG_ARCH_VT8500=y
CONFIG_ARCH_WM8850=y
# CONFIG_ARCH_ZYNQ is not set
CONFIG_PLAT_ORION=y
CONFIG_ARM_TIMER_SP804=y

#
# Processor Type
#
CONFIG_CPU_PJ4B=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y

#
# Processor Features
#
# CONFIG_ARM_LPAE is not set
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
CONFIG_ARM_VIRT_EXT=y
# CONFIG_SWP_EMULATE is not set
# CONFIG_CPU_BIG_ENDIAN is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
CONFIG_CPU_DCACHE_DISABLE=y
CONFIG_CPU_BPREDICT_DISABLE=y
# CONFIG_KUSER_HELPERS is not set
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_CACHE_L2X0=y
CONFIG_CACHE_PL310=y
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
CONFIG_ARM_NR_BANKS=8
CONFIG_MULTI_IRQ_HANDLER=y
CONFIG_PJ4B_ERRATA_4742=y
# CONFIG_ARM_ERRATA_430973 is not set
CONFIG_PL310_ERRATA_588369=y
# CONFIG_ARM_ERRATA_643719 is not set
# CONFIG_ARM_ERRATA_720789 is not set
CONFIG_PL310_ERRATA_727915=y
CONFIG_PL310_ERRATA_753970=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_ARM_ERRATA_754327=y
CONFIG_ARM_ERRATA_764369=y
CONFIG_PL310_ERRATA_769419=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_ARM_ERRATA_798181=y
CONFIG_ARM_ERRATA_773022=y
CONFIG_TI_PRIV_EDMA=y

#
# Bus support
#
CONFIG_ARM_AMBA=y
# CONFIG_PCI is not set
# CONFIG_PCI_SYSCALL is not set
CONFIG_PCCARD=y
CONFIG_PCMCIA=y
# CONFIG_PCMCIA_LOAD_CIS is not set

#
# PC-card bridges
#

#
# Kernel Features
#
CONFIG_HAVE_SMP=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_HAVE_ARM_SCU=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_HAVE_ARM_TWD=y
CONFIG_MCPM=y
CONFIG_BIG_LITTLE=y
CONFIG_BL_SWITCHER=y
# CONFIG_BL_SWITCHER_DUMMY_IF is not set
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_NR_CPUS=4
CONFIG_HOTPLUG_CPU=y
CONFIG_ARM_PSCI=y
CONFIG_ARCH_NR_GPIO=1024
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_HZ_FIXED=0
CONFIG_HZ_100=y
# CONFIG_HZ_200 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_500 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
# CONFIG_THUMB2_KERNEL is not set
# CONFIG_AEABI is not set
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_COMPACTION is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
# CONFIG_BOUNCE is not set
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CLEANCACHE=y
# CONFIG_CMA is not set
# CONFIG_ZBUD is not set
CONFIG_FORCE_MAX_ZONEORDER=12
CONFIG_ALIGNMENT_TRAP=y
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_SECCOMP=y
CONFIG_CC_STACKPROTECTOR=y
CONFIG_SWIOTLB=y
CONFIG_IOMMU_HELPER=y

#
# Boot options
#
CONFIG_USE_OF=y
CONFIG_ATAGS=y
# CONFIG_DEPRECATED_PARAM_STRUCT is not set
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
CONFIG_CMDLINE=""
CONFIG_KEXEC=y
# CONFIG_ATAGS_PROC is not set
CONFIG_CRASH_DUMP=y
CONFIG_AUTO_ZRELADDR=y

#
# CPU Power Management
#

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_STAT_DETAILS=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_GENERIC_CPUFREQ_CPU0=y

#
# ARM CPU frequency scaling drivers
#
CONFIG_ARM_HIGHBANK_CPUFREQ=y
CONFIG_ARM_IMX6Q_CPUFREQ=y
# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
CONFIG_ARM_TEGRA_CPUFREQ=y

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y

#
# ARM CPU Idle Drivers
#
# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set

#
# Floating point emulation
#

#
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
CONFIG_FPE_FASTFPE=y
# CONFIG_VFP is not set

#
# Userspace binary formats
#
# CONFIG_BINFMT_ELF is not set
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_BINFMT_SCRIPT=y
# CONFIG_HAVE_AOUT is not set
CONFIG_BINFMT_MISC=y
CONFIG_COREDUMP=y
CONFIG_ARTHUR=y

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=100
# CONFIG_PM_WAKELOCKS_GC is not set
# CONFIG_PM_RUNTIME is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
# CONFIG_APM_EMULATION is not set
CONFIG_ARCH_HAS_OPP=y
CONFIG_PM_OPP=y
CONFIG_PM_CLK=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_CPU_PM=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_NET is not set
CONFIG_HAVE_BPF_JIT=y

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH=""
# CONFIG_DEVTMPFS is not set
# CONFIG_STANDALONE is not set
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_GENERIC_CPU_DEVICES is not set
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_DMA_SHARED_BUFFER=y

#
# Bus devices
#
CONFIG_IMX_WEIM=y
CONFIG_MVEBU_MBUS=y
CONFIG_OMAP_OCP2SCP=y
CONFIG_OMAP_INTERCONNECT=y
# CONFIG_ARM_CCI is not set
CONFIG_MTD=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_AFS_PARTS=y
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AR7_PARTS is not set

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
CONFIG_FTL=y
CONFIG_NFTL=y
CONFIG_NFTL_RW=y
# CONFIG_INFTL is not set
CONFIG_RFD_FTL=y
CONFIG_SSFDC=y
CONFIG_SM_FTL=y
CONFIG_MTD_OOPS=y

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=y
CONFIG_MTD_ABSENT=y

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_IMPA7=y
CONFIG_MTD_PLATRAM=y

#
# Self-contained MTD device drivers
#
CONFIG_MTD_DATAFLASH=y
# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
CONFIG_MTD_DATAFLASH_OTP=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y
CONFIG_MTD_SLRAM=y
CONFIG_MTD_PHRAM=y
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=4096
CONFIG_MTDRAM_ERASE_SIZE=128
CONFIG_MTDRAM_ABS_POS=0
CONFIG_MTD_BLOCK2MTD=y

#
# Disk-On-Chip Device Drivers
#
CONFIG_MTD_DOCG3=y
CONFIG_BCH_CONST_M=14
CONFIG_BCH_CONST_T=4
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SMC is not set
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_BCH=y
CONFIG_MTD_NAND_ECC_BCH=y
# CONFIG_MTD_SM_COMMON is not set
# CONFIG_MTD_NAND_DENALI is not set
CONFIG_MTD_NAND_GPIO=y
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND_DISKONCHIP=y
# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
CONFIG_MTD_NAND_DOCG4=y
CONFIG_MTD_NAND_PXA3xx=y
# CONFIG_MTD_NAND_NANDSIM is not set
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_ORION=y
CONFIG_MTD_NAND_MXC=y
# CONFIG_MTD_ONENAND is not set

#
# LPDDR flash memory drivers
#
CONFIG_MTD_LPDDR=y
CONFIG_MTD_QINFO_PROBE=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_DTC=y
CONFIG_OF=y

#
# Device Tree and Open Firmware support
#
CONFIG_PROC_DEVICETREE=y
CONFIG_OF_SELFTEST=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_MTD=y
CONFIG_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_PARPORT_PC is not set
# CONFIG_PARPORT_GSC is not set
CONFIG_PARPORT_AX88796=y
CONFIG_PARPORT_1284=y
CONFIG_PARPORT_NOT_PC=y
# CONFIG_BLK_DEV is not set

#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=y
CONFIG_AD525X_DPOT=y
CONFIG_AD525X_DPOT_I2C=y
# CONFIG_AD525X_DPOT_SPI is not set
CONFIG_ATMEL_PWM=y
CONFIG_DUMMY_IRQ=y
CONFIG_ICS932S401=y
CONFIG_ATMEL_SSC=y
# CONFIG_ENCLOSURE_SERVICES is not set
CONFIG_APDS9802ALS=y
CONFIG_ISL29003=y
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
CONFIG_SENSORS_BH1780=y
# CONFIG_SENSORS_BH1770 is not set
CONFIG_SENSORS_APDS990X=y
# CONFIG_HMC6352 is not set
CONFIG_DS1682=y
CONFIG_TI_DAC7512=y
CONFIG_BMP085=y
CONFIG_BMP085_I2C=y
CONFIG_BMP085_SPI=y
CONFIG_USB_SWITCH_FSA9480=y
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
CONFIG_C2PORT=y

#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
# CONFIG_EEPROM_AT25 is not set
CONFIG_EEPROM_LEGACY=y
CONFIG_EEPROM_MAX6875=y
CONFIG_EEPROM_93CX6=y
# CONFIG_EEPROM_93XX46 is not set
CONFIG_EEPROM_SUNXI_SID=y

#
# Texas Instruments shared transport line discipline
#
CONFIG_SENSORS_LIS3_SPI=y
# CONFIG_SENSORS_LIS3_I2C is not set

#
# Altera FPGA firmware download module
#
CONFIG_ALTERA_STAPL=y

#
# Intel MIC Host Driver
#

#
# Intel MIC Card Driver
#
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
# CONFIG_BLK_DEV_SD is not set
CONFIG_CHR_DEV_ST=y
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
# CONFIG_BLK_DEV_SR_VENDOR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
CONFIG_SCSI_SCAN_ASYNC=y

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_SAS_ATTRS=y
CONFIG_SCSI_SAS_LIBSAS=y
CONFIG_SCSI_SAS_ATA=y
# CONFIG_SCSI_SAS_HOST_SMP is not set
CONFIG_SCSI_SRP_ATTRS=y
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_LIBFC is not set
# CONFIG_LIBFCOE is not set
CONFIG_SCSI_DEBUG=y
CONFIG_SCSI_VIRTIO=y
CONFIG_SCSI_LOWLEVEL_PCMCIA=y
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=y
# CONFIG_SCSI_DH_HP_SW is not set
CONFIG_SCSI_DH_EMC=y
# CONFIG_SCSI_DH_ALUA is not set
CONFIG_SCSI_OSD_INITIATOR=y
# CONFIG_SCSI_OSD_ULD is not set
CONFIG_SCSI_OSD_DPRINT_SENSE=1
CONFIG_SCSI_OSD_DEBUG=y
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
CONFIG_ATA_VERBOSE_ERROR=y
# CONFIG_SATA_PMP is not set

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI_PLATFORM=y
# CONFIG_AHCI_IMX is not set
# CONFIG_ATA_SFF is not set
# CONFIG_MD is not set
CONFIG_TARGET_CORE=y
# CONFIG_TCM_IBLOCK is not set
CONFIG_TCM_FILEIO=y
CONFIG_TCM_PSCSI=y
CONFIG_LOOPBACK_TARGET=y

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_POLLDEV=y
CONFIG_INPUT_SPARSEKMAP=y
CONFIG_INPUT_MATRIXKMAP=y

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
CONFIG_KEYBOARD_ADP5589=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1070 is not set
CONFIG_KEYBOARD_QT2160=y
CONFIG_KEYBOARD_LKKBD=y
# CONFIG_KEYBOARD_GPIO is not set
CONFIG_KEYBOARD_TCA6416=y
CONFIG_KEYBOARD_TCA8418=y
CONFIG_KEYBOARD_MATRIX=y
CONFIG_KEYBOARD_LM8323=y
CONFIG_KEYBOARD_LM8333=y
CONFIG_KEYBOARD_MAX7359=y
CONFIG_KEYBOARD_MCS=y
# CONFIG_KEYBOARD_MPR121 is not set
CONFIG_KEYBOARD_IMX=y
# CONFIG_KEYBOARD_NEWTON is not set
CONFIG_KEYBOARD_TEGRA=y
CONFIG_KEYBOARD_OPENCORES=y
# CONFIG_KEYBOARD_SAMSUNG is not set
CONFIG_KEYBOARD_STOWAWAY=y
CONFIG_KEYBOARD_SUNKBD=y
CONFIG_KEYBOARD_SH_KEYSC=y
CONFIG_KEYBOARD_STMPE=y
CONFIG_KEYBOARD_OMAP4=y
CONFIG_KEYBOARD_TWL4030=y
CONFIG_KEYBOARD_XTKBD=y
CONFIG_KEYBOARD_CROS_EC=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
CONFIG_JOYSTICK_A3D=y
CONFIG_JOYSTICK_ADI=y
CONFIG_JOYSTICK_COBRA=y
CONFIG_JOYSTICK_GF2K=y
CONFIG_JOYSTICK_GRIP=y
CONFIG_JOYSTICK_GRIP_MP=y
CONFIG_JOYSTICK_GUILLEMOT=y
CONFIG_JOYSTICK_INTERACT=y
# CONFIG_JOYSTICK_SIDEWINDER is not set
CONFIG_JOYSTICK_TMDC=y
CONFIG_JOYSTICK_IFORCE=y
CONFIG_JOYSTICK_IFORCE_USB=y
# CONFIG_JOYSTICK_IFORCE_232 is not set
# CONFIG_JOYSTICK_WARRIOR is not set
CONFIG_JOYSTICK_MAGELLAN=y
CONFIG_JOYSTICK_SPACEORB=y
CONFIG_JOYSTICK_SPACEBALL=y
# CONFIG_JOYSTICK_STINGER is not set
CONFIG_JOYSTICK_TWIDJOY=y
# CONFIG_JOYSTICK_ZHENHUA is not set
CONFIG_JOYSTICK_DB9=y
CONFIG_JOYSTICK_GAMECON=y
CONFIG_JOYSTICK_TURBOGRAFX=y
# CONFIG_JOYSTICK_AS5011 is not set
CONFIG_JOYSTICK_JOYDUMP=y
# CONFIG_JOYSTICK_XPAD is not set
# CONFIG_JOYSTICK_WALKERA0701 is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_AD7877=y
CONFIG_TOUCHSCREEN_AD7879=y
CONFIG_TOUCHSCREEN_AD7879_I2C=y
CONFIG_TOUCHSCREEN_AD7879_SPI=y
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
CONFIG_TOUCHSCREEN_AUO_PIXCIR=y
CONFIG_TOUCHSCREEN_BU21013=y
CONFIG_TOUCHSCREEN_CY8CTMG110=y
CONFIG_TOUCHSCREEN_CYTTSP_CORE=y
CONFIG_TOUCHSCREEN_CYTTSP_I2C=y
CONFIG_TOUCHSCREEN_CYTTSP_SPI=y
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=y
# CONFIG_TOUCHSCREEN_CYTTSP4_I2C is not set
CONFIG_TOUCHSCREEN_CYTTSP4_SPI=y
# CONFIG_TOUCHSCREEN_DA9052 is not set
CONFIG_TOUCHSCREEN_DYNAPRO=y
CONFIG_TOUCHSCREEN_HAMPSHIRE=y
CONFIG_TOUCHSCREEN_EETI=y
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
CONFIG_TOUCHSCREEN_ILI210X=y
CONFIG_TOUCHSCREEN_GUNZE=y
CONFIG_TOUCHSCREEN_ELO=y
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
CONFIG_TOUCHSCREEN_MCS5000=y
CONFIG_TOUCHSCREEN_MMS114=y
CONFIG_TOUCHSCREEN_MTOUCH=y
CONFIG_TOUCHSCREEN_INEXIO=y
CONFIG_TOUCHSCREEN_MK712=y
CONFIG_TOUCHSCREEN_PENMOUNT=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
CONFIG_TOUCHSCREEN_TOUCHRIGHT=y
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
CONFIG_TOUCHSCREEN_TI_AM335X_TSC=y
# CONFIG_TOUCHSCREEN_PIXCIR is not set
CONFIG_TOUCHSCREEN_WM831X=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=y
# CONFIG_TOUCHSCREEN_MC13783 is not set
# CONFIG_TOUCHSCREEN_USB_EGALAX is not set
# CONFIG_TOUCHSCREEN_USB_PANJIT is not set
# CONFIG_TOUCHSCREEN_USB_3M is not set
CONFIG_TOUCHSCREEN_USB_ITM=y
# CONFIG_TOUCHSCREEN_USB_ETURBO is not set
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
# CONFIG_TOUCHSCREEN_USB_IRTOUCH is not set
# CONFIG_TOUCHSCREEN_USB_IDEALTEK is not set
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
# CONFIG_TOUCHSCREEN_USB_E2I is not set
# CONFIG_TOUCHSCREEN_USB_ZYTRONIC is not set
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
# CONFIG_TOUCHSCREEN_USB_NEXIO is not set
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=y
CONFIG_TOUCHSCREEN_TSC_SERIO=y
CONFIG_TOUCHSCREEN_TSC2005=y
# CONFIG_TOUCHSCREEN_TSC2007 is not set
CONFIG_TOUCHSCREEN_W90X900=y
CONFIG_TOUCHSCREEN_ST1232=y
CONFIG_TOUCHSCREEN_STMPE=y
CONFIG_TOUCHSCREEN_SUR40=y
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZFORCE is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AD714X=y
# CONFIG_INPUT_AD714X_I2C is not set
CONFIG_INPUT_AD714X_SPI=y
CONFIG_INPUT_ARIZONA_HAPTICS=y
CONFIG_INPUT_BMA150=y
CONFIG_INPUT_MAX8925_ONKEY=y
CONFIG_INPUT_MC13783_PWRBUTTON=y
CONFIG_INPUT_MMA8450=y
CONFIG_INPUT_MPU3050=y
CONFIG_INPUT_GP2A=y
# CONFIG_INPUT_GPIO_TILT_POLLED is not set
CONFIG_INPUT_ATI_REMOTE2=y
CONFIG_INPUT_KEYSPAN_REMOTE=y
CONFIG_INPUT_KXTJ9=y
# CONFIG_INPUT_KXTJ9_POLLED_MODE is not set
CONFIG_INPUT_POWERMATE=y
CONFIG_INPUT_YEALINK=y
CONFIG_INPUT_CM109=y
CONFIG_INPUT_RETU_PWRBUTTON=y
CONFIG_INPUT_TWL4030_PWRBUTTON=y
# CONFIG_INPUT_TWL4030_VIBRA is not set
CONFIG_INPUT_TWL6040_VIBRA=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF50633_PMU is not set
CONFIG_INPUT_PCF8574=y
CONFIG_INPUT_GPIO_ROTARY_ENCODER=y
# CONFIG_INPUT_DA9052_ONKEY is not set
# CONFIG_INPUT_WM831X_ON is not set
# CONFIG_INPUT_ADXL34X is not set
CONFIG_INPUT_IMS_PCU=y
CONFIG_INPUT_CMA3000=y
CONFIG_INPUT_CMA3000_I2C=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_PARKBD is not set
CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
CONFIG_SERIO_ALTERA_PS2=y
CONFIG_SERIO_PS2MULT=y
# CONFIG_SERIO_ARC_PS2 is not set
CONFIG_SERIO_APBPS2=y
CONFIG_SERIO_OLPC_APSP=y
CONFIG_GAMEPORT=y
CONFIG_GAMEPORT_NS558=y
# CONFIG_GAMEPORT_L4 is not set

#
# Character devices
#
CONFIG_TTY=y
# CONFIG_VT is not set
# CONFIG_UNIX98_PTYS is not set
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_TRACE_ROUTER is not set
CONFIG_TRACE_SINK=y
# CONFIG_DEVKMEM is not set

#
# Serial drivers
#
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
# CONFIG_SERIAL_8250_CONSOLE is not set
# CONFIG_SERIAL_8250_DMA is not set
CONFIG_SERIAL_8250_CS=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
# CONFIG_SERIAL_8250_RSA is not set
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_EM=y

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_AMBA_PL010 is not set
# CONFIG_SERIAL_AMBA_PL011 is not set
# CONFIG_SERIAL_TEGRA is not set
CONFIG_SERIAL_MAX3100=y
# CONFIG_SERIAL_MAX310X is not set
CONFIG_SERIAL_IMX=y
# CONFIG_SERIAL_IMX_CONSOLE is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=2
CONFIG_SERIAL_SH_SCI_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_VT8500 is not set
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_SERIAL_OMAP is not set
CONFIG_SERIAL_SCCNXP=y
CONFIG_SERIAL_SCCNXP_CONSOLE=y
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_SERIAL_ALTERA_JTAGUART=y
# CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE is not set
# CONFIG_SERIAL_ALTERA_UART is not set
CONFIG_SERIAL_IFX6X60=y
# CONFIG_SERIAL_XILINX_PS_UART is not set
CONFIG_SERIAL_EFM32_UART=y
CONFIG_SERIAL_EFM32_UART_CONSOLE=y
CONFIG_SERIAL_ARC=y
# CONFIG_SERIAL_ARC_CONSOLE is not set
CONFIG_SERIAL_ARC_NR_PORTS=1
CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_ST_ASC=y
CONFIG_SERIAL_ST_ASC_CONSOLE=y
CONFIG_TTY_PRINTK=y
CONFIG_PRINTER=y
# CONFIG_LP_CONSOLE is not set
CONFIG_PPDEV=y
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
CONFIG_VIRTIO_CONSOLE=y
CONFIG_IPMI_HANDLER=y
# CONFIG_IPMI_PANIC_EVENT is not set
CONFIG_IPMI_DEVICE_INTERFACE=y
CONFIG_IPMI_SI=y
CONFIG_IPMI_WATCHDOG=y
# CONFIG_IPMI_POWEROFF is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
CONFIG_HW_RANDOM_ATMEL=y
# CONFIG_HW_RANDOM_OMAP is not set
CONFIG_HW_RANDOM_VIRTIO=y
# CONFIG_HW_RANDOM_EXYNOS is not set
CONFIG_HW_RANDOM_TPM=y
# CONFIG_NVRAM is not set
CONFIG_R3964=y

#
# PCMCIA character devices
#
CONFIG_SYNCLINK_CS=y
CONFIG_CARDMAN_4000=y
CONFIG_CARDMAN_4040=y
CONFIG_RAW_DRIVER=y
CONFIG_MAX_RAW_DEVS=256
CONFIG_TCG_TPM=y
# CONFIG_TCG_TIS_I2C_ATMEL is not set
CONFIG_TCG_TIS_I2C_INFINEON=y
CONFIG_TCG_TIS_I2C_NUVOTON=y
CONFIG_TCG_ST33_I2C=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_PCA9541=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_CBUS_GPIO=y
CONFIG_I2C_DAVINCI=y
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_IMX=y
CONFIG_I2C_MV64XXX=y
CONFIG_I2C_NOMADIK=y
CONFIG_I2C_OCORES=y
# CONFIG_I2C_OMAP is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_PXA_PCI is not set
# CONFIG_I2C_SH_MOBILE is not set
CONFIG_I2C_SIMTEC=y
# CONFIG_I2C_TEGRA is not set
CONFIG_I2C_WMT=y
# CONFIG_I2C_XILINX is not set
CONFIG_I2C_RCAR=y

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_PARPORT is not set
CONFIG_I2C_PARPORT_LIGHT=y
CONFIG_I2C_TAOS_EVM=y
# CONFIG_I2C_TINY_USB is not set
CONFIG_I2C_VIPERBOARD=y

#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_DEBUG_CORE=y
CONFIG_I2C_DEBUG_ALGO=y
CONFIG_I2C_DEBUG_BUS=y
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y

#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=y
CONFIG_SPI_ATMEL=y
CONFIG_SPI_BCM2835=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_BUTTERFLY=y
CONFIG_SPI_DAVINCI=y
# CONFIG_SPI_EFM32 is not set
CONFIG_SPI_EP93XX=y
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_IMX=y
CONFIG_SPI_LM70_LLP=y
# CONFIG_SPI_FSL_SPI is not set
CONFIG_SPI_FSL_DSPI=y
# CONFIG_SPI_OC_TINY is not set
CONFIG_SPI_OMAP24XX=y
# CONFIG_SPI_TI_QSPI is not set
CONFIG_SPI_OMAP_100K=y
CONFIG_SPI_ORION=y
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_PXA2XX_PCI is not set
CONFIG_SPI_SC18IS602=y
# CONFIG_SPI_SH is not set
CONFIG_SPI_SH_HSPI=y
CONFIG_SPI_TEGRA114=y
CONFIG_SPI_TEGRA20_SFLASH=y
CONFIG_SPI_TEGRA20_SLINK=y
CONFIG_SPI_TXX9=y
CONFIG_SPI_XCOMM=y
CONFIG_SPI_XILINX=y
# CONFIG_SPI_DESIGNWARE is not set

#
# SPI Protocol Masters
#
# CONFIG_SPI_SPIDEV is not set
CONFIG_SPI_TLE62X0=y
CONFIG_HSI=y
CONFIG_HSI_BOARDINFO=y

#
# HSI clients
#
# CONFIG_HSI_CHAR is not set

#
# PPS support
#
CONFIG_PPS=y
CONFIG_PPS_DEBUG=y

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
CONFIG_PPS_CLIENT_LDISC=y
# CONFIG_PPS_CLIENT_PARPORT is not set
CONFIG_PPS_CLIENT_GPIO=y

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# CONFIG_PTP_1588_CLOCK_PCH is not set
CONFIG_PINCTRL=y

#
# Pin controllers
#
CONFIG_PINMUX=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
CONFIG_DEBUG_PINCTRL=y
CONFIG_PINCTRL_IMX=y
CONFIG_PINCTRL_IMX51=y
CONFIG_PINCTRL_IMX6Q=y
CONFIG_PINCTRL_VF610=y
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PINCTRL_SUNXI=y
CONFIG_PINCTRL_TEGRA=y
CONFIG_PINCTRL_TEGRA30=y
CONFIG_PINCTRL_MVEBU=y
CONFIG_PINCTRL_ARMADA_370=y
CONFIG_PINCTRL_WMT=y
CONFIG_PINCTRL_WM8850=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_DEVRES=y
CONFIG_OF_GPIO=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC=y
# CONFIG_GPIO_DA9052 is not set
CONFIG_GPIO_MAX730X=y

#
# Memory mapped GPIO drivers:
#
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_EM is not set
CONFIG_GPIO_MVEBU=y
CONFIG_GPIO_MXC=y
CONFIG_GPIO_PL061=y
# CONFIG_GPIO_RCAR is not set
CONFIG_GPIO_TS5500=y
# CONFIG_GPIO_GRGPIO is not set

#
# I2C GPIO expanders:
#
CONFIG_GPIO_ARIZONA=y
CONFIG_GPIO_MAX7300=y
CONFIG_GPIO_MAX732X=y
# CONFIG_GPIO_MAX732X_IRQ is not set
# CONFIG_GPIO_PCA953X_IRQ is not set
CONFIG_GPIO_PCF857X=y
# CONFIG_GPIO_SX150X is not set
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_TWL4030=y
CONFIG_GPIO_TWL6040=y
# CONFIG_GPIO_WM831X is not set
CONFIG_GPIO_WM8350=y
CONFIG_GPIO_WM8994=y
CONFIG_GPIO_ADP5588=y
CONFIG_GPIO_ADP5588_IRQ=y
CONFIG_GPIO_ADNP=y

#
# PCI GPIO expanders:
#

#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
CONFIG_GPIO_MC33880=y
CONFIG_GPIO_74X164=y

#
# AC97 GPIO expanders:
#

#
# LPC GPIO expanders:
#

#
# MODULbus GPIO expanders:
#
CONFIG_GPIO_TPS65910=y
# CONFIG_GPIO_BCM_KONA is not set

#
# USB GPIO expanders:
#
CONFIG_GPIO_VIPERBOARD=y
CONFIG_W1=y

#
# 1-wire Bus Masters
#
# CONFIG_W1_MASTER_DS2490 is not set
CONFIG_W1_MASTER_DS2482=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_MASTER_DS1WM=y
# CONFIG_W1_MASTER_GPIO is not set
# CONFIG_HDQ_MASTER_OMAP is not set

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=y
# CONFIG_W1_SLAVE_SMEM is not set
# CONFIG_W1_SLAVE_DS2408 is not set
# CONFIG_W1_SLAVE_DS2413 is not set
CONFIG_W1_SLAVE_DS2423=y
CONFIG_W1_SLAVE_DS2431=y
CONFIG_W1_SLAVE_DS2433=y
# CONFIG_W1_SLAVE_DS2433_CRC is not set
CONFIG_W1_SLAVE_DS2760=y
# CONFIG_W1_SLAVE_DS2780 is not set
# CONFIG_W1_SLAVE_DS2781 is not set
CONFIG_W1_SLAVE_DS28E04=y
# CONFIG_W1_SLAVE_BQ27000 is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_PDA_POWER=y
# CONFIG_GENERIC_ADC_BATTERY is not set
CONFIG_MAX8925_POWER=y
# CONFIG_WM831X_BACKUP is not set
# CONFIG_WM831X_POWER is not set
CONFIG_WM8350_POWER=y
CONFIG_TEST_POWER=y
CONFIG_BATTERY_DS2760=y
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
CONFIG_BATTERY_SBS=y
CONFIG_BATTERY_BQ27x00=y
CONFIG_BATTERY_BQ27X00_I2C=y
CONFIG_BATTERY_BQ27X00_PLATFORM=y
CONFIG_BATTERY_DA9052=y
# CONFIG_BATTERY_MAX17040 is not set
CONFIG_BATTERY_MAX17042=y
CONFIG_BATTERY_TWL4030_MADC=y
CONFIG_CHARGER_PCF50633=y
CONFIG_BATTERY_RX51=y
CONFIG_CHARGER_ISP1704=y
# CONFIG_CHARGER_MAX8903 is not set
CONFIG_CHARGER_TWL4030=y
CONFIG_CHARGER_LP8727=y
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
CONFIG_CHARGER_BQ2415X=y
CONFIG_CHARGER_BQ24190=y
# CONFIG_CHARGER_BQ24735 is not set
CONFIG_CHARGER_SMB347=y
CONFIG_BATTERY_GOLDFISH=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
# CONFIG_POWER_RESET_QNAP is not set
CONFIG_POWER_RESET_RESTART=y
# CONFIG_POWER_AVS is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y

#
# Sonics Silicon Backplane
#
CONFIG_SSB=y
CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
# CONFIG_SSB_PCMCIAHOST is not set
CONFIG_SSB_SDIOHOST_POSSIBLE=y
# CONFIG_SSB_SDIOHOST is not set
CONFIG_SSB_SILENT=y
CONFIG_SSB_DRIVER_GPIO=y
CONFIG_BCMA_POSSIBLE=y

#
# Broadcom specific AMBA
#
CONFIG_BCMA=y
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
# CONFIG_BCMA_DEBUG is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
CONFIG_MFD_AS3711=y
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
CONFIG_MFD_AAT2870_CORE=y
CONFIG_MFD_CROS_EC=y
CONFIG_MFD_CROS_EC_I2C=y
CONFIG_MFD_CROS_EC_SPI=y
CONFIG_MFD_ASIC3=y
# CONFIG_PMIC_DA903X is not set
CONFIG_PMIC_DA9052=y
CONFIG_MFD_DA9052_SPI=y
CONFIG_MFD_DA9052_I2C=y
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9063 is not set
CONFIG_MFD_MC13783=y
CONFIG_MFD_MC13XXX=y
# CONFIG_MFD_MC13XXX_SPI is not set
CONFIG_MFD_MC13XXX_I2C=y
CONFIG_HTC_EGPIO=y
CONFIG_HTC_PASIC3=y
# CONFIG_HTC_I2CPLD is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
CONFIG_MFD_88PM805=y
# CONFIG_MFD_88PM860X is not set
CONFIG_MFD_MAX77686=y
# CONFIG_MFD_MAX77693 is not set
CONFIG_MFD_MAX8907=y
CONFIG_MFD_MAX8925=y
CONFIG_MFD_MAX8997=y
CONFIG_MFD_MAX8998=y
# CONFIG_EZX_PCAP is not set
CONFIG_MFD_VIPERBOARD=y
CONFIG_MFD_RETU=y
CONFIG_MFD_PCF50633=y
CONFIG_PCF50633_ADC=y
CONFIG_PCF50633_GPIO=y
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_SEC_CORE=y
CONFIG_MFD_SI476X_CORE=y
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SMSC is not set
CONFIG_ABX500_CORE=y
CONFIG_AB3100_CORE=y
CONFIG_AB3100_OTP=y
CONFIG_MFD_STMPE=y

#
# STMicroelectronics STMPE Interface Drivers
#
# CONFIG_STMPE_I2C is not set
CONFIG_STMPE_SPI=y
CONFIG_MFD_SYSCON=y
CONFIG_MFD_TI_AM335X_TSCADC=y
CONFIG_MFD_LP8788=y
CONFIG_MFD_OMAP_USB_HOST=y
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
CONFIG_TPS65010=y
CONFIG_TPS6507X=y
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TPS6586X is not set
CONFIG_MFD_TPS65910=y
CONFIG_MFD_TPS65912=y
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
CONFIG_TWL4030_CORE=y
CONFIG_TWL4030_MADC=y
# CONFIG_TWL4030_POWER is not set
CONFIG_MFD_TWL4030_AUDIO=y
CONFIG_TWL6040_CORE=y
CONFIG_MFD_WL1273_CORE=y
CONFIG_MFD_LM3533=y
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
CONFIG_MFD_ARIZONA=y
CONFIG_MFD_ARIZONA_I2C=y
CONFIG_MFD_ARIZONA_SPI=y
# CONFIG_MFD_WM5102 is not set
CONFIG_MFD_WM5110=y
# CONFIG_MFD_WM8997 is not set
# CONFIG_MFD_WM8400 is not set
CONFIG_MFD_WM831X=y
# CONFIG_MFD_WM831X_I2C is not set
CONFIG_MFD_WM831X_SPI=y
CONFIG_MFD_WM8350=y
CONFIG_MFD_WM8350_I2C=y
CONFIG_MFD_WM8994=y
# CONFIG_VEXPRESS_CONFIG is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_DEBUG=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_AD5398 is not set
CONFIG_REGULATOR_ANATOP=y
# CONFIG_REGULATOR_AAT2870 is not set
CONFIG_REGULATOR_AB3100=y
CONFIG_REGULATOR_ARIZONA=y
# CONFIG_REGULATOR_AS3711 is not set
CONFIG_REGULATOR_DA9052=y
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_FAN53555 is not set
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_ISL6271A=y
# CONFIG_REGULATOR_LP3971 is not set
CONFIG_REGULATOR_LP3972=y
CONFIG_REGULATOR_LP872X=y
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LP8788 is not set
# CONFIG_REGULATOR_MAX1586 is not set
CONFIG_REGULATOR_MAX8649=y
# CONFIG_REGULATOR_MAX8660 is not set
CONFIG_REGULATOR_MAX8907=y
CONFIG_REGULATOR_MAX8925=y
CONFIG_REGULATOR_MAX8952=y
CONFIG_REGULATOR_MAX8973=y
# CONFIG_REGULATOR_MAX8997 is not set
# CONFIG_REGULATOR_MAX8998 is not set
# CONFIG_REGULATOR_MAX77686 is not set
CONFIG_REGULATOR_MC13XXX_CORE=y
CONFIG_REGULATOR_MC13783=y
# CONFIG_REGULATOR_MC13892 is not set
CONFIG_REGULATOR_PCF50633=y
CONFIG_REGULATOR_PFUZE100=y
# CONFIG_REGULATOR_S2MPS11 is not set
CONFIG_REGULATOR_S5M8767=y
CONFIG_REGULATOR_TI_ABB=y
# CONFIG_REGULATOR_TPS51632 is not set
CONFIG_REGULATOR_TPS62360=y
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
CONFIG_REGULATOR_TPS6524X=y
# CONFIG_REGULATOR_TPS65910 is not set
CONFIG_REGULATOR_TWL4030=y
# CONFIG_REGULATOR_WM831X is not set
CONFIG_REGULATOR_WM8350=y
CONFIG_REGULATOR_WM8994=y
CONFIG_MEDIA_SUPPORT=y

#
# Multimedia core support
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_RC_SUPPORT is not set
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEO_ADV_DEBUG=y
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_VIDEOBUF_GEN=y
CONFIG_VIDEOBUF_VMALLOC=y
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEO_V4L2_INT_DEVICE=y
# CONFIG_TTPCI_EEPROM is not set

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=y
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
CONFIG_USB_GSPCA=y
# CONFIG_USB_M5602 is not set
CONFIG_USB_STV06XX=y
CONFIG_USB_GL860=y
CONFIG_USB_GSPCA_BENQ=y
# CONFIG_USB_GSPCA_CONEX is not set
CONFIG_USB_GSPCA_CPIA1=y
CONFIG_USB_GSPCA_ETOMS=y
# CONFIG_USB_GSPCA_FINEPIX is not set
# CONFIG_USB_GSPCA_JEILINJ is not set
# CONFIG_USB_GSPCA_JL2005BCD is not set
CONFIG_USB_GSPCA_KINECT=y
CONFIG_USB_GSPCA_KONICA=y
# CONFIG_USB_GSPCA_MARS is not set
CONFIG_USB_GSPCA_MR97310A=y
CONFIG_USB_GSPCA_NW80X=y
CONFIG_USB_GSPCA_OV519=y
CONFIG_USB_GSPCA_OV534=y
CONFIG_USB_GSPCA_OV534_9=y
CONFIG_USB_GSPCA_PAC207=y
CONFIG_USB_GSPCA_PAC7302=y
CONFIG_USB_GSPCA_PAC7311=y
CONFIG_USB_GSPCA_SE401=y
# CONFIG_USB_GSPCA_SN9C2028 is not set
CONFIG_USB_GSPCA_SN9C20X=y
# CONFIG_USB_GSPCA_SONIXB is not set
CONFIG_USB_GSPCA_SONIXJ=y
# CONFIG_USB_GSPCA_SPCA500 is not set
CONFIG_USB_GSPCA_SPCA501=y
CONFIG_USB_GSPCA_SPCA505=y
CONFIG_USB_GSPCA_SPCA506=y
CONFIG_USB_GSPCA_SPCA508=y
CONFIG_USB_GSPCA_SPCA561=y
CONFIG_USB_GSPCA_SPCA1528=y
# CONFIG_USB_GSPCA_SQ905 is not set
CONFIG_USB_GSPCA_SQ905C=y
CONFIG_USB_GSPCA_SQ930X=y
# CONFIG_USB_GSPCA_STK014 is not set
CONFIG_USB_GSPCA_STK1135=y
CONFIG_USB_GSPCA_STV0680=y
CONFIG_USB_GSPCA_SUNPLUS=y
CONFIG_USB_GSPCA_T613=y
# CONFIG_USB_GSPCA_TOPRO is not set
CONFIG_USB_GSPCA_TV8532=y
CONFIG_USB_GSPCA_VC032X=y
CONFIG_USB_GSPCA_VICAM=y
CONFIG_USB_GSPCA_XIRLINK_CIT=y
# CONFIG_USB_GSPCA_ZC3XX is not set
CONFIG_USB_PWC=y
CONFIG_USB_PWC_DEBUG=y
# CONFIG_USB_PWC_INPUT_EVDEV is not set
CONFIG_VIDEO_CPIA2=y
CONFIG_USB_ZR364XX=y
CONFIG_USB_STKWEBCAM=y
CONFIG_USB_S2255=y
CONFIG_USB_SN9C102=y
CONFIG_VIDEO_USBTV=y

#
# Webcam, TV (analog/digital) USB devices
#
# CONFIG_VIDEO_EM28XX is not set
# CONFIG_V4L_PLATFORM_DRIVERS is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
# CONFIG_V4L_TEST_DRIVERS is not set

#
# Supported MMC/SDIO adapters
#
# CONFIG_MEDIA_PARPORT_SUPPORT is not set
CONFIG_CYPRESS_FIRMWARE=y

#
# Media ancillary drivers (tuners, sensors, i2c, frontends)
#
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set

#
# Encoders, decoders, sensors and other helper chips
#

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_TVAUDIO=y
CONFIG_VIDEO_TDA7432=y
# CONFIG_VIDEO_TDA9840 is not set
CONFIG_VIDEO_TEA6415C=y
CONFIG_VIDEO_TEA6420=y
CONFIG_VIDEO_MSP3400=y
# CONFIG_VIDEO_CS5345 is not set
CONFIG_VIDEO_CS53L32A=y
CONFIG_VIDEO_TLV320AIC23B=y
CONFIG_VIDEO_UDA1342=y
CONFIG_VIDEO_WM8775=y
CONFIG_VIDEO_WM8739=y
# CONFIG_VIDEO_VP27SMPX is not set
CONFIG_VIDEO_SONY_BTF_MPX=y

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=y

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=y
CONFIG_VIDEO_ADV7183=y
CONFIG_VIDEO_ADV7604=y
CONFIG_VIDEO_ADV7842=y
CONFIG_VIDEO_BT819=y
CONFIG_VIDEO_BT856=y
CONFIG_VIDEO_BT866=y
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_ML86V7667 is not set
# CONFIG_VIDEO_SAA7110 is not set
# CONFIG_VIDEO_SAA711X is not set
CONFIG_VIDEO_SAA7191=y
# CONFIG_VIDEO_TVP514X is not set
# CONFIG_VIDEO_TVP5150 is not set
CONFIG_VIDEO_TVP7002=y
# CONFIG_VIDEO_TW2804 is not set
CONFIG_VIDEO_TW9903=y
CONFIG_VIDEO_TW9906=y
CONFIG_VIDEO_VPX3220=y

#
# Video and audio decoders
#
# CONFIG_VIDEO_SAA717X is not set
# CONFIG_VIDEO_CX25840 is not set

#
# Video encoders
#
CONFIG_VIDEO_SAA7127=y
# CONFIG_VIDEO_SAA7185 is not set
CONFIG_VIDEO_ADV7170=y
CONFIG_VIDEO_ADV7175=y
# CONFIG_VIDEO_ADV7343 is not set
CONFIG_VIDEO_ADV7393=y
# CONFIG_VIDEO_ADV7511 is not set
CONFIG_VIDEO_AD9389B=y
CONFIG_VIDEO_AK881X=y
# CONFIG_VIDEO_THS8200 is not set

#
# Camera sensor devices
#
CONFIG_VIDEO_OV7640=y
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_OV9650 is not set
# CONFIG_VIDEO_VS6624 is not set
# CONFIG_VIDEO_MT9M032 is not set
# CONFIG_VIDEO_MT9P031 is not set
CONFIG_VIDEO_MT9T001=y
CONFIG_VIDEO_MT9V011=y
CONFIG_VIDEO_MT9V032=y
# CONFIG_VIDEO_TCM825X is not set
CONFIG_VIDEO_SR030PC30=y
CONFIG_VIDEO_NOON010PC30=y
# CONFIG_VIDEO_M5MOLS is not set
CONFIG_VIDEO_S5K6AA=y
CONFIG_VIDEO_S5K4ECGX=y
# CONFIG_VIDEO_SMIAPP is not set
CONFIG_VIDEO_S5C73M3=y

#
# Flash devices
#
# CONFIG_VIDEO_ADP1653 is not set
CONFIG_VIDEO_AS3645A=y
CONFIG_VIDEO_LM3560=y

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=y
# CONFIG_VIDEO_UPD64083 is not set

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_THS7303=y
CONFIG_VIDEO_M52790=y

#
# Sensors used on soc_camera driver
#

#
# Customise DVB Frontends
#
# CONFIG_DVB_AU8522_V4L is not set
# CONFIG_DVB_TUNER_DIB0070 is not set
CONFIG_DVB_TUNER_DIB0090=y

#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=y

#
# Graphics support
#
CONFIG_TEGRA_HOST1X=y
# CONFIG_TEGRA_HOST1X_FIREWALL is not set
CONFIG_DRM=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y

#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=y
# CONFIG_DRM_I2C_SIL164 is not set
CONFIG_DRM_I2C_NXP_TDA998X=y
CONFIG_DRM_EXYNOS=y
CONFIG_DRM_EXYNOS_DMABUF=y
# CONFIG_DRM_EXYNOS_HDMI is not set
# CONFIG_DRM_EXYNOS_VIDI is not set
# CONFIG_DRM_EXYNOS_G2D is not set
# CONFIG_DRM_UDL is not set
CONFIG_DRM_ARMADA=y
CONFIG_DRM_ARMADA_TDA1998X=y
# CONFIG_DRM_RCAR_DU is not set
CONFIG_DRM_SHMOBILE=y
CONFIG_DRM_OMAP=y
CONFIG_DRM_OMAP_NUM_CRTCS=1
# CONFIG_DRM_TILCDC is not set
# CONFIG_DRM_TEGRA is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y

#
# Frame buffer hardware drivers
#
CONFIG_FB_ARMCLCD=y
CONFIG_FB_S1D13XXX=y
CONFIG_FB_VT8500=y
CONFIG_FB_WM8505=y
# CONFIG_FB_WMT_GE_ROPS is not set
CONFIG_FB_TMIO=y
# CONFIG_FB_TMIO_ACCELL is not set
CONFIG_FB_SMSCUFX=y
CONFIG_FB_UDL=y
CONFIG_FB_GOLDFISH=y
# CONFIG_FB_DA8XX is not set
CONFIG_FB_VIRTUAL=y
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MX3 is not set
# CONFIG_FB_BROADSHEET is not set
CONFIG_FB_AUO_K190X=y
CONFIG_FB_AUO_K1900=y
CONFIG_FB_AUO_K1901=y
CONFIG_FB_SIMPLE=y
CONFIG_OMAP2_DSS=y
CONFIG_OMAP2_DSS_DEBUG=y
# CONFIG_OMAP2_DSS_DEBUGFS is not set
# CONFIG_OMAP2_DSS_DPI is not set
CONFIG_OMAP2_DSS_VENC=y
CONFIG_OMAP4_DSS_HDMI=y
CONFIG_OMAP4_DSS_HDMI_AUDIO=y
# CONFIG_OMAP2_DSS_SDI is not set
CONFIG_OMAP2_DSS_DSI=y
CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y

#
# OMAP Display Device Drivers (new device model)
#
CONFIG_DISPLAY_ENCODER_TFP410=y
# CONFIG_DISPLAY_ENCODER_TPD12S015 is not set
CONFIG_DISPLAY_CONNECTOR_DVI=y
CONFIG_DISPLAY_CONNECTOR_HDMI=y
CONFIG_DISPLAY_CONNECTOR_ANALOG_TV=y
CONFIG_DISPLAY_PANEL_DPI=y
CONFIG_DISPLAY_PANEL_DSI_CM=y
CONFIG_DISPLAY_PANEL_SONY_ACX565AKM=y
CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02=y
CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=y
# CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1 is not set
CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1=y
CONFIG_DISPLAY_PANEL_NEC_NL8048HL11=y
CONFIG_EXYNOS_VIDEO=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_L4F00242T03=y
# CONFIG_LCD_LMS283GF05 is not set
CONFIG_LCD_LTV350QV=y
CONFIG_LCD_ILI922X=y
# CONFIG_LCD_ILI9320 is not set
CONFIG_LCD_TDO24M=y
# CONFIG_LCD_VGG2432A4 is not set
# CONFIG_LCD_PLATFORM is not set
CONFIG_LCD_S6E63M0=y
CONFIG_LCD_LD9040=y
# CONFIG_LCD_AMS369FG06 is not set
# CONFIG_LCD_LMS501KF03 is not set
CONFIG_LCD_HX8357=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_ATMEL_PWM is not set
CONFIG_BACKLIGHT_GENERIC=y
# CONFIG_BACKLIGHT_LM3533 is not set
# CONFIG_BACKLIGHT_PWM is not set
# CONFIG_BACKLIGHT_DA9052 is not set
# CONFIG_BACKLIGHT_MAX8925 is not set
CONFIG_BACKLIGHT_WM831X=y
CONFIG_BACKLIGHT_ADP8860=y
CONFIG_BACKLIGHT_ADP8870=y
CONFIG_BACKLIGHT_PCF50633=y
# CONFIG_BACKLIGHT_AAT2870 is not set
CONFIG_BACKLIGHT_LM3630A=y
CONFIG_BACKLIGHT_LM3639=y
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_LP8788 is not set
CONFIG_BACKLIGHT_PANDORA=y
CONFIG_BACKLIGHT_AS3711=y
CONFIG_BACKLIGHT_GPIO=y
# CONFIG_BACKLIGHT_LV5207LP is not set
CONFIG_BACKLIGHT_BD6107=y
# CONFIG_LOGO is not set
CONFIG_FB_SSD1307=y
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_COMPRESS_OFFLOAD=y
CONFIG_SND_JACK=y
# CONFIG_SND_SEQUENCER is not set
CONFIG_SND_OSSEMUL=y
# CONFIG_SND_MIXER_OSS is not set
CONFIG_SND_PCM_OSS=y
# CONFIG_SND_PCM_OSS_PLUGINS is not set
# CONFIG_SND_HRTIMER is not set
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_VERBOSE_PROCFS=y
CONFIG_SND_VERBOSE_PRINTK=y
CONFIG_SND_DEBUG=y
CONFIG_SND_DEBUG_VERBOSE=y
# CONFIG_SND_PCM_XRUN_DEBUG is not set
CONFIG_SND_VMASTER=y
# CONFIG_SND_RAWMIDI_SEQ is not set
# CONFIG_SND_OPL3_LIB_SEQ is not set
# CONFIG_SND_OPL4_LIB_SEQ is not set
# CONFIG_SND_SBAWE_SEQ is not set
# CONFIG_SND_EMU10K1_SEQ is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_SPI=y
CONFIG_SND_AT73C213=y
CONFIG_SND_AT73C213_TARGET_BITRATE=48000
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_USB_UA101=y
# CONFIG_SND_USB_CAIAQ is not set
CONFIG_SND_USB_6FIRE=y
# CONFIG_SND_USB_HIFACE is not set
CONFIG_SND_PCMCIA=y
# CONFIG_SND_VXPOCKET is not set
CONFIG_SND_PDAUDIOCF=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_ATMEL_SOC=y
CONFIG_SND_EP93XX_SOC=y
# CONFIG_SND_DAVINCI_SOC is not set
CONFIG_SND_DESIGNWARE_I2S=y
CONFIG_SND_SOC_FSL_SPDIF=y
CONFIG_SND_IMX_SOC=y
CONFIG_SND_SOC_IMX_SSI=y
CONFIG_SND_SOC_IMX_PCM_FIQ=y
CONFIG_SND_SOC_IMX_PCM_DMA=y
CONFIG_SND_SOC_IMX_AUDMUX=y
CONFIG_SND_SOC_EUKREA_TLV320=y
# CONFIG_SND_SOC_IMX_WM8962 is not set
# CONFIG_SND_SOC_IMX_SGTL5000 is not set
CONFIG_SND_SOC_IMX_SPDIF=y
CONFIG_SND_SOC_IMX_MC13783=y
CONFIG_SND_OMAP_SOC=y
CONFIG_SND_OMAP_SOC_DMIC=y
CONFIG_SND_OMAP_SOC_MCBSP=y
CONFIG_SND_OMAP_SOC_MCPDM=y
CONFIG_SND_OMAP_SOC_HDMI=y
CONFIG_SND_OMAP_SOC_RX51=y
CONFIG_SND_OMAP_SOC_OMAP_TWL4030=y
CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=y
CONFIG_SND_OMAP_SOC_OMAP_HDMI=y
# CONFIG_SND_KIRKWOOD_SOC is not set
CONFIG_SND_MXS_SOC=y
CONFIG_SND_SOC_MXS_SGTL5000=y
CONFIG_SND_SOC_TEGRA=y
# CONFIG_SND_SOC_TEGRA_RT5640 is not set
# CONFIG_SND_SOC_TEGRA_WM8753 is not set
# CONFIG_SND_SOC_TEGRA_WM8903 is not set
CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
CONFIG_SND_SOC_TEGRA_ALC5632=y
CONFIG_SND_SOC_I2C_AND_SPI=y
CONFIG_SND_SOC_ALL_CODECS=y
CONFIG_SND_SOC_ARIZONA=y
CONFIG_SND_SOC_WM_HUBS=y
CONFIG_SND_SOC_WM_ADSP=y
CONFIG_SND_SOC_AB8500_CODEC=y
CONFIG_SND_SOC_AD1836=y
CONFIG_SND_SOC_AD193X=y
CONFIG_SND_SOC_AD73311=y
CONFIG_SND_SOC_ADAU1701=y
CONFIG_SND_SOC_ADAU1373=y
CONFIG_SND_SOC_ADAV80X=y
CONFIG_SND_SOC_ADS117X=y
CONFIG_SND_SOC_AK4104=y
CONFIG_SND_SOC_AK4535=y
CONFIG_SND_SOC_AK4641=y
CONFIG_SND_SOC_AK4642=y
CONFIG_SND_SOC_AK4671=y
CONFIG_SND_SOC_AK5386=y
CONFIG_SND_SOC_ALC5623=y
CONFIG_SND_SOC_ALC5632=y
CONFIG_SND_SOC_CS42L51=y
CONFIG_SND_SOC_CS42L52=y
CONFIG_SND_SOC_CS42L73=y
CONFIG_SND_SOC_CS4270=y
CONFIG_SND_SOC_CS4271=y
CONFIG_SND_SOC_CX20442=y
CONFIG_SND_SOC_JZ4740_CODEC=y
CONFIG_SND_SOC_L3=y
CONFIG_SND_SOC_DA7210=y
CONFIG_SND_SOC_DA7213=y
CONFIG_SND_SOC_DA732X=y
CONFIG_SND_SOC_DA9055=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_DMIC=y
CONFIG_SND_SOC_ISABELLE=y
CONFIG_SND_SOC_LM49453=y
CONFIG_SND_SOC_MAX98088=y
CONFIG_SND_SOC_MAX98090=y
CONFIG_SND_SOC_MAX98095=y
CONFIG_SND_SOC_MAX9850=y
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_PCM1681=y
CONFIG_SND_SOC_PCM1792A=y
CONFIG_SND_SOC_PCM3008=y
CONFIG_SND_SOC_RT5631=y
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_SGTL5000=y
CONFIG_SND_SOC_SI476X=y
CONFIG_SND_SOC_SIGMADSP=y
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SOC_SSM2518=y
CONFIG_SND_SOC_SSM2602=y
CONFIG_SND_SOC_STA32X=y
CONFIG_SND_SOC_STA529=y
CONFIG_SND_SOC_TAS5086=y
CONFIG_SND_SOC_TLV320AIC23=y
CONFIG_SND_SOC_TLV320AIC26=y
CONFIG_SND_SOC_TLV320AIC32X4=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_TLV320DAC33=y
CONFIG_SND_SOC_TWL4030=y
CONFIG_SND_SOC_TWL6040=y
CONFIG_SND_SOC_UDA134X=y
CONFIG_SND_SOC_UDA1380=y
CONFIG_SND_SOC_WL1273=y
CONFIG_SND_SOC_WM0010=y
CONFIG_SND_SOC_WM1250_EV1=y
CONFIG_SND_SOC_WM2000=y
CONFIG_SND_SOC_WM2200=y
CONFIG_SND_SOC_WM5100=y
CONFIG_SND_SOC_WM5110=y
CONFIG_SND_SOC_WM8350=y
CONFIG_SND_SOC_WM8510=y
CONFIG_SND_SOC_WM8523=y
CONFIG_SND_SOC_WM8580=y
CONFIG_SND_SOC_WM8711=y
CONFIG_SND_SOC_WM8727=y
CONFIG_SND_SOC_WM8728=y
CONFIG_SND_SOC_WM8731=y
CONFIG_SND_SOC_WM8737=y
CONFIG_SND_SOC_WM8741=y
CONFIG_SND_SOC_WM8750=y
CONFIG_SND_SOC_WM8753=y
CONFIG_SND_SOC_WM8770=y
CONFIG_SND_SOC_WM8776=y
CONFIG_SND_SOC_WM8782=y
CONFIG_SND_SOC_WM8804=y
CONFIG_SND_SOC_WM8900=y
CONFIG_SND_SOC_WM8903=y
CONFIG_SND_SOC_WM8904=y
CONFIG_SND_SOC_WM8940=y
CONFIG_SND_SOC_WM8955=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SOC_WM8961=y
CONFIG_SND_SOC_WM8962=y
CONFIG_SND_SOC_WM8971=y
CONFIG_SND_SOC_WM8974=y
CONFIG_SND_SOC_WM8978=y
CONFIG_SND_SOC_WM8983=y
CONFIG_SND_SOC_WM8985=y
CONFIG_SND_SOC_WM8988=y
CONFIG_SND_SOC_WM8990=y
CONFIG_SND_SOC_WM8991=y
CONFIG_SND_SOC_WM8993=y
CONFIG_SND_SOC_WM8994=y
CONFIG_SND_SOC_WM8995=y
CONFIG_SND_SOC_WM8996=y
CONFIG_SND_SOC_WM9081=y
CONFIG_SND_SOC_WM9090=y
CONFIG_SND_SOC_LM4857=y
CONFIG_SND_SOC_MAX9768=y
CONFIG_SND_SOC_MAX9877=y
CONFIG_SND_SOC_MC13783=y
CONFIG_SND_SOC_ML26124=y
CONFIG_SND_SOC_TPA6130A2=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SOUND_PRIME=y

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=y
# CONFIG_HID_GENERIC is not set

#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
CONFIG_HID_ACRUX=y
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=y
CONFIG_HID_AUREAL=y
CONFIG_HID_BELKIN=y
# CONFIG_HID_CHERRY is not set
CONFIG_HID_CHICONY=y
# CONFIG_HID_PRODIKEYS is not set
CONFIG_HID_CYPRESS=y
CONFIG_HID_DRAGONRISE=y
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=y
CONFIG_HID_ELECOM=y
# CONFIG_HID_EZKEY is not set
CONFIG_HID_KEYTOUCH=y
CONFIG_HID_KYE=y
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
CONFIG_HID_GYRATION=y
# CONFIG_HID_ICADE is not set
CONFIG_HID_TWINHAN=y
CONFIG_HID_KENSINGTON=y
# CONFIG_HID_LCPOWER is not set
CONFIG_HID_LENOVO_TPKBD=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_LOGITECH_DJ=y
# CONFIG_LOGITECH_FF is not set
# CONFIG_LOGIRUMBLEPAD2_FF is not set
CONFIG_LOGIG940_FF=y
# CONFIG_LOGIWHEELS_FF is not set
CONFIG_HID_MAGICMOUSE=y
CONFIG_HID_MICROSOFT=y
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
CONFIG_HID_ORTEK=y
# CONFIG_HID_PANTHERLORD is not set
CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y
# CONFIG_HID_PICOLCD_FB is not set
# CONFIG_HID_PICOLCD_BACKLIGHT is not set
# CONFIG_HID_PICOLCD_LCD is not set
CONFIG_HID_PICOLCD_LEDS=y
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SAMSUNG is not set
CONFIG_HID_SPEEDLINK=y
CONFIG_HID_STEELSERIES=y
CONFIG_HID_SUNPLUS=y
CONFIG_HID_GREENASIA=y
# CONFIG_GREENASIA_FF is not set
# CONFIG_HID_SMARTJOYPLUS is not set
CONFIG_HID_TIVO=y
CONFIG_HID_TOPSEED=y
CONFIG_HID_THINGM=y
# CONFIG_HID_THRUSTMASTER is not set
CONFIG_HID_WACOM=y
# CONFIG_HID_WIIMOTE is not set
CONFIG_HID_XINMO=y
CONFIG_HID_ZEROPLUS=y
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=y
# CONFIG_HID_SENSOR_HUB is not set

#
# USB HID support
#
# CONFIG_USB_HID is not set
CONFIG_HID_PID=y

#
# USB HID Boot Protocol drivers
#
CONFIG_USB_KBD=y
CONFIG_USB_MOUSE=y

#
# I2C HID support
#
CONFIG_I2C_HID=y
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_MON is not set
CONFIG_USB_WUSB_CBAF=y
CONFIG_USB_WUSB_CBAF_DEBUG=y

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
# CONFIG_USB_EHCI_MXC is not set
CONFIG_USB_EHCI_HCD_OMAP=y
CONFIG_USB_EHCI_HCD_ORION=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=y
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1362_HCD=y
CONFIG_USB_FUSBH200_HCD=y
CONFIG_USB_FOTG210_HCD=y
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_HCD_SSB is not set
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC=y
CONFIG_USB_UHCI_PLATFORM=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
CONFIG_USB_IMX21_HCD=y
CONFIG_USB_HCD_BCMA=y
CONFIG_USB_HCD_SSB=y
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
CONFIG_USB_PRINTER=y
CONFIG_USB_WDM=y
CONFIG_USB_TMC=y

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
# CONFIG_USB_STORAGE is not set

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_DWC3 is not set
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_HOST=y
# CONFIG_USB_CHIPIDEA_DEBUG is not set

#
# USB port drivers
#
CONFIG_USB_USS720=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=y
# CONFIG_USB_SERIAL_AIRCABLE is not set
CONFIG_USB_SERIAL_ARK3116=y
# CONFIG_USB_SERIAL_BELKIN is not set
CONFIG_USB_SERIAL_CH341=y
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
CONFIG_USB_SERIAL_CP210X=y
CONFIG_USB_SERIAL_CYPRESS_M8=y
CONFIG_USB_SERIAL_EMPEG=y
# CONFIG_USB_SERIAL_FTDI_SIO is not set
CONFIG_USB_SERIAL_VISOR=y
CONFIG_USB_SERIAL_IPAQ=y
CONFIG_USB_SERIAL_IR=y
CONFIG_USB_SERIAL_EDGEPORT=y
CONFIG_USB_SERIAL_EDGEPORT_TI=y
# CONFIG_USB_SERIAL_F81232 is not set
CONFIG_USB_SERIAL_GARMIN=y
# CONFIG_USB_SERIAL_IPW is not set
# CONFIG_USB_SERIAL_IUU is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
CONFIG_USB_SERIAL_KEYSPAN=y
# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
CONFIG_USB_SERIAL_KLSI=y
CONFIG_USB_SERIAL_KOBIL_SCT=y
CONFIG_USB_SERIAL_MCT_U232=y
# CONFIG_USB_SERIAL_METRO is not set
# CONFIG_USB_SERIAL_MOS7720 is not set
CONFIG_USB_SERIAL_MOS7840=y
CONFIG_USB_SERIAL_NAVMAN=y
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_OTI6858 is not set
CONFIG_USB_SERIAL_QCAUX=y
# CONFIG_USB_SERIAL_QUALCOMM is not set
CONFIG_USB_SERIAL_SPCP8X5=y
# CONFIG_USB_SERIAL_SAFE is not set
CONFIG_USB_SERIAL_SIERRAWIRELESS=y
CONFIG_USB_SERIAL_SYMBOL=y
# CONFIG_USB_SERIAL_TI is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
CONFIG_USB_SERIAL_XIRCOM=y
CONFIG_USB_SERIAL_WWAN=y
CONFIG_USB_SERIAL_OPTION=y
# CONFIG_USB_SERIAL_OMNINET is not set
CONFIG_USB_SERIAL_OPTICON=y
CONFIG_USB_SERIAL_XSENS_MT=y
CONFIG_USB_SERIAL_WISHBONE=y
# CONFIG_USB_SERIAL_ZTE is not set
CONFIG_USB_SERIAL_SSU100=y
# CONFIG_USB_SERIAL_QT2 is not set
# CONFIG_USB_SERIAL_DEBUG is not set

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=y
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
CONFIG_USB_SEVSEG=y
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
CONFIG_USB_LED=y
CONFIG_USB_CYPRESS_CY7C63=y
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
CONFIG_USB_SISUSBVGA=y
CONFIG_USB_LD=y
CONFIG_USB_TRANCEVIBRATOR=y
CONFIG_USB_IOWARRIOR=y
CONFIG_USB_TEST=y
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
CONFIG_USB_ISIGHTFW=y
CONFIG_USB_YUREX=y
CONFIG_USB_EZUSB_FX2=y
# CONFIG_USB_HSIC_USB3503 is not set

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_OMAP_CONTROL_USB=y
# CONFIG_OMAP_USB3 is not set
CONFIG_AM335X_CONTROL_USB=y
CONFIG_AM335X_PHY_USB=y
# CONFIG_SAMSUNG_USB2PHY is not set
# CONFIG_SAMSUNG_USB3PHY is not set
# CONFIG_USB_GPIO_VBUS is not set
CONFIG_USB_ISP1301=y
# CONFIG_USB_MXS_PHY is not set
CONFIG_USB_RCAR_PHY=y
CONFIG_USB_RCAR_GEN2_PHY=y
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# CONFIG_USB_GADGET is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set
CONFIG_MMC_CLKGATE=y

#
# MMC/SD/SDIO Card Drivers
#
# CONFIG_MMC_BLOCK is not set
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
# CONFIG_MMC_SDHCI_TEGRA is not set
CONFIG_MMC_SDHCI_PXAV3=y
CONFIG_MMC_SDHCI_PXAV2=y
CONFIG_MMC_OMAP=y
# CONFIG_MMC_OMAP_HS is not set
# CONFIG_MMC_MXC is not set
CONFIG_MMC_MVSDIO=y
CONFIG_MMC_TMIO_CORE=y
CONFIG_MMC_TMIO=y
# CONFIG_MMC_DW is not set
# CONFIG_MMC_VUB300 is not set
CONFIG_MMC_USHC=y
CONFIG_MMC_WMT=y
CONFIG_MEMSTICK=y
CONFIG_MEMSTICK_DEBUG=y

#
# MemoryStick drivers
#
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
# CONFIG_MSPRO_BLOCK is not set
CONFIG_MS_BLOCK=y

#
# MemoryStick Host Controller Drivers
#
CONFIG_LEDS_GPIO_REGISTER=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y

#
# LED drivers
#
CONFIG_LEDS_ATMEL_PWM=y
CONFIG_LEDS_LM3530=y
CONFIG_LEDS_LM3533=y
CONFIG_LEDS_LM3642=y
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_LP5521=y
# CONFIG_LEDS_LP5523 is not set
# CONFIG_LEDS_LP5562 is not set
CONFIG_LEDS_LP8501=y
CONFIG_LEDS_LP8788=y
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA963X is not set
CONFIG_LEDS_PCA9685=y
CONFIG_LEDS_WM831X_STATUS=y
# CONFIG_LEDS_WM8350 is not set
CONFIG_LEDS_DA9052=y
CONFIG_LEDS_DAC124S085=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2802=y
CONFIG_LEDS_LT3593=y
# CONFIG_LEDS_MC13783 is not set
CONFIG_LEDS_ASIC3=y
CONFIG_LEDS_TCA6507=y
CONFIG_LEDS_MAX8997=y
CONFIG_LEDS_LM355x=y
# CONFIG_LEDS_OT200 is not set
CONFIG_LEDS_BLINKM=y

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
# CONFIG_LEDS_TRIGGER_ONESHOT is not set
# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
# CONFIG_LEDS_TRIGGER_GPIO is not set
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
# CONFIG_LEDS_TRIGGER_CAMERA is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_EDAC is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set

#
# RTC interfaces
#
# CONFIG_RTC_INTF_SYSFS is not set
# CONFIG_RTC_INTF_PROC is not set
CONFIG_RTC_INTF_DEV=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_DRV_TEST=y

#
# I2C RTC drivers
#
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_DS1374=y
CONFIG_RTC_DRV_DS1672=y
# CONFIG_RTC_DRV_DS3232 is not set
CONFIG_RTC_DRV_LP8788=y
CONFIG_RTC_DRV_MAX6900=y
CONFIG_RTC_DRV_MAX8907=y
CONFIG_RTC_DRV_MAX8925=y
CONFIG_RTC_DRV_MAX8998=y
# CONFIG_RTC_DRV_MAX8997 is not set
CONFIG_RTC_DRV_MAX77686=y
# CONFIG_RTC_DRV_RS5C372 is not set
CONFIG_RTC_DRV_ISL1208=y
# CONFIG_RTC_DRV_ISL12022 is not set
CONFIG_RTC_DRV_X1205=y
CONFIG_RTC_DRV_PCF2127=y
CONFIG_RTC_DRV_PCF8523=y
CONFIG_RTC_DRV_PCF8563=y
# CONFIG_RTC_DRV_PCF8583 is not set
CONFIG_RTC_DRV_M41T80=y
CONFIG_RTC_DRV_M41T80_WDT=y
# CONFIG_RTC_DRV_BQ32K is not set
CONFIG_RTC_DRV_TWL4030=y
CONFIG_RTC_DRV_TPS65910=y
# CONFIG_RTC_DRV_S35390A is not set
CONFIG_RTC_DRV_FM3130=y
CONFIG_RTC_DRV_RX8581=y
CONFIG_RTC_DRV_RX8025=y
CONFIG_RTC_DRV_EM3027=y
# CONFIG_RTC_DRV_RV3029C2 is not set
# CONFIG_RTC_DRV_S5M is not set

#
# SPI RTC drivers
#
CONFIG_RTC_DRV_M41T93=y
# CONFIG_RTC_DRV_M41T94 is not set
CONFIG_RTC_DRV_DS1305=y
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
CONFIG_RTC_DRV_R9701=y
CONFIG_RTC_DRV_RS5C348=y
CONFIG_RTC_DRV_DS3234=y
# CONFIG_RTC_DRV_PCF2123 is not set
CONFIG_RTC_DRV_RX4581=y

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_CMOS=y
CONFIG_RTC_DRV_DS1286=y
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
CONFIG_RTC_DRV_DS1742=y
CONFIG_RTC_DRV_DA9052=y
# CONFIG_RTC_DRV_STK17TA8 is not set
CONFIG_RTC_DRV_M48T86=y
CONFIG_RTC_DRV_M48T35=y
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
CONFIG_RTC_DRV_BQ4802=y
CONFIG_RTC_DRV_RP5C01=y
CONFIG_RTC_DRV_V3020=y
# CONFIG_RTC_DRV_DS2404 is not set
CONFIG_RTC_DRV_WM831X=y
CONFIG_RTC_DRV_WM8350=y
# CONFIG_RTC_DRV_PCF50633 is not set
# CONFIG_RTC_DRV_AB3100 is not set

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_IMXDI=y
CONFIG_RTC_DRV_OMAP=y
# CONFIG_RTC_DRV_PL030 is not set
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_VT8500=y
CONFIG_RTC_DRV_MV=y
# CONFIG_RTC_DRV_MC13XXX is not set
CONFIG_RTC_DRV_TEGRA=y
CONFIG_RTC_DRV_MXC=y
CONFIG_RTC_DRV_SNVS=y
# CONFIG_RTC_DRV_MOXART is not set

#
# HID Sensor RTC drivers
#
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_AMBA_PL08X=y
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
CONFIG_MV_XOR=y
CONFIG_MX3_IPU=y
CONFIG_MX3_IPU_IRQS=4
CONFIG_TEGRA20_APB_DMA=y
CONFIG_TIMB_DMA=y
CONFIG_TI_EDMA=y
CONFIG_PL330_DMA=y
CONFIG_IMX_SDMA=y
# CONFIG_IMX_DMA is not set
# CONFIG_MXS_DMA is not set
CONFIG_DMA_OMAP=y
# CONFIG_TI_CPPI41 is not set
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_OF=y

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
CONFIG_DMATEST=y
CONFIG_DMA_ENGINE_RAID=y
CONFIG_AUXDISPLAY=y
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=y
# CONFIG_UIO_DMEM_GENIRQ is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO=y

#
# Virtio drivers
#
CONFIG_VIRTIO_BALLOON=y
# CONFIG_VIRTIO_MMIO is not set

#
# Microsoft Hyper-V guest support
#
CONFIG_STAGING=y
# CONFIG_ECHO is not set
CONFIG_PANEL=y
CONFIG_PANEL_PARPORT=0
CONFIG_PANEL_PROFILE=5
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_RTS5139 is not set
# CONFIG_TRANZPORT is not set
CONFIG_LINE6_USB=y
# CONFIG_LINE6_USB_IMPULSE_RESPONSE is not set
# CONFIG_USB_SERIAL_QUATECH2 is not set

#
# IIO staging drivers
#

#
# Accelerometers
#
CONFIG_ADIS16201=y
# CONFIG_ADIS16203 is not set
CONFIG_ADIS16204=y
CONFIG_ADIS16209=y
CONFIG_ADIS16220=y
CONFIG_ADIS16240=y
# CONFIG_LIS3L02DQ is not set
CONFIG_SCA3000=y

#
# Analog to digital converters
#
CONFIG_AD7291=y
CONFIG_AD7606=y
CONFIG_AD7606_IFACE_PARALLEL=y
CONFIG_AD7606_IFACE_SPI=y
CONFIG_AD799X=y
CONFIG_AD799X_RING_BUFFER=y
CONFIG_AD7780=y
# CONFIG_AD7816 is not set
CONFIG_AD7192=y
# CONFIG_AD7280 is not set
# CONFIG_LPC32XX_ADC is not set
# CONFIG_MXS_LRADC is not set
CONFIG_SPEAR_ADC=y

#
# Analog digital bi-direction converters
#
CONFIG_ADT7316=y
# CONFIG_ADT7316_SPI is not set
CONFIG_ADT7316_I2C=y

#
# Capacitance to digital converters
#
# CONFIG_AD7150 is not set
CONFIG_AD7152=y
CONFIG_AD7746=y

#
# Direct Digital Synthesis
#
CONFIG_AD5930=y
CONFIG_AD9832=y
CONFIG_AD9834=y
CONFIG_AD9850=y
# CONFIG_AD9852 is not set
CONFIG_AD9910=y
CONFIG_AD9951=y

#
# Digital gyroscope sensors
#
CONFIG_ADIS16060=y

#
# Network Analyzer, Impedance Converters
#
CONFIG_AD5933=y

#
# Light sensors
#
# CONFIG_SENSORS_ISL29018 is not set
# CONFIG_SENSORS_ISL29028 is not set
# CONFIG_TSL2583 is not set
CONFIG_TSL2x7x=y

#
# Magnetometer sensors
#
# CONFIG_SENSORS_HMC5843 is not set

#
# Active energy metering IC
#
CONFIG_ADE7753=y
# CONFIG_ADE7754 is not set
CONFIG_ADE7758=y
# CONFIG_ADE7759 is not set
# CONFIG_ADE7854 is not set

#
# Resolver to digital converters
#
# CONFIG_AD2S90 is not set
# CONFIG_AD2S1200 is not set
CONFIG_AD2S1210=y

#
# Triggers - standalone
#
# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set
CONFIG_IIO_DUMMY_EVGEN=y
CONFIG_IIO_SIMPLE_DUMMY=y
CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y
CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y
# CONFIG_ZSMALLOC is not set
CONFIG_FT1000=y

#
# Speakup console speech
#
# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
CONFIG_MFD_NVEC=y
# CONFIG_KEYBOARD_NVEC is not set
# CONFIG_SERIO_NVEC_PS2 is not set
# CONFIG_NVEC_POWER is not set
CONFIG_NVEC_PAZ00=y
# CONFIG_STAGING_MEDIA is not set

#
# Android
#
# CONFIG_ANDROID is not set
# CONFIG_CED1401 is not set
CONFIG_DRM_IMX=y
CONFIG_DRM_IMX_FB_HELPER=y
# CONFIG_DRM_IMX_PARALLEL_DISPLAY is not set
CONFIG_DRM_IMX_TVE=y
CONFIG_DRM_IMX_LDB=y
CONFIG_DGRP=y
CONFIG_MTD_SPINAND_MT29F=y
CONFIG_MTD_SPINAND_ONDIEECC=y
# CONFIG_USB_DWC2 is not set
# CONFIG_DGAP is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Common Clock Framework
#
CONFIG_COMMON_CLK_DEBUG=y
CONFIG_COMMON_CLK_WM831X=y
CONFIG_COMMON_CLK_MAX77686=y
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_S2MPS11 is not set
CONFIG_CLK_TWL6040=y
CONFIG_COMMON_CLK_KEYSTONE=y
CONFIG_MVEBU_CLK_COMMON=y
CONFIG_MVEBU_CLK_CPU=y
CONFIG_ARMADA_370_CLK=y

#
# Hardware Spinlock drivers
#
CONFIG_CLKSRC_OF=y
CONFIG_CLKSRC_MMIO=y
CONFIG_DW_APB_TIMER=y
CONFIG_DW_APB_TIMER_OF=y
CONFIG_ARMADA_370_XP_TIMER=y
CONFIG_SUN4I_TIMER=y
CONFIG_VT8500_TIMER=y
# CONFIG_CLKSRC_EFM32 is not set
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GLOBAL_TIMER=y
CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
CONFIG_VF_PIT_TIMER=y
CONFIG_MAILBOX=y
CONFIG_PL320_MBOX=y
CONFIG_OMAP_MBOX=y
CONFIG_OMAP2PLUS_MBOX=y
CONFIG_OMAP_MBOX_KFIFO_SIZE=256
CONFIG_IOMMU_SUPPORT=y
CONFIG_OF_IOMMU=y
# CONFIG_OMAP_IOMMU is not set
# CONFIG_SHMOBILE_IOMMU is not set

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
CONFIG_STE_MODEM_RPROC=y

#
# Rpmsg drivers
#
# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
CONFIG_MEMORY=y
# CONFIG_TI_EMIF is not set
CONFIG_MVEBU_DEVBUS=y
# CONFIG_TEGRA30_MC is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2

#
# Accelerometers
#
CONFIG_BMA180=y
CONFIG_IIO_ST_ACCEL_3AXIS=y
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=y
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=y
# CONFIG_KXSD9 is not set

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=y
CONFIG_AD7266=y
CONFIG_AD7298=y
CONFIG_AD7476=y
# CONFIG_AD7791 is not set
CONFIG_AD7793=y
CONFIG_AD7887=y
# CONFIG_AD7923 is not set
CONFIG_EXYNOS_ADC=y
# CONFIG_LP8788_ADC is not set
CONFIG_MAX1363=y
# CONFIG_MCP320X is not set
CONFIG_MCP3422=y
# CONFIG_NAU7802 is not set
CONFIG_TI_ADC081C=y
CONFIG_TI_AM335X_ADC=y
CONFIG_TWL6030_GPADC=y
CONFIG_VIPERBOARD_ADC=y

#
# Amplifiers
#
CONFIG_AD8366=y

#
# Hid Sensor IIO Common
#
CONFIG_IIO_ST_SENSORS_I2C=y
CONFIG_IIO_ST_SENSORS_SPI=y
CONFIG_IIO_ST_SENSORS_CORE=y

#
# Digital to analog converters
#
CONFIG_AD5064=y
# CONFIG_AD5360 is not set
CONFIG_AD5380=y
CONFIG_AD5421=y
# CONFIG_AD5446 is not set
CONFIG_AD5449=y
CONFIG_AD5504=y
# CONFIG_AD5624R_SPI is not set
# CONFIG_AD5686 is not set
CONFIG_AD5755=y
# CONFIG_AD5764 is not set
CONFIG_AD5791=y
# CONFIG_AD7303 is not set
# CONFIG_MAX517 is not set
CONFIG_MCP4725=y

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=y

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=y

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=y
# CONFIG_ADIS16130 is not set
CONFIG_ADIS16136=y
# CONFIG_ADIS16260 is not set
CONFIG_ADXRS450=y
CONFIG_IIO_ST_GYRO_3AXIS=y
CONFIG_IIO_ST_GYRO_I2C_3AXIS=y
CONFIG_IIO_ST_GYRO_SPI_3AXIS=y
CONFIG_ITG3200=y

#
# Inertial measurement units
#
CONFIG_ADIS16400=y
# CONFIG_ADIS16480 is not set
CONFIG_IIO_ADIS_LIB=y
CONFIG_IIO_ADIS_LIB_BUFFER=y
CONFIG_INV_MPU6050_IIO=y

#
# Light sensors
#
# CONFIG_ADJD_S311 is not set
# CONFIG_APDS9300 is not set
# CONFIG_CM36651 is not set
CONFIG_GP2AP020A00F=y
# CONFIG_SENSORS_LM3533 is not set
CONFIG_TCS3472=y
CONFIG_SENSORS_TSL2563=y
CONFIG_TSL4531=y
# CONFIG_VCNL4000 is not set

#
# Magnetometer sensors
#
CONFIG_AK8975=y
CONFIG_MAG3110=y
CONFIG_IIO_ST_MAGN_3AXIS=y
CONFIG_IIO_ST_MAGN_I2C_3AXIS=y
CONFIG_IIO_ST_MAGN_SPI_3AXIS=y

#
# Triggers - standalone
#
CONFIG_IIO_INTERRUPT_TRIGGER=y
CONFIG_IIO_SYSFS_TRIGGER=y

#
# Pressure sensors
#
CONFIG_IIO_ST_PRESS=y
CONFIG_IIO_ST_PRESS_I2C=y
CONFIG_IIO_ST_PRESS_SPI=y

#
# Temperature sensors
#
CONFIG_TMP006=y
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_PWM_IMX=y
CONFIG_PWM_PCA9685=y
# CONFIG_PWM_TEGRA is not set
# CONFIG_PWM_TIECAP is not set
CONFIG_PWM_TIEHRPWM=y
CONFIG_PWM_TIPWMSS=y
# CONFIG_PWM_TWL is not set
# CONFIG_PWM_TWL_LED is not set
# CONFIG_PWM_VT8500 is not set
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
# CONFIG_RESET_CONTROLLER is not set
# CONFIG_FMC is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
CONFIG_OMAP_USB2=y
# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
CONFIG_POWERCAP=y

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
CONFIG_EXT2_FS_XIP=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
CONFIG_EXT3_FS_SECURITY=y
# CONFIG_EXT4_FS is not set
CONFIG_FS_XIP=y
CONFIG_JBD=y
CONFIG_JBD_DEBUG=y
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=y
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=y
# CONFIG_JFS_POSIX_ACL is not set
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
CONFIG_JFS_STATISTICS=y
# CONFIG_XFS_FS is not set
CONFIG_GFS2_FS=y
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
CONFIG_BTRFS_FS_CHECK_INTEGRITY=y
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
CONFIG_BTRFS_DEBUG=y
# CONFIG_BTRFS_ASSERT is not set
CONFIG_NILFS2_FS=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
CONFIG_QUOTA=y
# CONFIG_PRINT_QUOTA_WARNING is not set
CONFIG_QUOTA_DEBUG=y
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
# CONFIG_AUTOFS4_FS is not set
CONFIG_FUSE_FS=y
CONFIG_CUSE=y

#
# Caches
#
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
CONFIG_FSCACHE_HISTOGRAM=y
# CONFIG_FSCACHE_DEBUG is not set
# CONFIG_FSCACHE_OBJECT_LIST is not set
CONFIG_CACHEFILES=y
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_HISTOGRAM is not set

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=y
# CONFIG_JOLIET is not set
CONFIG_ZISOFS=y
CONFIG_UDF_FS=y
CONFIG_UDF_NLS=y

#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_VMCORE is not set
# CONFIG_PROC_SYSCTL is not set
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
# CONFIG_HUGETLB_PAGE is not set
CONFIG_CONFIGFS_FS=y
CONFIG_MISC_FILESYSTEMS=y
CONFIG_ADFS_FS=y
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
CONFIG_HFSPLUS_FS=y
# CONFIG_HFSPLUS_FS_POSIX_ACL is not set
CONFIG_BEFS_FS=y
CONFIG_BEFS_DEBUG=y
CONFIG_BFS_FS=y
CONFIG_EFS_FS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_WRITEBUFFER is not set
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
CONFIG_JFFS2_FS_POSIX_ACL=y
CONFIG_JFFS2_FS_SECURITY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
# CONFIG_JFFS2_ZLIB is not set
# CONFIG_JFFS2_LZO is not set
# CONFIG_JFFS2_RTIME is not set
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UBIFS_FS_LZO is not set
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_LOGFS=y
CONFIG_CRAMFS=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
# CONFIG_SQUASHFS_ZLIB is not set
CONFIG_SQUASHFS_LZO=y
# CONFIG_SQUASHFS_XZ is not set
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
CONFIG_MINIX_FS=y
# CONFIG_OMFS_FS is not set
CONFIG_HPFS_FS=y
CONFIG_QNX4FS_FS=y
CONFIG_QNX6FS_FS=y
# CONFIG_QNX6FS_DEBUG is not set
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_BLOCK=y
# CONFIG_ROMFS_BACKED_BY_MTD is not set
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
CONFIG_ROMFS_ON_BLOCK=y
CONFIG_PSTORE=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_FTRACE=y
CONFIG_PSTORE_RAM=y
CONFIG_SYSV_FS=y
CONFIG_UFS_FS=y
CONFIG_UFS_FS_WRITE=y
# CONFIG_UFS_DEBUG is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_STAT_FS is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
# CONFIG_F2FS_FS_SECURITY is not set
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=y
CONFIG_NLS_CODEPAGE_855=y
CONFIG_NLS_CODEPAGE_857=y
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
# CONFIG_NLS_CODEPAGE_864 is not set
CONFIG_NLS_CODEPAGE_865=y
CONFIG_NLS_CODEPAGE_866=y
CONFIG_NLS_CODEPAGE_869=y
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
CONFIG_NLS_CODEPAGE_949=y
CONFIG_NLS_CODEPAGE_874=y
# CONFIG_NLS_ISO8859_8 is not set
CONFIG_NLS_CODEPAGE_1250=y
CONFIG_NLS_CODEPAGE_1251=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
# CONFIG_NLS_ISO8859_3 is not set
CONFIG_NLS_ISO8859_4=y
CONFIG_NLS_ISO8859_5=y
CONFIG_NLS_ISO8859_6=y
CONFIG_NLS_ISO8859_7=y
CONFIG_NLS_ISO8859_9=y
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
CONFIG_NLS_KOI8_R=y
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_MAC_ROMAN=y
# CONFIG_NLS_MAC_CELTIC is not set
CONFIG_NLS_MAC_CENTEURO=y
CONFIG_NLS_MAC_CROATIAN=y
# CONFIG_NLS_MAC_CYRILLIC is not set
CONFIG_NLS_MAC_GAELIC=y
CONFIG_NLS_MAC_GREEK=y
CONFIG_NLS_MAC_ICELAND=y
CONFIG_NLS_MAC_INUIT=y
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
CONFIG_NLS_UTF8=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4

#
# Compile-time checks and compiler options
#
# CONFIG_DEBUG_INFO is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_READABLE_ASM=y
CONFIG_UNUSED_SYMBOLS=y
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_FRAME_POINTER=y
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_MAGIC_SYSRQ is not set
CONFIG_DEBUG_KERNEL=y

#
# Memory Debugging
#
CONFIG_DEBUG_PAGEALLOC=y
CONFIG_WANT_PAGE_DEBUG_FLAGS=y
CONFIG_PAGE_POISONING=y
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=400
CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUG_VM=y
# CONFIG_DEBUG_VM_RB is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
CONFIG_DEBUG_PER_CPU_MAPS=y
CONFIG_DEBUG_HIGHMEM=y
# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Lockups and Hangs
#
CONFIG_LOCKUP_DETECTOR=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHEDSTATS is not set
CONFIG_TIMER_STATS=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
# CONFIG_DEBUG_RT_MUTEXES is not set
CONFIG_RT_MUTEX_TESTER=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
CONFIG_LOCKDEP=y
# CONFIG_LOCK_STAT is not set
CONFIG_DEBUG_LOCKDEP=y
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
CONFIG_DEBUG_LOCKING_API_SELFTESTS=y
CONFIG_TRACE_IRQFLAGS=y
CONFIG_STACKTRACE=y
CONFIG_DEBUG_KOBJECT=y
CONFIG_DEBUG_WRITECOUNT=y
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_SG is not set
CONFIG_DEBUG_NOTIFIERS=y
CONFIG_DEBUG_CREDENTIALS=y

#
# RCU Debugging
#
# CONFIG_PROVE_RCU is not set
# CONFIG_SPARSE_RCU_POINTER is not set
CONFIG_RCU_TORTURE_TEST=y
CONFIG_RCU_TORTURE_TEST_RUNNABLE=y
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_CPU_STALL_INFO=y
# CONFIG_RCU_TRACE is not set
CONFIG_DEBUG_BLOCK_EXT_DEVT=y
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACER_MAX_TRACE=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_RING_BUFFER_ALLOW_SWAP=y
CONFIG_TRACING=y
CONFIG_GENERIC_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
CONFIG_FUNCTION_TRACER=y
CONFIG_FUNCTION_GRAPH_TRACER=y
CONFIG_IRQSOFF_TRACER=y
CONFIG_SCHED_TRACER=y
CONFIG_FTRACE_SYSCALLS=y
CONFIG_TRACER_SNAPSHOT=y
CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_PROBE_EVENTS is not set
# CONFIG_DYNAMIC_FTRACE is not set
CONFIG_FUNCTION_PROFILER=y
CONFIG_FTRACE_SELFTEST=y
CONFIG_FTRACE_STARTUP_TEST=y
CONFIG_EVENT_TRACE_TEST_SYSCALLS=y
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set

#
# Runtime Testing
#
CONFIG_LKDTM=y
CONFIG_TEST_LIST_SORT=y
# CONFIG_BACKTRACE_SELF_TEST is not set
CONFIG_RBTREE_TEST=y
# CONFIG_ATOMIC64_SELFTEST is not set
CONFIG_TEST_STRING_HELPERS=y
# CONFIG_TEST_KSTRTOX is not set
CONFIG_DMA_API_DEBUG=y
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_STRICT_DEVMEM=y
CONFIG_OLD_MCOUNT=y
# CONFIG_DEBUG_USER is not set
# CONFIG_DEBUG_LL is not set
CONFIG_DEBUG_IMX_UART_PORT=1
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
# CONFIG_DEBUG_UART_PL01X is not set
# CONFIG_DEBUG_UART_8250 is not set
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
# CONFIG_OC_ETM is not set
# CONFIG_PID_IN_CONTEXTIDR is not set

#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
# CONFIG_SECURITY is not set
CONFIG_SECURITYFS=y
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_XOR_BLOCKS=y
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_PCOMP=y
CONFIG_CRYPTO_PCOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_WORKQUEUE=y
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_AUTHENC=y

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SEQIV=y

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_LRW is not set
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=y

#
# Hash modes
#
# CONFIG_CRYPTO_CMAC is not set
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
CONFIG_CRYPTO_VMAC=y

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_MD4=y
# CONFIG_CRYPTO_MD5 is not set
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_RMD128=y
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_RMD256=y
CONFIG_CRYPTO_RMD320=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_ARM=y
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_SHA512 is not set
CONFIG_CRYPTO_TGR192=y
CONFIG_CRYPTO_WP512=y

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
# CONFIG_CRYPTO_KHAZAD is not set
CONFIG_CRYPTO_SALSA20=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_ZLIB=y
# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_LZ4 is not set
CONFIG_CRYPTO_LZ4HC=y

#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
# CONFIG_CRYPTO_HW is not set
CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_BITREVERSE=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IO=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
# CONFIG_CRC_CCITT is not set
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=y
# CONFIG_CRC8 is not set
CONFIG_RANDOM32_SELFTEST=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
# CONFIG_XZ_DEC is not set
# CONFIG_XZ_DEC_BCJ is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_REED_SOLOMON_DEC16=y
CONFIG_BCH=y
CONFIG_BCH_CONST_PARAMS=y
CONFIG_BTREE=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_DMA=y
# CONFIG_CPUMASK_OFFSTACK is not set
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
# CONFIG_AVERAGE is not set
CONFIG_CORDIC=y
# CONFIG_DDR is not set
CONFIG_VIRTUALIZATION=y

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Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Felipe Balbi]

[-- Attachment #1.1: Type: text/plain, Size: 1642 bytes --]

On Thu, Jan 09, 2014 at 12:40:59PM -0600, Felipe Balbi wrote:
> Hi,
> 
> On Thu, Jan 09, 2014 at 11:22:17AM -0600, Felipe Balbi wrote:
> > > Changes compared to previous version:
> > > - Dropped any changes to generic clock drivers, as it seems impossible
> > >   to agree anything in short term, this means the patch set shrank in
> > >   size from 49 patches to 40 (first 9 patches were dropped).
> > > - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
> > >   to drivers/clk/ti, and made the modifications needed to the TI version
> > >   of the clock drivers only (based on discussions with Mike, this is fine)
> > > - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
> > >   with any generic implementation we might have at some point, migrating
> > >   this to the generic version should be easy enough also.
> > > - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
> > >   versions and resulted into an orphan clock node
> > > - Fixed compile problem for omap5 only build reported by Felipe
> > > - Fixed a couple of sparse warnings
> > > - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
> > >   instead of __raw_readl / __raw_writel
> > 
> > just caught a build breakage. .config attached
> 
> forgot to give you build errors found, they're here:
> http://hastebin.com/jibuyuyoto.vbs
> 
> Also, just caught another build breakage:
> 
> http://hastebin.com/reravalupe.vbs
> 
> .config attached

hmm, quite a few configs are failing, seems like have DRA7xx without
OMAP4 or OMAP5 breaks builds.

-- 
balbi

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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Nishanth Menon]

On 01/09/2014 08:00 AM, Tero Kristo wrote:
> Hi,
> 
> So, bad luck number release for this, as v12 wasn't sufficient still.
> 
> Changes compared to previous version:
> - Dropped any changes to generic clock drivers, as it seems impossible
>   to agree anything in short term, this means the patch set shrank in
>   size from 49 patches to 40 (first 9 patches were dropped).
> - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
>   to drivers/clk/ti, and made the modifications needed to the TI version
>   of the clock drivers only (based on discussions with Mike, this is fine)
> - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
>   with any generic implementation we might have at some point, migrating
>   this to the generic version should be easy enough also.
> - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
>   versions and resulted into an orphan clock node
> - Fixed compile problem for omap5 only build reported by Felipe
> - Fixed a couple of sparse warnings
> - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
>   instead of __raw_readl / __raw_writel
> 
> Testing done:
> - omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
> - omap4-panda-es: boot / suspend-resume (RET)
> - omap5-uevm: boot
> - am335x-bone: boot
> - dra7-evm: boot
> 
> Maintainer friendly branches also available:
> 
> tree: https://github.com/t-kristo/linux-pm.git
> 
> clk driver only (Mike): clk-next-dt-clks-v13
> DTS data only (Benoit): dts_for_3.14-dt-clks-v13
> full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13
> 
> -Tero
> 

Maintainer branches conflicts (using 3.13-rc7-dt-clks-v13):
=============================
Conflict resolution during rebase to maintainer's -14 branches:

1. (trivial) Against mike's clk-next dbdf6ff Merge branch
'clk-next-unregister' into clk-next

Could not apply 2edf7ad... CLK: TI: add DT alias clock registration
mechanism
conflict drivers/clk/Makefile (trivial fix)

2. (manual, but changes are easy) Against Tony's omap-for-v3.14/be
fc6ca98 ARM: OMAP: debug-leds: raw read and write endian fix

ARM: OMAP2+: clock: use driver API instead of direct memory read/write

conflicts with be changes on Tony's be branch.
commit 80f304dd2360cf5d50953c4eb4e902536f6a1263
    ARM: OMAP2+: raw read and write endian fix

Conflict:
arch/arm/mach-omap2/clkt_clksel.c
arch/arm/mach-omap2/clkt_dpll.c
arch/arm/mach-omap2/clkt_iclk.c
arch/arm/mach-omap2/clock.c
arch/arm/mach-omap2/clock36xx.c
arch/arm/mach-omap2/dpll3xxx.c
arch/arm/mach-omap2/dpll44xx.c

Both change raw_readls -> should now be just clk api instead which
already does readl_relaxed etc.. If Tony feels like, then we should
probably post a branch based on 'be' branch for easy merge.

3. I could not detect any merge conflict against Benoit's queued up
series (but maybe he has'nt pushed everything to remote tree)..


Patch verification report:
==========================
Report: http://pastebin.mozilla.org/3976492


* sparse warning added in [PATCH 06/40] CLK: ti: add support for ti
divider-clock, [PATCH 10/40] clk: ti: add support for basic mux clock
+drivers/clk/ti/divider.c: warning: context imbalance in
'ti_clk_divider_set_rate' - different lock contexts for basic block
+drivers/clk/ti/mux.c: warning: context imbalance in
'ti_clk_mux_set_parent' - different lock contexts for basic block

* checkpatch warning [PATCH 16/40] CLK: TI: add am33xx clock init
file, [PATCH 18/40] CLK: TI: add omap3 clock init file
WARNING: static const char * array should probably be static const
char * const


Boot reports:
=============
- previous orphan clocks seem solved.
- All available platforms seem to boot fine and no regression could be
seen on initial view

OMAP2430:
  1. SDP2430
    before: http://pastebin.mozilla.org/3976359
    after: http://pastebin.mozilla.org/3976467

AM335x:
  2. am335x-evm
    before: http://pastebin.mozilla.org/3976284
    after: http://pastebin.mozilla.org/3976374
  3. am335x-sk
    before: http://pastebin.mozilla.org/3976295
    after: http://pastebin.mozilla.org/3976375
  4. BeagleBone Black:
    before: http://pastebin.mozilla.org/3976321
    after: http://pastebin.mozilla.org/3976441

AM3517:
  5. am3517-evm
    before: http://pastebin.mozilla.org/3976297
    after: http://pastebin.mozilla.org/3976397
  6. craneboard
    before: http://pastebin.mozilla.org/3976322
    after: http://pastebin.mozilla.org/3976452

OMAP3430:
  7. ldp
    before: http://pastebin.mozilla.org/3976356
    after: http://pastebin.mozilla.org/3976455
  8. sdp3430
    before: http://pastebin.mozilla.org/3976360
    after: http://pastebin.mozilla.org/3976468

OMAP3630/DM3730:
  9. am37x-evm
    before: http://pastebin.mozilla.org/3976300
    after: http://pastebin.mozilla.org/3976398
  10. beagle-XM
    before: http://pastebin.mozilla.org/3976319
    after: http://pastebin.mozilla.org/3976440

OMAP4430:
  11. SDP4430
    before: http://pastebin.mozilla.org/3976361
    after: http://pastebin.mozilla.org/3976470

OMAP4460:
  12. PandaBoard-ES
    before: http://pastebin.mozilla.org/3976358
    after: http://pastebin.mozilla.org/3976456

OMAP5432:
  13. OMAP5uEVM
    before: http://pastebin.mozilla.org/3976362 (no boot)
    after: http://pastebin.mozilla.org/3976471 (boot)

DRA7:
  14. dra7evm
    before: http://pastebin.mozilla.org/3976354 (no boot)
    after: http://pastebin.mozilla.org/3976453 (boot)

AM437x:
  15. am43xx-epos + out-of-tree patches for engineering samples
    before: http://pastebin.mozilla.org/3976306 (no boot)
    after: http://pastebin.mozilla.org/3976399 (boot)

-- 
Regards,
Nishanth Menon

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 7754 bytes --]

Hi,

On Thu, Jan 09, 2014 at 03:22:03PM -0600, Nishanth Menon wrote:
> > So, bad luck number release for this, as v12 wasn't sufficient still.
> > 
> > Changes compared to previous version:
> > - Dropped any changes to generic clock drivers, as it seems impossible
> >   to agree anything in short term, this means the patch set shrank in
> >   size from 49 patches to 40 (first 9 patches were dropped).
> > - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
> >   to drivers/clk/ti, and made the modifications needed to the TI version
> >   of the clock drivers only (based on discussions with Mike, this is fine)
> > - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
> >   with any generic implementation we might have at some point, migrating
> >   this to the generic version should be easy enough also.
> > - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
> >   versions and resulted into an orphan clock node
> > - Fixed compile problem for omap5 only build reported by Felipe
> > - Fixed a couple of sparse warnings
> > - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
> >   instead of __raw_readl / __raw_writel
> > 
> > Testing done:
> > - omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
> > - omap4-panda-es: boot / suspend-resume (RET)
> > - omap5-uevm: boot
> > - am335x-bone: boot
> > - dra7-evm: boot
> > 
> > Maintainer friendly branches also available:
> > 
> > tree: https://github.com/t-kristo/linux-pm.git
> > 
> > clk driver only (Mike): clk-next-dt-clks-v13
> > DTS data only (Benoit): dts_for_3.14-dt-clks-v13
> > full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13
> > 
> > -Tero
> > 
> 
> Maintainer branches conflicts (using 3.13-rc7-dt-clks-v13):
> =============================
> Conflict resolution during rebase to maintainer's -14 branches:
> 
> 1. (trivial) Against mike's clk-next dbdf6ff Merge branch
> 'clk-next-unregister' into clk-next
> 
> Could not apply 2edf7ad... CLK: TI: add DT alias clock registration
> mechanism
> conflict drivers/clk/Makefile (trivial fix)
> 
> 2. (manual, but changes are easy) Against Tony's omap-for-v3.14/be
> fc6ca98 ARM: OMAP: debug-leds: raw read and write endian fix
> 
> ARM: OMAP2+: clock: use driver API instead of direct memory read/write
> 
> conflicts with be changes on Tony's be branch.
> commit 80f304dd2360cf5d50953c4eb4e902536f6a1263
>     ARM: OMAP2+: raw read and write endian fix
> 
> Conflict:
> arch/arm/mach-omap2/clkt_clksel.c
> arch/arm/mach-omap2/clkt_dpll.c
> arch/arm/mach-omap2/clkt_iclk.c
> arch/arm/mach-omap2/clock.c
> arch/arm/mach-omap2/clock36xx.c
> arch/arm/mach-omap2/dpll3xxx.c
> arch/arm/mach-omap2/dpll44xx.c
> 
> Both change raw_readls -> should now be just clk api instead which
> already does readl_relaxed etc.. If Tony feels like, then we should
> probably post a branch based on 'be' branch for easy merge.
> 
> 3. I could not detect any merge conflict against Benoit's queued up
> series (but maybe he has'nt pushed everything to remote tree)..
> 
> 
> Patch verification report:
> ==========================
> Report: http://pastebin.mozilla.org/3976492
> 
> 
> * sparse warning added in [PATCH 06/40] CLK: ti: add support for ti
> divider-clock, [PATCH 10/40] clk: ti: add support for basic mux clock
> +drivers/clk/ti/divider.c: warning: context imbalance in
> 'ti_clk_divider_set_rate' - different lock contexts for basic block
> +drivers/clk/ti/mux.c: warning: context imbalance in
> 'ti_clk_mux_set_parent' - different lock contexts for basic block
> 
> * checkpatch warning [PATCH 16/40] CLK: TI: add am33xx clock init
> file, [PATCH 18/40] CLK: TI: add omap3 clock init file
> WARNING: static const char * array should probably be static const
> char * const
> 
> 
> Boot reports:
> =============
> - previous orphan clocks seem solved.
> - All available platforms seem to boot fine and no regression could be
> seen on initial view
> 
> OMAP2430:
>   1. SDP2430
>     before: http://pastebin.mozilla.org/3976359
>     after: http://pastebin.mozilla.org/3976467
> 
> AM335x:
>   2. am335x-evm
>     before: http://pastebin.mozilla.org/3976284
>     after: http://pastebin.mozilla.org/3976374
>   3. am335x-sk
>     before: http://pastebin.mozilla.org/3976295
>     after: http://pastebin.mozilla.org/3976375
>   4. BeagleBone Black:
>     before: http://pastebin.mozilla.org/3976321
>     after: http://pastebin.mozilla.org/3976441
> 
> AM3517:
>   5. am3517-evm
>     before: http://pastebin.mozilla.org/3976297
>     after: http://pastebin.mozilla.org/3976397
>   6. craneboard
>     before: http://pastebin.mozilla.org/3976322
>     after: http://pastebin.mozilla.org/3976452
> 
> OMAP3430:
>   7. ldp
>     before: http://pastebin.mozilla.org/3976356
>     after: http://pastebin.mozilla.org/3976455
>   8. sdp3430
>     before: http://pastebin.mozilla.org/3976360
>     after: http://pastebin.mozilla.org/3976468
> 
> OMAP3630/DM3730:
>   9. am37x-evm
>     before: http://pastebin.mozilla.org/3976300
>     after: http://pastebin.mozilla.org/3976398
>   10. beagle-XM
>     before: http://pastebin.mozilla.org/3976319
>     after: http://pastebin.mozilla.org/3976440
> 
> OMAP4430:
>   11. SDP4430
>     before: http://pastebin.mozilla.org/3976361
>     after: http://pastebin.mozilla.org/3976470
> 
> OMAP4460:
>   12. PandaBoard-ES
>     before: http://pastebin.mozilla.org/3976358
>     after: http://pastebin.mozilla.org/3976456
> 
> OMAP5432:
>   13. OMAP5uEVM
>     before: http://pastebin.mozilla.org/3976362 (no boot)
>     after: http://pastebin.mozilla.org/3976471 (boot)
> 
> DRA7:
>   14. dra7evm
>     before: http://pastebin.mozilla.org/3976354 (no boot)
>     after: http://pastebin.mozilla.org/3976453 (boot)
> 
> AM437x:
>   15. am43xx-epos + out-of-tree patches for engineering samples
>     before: http://pastebin.mozilla.org/3976306 (no boot)
>     after: http://pastebin.mozilla.org/3976399 (boot)

to add here, I ran 70 different randconfigs, all seeds are available on
pastebin (took RMK's 4430sdp seed as a starting point):

am33xx-only.config	http://pastebin.com/nVA3xSwb
am43xx-only.config	http://pastebin.com/RbUdKuUh
dra7xx-only.config	http://pastebin.com/ribnaSzS
omap2-only.config	http://pastebin.com/QPUG0wqe
omap3-only.config	http://pastebin.com/B8ctX8yM
omap4-only.config	http://pastebin.com/3D8NAExm
omap5-only.config	http://pastebin.com/3mtQN38Z

Had a total of 16 failing builds, all .configs were also published on
pastebin:

config-am33xx-only.config-1	http://pastebin.com/5xhXZpev
config-am33xx-only.config-2	http://pastebin.com/NsrruJcQ
config-am33xx-only.config-3	http://pastebin.com/CGbB3qb8
config-am33xx-only.config-4	http://pastebin.com/86cu0uZ1
config-am43xx-only.config-1	http://pastebin.com/MCBCAd4X
config-am43xx-only.config-3	http://pastebin.com/hVpCgwSn
config-am43xx-only.config-4	http://pastebin.com/8SXAKHed
config-am43xx-only.config-6	http://pastebin.com/59riPMfw
config-am43xx-only.config-8	http://pastebin.com/03bt2VEZ
config-am43xx-only.config-9	http://pastebin.com/tePGwtWA
config-am43xx-only.config-10	http://pastebin.com/nrtXPqrF
config-omap2-only.config-2	http://pastebin.com/AKyvMqQU
config-omap2-only.config-4	http://paste.debian.net/75329
config-omap2-only.config-5	http://paste.debian.net/75330/
config-omap2-only.config-7	http://paste.debian.net/75332/
config-omap2-only.config-10	http://paste.debian.net/75333/

Failing configs all build fine on v3.13-rc7 except for
config-omap2-only.config-10, which fails due to a broken staging driver.

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tero Kristo]

On 01/10/2014 01:15 AM, Felipe Balbi wrote:
> Hi,
>
> On Thu, Jan 09, 2014 at 03:22:03PM -0600, Nishanth Menon wrote:
>>> So, bad luck number release for this, as v12 wasn't sufficient still.
>>>
>>> Changes compared to previous version:
>>> - Dropped any changes to generic clock drivers, as it seems impossible
>>>    to agree anything in short term, this means the patch set shrank in
>>>    size from 49 patches to 40 (first 9 patches were dropped).
>>> - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
>>>    to drivers/clk/ti, and made the modifications needed to the TI version
>>>    of the clock drivers only (based on discussions with Mike, this is fine)
>>> - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
>>>    with any generic implementation we might have at some point, migrating
>>>    this to the generic version should be easy enough also.
>>> - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
>>>    versions and resulted into an orphan clock node
>>> - Fixed compile problem for omap5 only build reported by Felipe
>>> - Fixed a couple of sparse warnings
>>> - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
>>>    instead of __raw_readl / __raw_writel
>>>
>>> Testing done:
>>> - omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
>>> - omap4-panda-es: boot / suspend-resume (RET)
>>> - omap5-uevm: boot
>>> - am335x-bone: boot
>>> - dra7-evm: boot
>>>
>>> Maintainer friendly branches also available:
>>>
>>> tree: https://github.com/t-kristo/linux-pm.git
>>>
>>> clk driver only (Mike): clk-next-dt-clks-v13
>>> DTS data only (Benoit): dts_for_3.14-dt-clks-v13
>>> full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13
>>>
>>> -Tero
>>>
>>
>> Maintainer branches conflicts (using 3.13-rc7-dt-clks-v13):
>> =============================
>> Conflict resolution during rebase to maintainer's -14 branches:
>>
>> 1. (trivial) Against mike's clk-next dbdf6ff Merge branch
>> 'clk-next-unregister' into clk-next
>>
>> Could not apply 2edf7ad... CLK: TI: add DT alias clock registration
>> mechanism
>> conflict drivers/clk/Makefile (trivial fix)
>>
>> 2. (manual, but changes are easy) Against Tony's omap-for-v3.14/be
>> fc6ca98 ARM: OMAP: debug-leds: raw read and write endian fix
>>
>> ARM: OMAP2+: clock: use driver API instead of direct memory read/write
>>
>> conflicts with be changes on Tony's be branch.
>> commit 80f304dd2360cf5d50953c4eb4e902536f6a1263
>>      ARM: OMAP2+: raw read and write endian fix
>>
>> Conflict:
>> arch/arm/mach-omap2/clkt_clksel.c
>> arch/arm/mach-omap2/clkt_dpll.c
>> arch/arm/mach-omap2/clkt_iclk.c
>> arch/arm/mach-omap2/clock.c
>> arch/arm/mach-omap2/clock36xx.c
>> arch/arm/mach-omap2/dpll3xxx.c
>> arch/arm/mach-omap2/dpll44xx.c
>>
>> Both change raw_readls -> should now be just clk api instead which
>> already does readl_relaxed etc.. If Tony feels like, then we should
>> probably post a branch based on 'be' branch for easy merge.
>>
>> 3. I could not detect any merge conflict against Benoit's queued up
>> series (but maybe he has'nt pushed everything to remote tree)..
>>
>>
>> Patch verification report:
>> ==========================
>> Report: http://pastebin.mozilla.org/3976492
>>
>>
>> * sparse warning added in [PATCH 06/40] CLK: ti: add support for ti
>> divider-clock, [PATCH 10/40] clk: ti: add support for basic mux clock
>> +drivers/clk/ti/divider.c: warning: context imbalance in
>> 'ti_clk_divider_set_rate' - different lock contexts for basic block
>> +drivers/clk/ti/mux.c: warning: context imbalance in
>> 'ti_clk_mux_set_parent' - different lock contexts for basic block
>>
>> * checkpatch warning [PATCH 16/40] CLK: TI: add am33xx clock init
>> file, [PATCH 18/40] CLK: TI: add omap3 clock init file
>> WARNING: static const char * array should probably be static const
>> char * const
>>
>>
>> Boot reports:
>> =============
>> - previous orphan clocks seem solved.
>> - All available platforms seem to boot fine and no regression could be
>> seen on initial view
>>
>> OMAP2430:
>>    1. SDP2430
>>      before: http://pastebin.mozilla.org/3976359
>>      after: http://pastebin.mozilla.org/3976467
>>
>> AM335x:
>>    2. am335x-evm
>>      before: http://pastebin.mozilla.org/3976284
>>      after: http://pastebin.mozilla.org/3976374
>>    3. am335x-sk
>>      before: http://pastebin.mozilla.org/3976295
>>      after: http://pastebin.mozilla.org/3976375
>>    4. BeagleBone Black:
>>      before: http://pastebin.mozilla.org/3976321
>>      after: http://pastebin.mozilla.org/3976441
>>
>> AM3517:
>>    5. am3517-evm
>>      before: http://pastebin.mozilla.org/3976297
>>      after: http://pastebin.mozilla.org/3976397
>>    6. craneboard
>>      before: http://pastebin.mozilla.org/3976322
>>      after: http://pastebin.mozilla.org/3976452
>>
>> OMAP3430:
>>    7. ldp
>>      before: http://pastebin.mozilla.org/3976356
>>      after: http://pastebin.mozilla.org/3976455
>>    8. sdp3430
>>      before: http://pastebin.mozilla.org/3976360
>>      after: http://pastebin.mozilla.org/3976468
>>
>> OMAP3630/DM3730:
>>    9. am37x-evm
>>      before: http://pastebin.mozilla.org/3976300
>>      after: http://pastebin.mozilla.org/3976398
>>    10. beagle-XM
>>      before: http://pastebin.mozilla.org/3976319
>>      after: http://pastebin.mozilla.org/3976440
>>
>> OMAP4430:
>>    11. SDP4430
>>      before: http://pastebin.mozilla.org/3976361
>>      after: http://pastebin.mozilla.org/3976470
>>
>> OMAP4460:
>>    12. PandaBoard-ES
>>      before: http://pastebin.mozilla.org/3976358
>>      after: http://pastebin.mozilla.org/3976456
>>
>> OMAP5432:
>>    13. OMAP5uEVM
>>      before: http://pastebin.mozilla.org/3976362 (no boot)
>>      after: http://pastebin.mozilla.org/3976471 (boot)
>>
>> DRA7:
>>    14. dra7evm
>>      before: http://pastebin.mozilla.org/3976354 (no boot)
>>      after: http://pastebin.mozilla.org/3976453 (boot)
>>
>> AM437x:
>>    15. am43xx-epos + out-of-tree patches for engineering samples
>>      before: http://pastebin.mozilla.org/3976306 (no boot)
>>      after: http://pastebin.mozilla.org/3976399 (boot)
>
> to add here, I ran 70 different randconfigs, all seeds are available on
> pastebin (took RMK's 4430sdp seed as a starting point):
>
> am33xx-only.config	http://pastebin.com/nVA3xSwb
> am43xx-only.config	http://pastebin.com/RbUdKuUh
> dra7xx-only.config	http://pastebin.com/ribnaSzS
> omap2-only.config	http://pastebin.com/QPUG0wqe
> omap3-only.config	http://pastebin.com/B8ctX8yM
> omap4-only.config	http://pastebin.com/3D8NAExm
> omap5-only.config	http://pastebin.com/3mtQN38Z
>
> Had a total of 16 failing builds, all .configs were also published on
> pastebin:
>
> config-am33xx-only.config-1	http://pastebin.com/5xhXZpev
> config-am33xx-only.config-2	http://pastebin.com/NsrruJcQ
> config-am33xx-only.config-3	http://pastebin.com/CGbB3qb8
> config-am33xx-only.config-4	http://pastebin.com/86cu0uZ1
> config-am43xx-only.config-1	http://pastebin.com/MCBCAd4X
> config-am43xx-only.config-3	http://pastebin.com/hVpCgwSn
> config-am43xx-only.config-4	http://pastebin.com/8SXAKHed
> config-am43xx-only.config-6	http://pastebin.com/59riPMfw
> config-am43xx-only.config-8	http://pastebin.com/03bt2VEZ
> config-am43xx-only.config-9	http://pastebin.com/tePGwtWA
> config-am43xx-only.config-10	http://pastebin.com/nrtXPqrF
> config-omap2-only.config-2	http://pastebin.com/AKyvMqQU
> config-omap2-only.config-4	http://paste.debian.net/75329
> config-omap2-only.config-5	http://paste.debian.net/75330/
> config-omap2-only.config-7	http://paste.debian.net/75332/
> config-omap2-only.config-10	http://paste.debian.net/75333/
>
> Failing configs all build fine on v3.13-rc7 except for
> config-omap2-only.config-10, which fails due to a broken staging driver.
>

I think all of these fails are caused by the initially bugged Makefile + 
Kconfig under mach-omap2. Seems like they can be fixed by the patches I 
inlined at the end (will also post them as proper patches to l-o list 
after this.) The question is, should Mike go ahead and merge these along 
with the base clk patches or how should we handle them? Patch 1 must be 
merged, patch 2 is a nice to have one which allows DRA7 only builds 
(doing DRA7 only build currently seems not possible.)

-Tero

-----------

 From f552421bbfe85ffba1f10df7a286216aa822a749 Mon Sep 17 00:00:00 2001
From: Tero Kristo <t-kristo@ti.com>
Date: Fri, 10 Jan 2014 11:20:18 +0200
Subject: [PATCH 1/2] ARM: DRA7XX/AM43XX: randconfig fixes

DRA7XX and AM43XX were missing common clock code from the Makefile, which
causes build breakage in DRA7XX / AM43XX only builds once clock support
for these SoCs is added. Add the missing entries to the Makefile as
preparation of this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
  arch/arm/mach-omap2/Makefile |    3 +++
  1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 088305f..96a990f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -191,6 +191,9 @@ obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
  obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o
  obj-$(CONFIG_SOC_OMAP5)			+= $(clock-common)
  obj-$(CONFIG_SOC_OMAP5)			+= dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX)		+= $(clock-common)
+obj-$(CONFIG_SOC_DRA7XX)		+= dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_AM43XX)		+= $(clock-common) dpll3xxx.o

  # OMAP2 clock rate set data (old "OPP" data)
  obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
-- 
1.7.9.5

------------------

 From 14d3443d5fd8d16d4422de84cff16f4bc78f03dc Mon Sep 17 00:00:00 2001
From: Tero Kristo <t-kristo@ti.com>
Date: Fri, 10 Jan 2014 11:25:28 +0200
Subject: [PATCH 2/2] ARM: DRA7XX: Add support for DRA7XX only build

SOC_DRA7XX was under wrong menu within Kconfig file, which prevented
DRA7XX only build. Fixed the kconfig options for this SoC as we are
there. voltage.c needs to be added to the DRA7XX build also, otherwise
DRA7XX only build will fail.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
  arch/arm/mach-omap2/Kconfig  |   18 ++++++++++--------
  arch/arm/mach-omap2/Makefile |    1 +
  2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dc21df1..e65948a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -76,6 +76,16 @@ config SOC_AM43XX
  	select ARM_GIC
  	select MACH_OMAP_GENERIC

+config SOC_DRA7XX
+	bool "TI DRA7XX"
+	depends on ARCH_MULTI_V7
+	select ARCH_OMAP2PLUS
+	select ARM_CPU_SUSPEND if PM
+	select ARM_GIC
+	select CPU_V7
+	select HAVE_SMP
+	select HAVE_ARM_ARCH_TIMER
+
  config ARCH_OMAP2PLUS
  	bool
  	select ARCH_HAS_BANDGAP
@@ -128,14 +138,6 @@ config SOC_HAS_REALTIME_COUNTER
  	depends on SOC_OMAP5 || SOC_DRA7XX
  	default y

-config SOC_DRA7XX
-	bool "TI DRA7XX"
-	select ARM_ARCH_TIMER
-	select CPU_V7
-	select ARM_GIC
-	select HAVE_SMP
-	select COMMON_CLK
-
  comment "OMAP Core Type"
  	depends on ARCH_OMAP2

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 96a990f..8ebe9f3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -132,6 +132,7 @@ obj-$(CONFIG_SOC_AM33XX)		+= $(voltagedomain-common)
  obj-$(CONFIG_SOC_AM43XX)		+= $(voltagedomain-common)
  obj-$(CONFIG_SOC_OMAP5)			+= $(voltagedomain-common)
  obj-$(CONFIG_SOC_OMAP5)                += voltagedomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX)		+= $(voltagedomain-common)

  # OMAP powerdomain framework
  powerdomain-common			+= powerdomain.o powerdomain-common.o
-- 
1.7.9.5

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 9017 bytes --]

Hi,

On Fri, Jan 10, 2014 at 11:52:49AM +0200, Tero Kristo wrote:
> On 01/10/2014 01:15 AM, Felipe Balbi wrote:
> >Hi,
> >
> >On Thu, Jan 09, 2014 at 03:22:03PM -0600, Nishanth Menon wrote:
> >>>So, bad luck number release for this, as v12 wasn't sufficient still.
> >>>
> >>>Changes compared to previous version:
> >>>- Dropped any changes to generic clock drivers, as it seems impossible
> >>>   to agree anything in short term, this means the patch set shrank in
> >>>   size from 49 patches to 40 (first 9 patches were dropped).
> >>>- Copy pasted implementation for clk-divider and clk-mux from drivers/clk
> >>>   to drivers/clk/ti, and made the modifications needed to the TI version
> >>>   of the clock drivers only (based on discussions with Mike, this is fine)
> >>>- Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
> >>>   with any generic implementation we might have at some point, migrating
> >>>   this to the generic version should be easy enough also.
> >>>- Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
> >>>   versions and resulted into an orphan clock node
> >>>- Fixed compile problem for omap5 only build reported by Felipe
> >>>- Fixed a couple of sparse warnings
> >>>- changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
> >>>   instead of __raw_readl / __raw_writel
> >>>
> >>>Testing done:
> >>>- omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
> >>>- omap4-panda-es: boot / suspend-resume (RET)
> >>>- omap5-uevm: boot
> >>>- am335x-bone: boot
> >>>- dra7-evm: boot
> >>>
> >>>Maintainer friendly branches also available:
> >>>
> >>>tree: https://github.com/t-kristo/linux-pm.git
> >>>
> >>>clk driver only (Mike): clk-next-dt-clks-v13
> >>>DTS data only (Benoit): dts_for_3.14-dt-clks-v13
> >>>full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13
> >>>
> >>>-Tero
> >>>
> >>
> >>Maintainer branches conflicts (using 3.13-rc7-dt-clks-v13):
> >>=============================
> >>Conflict resolution during rebase to maintainer's -14 branches:
> >>
> >>1. (trivial) Against mike's clk-next dbdf6ff Merge branch
> >>'clk-next-unregister' into clk-next
> >>
> >>Could not apply 2edf7ad... CLK: TI: add DT alias clock registration
> >>mechanism
> >>conflict drivers/clk/Makefile (trivial fix)
> >>
> >>2. (manual, but changes are easy) Against Tony's omap-for-v3.14/be
> >>fc6ca98 ARM: OMAP: debug-leds: raw read and write endian fix
> >>
> >>ARM: OMAP2+: clock: use driver API instead of direct memory read/write
> >>
> >>conflicts with be changes on Tony's be branch.
> >>commit 80f304dd2360cf5d50953c4eb4e902536f6a1263
> >>     ARM: OMAP2+: raw read and write endian fix
> >>
> >>Conflict:
> >>arch/arm/mach-omap2/clkt_clksel.c
> >>arch/arm/mach-omap2/clkt_dpll.c
> >>arch/arm/mach-omap2/clkt_iclk.c
> >>arch/arm/mach-omap2/clock.c
> >>arch/arm/mach-omap2/clock36xx.c
> >>arch/arm/mach-omap2/dpll3xxx.c
> >>arch/arm/mach-omap2/dpll44xx.c
> >>
> >>Both change raw_readls -> should now be just clk api instead which
> >>already does readl_relaxed etc.. If Tony feels like, then we should
> >>probably post a branch based on 'be' branch for easy merge.
> >>
> >>3. I could not detect any merge conflict against Benoit's queued up
> >>series (but maybe he has'nt pushed everything to remote tree)..
> >>
> >>
> >>Patch verification report:
> >>==========================
> >>Report: http://pastebin.mozilla.org/3976492
> >>
> >>
> >>* sparse warning added in [PATCH 06/40] CLK: ti: add support for ti
> >>divider-clock, [PATCH 10/40] clk: ti: add support for basic mux clock
> >>+drivers/clk/ti/divider.c: warning: context imbalance in
> >>'ti_clk_divider_set_rate' - different lock contexts for basic block
> >>+drivers/clk/ti/mux.c: warning: context imbalance in
> >>'ti_clk_mux_set_parent' - different lock contexts for basic block
> >>
> >>* checkpatch warning [PATCH 16/40] CLK: TI: add am33xx clock init
> >>file, [PATCH 18/40] CLK: TI: add omap3 clock init file
> >>WARNING: static const char * array should probably be static const
> >>char * const
> >>
> >>
> >>Boot reports:
> >>=============
> >>- previous orphan clocks seem solved.
> >>- All available platforms seem to boot fine and no regression could be
> >>seen on initial view
> >>
> >>OMAP2430:
> >>   1. SDP2430
> >>     before: http://pastebin.mozilla.org/3976359
> >>     after: http://pastebin.mozilla.org/3976467
> >>
> >>AM335x:
> >>   2. am335x-evm
> >>     before: http://pastebin.mozilla.org/3976284
> >>     after: http://pastebin.mozilla.org/3976374
> >>   3. am335x-sk
> >>     before: http://pastebin.mozilla.org/3976295
> >>     after: http://pastebin.mozilla.org/3976375
> >>   4. BeagleBone Black:
> >>     before: http://pastebin.mozilla.org/3976321
> >>     after: http://pastebin.mozilla.org/3976441
> >>
> >>AM3517:
> >>   5. am3517-evm
> >>     before: http://pastebin.mozilla.org/3976297
> >>     after: http://pastebin.mozilla.org/3976397
> >>   6. craneboard
> >>     before: http://pastebin.mozilla.org/3976322
> >>     after: http://pastebin.mozilla.org/3976452
> >>
> >>OMAP3430:
> >>   7. ldp
> >>     before: http://pastebin.mozilla.org/3976356
> >>     after: http://pastebin.mozilla.org/3976455
> >>   8. sdp3430
> >>     before: http://pastebin.mozilla.org/3976360
> >>     after: http://pastebin.mozilla.org/3976468
> >>
> >>OMAP3630/DM3730:
> >>   9. am37x-evm
> >>     before: http://pastebin.mozilla.org/3976300
> >>     after: http://pastebin.mozilla.org/3976398
> >>   10. beagle-XM
> >>     before: http://pastebin.mozilla.org/3976319
> >>     after: http://pastebin.mozilla.org/3976440
> >>
> >>OMAP4430:
> >>   11. SDP4430
> >>     before: http://pastebin.mozilla.org/3976361
> >>     after: http://pastebin.mozilla.org/3976470
> >>
> >>OMAP4460:
> >>   12. PandaBoard-ES
> >>     before: http://pastebin.mozilla.org/3976358
> >>     after: http://pastebin.mozilla.org/3976456
> >>
> >>OMAP5432:
> >>   13. OMAP5uEVM
> >>     before: http://pastebin.mozilla.org/3976362 (no boot)
> >>     after: http://pastebin.mozilla.org/3976471 (boot)
> >>
> >>DRA7:
> >>   14. dra7evm
> >>     before: http://pastebin.mozilla.org/3976354 (no boot)
> >>     after: http://pastebin.mozilla.org/3976453 (boot)
> >>
> >>AM437x:
> >>   15. am43xx-epos + out-of-tree patches for engineering samples
> >>     before: http://pastebin.mozilla.org/3976306 (no boot)
> >>     after: http://pastebin.mozilla.org/3976399 (boot)
> >
> >to add here, I ran 70 different randconfigs, all seeds are available on
> >pastebin (took RMK's 4430sdp seed as a starting point):
> >
> >am33xx-only.config	http://pastebin.com/nVA3xSwb
> >am43xx-only.config	http://pastebin.com/RbUdKuUh
> >dra7xx-only.config	http://pastebin.com/ribnaSzS
> >omap2-only.config	http://pastebin.com/QPUG0wqe
> >omap3-only.config	http://pastebin.com/B8ctX8yM
> >omap4-only.config	http://pastebin.com/3D8NAExm
> >omap5-only.config	http://pastebin.com/3mtQN38Z
> >
> >Had a total of 16 failing builds, all .configs were also published on
> >pastebin:
> >
> >config-am33xx-only.config-1	http://pastebin.com/5xhXZpev
> >config-am33xx-only.config-2	http://pastebin.com/NsrruJcQ
> >config-am33xx-only.config-3	http://pastebin.com/CGbB3qb8
> >config-am33xx-only.config-4	http://pastebin.com/86cu0uZ1
> >config-am43xx-only.config-1	http://pastebin.com/MCBCAd4X
> >config-am43xx-only.config-3	http://pastebin.com/hVpCgwSn
> >config-am43xx-only.config-4	http://pastebin.com/8SXAKHed
> >config-am43xx-only.config-6	http://pastebin.com/59riPMfw
> >config-am43xx-only.config-8	http://pastebin.com/03bt2VEZ
> >config-am43xx-only.config-9	http://pastebin.com/tePGwtWA
> >config-am43xx-only.config-10	http://pastebin.com/nrtXPqrF
> >config-omap2-only.config-2	http://pastebin.com/AKyvMqQU
> >config-omap2-only.config-4	http://paste.debian.net/75329
> >config-omap2-only.config-5	http://paste.debian.net/75330/
> >config-omap2-only.config-7	http://paste.debian.net/75332/
> >config-omap2-only.config-10	http://paste.debian.net/75333/
> >
> >Failing configs all build fine on v3.13-rc7 except for
> >config-omap2-only.config-10, which fails due to a broken staging driver.
> >
> 
> I think all of these fails are caused by the initially bugged
> Makefile + Kconfig under mach-omap2. Seems like they can be fixed by
> the patches I inlined at the end (will also post them as proper
> patches to l-o list after this.) The question is, should Mike go
> ahead and merge these along with the base clk patches or how should
> we handle them? Patch 1 must be merged, patch 2 is a nice to have one
> which allows DRA7 only builds (doing DRA7 only build currently seems
> not possible.)

If it's OK with Tony, I would suggest having a branch with both patches
below which both Tony and Mike merge before merging CCF series. That way
we avoid bisection problems.

-- 
balbi

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Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tero Kristo]

On 01/10/2014 06:13 PM, Felipe Balbi wrote:
> Hi,
>
> On Fri, Jan 10, 2014 at 11:52:49AM +0200, Tero Kristo wrote:
>> On 01/10/2014 01:15 AM, Felipe Balbi wrote:
>>> Hi,
>>>
>>> On Thu, Jan 09, 2014 at 03:22:03PM -0600, Nishanth Menon wrote:
>>>>> So, bad luck number release for this, as v12 wasn't sufficient still.
>>>>>
>>>>> Changes compared to previous version:
>>>>> - Dropped any changes to generic clock drivers, as it seems impossible
>>>>>    to agree anything in short term, this means the patch set shrank in
>>>>>    size from 49 patches to 40 (first 9 patches were dropped).
>>>>> - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
>>>>>    to drivers/clk/ti, and made the modifications needed to the TI version
>>>>>    of the clock drivers only (based on discussions with Mike, this is fine)
>>>>> - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
>>>>>    with any generic implementation we might have at some point, migrating
>>>>>    this to the generic version should be easy enough also.
>>>>> - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
>>>>>    versions and resulted into an orphan clock node
>>>>> - Fixed compile problem for omap5 only build reported by Felipe
>>>>> - Fixed a couple of sparse warnings
>>>>> - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
>>>>>    instead of __raw_readl / __raw_writel
>>>>>
>>>>> Testing done:
>>>>> - omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
>>>>> - omap4-panda-es: boot / suspend-resume (RET)
>>>>> - omap5-uevm: boot
>>>>> - am335x-bone: boot
>>>>> - dra7-evm: boot
>>>>>
>>>>> Maintainer friendly branches also available:
>>>>>
>>>>> tree: https://github.com/t-kristo/linux-pm.git
>>>>>
>>>>> clk driver only (Mike): clk-next-dt-clks-v13
>>>>> DTS data only (Benoit): dts_for_3.14-dt-clks-v13
>>>>> full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13
>>>>>
>>>>> -Tero
>>>>>
>>>>
>>>> Maintainer branches conflicts (using 3.13-rc7-dt-clks-v13):
>>>> =============================
>>>> Conflict resolution during rebase to maintainer's -14 branches:
>>>>
>>>> 1. (trivial) Against mike's clk-next dbdf6ff Merge branch
>>>> 'clk-next-unregister' into clk-next
>>>>
>>>> Could not apply 2edf7ad... CLK: TI: add DT alias clock registration
>>>> mechanism
>>>> conflict drivers/clk/Makefile (trivial fix)
>>>>
>>>> 2. (manual, but changes are easy) Against Tony's omap-for-v3.14/be
>>>> fc6ca98 ARM: OMAP: debug-leds: raw read and write endian fix
>>>>
>>>> ARM: OMAP2+: clock: use driver API instead of direct memory read/write
>>>>
>>>> conflicts with be changes on Tony's be branch.
>>>> commit 80f304dd2360cf5d50953c4eb4e902536f6a1263
>>>>      ARM: OMAP2+: raw read and write endian fix
>>>>
>>>> Conflict:
>>>> arch/arm/mach-omap2/clkt_clksel.c
>>>> arch/arm/mach-omap2/clkt_dpll.c
>>>> arch/arm/mach-omap2/clkt_iclk.c
>>>> arch/arm/mach-omap2/clock.c
>>>> arch/arm/mach-omap2/clock36xx.c
>>>> arch/arm/mach-omap2/dpll3xxx.c
>>>> arch/arm/mach-omap2/dpll44xx.c
>>>>
>>>> Both change raw_readls -> should now be just clk api instead which
>>>> already does readl_relaxed etc.. If Tony feels like, then we should
>>>> probably post a branch based on 'be' branch for easy merge.
>>>>
>>>> 3. I could not detect any merge conflict against Benoit's queued up
>>>> series (but maybe he has'nt pushed everything to remote tree)..
>>>>
>>>>
>>>> Patch verification report:
>>>> ==========================
>>>> Report: http://pastebin.mozilla.org/3976492
>>>>
>>>>
>>>> * sparse warning added in [PATCH 06/40] CLK: ti: add support for ti
>>>> divider-clock, [PATCH 10/40] clk: ti: add support for basic mux clock
>>>> +drivers/clk/ti/divider.c: warning: context imbalance in
>>>> 'ti_clk_divider_set_rate' - different lock contexts for basic block
>>>> +drivers/clk/ti/mux.c: warning: context imbalance in
>>>> 'ti_clk_mux_set_parent' - different lock contexts for basic block
>>>>
>>>> * checkpatch warning [PATCH 16/40] CLK: TI: add am33xx clock init
>>>> file, [PATCH 18/40] CLK: TI: add omap3 clock init file
>>>> WARNING: static const char * array should probably be static const
>>>> char * const
>>>>
>>>>
>>>> Boot reports:
>>>> =============
>>>> - previous orphan clocks seem solved.
>>>> - All available platforms seem to boot fine and no regression could be
>>>> seen on initial view
>>>>
>>>> OMAP2430:
>>>>    1. SDP2430
>>>>      before: http://pastebin.mozilla.org/3976359
>>>>      after: http://pastebin.mozilla.org/3976467
>>>>
>>>> AM335x:
>>>>    2. am335x-evm
>>>>      before: http://pastebin.mozilla.org/3976284
>>>>      after: http://pastebin.mozilla.org/3976374
>>>>    3. am335x-sk
>>>>      before: http://pastebin.mozilla.org/3976295
>>>>      after: http://pastebin.mozilla.org/3976375
>>>>    4. BeagleBone Black:
>>>>      before: http://pastebin.mozilla.org/3976321
>>>>      after: http://pastebin.mozilla.org/3976441
>>>>
>>>> AM3517:
>>>>    5. am3517-evm
>>>>      before: http://pastebin.mozilla.org/3976297
>>>>      after: http://pastebin.mozilla.org/3976397
>>>>    6. craneboard
>>>>      before: http://pastebin.mozilla.org/3976322
>>>>      after: http://pastebin.mozilla.org/3976452
>>>>
>>>> OMAP3430:
>>>>    7. ldp
>>>>      before: http://pastebin.mozilla.org/3976356
>>>>      after: http://pastebin.mozilla.org/3976455
>>>>    8. sdp3430
>>>>      before: http://pastebin.mozilla.org/3976360
>>>>      after: http://pastebin.mozilla.org/3976468
>>>>
>>>> OMAP3630/DM3730:
>>>>    9. am37x-evm
>>>>      before: http://pastebin.mozilla.org/3976300
>>>>      after: http://pastebin.mozilla.org/3976398
>>>>    10. beagle-XM
>>>>      before: http://pastebin.mozilla.org/3976319
>>>>      after: http://pastebin.mozilla.org/3976440
>>>>
>>>> OMAP4430:
>>>>    11. SDP4430
>>>>      before: http://pastebin.mozilla.org/3976361
>>>>      after: http://pastebin.mozilla.org/3976470
>>>>
>>>> OMAP4460:
>>>>    12. PandaBoard-ES
>>>>      before: http://pastebin.mozilla.org/3976358
>>>>      after: http://pastebin.mozilla.org/3976456
>>>>
>>>> OMAP5432:
>>>>    13. OMAP5uEVM
>>>>      before: http://pastebin.mozilla.org/3976362 (no boot)
>>>>      after: http://pastebin.mozilla.org/3976471 (boot)
>>>>
>>>> DRA7:
>>>>    14. dra7evm
>>>>      before: http://pastebin.mozilla.org/3976354 (no boot)
>>>>      after: http://pastebin.mozilla.org/3976453 (boot)
>>>>
>>>> AM437x:
>>>>    15. am43xx-epos + out-of-tree patches for engineering samples
>>>>      before: http://pastebin.mozilla.org/3976306 (no boot)
>>>>      after: http://pastebin.mozilla.org/3976399 (boot)
>>>
>>> to add here, I ran 70 different randconfigs, all seeds are available on
>>> pastebin (took RMK's 4430sdp seed as a starting point):
>>>
>>> am33xx-only.config	http://pastebin.com/nVA3xSwb
>>> am43xx-only.config	http://pastebin.com/RbUdKuUh
>>> dra7xx-only.config	http://pastebin.com/ribnaSzS
>>> omap2-only.config	http://pastebin.com/QPUG0wqe
>>> omap3-only.config	http://pastebin.com/B8ctX8yM
>>> omap4-only.config	http://pastebin.com/3D8NAExm
>>> omap5-only.config	http://pastebin.com/3mtQN38Z
>>>
>>> Had a total of 16 failing builds, all .configs were also published on
>>> pastebin:
>>>
>>> config-am33xx-only.config-1	http://pastebin.com/5xhXZpev
>>> config-am33xx-only.config-2	http://pastebin.com/NsrruJcQ
>>> config-am33xx-only.config-3	http://pastebin.com/CGbB3qb8
>>> config-am33xx-only.config-4	http://pastebin.com/86cu0uZ1
>>> config-am43xx-only.config-1	http://pastebin.com/MCBCAd4X
>>> config-am43xx-only.config-3	http://pastebin.com/hVpCgwSn
>>> config-am43xx-only.config-4	http://pastebin.com/8SXAKHed
>>> config-am43xx-only.config-6	http://pastebin.com/59riPMfw
>>> config-am43xx-only.config-8	http://pastebin.com/03bt2VEZ
>>> config-am43xx-only.config-9	http://pastebin.com/tePGwtWA
>>> config-am43xx-only.config-10	http://pastebin.com/nrtXPqrF
>>> config-omap2-only.config-2	http://pastebin.com/AKyvMqQU
>>> config-omap2-only.config-4	http://paste.debian.net/75329
>>> config-omap2-only.config-5	http://paste.debian.net/75330/
>>> config-omap2-only.config-7	http://paste.debian.net/75332/
>>> config-omap2-only.config-10	http://paste.debian.net/75333/
>>>
>>> Failing configs all build fine on v3.13-rc7 except for
>>> config-omap2-only.config-10, which fails due to a broken staging driver.
>>>
>>
>> I think all of these fails are caused by the initially bugged
>> Makefile + Kconfig under mach-omap2. Seems like they can be fixed by
>> the patches I inlined at the end (will also post them as proper
>> patches to l-o list after this.) The question is, should Mike go
>> ahead and merge these along with the base clk patches or how should
>> we handle them? Patch 1 must be merged, patch 2 is a nice to have one
>> which allows DRA7 only builds (doing DRA7 only build currently seems
>> not possible.)
>
> If it's OK with Tony, I would suggest having a branch with both patches
> below which both Tony and Mike merge before merging CCF series. That way
> we avoid bisection problems.

That reminds me, I think the baseline branch for the mach-omap2 patches 
is still somewhat unclear to me, what should be used for this? And which 
patches should be put there (the mach-omap2 patches depend on the 
drivers/clk/ti part basically, so I need to put at least those there also.)

-Tero

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [140110 08:32]:
> On 01/10/2014 06:13 PM, Felipe Balbi wrote:
> >On Fri, Jan 10, 2014 at 11:52:49AM +0200, Tero Kristo wrote:
> >>On 01/10/2014 01:15 AM, Felipe Balbi wrote:
> >>>On Thu, Jan 09, 2014 at 03:22:03PM -0600, Nishanth Menon wrote:
> >>>>
> >>>>conflicts with be changes on Tony's be branch.
> >>>>commit 80f304dd2360cf5d50953c4eb4e902536f6a1263
> >>>>     ARM: OMAP2+: raw read and write endian fix
> >>>>
> >>>>Conflict:
> >>>>arch/arm/mach-omap2/clkt_clksel.c
> >>>>arch/arm/mach-omap2/clkt_dpll.c
> >>>>arch/arm/mach-omap2/clkt_iclk.c
> >>>>arch/arm/mach-omap2/clock.c
> >>>>arch/arm/mach-omap2/clock36xx.c
> >>>>arch/arm/mach-omap2/dpll3xxx.c
> >>>>arch/arm/mach-omap2/dpll44xx.c
> >>>>
> >>>>Both change raw_readls -> should now be just clk api instead which
> >>>>already does readl_relaxed etc.. If Tony feels like, then we should
> >>>>probably post a branch based on 'be' branch for easy merge.

This should be a trivial merge conflict to handle, so let's not base
things on the BE changes.

> >>I think all of these fails are caused by the initially bugged
> >>Makefile + Kconfig under mach-omap2. Seems like they can be fixed by
> >>the patches I inlined at the end (will also post them as proper
> >>patches to l-o list after this.) The question is, should Mike go
> >>ahead and merge these along with the base clk patches or how should
> >>we handle them? Patch 1 must be merged, patch 2 is a nice to have one
> >>which allows DRA7 only builds (doing DRA7 only build currently seems
> >>not possible.)
> >
> >If it's OK with Tony, I would suggest having a branch with both patches
> >below which both Tony and Mike merge before merging CCF series. That way
> >we avoid bisection problems.

I can queue those two separately as fixes.
 
> That reminds me, I think the baseline branch for the mach-omap2
> patches is still somewhat unclear to me, what should be used for
> this? And which patches should be put there (the mach-omap2 patches
> depend on the drivers/clk/ti part basically, so I need to put at
> least those there also.)

I would keep the clock patches against some mainline -rc commit if
possible, and if there are non trivial merge conflicts, the omap
to use as the base is commit adfe9361b236154215d4b0fc8b6d79995394b15c.

In any case, it's probably best that Mike merges this all via his
clock tree unless there non-trivial merge conflicts.

Regards,

Tony

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tero Kristo]

On 01/10/2014 08:51 PM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [140110 08:32]:
>> On 01/10/2014 06:13 PM, Felipe Balbi wrote:
>>> On Fri, Jan 10, 2014 at 11:52:49AM +0200, Tero Kristo wrote:
>>>> On 01/10/2014 01:15 AM, Felipe Balbi wrote:
>>>>> On Thu, Jan 09, 2014 at 03:22:03PM -0600, Nishanth Menon wrote:
>>>>>>
>>>>>> conflicts with be changes on Tony's be branch.
>>>>>> commit 80f304dd2360cf5d50953c4eb4e902536f6a1263
>>>>>>      ARM: OMAP2+: raw read and write endian fix
>>>>>>
>>>>>> Conflict:
>>>>>> arch/arm/mach-omap2/clkt_clksel.c
>>>>>> arch/arm/mach-omap2/clkt_dpll.c
>>>>>> arch/arm/mach-omap2/clkt_iclk.c
>>>>>> arch/arm/mach-omap2/clock.c
>>>>>> arch/arm/mach-omap2/clock36xx.c
>>>>>> arch/arm/mach-omap2/dpll3xxx.c
>>>>>> arch/arm/mach-omap2/dpll44xx.c
>>>>>>
>>>>>> Both change raw_readls -> should now be just clk api instead which
>>>>>> already does readl_relaxed etc.. If Tony feels like, then we should
>>>>>> probably post a branch based on 'be' branch for easy merge.
>
> This should be a trivial merge conflict to handle, so let's not base
> things on the BE changes.
>
>>>> I think all of these fails are caused by the initially bugged
>>>> Makefile + Kconfig under mach-omap2. Seems like they can be fixed by
>>>> the patches I inlined at the end (will also post them as proper
>>>> patches to l-o list after this.) The question is, should Mike go
>>>> ahead and merge these along with the base clk patches or how should
>>>> we handle them? Patch 1 must be merged, patch 2 is a nice to have one
>>>> which allows DRA7 only builds (doing DRA7 only build currently seems
>>>> not possible.)
>>>
>>> If it's OK with Tony, I would suggest having a branch with both patches
>>> below which both Tony and Mike merge before merging CCF series. That way
>>> we avoid bisection problems.
>
> I can queue those two separately as fixes.
>
>> That reminds me, I think the baseline branch for the mach-omap2
>> patches is still somewhat unclear to me, what should be used for
>> this? And which patches should be put there (the mach-omap2 patches
>> depend on the drivers/clk/ti part basically, so I need to put at
>> least those there also.)
>
> I would keep the clock patches against some mainline -rc commit if
> possible, and if there are non trivial merge conflicts, the omap
> to use as the base is commit adfe9361b236154215d4b0fc8b6d79995394b15c.
>
> In any case, it's probably best that Mike merges this all via his
> clock tree unless there non-trivial merge conflicts.
>

I just pushed a branch against rc7 with makefile fixes in place to fix 
omap1 and omap2 only builds for this stuff. Inlined the delta here at 
the end. Do you want me to repost the series as v14 for this or is the 
attached delta ok for review purposes? All the changes have been 
squashed to existing patches (except the 2 patches I posted separately 
for DRA7xx / AM43xx only builds.)

The test branch itself can be found here:

tree: https://github.com/t-kristo/linux-pm.git
branch: 3.13-rc7-dt-clks-v13-build-fixes

Felipe, care to run your randconfig magic for this?

-Tero

----------------
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dc21df1..e65948a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -76,6 +76,16 @@ config SOC_AM43XX
  	select ARM_GIC
  	select MACH_OMAP_GENERIC

+config SOC_DRA7XX
+	bool "TI DRA7XX"
+	depends on ARCH_MULTI_V7
+	select ARCH_OMAP2PLUS
+	select ARM_CPU_SUSPEND if PM
+	select ARM_GIC
+	select CPU_V7
+	select HAVE_SMP
+	select HAVE_ARM_ARCH_TIMER
+
  config ARCH_OMAP2PLUS
  	bool
  	select ARCH_HAS_BANDGAP
@@ -128,14 +138,6 @@ config SOC_HAS_REALTIME_COUNTER
  	depends on SOC_OMAP5 || SOC_DRA7XX
  	default y

-config SOC_DRA7XX
-	bool "TI DRA7XX"
-	select ARM_ARCH_TIMER
-	select CPU_V7
-	select ARM_GIC
-	select HAVE_SMP
-	select COMMON_CLK
-
  comment "OMAP Core Type"
  	depends on ARCH_OMAP2

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 088305f..8ebe9f3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -132,6 +132,7 @@ obj-$(CONFIG_SOC_AM33XX)		+= $(voltagedomain-common)
  obj-$(CONFIG_SOC_AM43XX)		+= $(voltagedomain-common)
  obj-$(CONFIG_SOC_OMAP5)			+= $(voltagedomain-common)
  obj-$(CONFIG_SOC_OMAP5)                += voltagedomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX)		+= $(voltagedomain-common)

  # OMAP powerdomain framework
  powerdomain-common			+= powerdomain.o powerdomain-common.o
@@ -191,6 +192,9 @@ obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
  obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o
  obj-$(CONFIG_SOC_OMAP5)			+= $(clock-common)
  obj-$(CONFIG_SOC_OMAP5)			+= dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX)		+= $(clock-common)
+obj-$(CONFIG_SOC_DRA7XX)		+= dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_AM43XX)		+= $(clock-common) dpll3xxx.o

  # OMAP2 clock rate set data (old "OPP" data)
  obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index c61f768..41bd909 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -35,7 +35,7 @@ obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
  obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
  obj-$(CONFIG_COMMON_CLK_XGENE)  += clk-xgene.o
  obj-$(CONFIG_COMMON_CLK_KEYSTONE)	+= keystone/
-obj-$(CONFIG_ARCH_OMAP)		+= ti/
+obj-$(CONFIG_ARCH_OMAP2PLUS)	+= ti/

  obj-$(CONFIG_X86)		+= x86/

diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 007c3c2..4319d40 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,10 +1,11 @@
  ifneq ($(CONFIG_OF),)
-obj-y					+= clk.o dpll.o autoidle.o divider.o \
-					   fixed-factor.o gate.o clockdomain.o \
-					   composite.o mux.o apll.o clk-43xx.o
-obj-$(CONFIG_SOC_AM33XX)		+= clk-33xx.o
-obj-$(CONFIG_ARCH_OMAP3)		+= interface.o clk-3xxx.o
-obj-$(CONFIG_ARCH_OMAP4)		+= clk-44xx.o
-obj-$(CONFIG_SOC_OMAP5)			+= clk-54xx.o
-obj-$(CONFIG_SOC_DRA7XX)		+= clk-7xx.o
+obj-y					+= clk.o autoidle.o clockdomain.o
+clk-common				= dpll.o composite.o divider.o gate.o \
+					  fixed-factor.o mux.o apll.o
+obj-$(CONFIG_SOC_AM33XX)		+= $(clk-common) clk-33xx.o
+obj-$(CONFIG_ARCH_OMAP3)		+= $(clk-common) interface.o clk-3xxx.o
+obj-$(CONFIG_ARCH_OMAP4)		+= $(clk-common) clk-44xx.o
+obj-$(CONFIG_SOC_OMAP5)			+= $(clk-common) clk-54xx.o
+obj-$(CONFIG_SOC_DRA7XX)		+= $(clk-common) clk-7xx.o
+obj-$(CONFIG_SOC_AM43XX)		+= $(clk-common) clk-43xx.o
  endif

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Felipe Balbi]

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On Tue, Jan 14, 2014 at 02:41:40PM +0200, Tero Kristo wrote:
> On 01/10/2014 08:51 PM, Tony Lindgren wrote:
> >* Tero Kristo <t-kristo@ti.com> [140110 08:32]:
> >>On 01/10/2014 06:13 PM, Felipe Balbi wrote:
> >>>On Fri, Jan 10, 2014 at 11:52:49AM +0200, Tero Kristo wrote:
> >>>>On 01/10/2014 01:15 AM, Felipe Balbi wrote:
> >>>>>On Thu, Jan 09, 2014 at 03:22:03PM -0600, Nishanth Menon wrote:
> >>>>>>
> >>>>>>conflicts with be changes on Tony's be branch.
> >>>>>>commit 80f304dd2360cf5d50953c4eb4e902536f6a1263
> >>>>>>     ARM: OMAP2+: raw read and write endian fix
> >>>>>>
> >>>>>>Conflict:
> >>>>>>arch/arm/mach-omap2/clkt_clksel.c
> >>>>>>arch/arm/mach-omap2/clkt_dpll.c
> >>>>>>arch/arm/mach-omap2/clkt_iclk.c
> >>>>>>arch/arm/mach-omap2/clock.c
> >>>>>>arch/arm/mach-omap2/clock36xx.c
> >>>>>>arch/arm/mach-omap2/dpll3xxx.c
> >>>>>>arch/arm/mach-omap2/dpll44xx.c
> >>>>>>
> >>>>>>Both change raw_readls -> should now be just clk api instead which
> >>>>>>already does readl_relaxed etc.. If Tony feels like, then we should
> >>>>>>probably post a branch based on 'be' branch for easy merge.
> >
> >This should be a trivial merge conflict to handle, so let's not base
> >things on the BE changes.
> >
> >>>>I think all of these fails are caused by the initially bugged
> >>>>Makefile + Kconfig under mach-omap2. Seems like they can be fixed by
> >>>>the patches I inlined at the end (will also post them as proper
> >>>>patches to l-o list after this.) The question is, should Mike go
> >>>>ahead and merge these along with the base clk patches or how should
> >>>>we handle them? Patch 1 must be merged, patch 2 is a nice to have one
> >>>>which allows DRA7 only builds (doing DRA7 only build currently seems
> >>>>not possible.)
> >>>
> >>>If it's OK with Tony, I would suggest having a branch with both patches
> >>>below which both Tony and Mike merge before merging CCF series. That way
> >>>we avoid bisection problems.
> >
> >I can queue those two separately as fixes.
> >
> >>That reminds me, I think the baseline branch for the mach-omap2
> >>patches is still somewhat unclear to me, what should be used for
> >>this? And which patches should be put there (the mach-omap2 patches
> >>depend on the drivers/clk/ti part basically, so I need to put at
> >>least those there also.)
> >
> >I would keep the clock patches against some mainline -rc commit if
> >possible, and if there are non trivial merge conflicts, the omap
> >to use as the base is commit adfe9361b236154215d4b0fc8b6d79995394b15c.
> >
> >In any case, it's probably best that Mike merges this all via his
> >clock tree unless there non-trivial merge conflicts.
> >
> 
> I just pushed a branch against rc7 with makefile fixes in place to
> fix omap1 and omap2 only builds for this stuff. Inlined the delta
> here at the end. Do you want me to repost the series as v14 for this
> or is the attached delta ok for review purposes? All the changes have
> been squashed to existing patches (except the 2 patches I posted
> separately for DRA7xx / AM43xx only builds.)
> 
> The test branch itself can be found here:
> 
> tree: https://github.com/t-kristo/linux-pm.git
> branch: 3.13-rc7-dt-clks-v13-build-fixes
> 
> Felipe, care to run your randconfig magic for this?

This branch builds just fine so far, I still have omap5 multiplaform and
uniplatform builds, but since that was working before i'm assuming it
won't break.

cheers

-- 
balbi

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Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Felipe Balbi]

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Hi,

On Tue, Jan 14, 2014 at 02:36:13PM -0600, Felipe Balbi wrote:
> > Felipe, care to run your randconfig magic for this?
> 
> This branch builds just fine so far, I still have omap5 multiplaform and
> uniplatform builds, but since that was working before i'm assuming it
> won't break.

No build failures in any of my 18 seeds (5 randconfigs of each), I'd
attach logs, but it's a 2.8MiB tarball, if anyone cares enough, I can
send it.

FWIW:

Acked-by: Felipe Balbi <balbi@ti.com>

cheers

-- 
balbi

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Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Mike Turquette]

Quoting Felipe Balbi (2014-01-14 18:04:21)
> Hi,
> 
> On Tue, Jan 14, 2014 at 02:36:13PM -0600, Felipe Balbi wrote:
> > > Felipe, care to run your randconfig magic for this?
> > 
> > This branch builds just fine so far, I still have omap5 multiplaform and
> > uniplatform builds, but since that was working before i'm assuming it
> > won't break.
> 
> No build failures in any of my 18 seeds (5 randconfigs of each), I'd
> attach logs, but it's a 2.8MiB tarball, if anyone cares enough, I can
> send it.
> 
> FWIW:
> 
> Acked-by: Felipe Balbi <balbi@ti.com>

Felipe,

That's great to hear. Thanks for testing.

Tero & Tony,

These 40 patches apply very cleanly on top of clk-next with 2
exceptions:

1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock data"
because I do not have arch/arm/boot/dts/am3517.dtsi in clk-next (based
on 3.13-rc1).

2) Minor merge conflict in arch/arm/boot/dts/omap3.dtsi which I think I
resolved correctly but would like verification.

I'd prefer to simply merge these patches into clk-next, which is the
most straightforward route. Any ideas on how to handle the missing
AM35xx dtsi data? It can always go as a separate fix after this stuff
gets merged which, ironically, is how that file was created in the first
place.

Regards,
Mike

> 
> cheers
> 
> -- 
> balbi

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Mike Turquette]

Quoting Mike Turquette (2014-01-14 19:16:32)
> Quoting Felipe Balbi (2014-01-14 18:04:21)
> > Hi,
> > 
> > On Tue, Jan 14, 2014 at 02:36:13PM -0600, Felipe Balbi wrote:
> > > > Felipe, care to run your randconfig magic for this?
> > > 
> > > This branch builds just fine so far, I still have omap5 multiplaform and
> > > uniplatform builds, but since that was working before i'm assuming it
> > > won't break.
> > 
> > No build failures in any of my 18 seeds (5 randconfigs of each), I'd
> > attach logs, but it's a 2.8MiB tarball, if anyone cares enough, I can
> > send it.
> > 
> > FWIW:
> > 
> > Acked-by: Felipe Balbi <balbi@ti.com>
> 
> Felipe,
> 
> That's great to hear. Thanks for testing.
> 
> Tero & Tony,
> 
> These 40 patches apply very cleanly on top of clk-next with 2
> exceptions:
> 
> 1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock data"
> because I do not have arch/arm/boot/dts/am3517.dtsi in clk-next (based
> on 3.13-rc1).
> 
> 2) Minor merge conflict in arch/arm/boot/dts/omap3.dtsi which I think I
> resolved correctly but would like verification.
> 
> I'd prefer to simply merge these patches into clk-next, which is the
> most straightforward route. Any ideas on how to handle the missing
> AM35xx dtsi data? It can always go as a separate fix after this stuff
> gets merged which, ironically, is how that file was created in the first
> place.

I've pushed my branch. Tero can you take a look and let me know if you
see any problems?

git://git.linaro.org/people/mike.turquette/linux.git clk-next-omap

Thanks!
Mike

> 
> Regards,
> Mike
> 
> > 
> > cheers
> > 
> > -- 
> > balbi

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tero Kristo]

On 01/15/2014 05:50 AM, Mike Turquette wrote:
> Quoting Mike Turquette (2014-01-14 19:16:32)
>> Quoting Felipe Balbi (2014-01-14 18:04:21)
>>> Hi,
>>>
>>> On Tue, Jan 14, 2014 at 02:36:13PM -0600, Felipe Balbi wrote:
>>>>> Felipe, care to run your randconfig magic for this?
>>>>
>>>> This branch builds just fine so far, I still have omap5 multiplaform and
>>>> uniplatform builds, but since that was working before i'm assuming it
>>>> won't break.
>>>
>>> No build failures in any of my 18 seeds (5 randconfigs of each), I'd
>>> attach logs, but it's a 2.8MiB tarball, if anyone cares enough, I can
>>> send it.
>>>
>>> FWIW:
>>>
>>> Acked-by: Felipe Balbi <balbi@ti.com>
>>
>> Felipe,
>>
>> That's great to hear. Thanks for testing.
>>
>> Tero & Tony,
>>
>> These 40 patches apply very cleanly on top of clk-next with 2
>> exceptions:
>>
>> 1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock data"
>> because I do not have arch/arm/boot/dts/am3517.dtsi in clk-next (based
>> on 3.13-rc1).
>>
>> 2) Minor merge conflict in arch/arm/boot/dts/omap3.dtsi which I think I
>> resolved correctly but would like verification.
>>
>> I'd prefer to simply merge these patches into clk-next, which is the
>> most straightforward route. Any ideas on how to handle the missing
>> AM35xx dtsi data? It can always go as a separate fix after this stuff
>> gets merged which, ironically, is how that file was created in the first
>> place.
>
> I've pushed my branch. Tero can you take a look and let me know if you
> see any problems?
>
> git://git.linaro.org/people/mike.turquette/linux.git clk-next-omap

Hey Mike,

Can't see any issues there, also gave it a quick boot test with the 
boards I have access to and seems to work fine.

-Tero

>
> Thanks!
> Mike
>
>>
>> Regards,
>> Mike
>>
>>>
>>> cheers
>>>
>>> --
>>> balbi

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Nishanth Menon]

On 01/15/2014 07:41 AM, Tero Kristo wrote:
> On 01/15/2014 05:50 AM, Mike Turquette wrote:
>> Quoting Mike Turquette (2014-01-14 19:16:32)
>>> Quoting Felipe Balbi (2014-01-14 18:04:21)
>>>> Hi,
>>>>
>>>> On Tue, Jan 14, 2014 at 02:36:13PM -0600, Felipe Balbi wrote:
>>>>>> Felipe, care to run your randconfig magic for this?
>>>>>
>>>>> This branch builds just fine so far, I still have omap5 multiplaform and
>>>>> uniplatform builds, but since that was working before i'm assuming it
>>>>> won't break.
>>>>
>>>> No build failures in any of my 18 seeds (5 randconfigs of each), I'd
>>>> attach logs, but it's a 2.8MiB tarball, if anyone cares enough, I can
>>>> send it.
>>>>
>>>> FWIW:
>>>>
>>>> Acked-by: Felipe Balbi <balbi@ti.com>
>>>
>>> Felipe,
>>>
>>> That's great to hear. Thanks for testing.
>>>
>>> Tero & Tony,
>>>
>>> These 40 patches apply very cleanly on top of clk-next with 2
>>> exceptions:
>>>
>>> 1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock data"
>>> because I do not have arch/arm/boot/dts/am3517.dtsi in clk-next (based
>>> on 3.13-rc1).
>>>
>>> 2) Minor merge conflict in arch/arm/boot/dts/omap3.dtsi which I think I
>>> resolved correctly but would like verification.
>>>
>>> I'd prefer to simply merge these patches into clk-next, which is the
>>> most straightforward route. Any ideas on how to handle the missing
>>> AM35xx dtsi data? It can always go as a separate fix after this stuff
>>> gets merged which, ironically, is how that file was created in the first
>>> place.
>>
>> I've pushed my branch. Tero can you take a look and let me know if you
>> see any problems?
>>
>> git://git.linaro.org/people/mike.turquette/linux.git clk-next-omap
> 
> Hey Mike,
> 
> Can't see any issues there, also gave it a quick boot test with the 
> boards I have access to and seems to work fine.
> 
Here are the logs with commit 12d0a30a45e3a85463a6cb2a9e886192e3123892
( i need an additional patch for legacy platform testing).

 1: am335x-evm: http://slexy.org/raw/s215zNjZFv
 2:  am335x-sk: http://slexy.org/raw/s20uTrPG7V
 3: am3517-evm: http://slexy.org/raw/s21XPhGMCt
(we should be based on .13-rc4 to get am3517 baseline patches -> So
due to the dropped am3517 patch, we stop booting here).
 4:  am37x-evm: http://slexy.org/raw/s20W2nuCQa
 5: am43xx-epos: http://slexy.org/raw/s2I2qc961B (no boot yet)
 6:    beag-xm: http://slexy.org/raw/s210lX2EvT
 7: bone-black: http://slexy.org/raw/s2NgHa78JC (still have the
fixed-regulator bug in rc1 so, wont boot to shell at rc1)
 8: am3517-crane: http://slexy.org/raw/s2r1Bt4Hk2 (need benoit'
for-next to boot)
 9:       dra7: http://slexy.org/raw/s21UWF0yYd (same fixed regulator
issue)
10:        ldp: http://slexy.org/raw/s2oWL6qt2t (dts for this is
pending merge in Tony's next)
11:    panda-es: http://slexy.org/raw/s20NEXs51M
12:    sdp2430: http://slexy.org/raw/s21kyDYjfk (dts for this pending
in Tony's next)
13:    sdp3430: http://slexy.org/raw/s2EYHpcAW0
14:    sdp4430: http://slexy.org/raw/s2QPK7cBUP
15:       uevm: http://slexy.org/raw/s21mMF6kN3 (same regulator stuff
kicks again)


am3517-evm is concerning for 14-rc1 boot, am43xx-epos looks concerning
too(not sure if there are follow on fixes in later rcs that allow it
to boot)
- considering that both did work on tests that I did based on next[1],
only thing i am concerned in am3517 patch dropped in clk-next-omap.

- will be good to get this merged on clk-next and see what we can get
results on linux-next tag.


[1] http://marc.info/?l=devicetree&m=138930255330882&w=2

-- 
Regards,
Nishanth Menon

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tony Lindgren]

* Mike Turquette <mturquette@linaro.org> [140114 19:52]:
> > 
> > These 40 patches apply very cleanly on top of clk-next with 2
> > exceptions:
> > 
> > 1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock data"
> > because I do not have arch/arm/boot/dts/am3517.dtsi in clk-next (based
> > on 3.13-rc1).
> > 
> > 2) Minor merge conflict in arch/arm/boot/dts/omap3.dtsi which I think I
> > resolved correctly but would like verification.
> > 
> > I'd prefer to simply merge these patches into clk-next, which is the
> > most straightforward route. Any ideas on how to handle the missing
> > AM35xx dtsi data? It can always go as a separate fix after this stuff
> > gets merged which, ironically, is how that file was created in the first
> > place.

You could do something like this to take advantage of fast forward and
not have to do a merge back from mainline:

$ git checkout -b am3517-clk v3.13-rc8 # or any other -rc with am3517.dtsi
$ git merge clk-next-omap # this fast forwards clk-next-omap to the desired -rc
$ git am am3517-clk-patch
$ git checkout clk-next
$ git merge clk-next-omap # this fast forwards clk-next to the desired -rc

Regards,

Tony 

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Mike Turquette]

Quoting Tony Lindgren (2014-01-15 09:13:23)
> * Mike Turquette <mturquette@linaro.org> [140114 19:52]:
> > > 
> > > These 40 patches apply very cleanly on top of clk-next with 2
> > > exceptions:
> > > 
> > > 1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock data"
> > > because I do not have arch/arm/boot/dts/am3517.dtsi in clk-next (based
> > > on 3.13-rc1).
> > > 
> > > 2) Minor merge conflict in arch/arm/boot/dts/omap3.dtsi which I think I
> > > resolved correctly but would like verification.
> > > 
> > > I'd prefer to simply merge these patches into clk-next, which is the
> > > most straightforward route. Any ideas on how to handle the missing
> > > AM35xx dtsi data? It can always go as a separate fix after this stuff
> > > gets merged which, ironically, is how that file was created in the first
> > > place.
> 
> You could do something like this to take advantage of fast forward and
> not have to do a merge back from mainline:
> 
> $ git checkout -b am3517-clk v3.13-rc8 # or any other -rc with am3517.dtsi
> $ git merge clk-next-omap # this fast forwards clk-next-omap to the desired -rc
> $ git am am3517-clk-patch
> $ git checkout clk-next
> $ git merge clk-next-omap # this fast forwards clk-next to the desired -rc

Tony,

That makes sense, but is there anything bad about doing that for a
branch you intend to send as a pull request? I don't see how any of the
commits get re-written or anything... I just wonder if there is some
subtlety that I am not accounting for that makes this approach bad for
sending to Linus.

Regards,
Mike

> 
> Regards,
> 
> Tony 

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tony Lindgren]

* Mike Turquette <mturquette@linaro.org> [140115 11:25]:
> Quoting Tony Lindgren (2014-01-15 09:13:23)
> > * Mike Turquette <mturquette@linaro.org> [140114 19:52]:
> > > > 
> > > > These 40 patches apply very cleanly on top of clk-next with 2
> > > > exceptions:
> > > > 
> > > > 1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock data"
> > > > because I do not have arch/arm/boot/dts/am3517.dtsi in clk-next (based
> > > > on 3.13-rc1).
> > > > 
> > > > 2) Minor merge conflict in arch/arm/boot/dts/omap3.dtsi which I think I
> > > > resolved correctly but would like verification.
> > > > 
> > > > I'd prefer to simply merge these patches into clk-next, which is the
> > > > most straightforward route. Any ideas on how to handle the missing
> > > > AM35xx dtsi data? It can always go as a separate fix after this stuff
> > > > gets merged which, ironically, is how that file was created in the first
> > > > place.
> > 
> > You could do something like this to take advantage of fast forward and
> > not have to do a merge back from mainline:
> > 
> > $ git checkout -b am3517-clk v3.13-rc8 # or any other -rc with am3517.dtsi
> > $ git merge clk-next-omap # this fast forwards clk-next-omap to the desired -rc
> > $ git am am3517-clk-patch
> > $ git checkout clk-next
> > $ git merge clk-next-omap # this fast forwards clk-next to the desired -rc
> 
> That makes sense, but is there anything bad about doing that for a
> branch you intend to send as a pull request? I don't see how any of the
> commits get re-written or anything... I just wonder if there is some
> subtlety that I am not accounting for that makes this approach bad for
> sending to Linus.

No there should not be any issues. That's the preferred way to keep
development branches updated and pullable in long term without any need
to rebase.

Note that there will be only a merge commit if there is a conflict,
otherwise the fast forward will be transparent. So the trick to avoiding
rebasing and back merges is to apply patches against what they need in a
local branch, then after testing merge that local branch into the development
branch. Then for the upsteam pull request, you just need to make it against
the -rc you merged in.

AFAIK what Linus does not like is doing a back merge to a development
branch from mainline, probably as it adds a pointless commit. Or rebasing
a branch as that way it won't stay pullable.

Regards,

Tony

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Mike Turquette]

Quoting Tony Lindgren (2014-01-15 11:35:48)
> * Mike Turquette <mturquette@linaro.org> [140115 11:25]:
> > Quoting Tony Lindgren (2014-01-15 09:13:23)
> > > * Mike Turquette <mturquette@linaro.org> [140114 19:52]:
> > > > > 
> > > > > These 40 patches apply very cleanly on top of clk-next with 2
> > > > > exceptions:
> > > > > 
> > > > > 1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock data"
> > > > > because I do not have arch/arm/boot/dts/am3517.dtsi in clk-next (based
> > > > > on 3.13-rc1).
> > > > > 
> > > > > 2) Minor merge conflict in arch/arm/boot/dts/omap3.dtsi which I think I
> > > > > resolved correctly but would like verification.
> > > > > 
> > > > > I'd prefer to simply merge these patches into clk-next, which is the
> > > > > most straightforward route. Any ideas on how to handle the missing
> > > > > AM35xx dtsi data? It can always go as a separate fix after this stuff
> > > > > gets merged which, ironically, is how that file was created in the first
> > > > > place.
> > > 
> > > You could do something like this to take advantage of fast forward and
> > > not have to do a merge back from mainline:
> > > 
> > > $ git checkout -b am3517-clk v3.13-rc8 # or any other -rc with am3517.dtsi
> > > $ git merge clk-next-omap # this fast forwards clk-next-omap to the desired -rc
> > > $ git am am3517-clk-patch
> > > $ git checkout clk-next
> > > $ git merge clk-next-omap # this fast forwards clk-next to the desired -rc
> > 
> > That makes sense, but is there anything bad about doing that for a
> > branch you intend to send as a pull request? I don't see how any of the
> > commits get re-written or anything... I just wonder if there is some
> > subtlety that I am not accounting for that makes this approach bad for
> > sending to Linus.
> 
> No there should not be any issues. That's the preferred way to keep
> development branches updated and pullable in long term without any need
> to rebase.
> 
> Note that there will be only a merge commit if there is a conflict,
> otherwise the fast forward will be transparent. So the trick to avoiding
> rebasing and back merges is to apply patches against what they need in a
> local branch, then after testing merge that local branch into the development
> branch. Then for the upsteam pull request, you just need to make it against
> the -rc you merged in.
> 
> AFAIK what Linus does not like is doing a back merge to a development
> branch from mainline, probably as it adds a pointless commit. Or rebasing
> a branch as that way it won't stay pullable.

Hi all,

I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
Tero's series. This includes the AM3517 bits now. I've pushed this
branch to clk-next-omap (force update) on my Linaro mirror. Can you do a
final sanity test before I merge this into clk-next?

Thanks!
Mike

> 
> Regards,
> 
> Tony

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Nishanth Menon]

On 01/16/2014 03:39 PM, Mike Turquette wrote:
> Quoting Tony Lindgren (2014-01-15 11:35:48)
>> * Mike Turquette <mturquette@linaro.org> [140115 11:25]:
>>> Quoting Tony Lindgren (2014-01-15 09:13:23)
>>>> * Mike Turquette <mturquette@linaro.org> [140114 19:52]:
>>>>>>
>>>>>> These 40 patches apply very cleanly on top of clk-next with 2
>>>>>> exceptions:
>>>>>>
>>>>>> 1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock data"
>>>>>> because I do not have arch/arm/boot/dts/am3517.dtsi in clk-next (based
>>>>>> on 3.13-rc1).
>>>>>>
>>>>>> 2) Minor merge conflict in arch/arm/boot/dts/omap3.dtsi which I think I
>>>>>> resolved correctly but would like verification.
>>>>>>
>>>>>> I'd prefer to simply merge these patches into clk-next, which is the
>>>>>> most straightforward route. Any ideas on how to handle the missing
>>>>>> AM35xx dtsi data? It can always go as a separate fix after this stuff
>>>>>> gets merged which, ironically, is how that file was created in the first
>>>>>> place.
>>>>
>>>> You could do something like this to take advantage of fast forward and
>>>> not have to do a merge back from mainline:
>>>>
>>>> $ git checkout -b am3517-clk v3.13-rc8 # or any other -rc with am3517.dtsi
>>>> $ git merge clk-next-omap # this fast forwards clk-next-omap to the desired -rc
>>>> $ git am am3517-clk-patch
>>>> $ git checkout clk-next
>>>> $ git merge clk-next-omap # this fast forwards clk-next to the desired -rc
>>>
>>> That makes sense, but is there anything bad about doing that for a
>>> branch you intend to send as a pull request? I don't see how any of the
>>> commits get re-written or anything... I just wonder if there is some
>>> subtlety that I am not accounting for that makes this approach bad for
>>> sending to Linus.
>>
>> No there should not be any issues. That's the preferred way to keep
>> development branches updated and pullable in long term without any need
>> to rebase.
>>
>> Note that there will be only a merge commit if there is a conflict,
>> otherwise the fast forward will be transparent. So the trick to avoiding
>> rebasing and back merges is to apply patches against what they need in a
>> local branch, then after testing merge that local branch into the development
>> branch. Then for the upsteam pull request, you just need to make it against
>> the -rc you merged in.
>>
>> AFAIK what Linus does not like is doing a back merge to a development
>> branch from mainline, probably as it adds a pointless commit. Or rebasing
>> a branch as that way it won't stay pullable.
> 
> Hi all,
> 
> I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
> Tero's series. This includes the AM3517 bits now. I've pushed this
> branch to clk-next-omap (force update) on my Linaro mirror. Can you do a
> final sanity test before I merge this into clk-next?

multi_v7_defconfig:
 1: am335x-evm:  Boot FAIL: http://slexy.org/raw/s25jHnIctr
mmc/regulator missing stuff
 2:  am335x-sk:  Boot FAIL: http://slexy.org/raw/s2e9oDkTbD
mmc/regulator missing stuff
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s2KL4qBOM6
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s20jAHD1DE
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21vXGDma7
 6:       beag:  Boot PASS: http://slexy.org/raw/s25ZJgkM9q
 7:       bone:  Boot PASS: http://slexy.org/raw/s21U0U2lVW
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot FAIL: http://slexy.org/raw/s24d4sXtTh
CONFIG_SOC_DRA7XX not present in multi_v7
10:        ldp: No Image built - Missing platform support?:
11:      panda:  Boot PASS: http://slexy.org/raw/s21KrJmEWB
12:    sdp2430: No Image built - Missing platform support?:
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s21uwA3Swz
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s21GE8FOPC
15:       uevm:  Boot FAIL: http://slexy.org/raw/s2E3NAziyb
mmc/regulator missing stuff
TOTAL = 15 boards, Booted Boards = 8, No Boot boards = 7

omap2plus_defconfig:
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2euW1YeS0
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s2nxn1i5Ea
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s20knQQExn
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s21L1hfSHF
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s2EpSMvtnF
 6:       beag:  Boot PASS: http://slexy.org/raw/s21Z8ytsMS
 7:       bone:  Boot PASS: http://slexy.org/raw/s21ZpxRieJ
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot PASS: http://slexy.org/raw/s2owXcv5DW
10:        ldp: No Image built - Missing platform support?:
11:      panda:  Boot PASS: http://slexy.org/raw/s215rSL4p0
12:    sdp2430: No Image built - Missing platform support?:
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s21dxlFJn7
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s20WIfzRqi
15:       uevm:  Boot PASS: http://slexy.org/raw/s20Ba9mBTv
TOTAL = 15 boards, Booted Boards = 12, No Boot boards = 3

the 3 no image built boards have pending dts patches in for-next from
Tony and Benoit. So, linux-next should eventually be good.

As far as I see: the test results are equivalent to the branch that
Tero posted.

Thanks for the patience and effort :).
-- 
Regards,
Nishanth Menon

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Kevin Hilman]

Mike Turquette <mturquette@linaro.org> writes:

[...]

> I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
> Tero's series. This includes the AM3517 bits now. I've pushed this
> branch to clk-next-omap (force update) on my Linaro mirror. Can you do a
> final sanity test before I merge this into clk-next?

I merged clk-next-omap into next-20140117 and build/boot tested
omap2plus_defconfig, multi_v7_defconfig and
multi_v7_defconfig+CONFIG_LPAE=y and all passed a basic boot test for
omap5uevm.

I'll add OMAP5 to the automated boot testing starting with the next
linux-next.

Kevin

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tony Lindgren]

* Kevin Hilman <khilman@linaro.org> [140117 09:48]:
> Mike Turquette <mturquette@linaro.org> writes:
> 
> [...]
> 
> > I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
> > Tero's series. This includes the AM3517 bits now. I've pushed this
> > branch to clk-next-omap (force update) on my Linaro mirror. Can you do a
> > final sanity test before I merge this into clk-next?
> 
> I merged clk-next-omap into next-20140117 and build/boot tested
> omap2plus_defconfig, multi_v7_defconfig and
> multi_v7_defconfig+CONFIG_LPAE=y and all passed a basic boot test for
> omap5uevm.
> 
> I'll add OMAP5 to the automated boot testing starting with the next
> linux-next.

OK that's good news. Looks like omap1_defconfig build has now started
failing though:

vers/built-in.o: In function `omap5xxx_dt_clk_init':
:(.init.text+0x846c): undefined reference to `omap2_clk_disable_autoidle_all'
drivers/built-in.o: In function `am43xx_dt_clk_init':
:(.init.text+0x856c): undefined reference to `omap2_clk_disable_autoidle_all'
drivers/built-in.o:(.rodata+0xc3c4): undefined reference to `omap3_clkoutx2_recalc'
drivers/built-in.o:(.rodata+0xc40c): undefined reference to `omap3_noncore_dpll_enable'
drivers/built-in.o:(.rodata+0xc410): undefined reference to `omap3_noncore_dpll_disable'
drivers/built-in.o:(.rodata+0xc41c): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0xc420): undefined reference to `omap2_dpll_round_rate'
drivers/built-in.o:(.rodata+0xc42c): undefined reference to `omap2_init_dpll_parent'
drivers/built-in.o:(.rodata+0xc430): undefined reference to `omap3_noncore_dpll_set_rate'
drivers/built-in.o:(.rodata+0xc470): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0xc474): undefined reference to `omap2_dpll_round_rate'
drivers/built-in.o:(.rodata+0xc480): undefined reference to `omap2_init_dpll_parent'
drivers/built-in.o:(.rodata+0xc4a0): undefined reference to `omap3_noncore_dpll_enable'
drivers/built-in.o:(.rodata+0xc4a4): undefined reference to `omap3_noncore_dpll_disable'
drivers/built-in.o:(.rodata+0xc4b0): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0xc4b4): undefined reference to `omap2_dpll_round_rate'
drivers/built-in.o:(.rodata+0xc4c0): undefined reference to `omap2_init_dpll_parent'
drivers/built-in.o:(.rodata+0xc4c4): undefined reference to `omap3_dpll4_set_rate'
drivers/built-in.o:(.rodata+0xc4e0): undefined reference to `omap3_noncore_dpll_enable'
drivers/built-in.o:(.rodata+0xc4e4): undefined reference to `omap3_noncore_dpll_disable'
drivers/built-in.o:(.rodata+0xc4f0): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0xc4f4): undefined reference to `omap2_dpll_round_rate'
drivers/built-in.o:(.rodata+0xc500): undefined reference to `omap2_init_dpll_parent'
drivers/built-in.o:(.rodata+0xc504): undefined reference to `omap3_noncore_dpll_set_rate'
drivers/built-in.o:(.rodata+0xc530): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0xc540): undefined reference to `omap2_init_dpll_parent'
drivers/built-in.o:(.rodata+0xc560): undefined reference to `omap3_noncore_dpll_enable'
drivers/built-in.o:(.rodata+0xc564): undefined reference to `omap3_noncore_dpll_disable'
drivers/built-in.o:(.rodata+0xc570): undefined reference to `omap4_dpll_regm4xen_recalc'
drivers/built-in.o:(.rodata+0xc574): undefined reference to `omap4_dpll_regm4xen_round_rate'
drivers/built-in.o:(.rodata+0xc580): undefined reference to `omap2_init_dpll_parent'
drivers/built-in.o:(.rodata+0xc584): undefined reference to `omap3_noncore_dpll_set_rate'
drivers/built-in.o:(.rodata+0xc5b0): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0xc5b4): undefined reference to `omap2_dpll_round_rate'
drivers/built-in.o:(.rodata+0xc5c0): undefined reference to `omap2_init_dpll_parent'
drivers/built-in.o:(.rodata+0xc5c4): undefined reference to `omap3_noncore_dpll_set_rate'
drivers/built-in.o:(.rodata+0xc63c): undefined reference to `omap2_dflt_clk_enable'
drivers/built-in.o:(.rodata+0xc640): undefined reference to `omap2_dflt_clk_disable'
drivers/built-in.o:(.rodata+0xc644): undefined reference to `omap2_dflt_clk_is_enabled'
drivers/built-in.o:(.rodata+0xc728): undefined reference to `omap2_clkops_enable_clkdm'
drivers/built-in.o:(.rodata+0xc72c): undefined reference to `omap2_clkops_disable_clkdm'
drivers/built-in.o:(.rodata+0xc754): undefined reference to `omap2_init_clk_clkdm'
drivers/built-in.o:(.rodata+0xc784): undefined reference to `omap2_dflt_clk_disable'
drivers/built-in.o:(.rodata+0xc788): undefined reference to `omap2_dflt_clk_is_enabled'
drivers/built-in.o:(.rodata+0xc7ac): undefined reference to `omap2_init_clk_clkdm'
drivers/built-in.o:(.rodata+0xc7c0): undefined reference to `omap2_dflt_clk_enable'
drivers/built-in.o:(.rodata+0xc7c4): undefined reference to `omap2_dflt_clk_disable'
drivers/built-in.o:(.rodata+0xc7c8): undefined reference to `omap2_dflt_clk_is_enabled'
drivers/built-in.o:(.rodata+0xc7ec): undefined reference to `omap2_init_clk_clkdm'
drivers/built-in.o:(.rodata+0xc838): undefined reference to `__clk_mux_determine_rate'
drivers/built-in.o:(.rodata+0xc904): undefined reference to `omap2_dflt_clk_enable'
drivers/built-in.o:(.rodata+0xc908): undefined reference to `omap2_dflt_clk_disable'
drivers/built-in.o:(.rodata+0xc90c): undefined reference to `omap2_dflt_clk_is_enabled'
drivers/built-in.o:(.rodata+0xc930): undefined reference to `omap2_init_clk_clkdm'

Regards,

Tony

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tero Kristo]

On 01/17/2014 07:53 PM, Tony Lindgren wrote:
> * Kevin Hilman <khilman@linaro.org> [140117 09:48]:
>> Mike Turquette <mturquette@linaro.org> writes:
>>
>> [...]
>>
>>> I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
>>> Tero's series. This includes the AM3517 bits now. I've pushed this
>>> branch to clk-next-omap (force update) on my Linaro mirror. Can you do a
>>> final sanity test before I merge this into clk-next?

I think you accidentally merged wrong branch to clk-next-omap with the 
latest refresh. This is one is missing the build-fixes now, when it 
earlier had those in.

The correct branch to merge was 3.13-rc7-dt-clks-v13-build-fixes.

This also causes the build failure below for omap1.

-Tero

>>
>> I merged clk-next-omap into next-20140117 and build/boot tested
>> omap2plus_defconfig, multi_v7_defconfig and
>> multi_v7_defconfig+CONFIG_LPAE=y and all passed a basic boot test for
>> omap5uevm.
>>
>> I'll add OMAP5 to the automated boot testing starting with the next
>> linux-next.
>
> OK that's good news. Looks like omap1_defconfig build has now started
> failing though:
>
> vers/built-in.o: In function `omap5xxx_dt_clk_init':
> :(.init.text+0x846c): undefined reference to `omap2_clk_disable_autoidle_all'
> drivers/built-in.o: In function `am43xx_dt_clk_init':
> :(.init.text+0x856c): undefined reference to `omap2_clk_disable_autoidle_all'
> drivers/built-in.o:(.rodata+0xc3c4): undefined reference to `omap3_clkoutx2_recalc'
> drivers/built-in.o:(.rodata+0xc40c): undefined reference to `omap3_noncore_dpll_enable'
> drivers/built-in.o:(.rodata+0xc410): undefined reference to `omap3_noncore_dpll_disable'
> drivers/built-in.o:(.rodata+0xc41c): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc420): undefined reference to `omap2_dpll_round_rate'
> drivers/built-in.o:(.rodata+0xc42c): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc430): undefined reference to `omap3_noncore_dpll_set_rate'
> drivers/built-in.o:(.rodata+0xc470): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc474): undefined reference to `omap2_dpll_round_rate'
> drivers/built-in.o:(.rodata+0xc480): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc4a0): undefined reference to `omap3_noncore_dpll_enable'
> drivers/built-in.o:(.rodata+0xc4a4): undefined reference to `omap3_noncore_dpll_disable'
> drivers/built-in.o:(.rodata+0xc4b0): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc4b4): undefined reference to `omap2_dpll_round_rate'
> drivers/built-in.o:(.rodata+0xc4c0): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc4c4): undefined reference to `omap3_dpll4_set_rate'
> drivers/built-in.o:(.rodata+0xc4e0): undefined reference to `omap3_noncore_dpll_enable'
> drivers/built-in.o:(.rodata+0xc4e4): undefined reference to `omap3_noncore_dpll_disable'
> drivers/built-in.o:(.rodata+0xc4f0): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc4f4): undefined reference to `omap2_dpll_round_rate'
> drivers/built-in.o:(.rodata+0xc500): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc504): undefined reference to `omap3_noncore_dpll_set_rate'
> drivers/built-in.o:(.rodata+0xc530): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc540): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc560): undefined reference to `omap3_noncore_dpll_enable'
> drivers/built-in.o:(.rodata+0xc564): undefined reference to `omap3_noncore_dpll_disable'
> drivers/built-in.o:(.rodata+0xc570): undefined reference to `omap4_dpll_regm4xen_recalc'
> drivers/built-in.o:(.rodata+0xc574): undefined reference to `omap4_dpll_regm4xen_round_rate'
> drivers/built-in.o:(.rodata+0xc580): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc584): undefined reference to `omap3_noncore_dpll_set_rate'
> drivers/built-in.o:(.rodata+0xc5b0): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc5b4): undefined reference to `omap2_dpll_round_rate'
> drivers/built-in.o:(.rodata+0xc5c0): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc5c4): undefined reference to `omap3_noncore_dpll_set_rate'
> drivers/built-in.o:(.rodata+0xc63c): undefined reference to `omap2_dflt_clk_enable'
> drivers/built-in.o:(.rodata+0xc640): undefined reference to `omap2_dflt_clk_disable'
> drivers/built-in.o:(.rodata+0xc644): undefined reference to `omap2_dflt_clk_is_enabled'
> drivers/built-in.o:(.rodata+0xc728): undefined reference to `omap2_clkops_enable_clkdm'
> drivers/built-in.o:(.rodata+0xc72c): undefined reference to `omap2_clkops_disable_clkdm'
> drivers/built-in.o:(.rodata+0xc754): undefined reference to `omap2_init_clk_clkdm'
> drivers/built-in.o:(.rodata+0xc784): undefined reference to `omap2_dflt_clk_disable'
> drivers/built-in.o:(.rodata+0xc788): undefined reference to `omap2_dflt_clk_is_enabled'
> drivers/built-in.o:(.rodata+0xc7ac): undefined reference to `omap2_init_clk_clkdm'
> drivers/built-in.o:(.rodata+0xc7c0): undefined reference to `omap2_dflt_clk_enable'
> drivers/built-in.o:(.rodata+0xc7c4): undefined reference to `omap2_dflt_clk_disable'
> drivers/built-in.o:(.rodata+0xc7c8): undefined reference to `omap2_dflt_clk_is_enabled'
> drivers/built-in.o:(.rodata+0xc7ec): undefined reference to `omap2_init_clk_clkdm'
> drivers/built-in.o:(.rodata+0xc838): undefined reference to `__clk_mux_determine_rate'
> drivers/built-in.o:(.rodata+0xc904): undefined reference to `omap2_dflt_clk_enable'
> drivers/built-in.o:(.rodata+0xc908): undefined reference to `omap2_dflt_clk_disable'
> drivers/built-in.o:(.rodata+0xc90c): undefined reference to `omap2_dflt_clk_is_enabled'
> drivers/built-in.o:(.rodata+0xc930): undefined reference to `omap2_init_clk_clkdm'
>
> Regards,
>
> Tony
>

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Mike Turquette]

Quoting Tero Kristo (2014-01-17 10:11:06)
> On 01/17/2014 07:53 PM, Tony Lindgren wrote:
> > * Kevin Hilman <khilman@linaro.org> [140117 09:48]:
> >> Mike Turquette <mturquette@linaro.org> writes:
> >>
> >> [...]
> >>
> >>> I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
> >>> Tero's series. This includes the AM3517 bits now. I've pushed this
> >>> branch to clk-next-omap (force update) on my Linaro mirror. Can you do a
> >>> final sanity test before I merge this into clk-next?
> 
> I think you accidentally merged wrong branch to clk-next-omap with the 
> latest refresh. This is one is missing the build-fixes now, when it 
> earlier had those in.
> 
> The correct branch to merge was 3.13-rc7-dt-clks-v13-build-fixes.
> 
> This also causes the build failure below for omap1.

You are right. I broke the OMAPs. I force updated clk-next-omap (and
clk-next) with the correct branch this time.

Regards,
Mike

> 
> -Tero
> 
> >>
> >> I merged clk-next-omap into next-20140117 and build/boot tested
> >> omap2plus_defconfig, multi_v7_defconfig and
> >> multi_v7_defconfig+CONFIG_LPAE=y and all passed a basic boot test for
> >> omap5uevm.
> >>
> >> I'll add OMAP5 to the automated boot testing starting with the next
> >> linux-next.
> >
> > OK that's good news. Looks like omap1_defconfig build has now started
> > failing though:
> >
> > vers/built-in.o: In function `omap5xxx_dt_clk_init':
> > :(.init.text+0x846c): undefined reference to `omap2_clk_disable_autoidle_all'
> > drivers/built-in.o: In function `am43xx_dt_clk_init':
> > :(.init.text+0x856c): undefined reference to `omap2_clk_disable_autoidle_all'
> > drivers/built-in.o:(.rodata+0xc3c4): undefined reference to `omap3_clkoutx2_recalc'
> > drivers/built-in.o:(.rodata+0xc40c): undefined reference to `omap3_noncore_dpll_enable'
> > drivers/built-in.o:(.rodata+0xc410): undefined reference to `omap3_noncore_dpll_disable'
> > drivers/built-in.o:(.rodata+0xc41c): undefined reference to `omap3_dpll_recalc'
> > drivers/built-in.o:(.rodata+0xc420): undefined reference to `omap2_dpll_round_rate'
> > drivers/built-in.o:(.rodata+0xc42c): undefined reference to `omap2_init_dpll_parent'
> > drivers/built-in.o:(.rodata+0xc430): undefined reference to `omap3_noncore_dpll_set_rate'
> > drivers/built-in.o:(.rodata+0xc470): undefined reference to `omap3_dpll_recalc'
> > drivers/built-in.o:(.rodata+0xc474): undefined reference to `omap2_dpll_round_rate'
> > drivers/built-in.o:(.rodata+0xc480): undefined reference to `omap2_init_dpll_parent'
> > drivers/built-in.o:(.rodata+0xc4a0): undefined reference to `omap3_noncore_dpll_enable'
> > drivers/built-in.o:(.rodata+0xc4a4): undefined reference to `omap3_noncore_dpll_disable'
> > drivers/built-in.o:(.rodata+0xc4b0): undefined reference to `omap3_dpll_recalc'
> > drivers/built-in.o:(.rodata+0xc4b4): undefined reference to `omap2_dpll_round_rate'
> > drivers/built-in.o:(.rodata+0xc4c0): undefined reference to `omap2_init_dpll_parent'
> > drivers/built-in.o:(.rodata+0xc4c4): undefined reference to `omap3_dpll4_set_rate'
> > drivers/built-in.o:(.rodata+0xc4e0): undefined reference to `omap3_noncore_dpll_enable'
> > drivers/built-in.o:(.rodata+0xc4e4): undefined reference to `omap3_noncore_dpll_disable'
> > drivers/built-in.o:(.rodata+0xc4f0): undefined reference to `omap3_dpll_recalc'
> > drivers/built-in.o:(.rodata+0xc4f4): undefined reference to `omap2_dpll_round_rate'
> > drivers/built-in.o:(.rodata+0xc500): undefined reference to `omap2_init_dpll_parent'
> > drivers/built-in.o:(.rodata+0xc504): undefined reference to `omap3_noncore_dpll_set_rate'
> > drivers/built-in.o:(.rodata+0xc530): undefined reference to `omap3_dpll_recalc'
> > drivers/built-in.o:(.rodata+0xc540): undefined reference to `omap2_init_dpll_parent'
> > drivers/built-in.o:(.rodata+0xc560): undefined reference to `omap3_noncore_dpll_enable'
> > drivers/built-in.o:(.rodata+0xc564): undefined reference to `omap3_noncore_dpll_disable'
> > drivers/built-in.o:(.rodata+0xc570): undefined reference to `omap4_dpll_regm4xen_recalc'
> > drivers/built-in.o:(.rodata+0xc574): undefined reference to `omap4_dpll_regm4xen_round_rate'
> > drivers/built-in.o:(.rodata+0xc580): undefined reference to `omap2_init_dpll_parent'
> > drivers/built-in.o:(.rodata+0xc584): undefined reference to `omap3_noncore_dpll_set_rate'
> > drivers/built-in.o:(.rodata+0xc5b0): undefined reference to `omap3_dpll_recalc'
> > drivers/built-in.o:(.rodata+0xc5b4): undefined reference to `omap2_dpll_round_rate'
> > drivers/built-in.o:(.rodata+0xc5c0): undefined reference to `omap2_init_dpll_parent'
> > drivers/built-in.o:(.rodata+0xc5c4): undefined reference to `omap3_noncore_dpll_set_rate'
> > drivers/built-in.o:(.rodata+0xc63c): undefined reference to `omap2_dflt_clk_enable'
> > drivers/built-in.o:(.rodata+0xc640): undefined reference to `omap2_dflt_clk_disable'
> > drivers/built-in.o:(.rodata+0xc644): undefined reference to `omap2_dflt_clk_is_enabled'
> > drivers/built-in.o:(.rodata+0xc728): undefined reference to `omap2_clkops_enable_clkdm'
> > drivers/built-in.o:(.rodata+0xc72c): undefined reference to `omap2_clkops_disable_clkdm'
> > drivers/built-in.o:(.rodata+0xc754): undefined reference to `omap2_init_clk_clkdm'
> > drivers/built-in.o:(.rodata+0xc784): undefined reference to `omap2_dflt_clk_disable'
> > drivers/built-in.o:(.rodata+0xc788): undefined reference to `omap2_dflt_clk_is_enabled'
> > drivers/built-in.o:(.rodata+0xc7ac): undefined reference to `omap2_init_clk_clkdm'
> > drivers/built-in.o:(.rodata+0xc7c0): undefined reference to `omap2_dflt_clk_enable'
> > drivers/built-in.o:(.rodata+0xc7c4): undefined reference to `omap2_dflt_clk_disable'
> > drivers/built-in.o:(.rodata+0xc7c8): undefined reference to `omap2_dflt_clk_is_enabled'
> > drivers/built-in.o:(.rodata+0xc7ec): undefined reference to `omap2_init_clk_clkdm'
> > drivers/built-in.o:(.rodata+0xc838): undefined reference to `__clk_mux_determine_rate'
> > drivers/built-in.o:(.rodata+0xc904): undefined reference to `omap2_dflt_clk_enable'
> > drivers/built-in.o:(.rodata+0xc908): undefined reference to `omap2_dflt_clk_disable'
> > drivers/built-in.o:(.rodata+0xc90c): undefined reference to `omap2_dflt_clk_is_enabled'
> > drivers/built-in.o:(.rodata+0xc930): undefined reference to `omap2_init_clk_clkdm'
> >
> > Regards,
> >
> > Tony
> >
> 

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Nishanth Menon]

On 01/17/2014 02:58 PM, Mike Turquette wrote:
> Quoting Tero Kristo (2014-01-17 10:11:06)
>> On 01/17/2014 07:53 PM, Tony Lindgren wrote:
>>> * Kevin Hilman <khilman@linaro.org> [140117 09:48]:
>>>> Mike Turquette <mturquette@linaro.org> writes:
>>>>
>>>> [...]
>>>>
>>>>> I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
>>>>> Tero's series. This includes the AM3517 bits now. I've pushed this
>>>>> branch to clk-next-omap (force update) on my Linaro mirror. Can you do a
>>>>> final sanity test before I merge this into clk-next?
>>
>> I think you accidentally merged wrong branch to clk-next-omap with the 
>> latest refresh. This is one is missing the build-fixes now, when it 
>> earlier had those in.
>>
>> The correct branch to merge was 3.13-rc7-dt-clks-v13-build-fixes.
>>
>> This also causes the build failure below for omap1.
> 
> You are right. I broke the OMAPs. I force updated clk-next-omap (and
> clk-next) with the correct branch this time.

Build tests: omap1_defconfig:
clk-next-6a0cad9: builds fine
clk-next-6a0cad9 + next-20140117: http://slexy.org/view/s2HgtvUtAl
	disabling CONFIG_BT, builds fine

Boot tests: clk-next-6a0cad9, clk-next-6a0cad9 + next-20140117 : No
regressions seen

Detailed Boot logs:

clk-next-6a0cad9 omap2plus_defconfig:
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s21idEk2IZ
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s21Q4w8gWT
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s21dT7y2CA
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2VFaOtuDP
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s20L0DBt1d
 6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s20gKsdH3A
 7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s2ZXTJswqY
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot PASS: http://slexy.org/raw/s2XZfjQz67
10:        ldp: No Image built - Missing platform support?:
11:   panda-es:  Boot PASS: http://slexy.org/raw/s2ESRQgBbc
12:    sdp2430: No Image built - Missing platform support?:
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s2YsAO3ZPJ
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2MxxggHkh
15:       uevm:  Boot PASS: http://slexy.org/raw/s2wJT0B7wf
TOTAL = 15 boards, Booted Boards = 12, No Boot boards = 3

clk-next-6a0cad9 multi_v7_defconfig:
 1: am335x-evm:  Boot FAIL: http://slexy.org/raw/s21AXBDbM9
* regulator/mmc missing here
 2:  am335x-sk:  Boot FAIL: http://slexy.org/raw/s21pQPhupJ
* regulator/mmc missing here
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s21iM7TEiQ
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2pBD6nplU
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s2X9mnCKhT
 6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s21CjzZtZ6
 7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s2vCfnss8N
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot FAIL: http://slexy.org/raw/s21Xn4t22A
* DRA7 not enabled?
10:        ldp: No Image built - Missing platform support?:
11:   panda-es:  Boot PASS: http://slexy.org/raw/s21ZoijL9i
12:    sdp2430: No Image built - Missing platform support?:
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s21rdIfh7S
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s21HXFj9cw
15:       uevm:  Boot FAIL: http://slexy.org/raw/s21m26VdbI
* regulator/mmc missing here
TOTAL = 15 boards, Booted Boards = 8, No Boot boards = 7

clk-next-6a0cad9 multi_v7_defconfig+CONFIG_LPAE=y:
 1: am335x-evm:  Boot FAIL: http://slexy.org/raw/s21GIuprIx
* regulator/mmc missing here
 2:  am335x-sk:  Boot FAIL: http://slexy.org/raw/s20Vy6K9Rg
* regulator/mmc missing here
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s20jXaoTYq
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s20bk4uHcb
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s2gVGjYMXz
 6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s26D0F2N1t
 7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s2ThmugNzC
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot FAIL: http://slexy.org/raw/s21HdQFchd
* DRA7 not enabled?
10:        ldp: No Image built - Missing platform support?:
11:   panda-es:  Boot PASS: http://slexy.org/raw/s2042Y9Pyb
12:    sdp2430: No Image built - Missing platform support?:
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s2NCg8nLki
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s25GxRkWcj
15:       uevm:  Boot FAIL: http://slexy.org/raw/s2Q7xBYM3a
* regulator/mmc missing here
TOTAL = 15 boards, Booted Boards = 8, No Boot boards = 7


clk-next-6a0cad9 + next-20140117 omap2plus_defconfig:
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2ll3LdMN2
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s2jyAF2Och
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s20nPsCcUS
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2Rn7Vqh8x
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s2frIhnu6Y
 6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s2GNee8kHF
 7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s2G7fD4rGD
 8:      crane: No Image built - Missing platform support?: (pending
merge from Benoit)
 9:       dra7:  Boot PASS: http://slexy.org/raw/s21W2zLl5q
10:        ldp:  Boot FAIL: http://slexy.org/raw/s21518Tibq
* intermittent failures seen previously as well -> debug pending
11:   panda-es:  Boot PASS: http://slexy.org/raw/s20WddZMVp
12:    sdp2430:  Boot PASS: http://slexy.org/raw/s2cVr3BLLi
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s21h9oDSCv
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s21PWBCUKn
15:       uevm:  Boot PASS: http://slexy.org/raw/s2OxDQtC9E
TOTAL = 15 boards, Booted Boards = 13, No Boot boards = 2

clk-next-6a0cad9 + next-20140117 multi_v7_defconfig:
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s20MpjXQ71
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s2T0vnX8s7
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s2hvsW2oVi
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2Li1DqaeQ
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s2MHh0c19C
 6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s21RnOxxUk
 7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s2qaKF0lqp
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot FAIL: http://slexy.org/raw/s203u2hQ1m
* DRA7 not enabled?
10:        ldp:  Boot PASS: http://slexy.org/raw/s2ug8MyzzE
11:   panda-es:  Boot FAIL: http://slexy.org/raw/s2NVPvwb2I
* known issue (https://patchwork.kernel.org/patch/3084521/)
12:    sdp2430:  Boot FAIL: v6 platform - wont boot with multi_v7
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s28vswaDnc
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s21wk2lqiC
15:       uevm:  Boot PASS: http://slexy.org/raw/s21soF15Dy
TOTAL = 15 boards, Booted Boards = 11, No Boot boards = 4

clk-next-6a0cad9 + next-20140117 multi_v7_defconfig + CONFIG_LPAE=y:
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s21GRhEOj4
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s20zcNsD8h
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s27U9IfRKR
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2zYyeonec
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21iCRjTHK
 6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s20bPGL3Sz
 7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s21AhFmkCk
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot FAIL: http://slexy.org/raw/s21Qh3sQRu
* DRA7 not enabled?
10:        ldp:  Boot PASS: http://slexy.org/raw/s21fvBfBgs
11:   panda-es:  Boot FAIL: http://slexy.org/raw/s20RsgVUZJ
* known issue (https://patchwork.kernel.org/patch/3084521/)
12:    sdp2430:  Boot FAIL: v6 platform - wont boot with multi_v7
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s20rhjjBwe
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2My0UfNPm
15:       uevm:  Boot PASS: http://slexy.org/raw/s21aqF6eMN
TOTAL = 15 boards, Booted Boards = 11, No Boot boards = 4



-- 
Regards,
Nishanth Menon

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Olof Johansson]

On Fri, Jan 17, 2014 at 4:02 PM, Nishanth Menon <nm@ti.com> wrote:

> clk-next-6a0cad9 + next-20140117 multi_v7_defconfig + CONFIG_LPAE=y:
>  1: am335x-evm:  Boot PASS: http://slexy.org/raw/s21GRhEOj4
>  2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s20zcNsD8h
>  3: am3517-evm:  Boot PASS: http://slexy.org/raw/s27U9IfRKR
>  4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2zYyeonec
>  5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21iCRjTHK
>  6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s20bPGL3Sz
>  7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s21AhFmkCk
>  8:      crane: No Image built - Missing platform support?:
>  9:       dra7:  Boot FAIL: http://slexy.org/raw/s21Qh3sQRu
> * DRA7 not enabled?
> 10:        ldp:  Boot PASS: http://slexy.org/raw/s21fvBfBgs
> 11:   panda-es:  Boot FAIL: http://slexy.org/raw/s20RsgVUZJ
> * known issue (https://patchwork.kernel.org/patch/3084521/)
> 12:    sdp2430:  Boot FAIL: v6 platform - wont boot with multi_v7
> 13:    sdp3430:  Boot PASS: http://slexy.org/raw/s20rhjjBwe
> 14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2My0UfNPm
> 15:       uevm:  Boot PASS: http://slexy.org/raw/s21aqF6eMN
> TOTAL = 15 boards, Booted Boards = 11, No Boot boards = 4


I have a hard time believing the above; A8/A9 boards are not bootable
with CONFIG_LPAE=y...


-Olof

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Nishanth Menon]

On 01/17/2014 06:12 PM, Olof Johansson wrote:
> On Fri, Jan 17, 2014 at 4:02 PM, Nishanth Menon <nm@ti.com> wrote:
> 
>> clk-next-6a0cad9 + next-20140117 multi_v7_defconfig + CONFIG_LPAE=y:
>>  1: am335x-evm:  Boot PASS: http://slexy.org/raw/s21GRhEOj4
>>  2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s20zcNsD8h
>>  3: am3517-evm:  Boot PASS: http://slexy.org/raw/s27U9IfRKR
>>  4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2zYyeonec
>>  5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21iCRjTHK
>>  6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s20bPGL3Sz
>>  7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s21AhFmkCk
>>  8:      crane: No Image built - Missing platform support?:
>>  9:       dra7:  Boot FAIL: http://slexy.org/raw/s21Qh3sQRu
>> * DRA7 not enabled?
>> 10:        ldp:  Boot PASS: http://slexy.org/raw/s21fvBfBgs
>> 11:   panda-es:  Boot FAIL: http://slexy.org/raw/s20RsgVUZJ
>> * known issue (https://patchwork.kernel.org/patch/3084521/)
>> 12:    sdp2430:  Boot FAIL: v6 platform - wont boot with multi_v7
>> 13:    sdp3430:  Boot PASS: http://slexy.org/raw/s20rhjjBwe
>> 14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2My0UfNPm
>> 15:       uevm:  Boot PASS: http://slexy.org/raw/s21aqF6eMN
>> TOTAL = 15 boards, Booted Boards = 11, No Boot boards = 4
> 
> 
> I have a hard time believing the above; A8/A9 boards are not bootable
> with CONFIG_LPAE=y...

You are right! Drat!! I had CONFIG_LPAE=y in my script, not
CONFIG_ARM_LPAE=y! Grrr...

Retest in a around 30 mins..

-- 
Regards,
Nishanth Menon

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Olof Johansson]

On Fri, Jan 17, 2014 at 4:19 PM, Nishanth Menon <nm@ti.com> wrote:
> On 01/17/2014 06:12 PM, Olof Johansson wrote:
>> On Fri, Jan 17, 2014 at 4:02 PM, Nishanth Menon <nm@ti.com> wrote:
>>
>>> clk-next-6a0cad9 + next-20140117 multi_v7_defconfig + CONFIG_LPAE=y:
>>>  1: am335x-evm:  Boot PASS: http://slexy.org/raw/s21GRhEOj4
>>>  2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s20zcNsD8h
>>>  3: am3517-evm:  Boot PASS: http://slexy.org/raw/s27U9IfRKR
>>>  4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2zYyeonec
>>>  5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21iCRjTHK
>>>  6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s20bPGL3Sz
>>>  7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s21AhFmkCk
>>>  8:      crane: No Image built - Missing platform support?:
>>>  9:       dra7:  Boot FAIL: http://slexy.org/raw/s21Qh3sQRu
>>> * DRA7 not enabled?
>>> 10:        ldp:  Boot PASS: http://slexy.org/raw/s21fvBfBgs
>>> 11:   panda-es:  Boot FAIL: http://slexy.org/raw/s20RsgVUZJ
>>> * known issue (https://patchwork.kernel.org/patch/3084521/)
>>> 12:    sdp2430:  Boot FAIL: v6 platform - wont boot with multi_v7
>>> 13:    sdp3430:  Boot PASS: http://slexy.org/raw/s20rhjjBwe
>>> 14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2My0UfNPm
>>> 15:       uevm:  Boot PASS: http://slexy.org/raw/s21aqF6eMN
>>> TOTAL = 15 boards, Booted Boards = 11, No Boot boards = 4
>>
>>
>> I have a hard time believing the above; A8/A9 boards are not bootable
>> with CONFIG_LPAE=y...
>
> You are right! Drat!! I had CONFIG_LPAE=y in my script, not
> CONFIG_ARM_LPAE=y! Grrr...
>
> Retest in a around 30 mins..

It's not a huge concern though; it's unlikely that LPAE makes a
functional difference on this patch series. It's still useful to catch
warnings, etc (most likely printk formats and the like).


-Olof

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Nishanth Menon]

On 01/17/2014 06:23 PM, Olof Johansson wrote:
> On Fri, Jan 17, 2014 at 4:19 PM, Nishanth Menon <nm@ti.com> wrote:
>> On 01/17/2014 06:12 PM, Olof Johansson wrote:
>>> On Fri, Jan 17, 2014 at 4:02 PM, Nishanth Menon <nm@ti.com> wrote:
>>>
>>>> clk-next-6a0cad9 + next-20140117 multi_v7_defconfig + CONFIG_LPAE=y:
>>>>  1: am335x-evm:  Boot PASS: http://slexy.org/raw/s21GRhEOj4
>>>>  2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s20zcNsD8h
>>>>  3: am3517-evm:  Boot PASS: http://slexy.org/raw/s27U9IfRKR
>>>>  4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2zYyeonec
>>>>  5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21iCRjTHK
>>>>  6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s20bPGL3Sz
>>>>  7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s21AhFmkCk
>>>>  8:      crane: No Image built - Missing platform support?:
>>>>  9:       dra7:  Boot FAIL: http://slexy.org/raw/s21Qh3sQRu
>>>> * DRA7 not enabled?
>>>> 10:        ldp:  Boot PASS: http://slexy.org/raw/s21fvBfBgs
>>>> 11:   panda-es:  Boot FAIL: http://slexy.org/raw/s20RsgVUZJ
>>>> * known issue (https://patchwork.kernel.org/patch/3084521/)
>>>> 12:    sdp2430:  Boot FAIL: v6 platform - wont boot with multi_v7
>>>> 13:    sdp3430:  Boot PASS: http://slexy.org/raw/s20rhjjBwe
>>>> 14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2My0UfNPm
>>>> 15:       uevm:  Boot PASS: http://slexy.org/raw/s21aqF6eMN
>>>> TOTAL = 15 boards, Booted Boards = 11, No Boot boards = 4
>>>
>>>
>>> I have a hard time believing the above; A8/A9 boards are not bootable
>>> with CONFIG_LPAE=y...
>>
>> You are right! Drat!! I had CONFIG_LPAE=y in my script, not
>> CONFIG_ARM_LPAE=y! Grrr...
>>
>> Retest in a around 30 mins..
> 
> It's not a huge concern though; it's unlikely that LPAE makes a
> functional difference on this patch series. It's still useful to catch
> warnings, etc (most likely printk formats and the like).
> 
I suppose, as expected:
clk-next-6a0cad9 + next-20140117 multi_v7_defconfig + CONFIG_ARM_LPAE=y
* .config = http://slexy.org/view/s208uSeQS8
* Build warnings: http://slexy.org/raw/s20n7YwbwN
 1: am335x-evm:  Boot FAIL: http://slexy.org/raw/s20tF2eUZG
 2:  am335x-sk:  Boot FAIL: http://slexy.org/raw/s2uP65lOMQ
 3: am3517-evm:  Boot FAIL: http://slexy.org/raw/s2Lx13gsFZ
 4:  am37x-evm:  Boot FAIL: http://slexy.org/raw/s2eOLXxvsT
 5: am43xx-epos:  Boot FAIL: http://slexy.org/raw/s24coJzGvR
 6: BeagleBoard-XM:  Boot FAIL: http://slexy.org/raw/s240WznuPd
 7: BeagleBone-Black:  Boot FAIL: http://slexy.org/raw/s20NG2UVTU
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot FAIL: http://slexy.org/raw/s21T3RpHx2
^^ might probably boot if we enable CONFIG_SOC_DRA7XX in multi_v7
(this is another A15 target)
10:        ldp:  Boot FAIL: http://slexy.org/raw/s2F4VO9hDM
11: PandaBoard-ES:  Boot FAIL: http://slexy.org/raw/s20HpzT1jW
12:    sdp2430:  Boot FAIL: http://slexy.org/raw/s21snV1EvL
13:    sdp3430:  Boot FAIL: http://slexy.org/raw/s2FwkVfG5R
14:    sdp4430:  Boot FAIL: http://slexy.org/raw/s2xiWxlpTj
15:       uevm:  Boot PASS: http://slexy.org/raw/s2LWUOmfiG
TOTAL = 15 boards, Booted Boards = 1, No Boot boards = 14

I am running a defconfig set check on next-20140117 and will do one
with next-20140118 once that is ready for comparison results

-- 
Regards,
Nishanth Menon

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Sebastian Reichel]

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On Fri, Jan 17, 2014 at 07:20:06PM -0600, Nishanth Menon wrote:
> On 01/17/2014 06:23 PM, Olof Johansson wrote:
> > On Fri, Jan 17, 2014 at 4:19 PM, Nishanth Menon <nm@ti.com> wrote:
> >> On 01/17/2014 06:12 PM, Olof Johansson wrote:
> >>> On Fri, Jan 17, 2014 at 4:02 PM, Nishanth Menon <nm@ti.com> wrote:
> >>>
> >>>> clk-next-6a0cad9 + next-20140117 multi_v7_defconfig + CONFIG_LPAE=y:
> >>>>  1: am335x-evm:  Boot PASS: http://slexy.org/raw/s21GRhEOj4
> >>>>  2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s20zcNsD8h
> >>>>  3: am3517-evm:  Boot PASS: http://slexy.org/raw/s27U9IfRKR
> >>>>  4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2zYyeonec
> >>>>  5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21iCRjTHK
> >>>>  6: beagleboard-xm:  Boot PASS: http://slexy.org/raw/s20bPGL3Sz
> >>>>  7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s21AhFmkCk
> >>>>  8:      crane: No Image built - Missing platform support?:
> >>>>  9:       dra7:  Boot FAIL: http://slexy.org/raw/s21Qh3sQRu
> >>>> * DRA7 not enabled?
> >>>> 10:        ldp:  Boot PASS: http://slexy.org/raw/s21fvBfBgs
> >>>> 11:   panda-es:  Boot FAIL: http://slexy.org/raw/s20RsgVUZJ
> >>>> * known issue (https://patchwork.kernel.org/patch/3084521/)
> >>>> 12:    sdp2430:  Boot FAIL: v6 platform - wont boot with multi_v7
> >>>> 13:    sdp3430:  Boot PASS: http://slexy.org/raw/s20rhjjBwe
> >>>> 14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2My0UfNPm
> >>>> 15:       uevm:  Boot PASS: http://slexy.org/raw/s21aqF6eMN
> >>>> TOTAL = 15 boards, Booted Boards = 11, No Boot boards = 4
> >>>
> >>>
> >>> I have a hard time believing the above; A8/A9 boards are not bootable
> >>> with CONFIG_LPAE=y...
> >>
> >> You are right! Drat!! I had CONFIG_LPAE=y in my script, not
> >> CONFIG_ARM_LPAE=y! Grrr...
> >>
> >> Retest in a around 30 mins..
> > 
> > It's not a huge concern though; it's unlikely that LPAE makes a
> > functional difference on this patch series. It's still useful to catch
> > warnings, etc (most likely printk formats and the like).
> > 
> I suppose, as expected:
> clk-next-6a0cad9 + next-20140117 multi_v7_defconfig + CONFIG_ARM_LPAE=y
> * .config = http://slexy.org/view/s208uSeQS8
> * Build warnings: http://slexy.org/raw/s20n7YwbwN
>  1: am335x-evm:  Boot FAIL: http://slexy.org/raw/s20tF2eUZG
>  2:  am335x-sk:  Boot FAIL: http://slexy.org/raw/s2uP65lOMQ
>  3: am3517-evm:  Boot FAIL: http://slexy.org/raw/s2Lx13gsFZ
>  4:  am37x-evm:  Boot FAIL: http://slexy.org/raw/s2eOLXxvsT
>  5: am43xx-epos:  Boot FAIL: http://slexy.org/raw/s24coJzGvR
>  6: BeagleBoard-XM:  Boot FAIL: http://slexy.org/raw/s240WznuPd
>  7: BeagleBone-Black:  Boot FAIL: http://slexy.org/raw/s20NG2UVTU
>  8:      crane: No Image built - Missing platform support?:
>  9:       dra7:  Boot FAIL: http://slexy.org/raw/s21T3RpHx2
> ^^ might probably boot if we enable CONFIG_SOC_DRA7XX in multi_v7
> (this is another A15 target)
> 10:        ldp:  Boot FAIL: http://slexy.org/raw/s2F4VO9hDM
> 11: PandaBoard-ES:  Boot FAIL: http://slexy.org/raw/s20HpzT1jW
> 12:    sdp2430:  Boot FAIL: http://slexy.org/raw/s21snV1EvL
> 13:    sdp3430:  Boot FAIL: http://slexy.org/raw/s2FwkVfG5R
> 14:    sdp4430:  Boot FAIL: http://slexy.org/raw/s2xiWxlpTj
> 15:       uevm:  Boot PASS: http://slexy.org/raw/s2LWUOmfiG
> TOTAL = 15 boards, Booted Boards = 1, No Boot boards = 14
> 
> I am running a defconfig set check on next-20140117 and will do one
> with next-20140118 once that is ready for comparison results

Just for reference: I tried booting Nokia N900 using mike's
clk-next-omap branch (HEAD = 3e04915):

n900:  Boot PASS: http://paste.debian.net/77085/

-- Sebastian

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Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Nishanth Menon]

On 01/17/2014 07:20 PM, Nishanth Menon wrote:
[...]
> I am running a defconfig set check on next-20140117 and will do one
> with next-20140118 once that is ready for comparison results
> 
baseline next-20140120
modified as follows:
multi_v7_defconfig - added CONFIG_SOC_DRA7XX
omap2plus_defconfig - added CONFIG_SOC_AM43XX
few patches for legacy boot platforms added in.

next-20140120-omap2plus_defconfig
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2vfJ5w6Na
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s21IdtacuB
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s2zrGqzI8r
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s21RLq4EzM
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21msOh70k
 6: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s2MyM1kbTJ
 7: BeagleBone-Black:  Boot PASS: http://slexy.org/raw/s2KmkjEQU5
 8:      crane: No Image built - Missing platform support?:
* Pending merge from Benoit's tree
 9:       dra7:  Boot PASS: http://slexy.org/raw/s20GK8ZSrL
10:        ldp:  Boot FAIL: http://slexy.org/raw/s20I1vJEY6
* Known issue on my setup :( - debug pending.
11: PandaBoard-ES:  Boot PASS: http://slexy.org/raw/s2SVGtHlwx
12:    sdp2430:  Boot PASS: http://slexy.org/raw/s214WyGCco
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s21fPHXoOB
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s20v0UJubl
15: OMAP5432uEVM:  Boot PASS: http://slexy.org/raw/s2jPgymund
TOTAL = 15 boards, Booted Boards = 13, No Boot boards = 2

next-20140120-multi_v7_defconfig
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2DcNIdR1p
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s2NWkEQIct
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s21rOVU9L3
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2xRLmJ9EW
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21487l9Tw
 6: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s2198moPea
 7: BeagleBone-Black:  Boot PASS: http://slexy.org/raw/s20wdS9zgf
 8:      crane: No Image built - Missing platform support?:
* pending merge from Benoit's tree
 9:       dra7:  Boot PASS: http://slexy.org/raw/s21Vr0foZS
10:        ldp:  Boot PASS: http://slexy.org/raw/s21PKycvVx
11: PandaBoard-ES:  Boot FAIL: http://slexy.org/raw/s20M5bdzFq
* kevin already reported this for CPU_IDLE enable
12:    sdp2430:  v6 platform - wont boot
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s2pmLQItJb
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s21FYwSVZz
15: OMAP5432uEVM:  Boot PASS: http://slexy.org/raw/s21O7xuAJp
TOTAL = 15 boards, Booted Boards = 12, No Boot boards = 3

next-20140120-multi_v7_defconfig + CONFIG_ARM_LPAE=y
 1: am335x-evm:  Boot FAIL: http://slexy.org/raw/s21YHQrdtf
 2:  am335x-sk:  Boot FAIL: http://slexy.org/raw/s20buoWhQw
 3: am3517-evm:  Boot FAIL: http://slexy.org/raw/s2VfH3LYFf
 4:  am37x-evm:  Boot FAIL: http://slexy.org/raw/s20Q4s7tjA
 5: am43xx-epos:  Boot FAIL: http://slexy.org/raw/s2tMG0ABLi
 6: BeagleBoard-XM:  Boot FAIL: http://slexy.org/raw/s20INrphLO
 7: BeagleBone-Black:  Boot FAIL: http://slexy.org/raw/s2ZKx9lyGc
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot PASS: http://slexy.org/raw/s21EV3vV4E
10:        ldp:  Boot FAIL: http://slexy.org/raw/s21aQ1vXWH
11: PandaBoard-ES:  Boot FAIL: http://slexy.org/raw/s20JMBxQUc
12:    sdp2430:  v6 platform - wont boot
13:    sdp3430:  Boot FAIL: http://slexy.org/raw/s20Itj0uX4
14:    sdp4430:  Boot FAIL: http://slexy.org/raw/s2BEPG9pjN
15: OMAP5432uEVM:  Boot PASS: http://slexy.org/raw/s20bOKUZev
TOTAL = 15 boards, Booted Boards = 2, No Boot boards = 13


in comparison  with previous next tag:
multi_v7_defconfig - added CONFIG_SOC_DRA7XX
omap2plus_defconfig - added CONFIG_SOC_AM43XX
few patches for legacy boot platforms added in.

next-20140117-omap2plus_defconfig
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2x6c41m1Q
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s24IkMtLwV
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s20ahoA1JR
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2hzZbe5fq
 5: am43xx-epos:  Boot FAIL: http://slexy.org/raw/s20875oeoW
 6: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s20luzJWbj
 7: BeagleBone-Black:  Boot PASS: http://slexy.org/raw/s2Z1YQqX1A
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot FAIL: http://slexy.org/raw/s2137kLALM
10:        ldp:  Boot FAIL: http://slexy.org/raw/s21S66NNnp
11: PandaBoard-ES:  Boot PASS: http://slexy.org/raw/s20XyDcifE
12:    sdp2430:  Boot PASS: http://slexy.org/raw/s234d7bWzB
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s250xvaBxy
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2g3As3XlA
15: OMAP5432uEVM:  Boot FAIL: http://slexy.org/raw/s21hOhWY4E
TOTAL = 15 boards, Booted Boards = 10, No Boot boards = 5

next-20140117-multi_v7_defconfig
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2M6DZp8D2
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s21WdeG7QL
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s2PanhpCqK
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s20nI7GNQS
 5: am43xx-epos:  Boot FAIL: http://slexy.org/raw/s2FFQpMN21
 6: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s2hy4PnWL6
 7: BeagleBone-Black:  Boot PASS: http://slexy.org/raw/s21tx10epo
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot FAIL: http://slexy.org/raw/s20itoFBdS
10:        ldp:  Boot PASS: http://slexy.org/raw/s213Un5KQW
11: PandaBoard-ES:  Boot FAIL: http://slexy.org/raw/s20B5kDMwg
12:    sdp2430:  Boot FAIL: http://slexy.org/raw/s21ZvpGpmK
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s20Ne0P2oX
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s215lq0bvl
15: OMAP5432uEVM:  Boot FAIL: http://slexy.org/raw/s2cUSAGe5h
TOTAL = 15 boards, Booted Boards = 9, No Boot boards = 6

next-20140117-multi_v7_defconfig + CONFIG_ARM_LPAE=y
 1: am335x-evm:  Boot FAIL: http://slexy.org/raw/s208rBie8T
 2:  am335x-sk:  Boot FAIL: http://slexy.org/raw/s2176U7Dph
 3: am3517-evm:  Boot FAIL: http://slexy.org/raw/s216noNiRN
 4:  am37x-evm:  Boot FAIL: http://slexy.org/raw/s21iF5KAJz
 5: am43xx-epos:  Boot FAIL: http://slexy.org/raw/s2lTTWBTzz
 6: BeagleBoard-XM:  Boot FAIL: http://slexy.org/raw/s20rHgs9kq
 7: BeagleBone-Black:  Boot FAIL: http://slexy.org/raw/s2yp7IWdE1
 8:      crane: No Image built - Missing platform support?:
 9:       dra7:  Boot FAIL: http://slexy.org/raw/s2GgOR9BzT
10:        ldp:  Boot FAIL: http://slexy.org/raw/s2u2OKWLpI
11: PandaBoard-ES:  Boot FAIL: http://slexy.org/raw/s2t3PluNV5
12:    sdp2430:  Boot FAIL: http://slexy.org/raw/s2biJ1CVJf
13:    sdp3430:  Boot FAIL: http://slexy.org/raw/s2K3G0fji6
14:    sdp4430:  Boot FAIL: http://slexy.org/raw/s2162mQFOS
15: OMAP5432uEVM:  Boot FAIL: http://slexy.org/raw/s2WbE4HU6Q
TOTAL = 15 boards, Booted Boards = 0, No Boot boards = 15


-- 
Regards,
Nishanth Menon

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tony Lindgren]

* Mike Turquette <mturquette@linaro.org> [140117 13:00]:
> Quoting Tero Kristo (2014-01-17 10:11:06)
> > On 01/17/2014 07:53 PM, Tony Lindgren wrote:
> > > * Kevin Hilman <khilman@linaro.org> [140117 09:48]:
> > >> Mike Turquette <mturquette@linaro.org> writes:
> > >>
> > >> [...]
> > >>
> > >>> I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
> > >>> Tero's series. This includes the AM3517 bits now. I've pushed this
> > >>> branch to clk-next-omap (force update) on my Linaro mirror. Can you do a
> > >>> final sanity test before I merge this into clk-next?
> > 
> > I think you accidentally merged wrong branch to clk-next-omap with the 
> > latest refresh. This is one is missing the build-fixes now, when it 
> > earlier had those in.
> > 
> > The correct branch to merge was 3.13-rc7-dt-clks-v13-build-fixes.
> > 
> > This also causes the build failure below for omap1.
> 
> You are right. I broke the OMAPs. I force updated clk-next-omap (and
> clk-next) with the correct branch this time.

OK works for me now, thanks.

Tony

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Nishanth Menon]

On 01/17/2014 11:46 AM, Kevin Hilman wrote:
> Mike Turquette <mturquette@linaro.org> writes:
> 
> [...]
> 
>> I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
>> Tero's series. This includes the AM3517 bits now. I've pushed this
>> branch to clk-next-omap (force update) on my Linaro mirror. Can you do a
>> final sanity test before I merge this into clk-next?
> 
> I merged clk-next-omap into next-20140117 and build/boot tested
> omap2plus_defconfig, multi_v7_defconfig and
> multi_v7_defconfig+CONFIG_LPAE=y and all passed a basic boot test for
> omap5uevm.
> 
> I'll add OMAP5 to the automated boot testing starting with the next
> linux-next.


Here are my logs for the similar configuration(with few patches for
legacy boot):

next-db23a6c + next-20140117 (omap2plus_defconfig)
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s20pGXG1jF
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s2ViUqyxYc
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s29qMTk2mS
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s20aZ0oDHS
 5:       beag:  Boot PASS: http://slexy.org/raw/s2DAKDwqRm
 6:       bone:  Boot PASS: http://slexy.org/raw/s215UVEmq2
 7:      crane: No Image built - Missing platform support?: (pending
merge from Benoit)
 8:       dra7:  Boot PASS: http://slexy.org/raw/s2CbtBGGxE
 9:        ldp:  Boot FAIL: http://slexy.org/raw/s20MOKNvPG
(been seeing this behavior on and off for some days now.. not really a
regression due to this series - need to debug this - could be setup
issues).
10:      panda:  Boot PASS: http://slexy.org/raw/s20RHdfXjS
11:    sdp2430:  Boot PASS: http://slexy.org/raw/s21fR9cQap
12:    sdp3430:  Boot PASS: http://slexy.org/raw/s209eZfYlQ
13:    sdp4430:  Boot PASS: http://slexy.org/raw/s21jemvEcd
14:       uevm:  Boot PASS: http://slexy.org/raw/s20OumuRI8
TOTAL = 14 boards, Booted Boards = 12, No Boot boards = 2

clk-next-db23a6c + next-20140117 (multi_v7_defconfig)
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s21kek3KDX
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s20b6Ypnpr
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s200aHOMA1
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2QwHWtLbB
 5:       beag:  Boot PASS: http://slexy.org/raw/s2120qe2nJ
 6:       bone:  Boot PASS: http://slexy.org/raw/s21SnQH1AY
 7:      crane: No Image built - Missing platform support?:
 8:       dra7:  Boot FAIL: http://slexy.org/raw/s20HxBFzIr
missing DRA7 in multi_v7
 9:        ldp:  Boot PASS: http://slexy.org/raw/s21vjb9GeV
10:      panda:  Boot FAIL: http://slexy.org/raw/s2WahEfqVw
kevin already reported this for CPU_IDLE enable
11:    sdp2430:  Boot FAIL: http://slexy.org/raw/s2ADmtqRhq
* multi_v7 does not boot v6 based boards
12:    sdp3430:  Boot PASS: http://slexy.org/raw/s2qM9hxrfi
13:    sdp4430:  Boot PASS: http://slexy.org/raw/s2ubbIBRA7
14:       uevm:  Boot PASS: http://slexy.org/raw/s2Y9xESvfH
TOTAL = 14 boards, Booted Boards = 10, No Boot boards = 4

clk-next-db23a6c + next-20140117 (multi_v7_defconfig + CONFIG_LPAE=y)
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s26sCQ0zqh
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s20BDyQWdB
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s21OPwGNo1
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s20tpjF0ri
 5:       beag:  Boot PASS: http://slexy.org/raw/s2jzkyRVaS
 6:       bone:  Boot PASS: http://slexy.org/raw/s20XodcZtZ
 7:      crane: No Image built - Missing platform support?:
 8:       dra7:  Boot FAIL: http://slexy.org/raw/s21cv8ni1H
missing DRA7 in multi_v7
 9:        ldp:  Boot PASS: http://slexy.org/raw/s22x4lqV3F
10:      panda:  Boot FAIL: http://slexy.org/raw/s200ETyoTB
kevin already reported this for CPU_IDLE enable
11:    sdp2430:  Boot FAIL: http://slexy.org/raw/s2lw3baFwx
* multi_v7 does not boot v6 based boards
12:    sdp3430:  Boot PASS: http://slexy.org/raw/s21i0TdsYs
13:    sdp4430:  Boot PASS: http://slexy.org/raw/s2DaYv6GVp
14:       uevm:  Boot PASS: http://slexy.org/raw/s2Q5IdWfMQ
TOTAL = 14 boards, Booted Boards = 10, No Boot boards = 4


-- 
Regards,
Nishanth Menon

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Joachim Eastwood]

On 9 January 2014 15:00, Tero Kristo <t-kristo@ti.com> wrote:
> Hi,
>
> So, bad luck number release for this, as v12 wasn't sufficient still.
>
> Changes compared to previous version:
> - Dropped any changes to generic clock drivers, as it seems impossible
>   to agree anything in short term, this means the patch set shrank in
>   size from 49 patches to 40 (first 9 patches were dropped).
> - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
>   to drivers/clk/ti, and made the modifications needed to the TI version
>   of the clock drivers only (based on discussions with Mike, this is fine)
> - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
>   with any generic implementation we might have at some point, migrating
>   this to the generic version should be easy enough also.
> - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
>   versions and resulted into an orphan clock node
> - Fixed compile problem for omap5 only build reported by Felipe
> - Fixed a couple of sparse warnings
> - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
>   instead of __raw_readl / __raw_writel
>
> Testing done:
> - omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
> - omap4-panda-es: boot / suspend-resume (RET)
> - omap5-uevm: boot
> - am335x-bone: boot
> - dra7-evm: boot
>
> Maintainer friendly branches also available:
>
> tree: https://github.com/t-kristo/linux-pm.git
>
> clk driver only (Mike): clk-next-dt-clks-v13
> DTS data only (Benoit): dts_for_3.14-dt-clks-v13
> full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13

I tested 3.13-rc7-dt-clks-v13 on top of a next branch I am working on
with a OMAP4460 and it's working fine.

A couple of things I noticed in the boot log:
[ 0.000000] ti_dt_clocks_register: failed to lookup clock node bandgap_fclk
[ 0.000000] smp_twd: clock not found -2

I am get the bandgap_fclk clock lookup fail since it doesn't exist on
4460 and I guess the bandgap_ts_fclk clock will fail the same way on
4430. So maybe you need to differentiate between 4460 and 4430 in
clk-44xx.c to get rid of this warning.

As for the smp_twd clock I assume we can add "clocks =
<&mpu_periphclk>" to local-timer@48240600 in omap4.dtsi to get rid of
the warning. I can cook up a patch here if it is the right thing to
do.
I think the smp_twd warning existed before I applied this patch set.

regards
Joachim Eastwood

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tero Kristo]

On 01/11/2014 06:35 PM, Joachim Eastwood wrote:
> On 9 January 2014 15:00, Tero Kristo <t-kristo@ti.com> wrote:
>> Hi,
>>
>> So, bad luck number release for this, as v12 wasn't sufficient still.
>>
>> Changes compared to previous version:
>> - Dropped any changes to generic clock drivers, as it seems impossible
>>    to agree anything in short term, this means the patch set shrank in
>>    size from 49 patches to 40 (first 9 patches were dropped).
>> - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
>>    to drivers/clk/ti, and made the modifications needed to the TI version
>>    of the clock drivers only (based on discussions with Mike, this is fine)
>> - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
>>    with any generic implementation we might have at some point, migrating
>>    this to the generic version should be easy enough also.
>> - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
>>    versions and resulted into an orphan clock node
>> - Fixed compile problem for omap5 only build reported by Felipe
>> - Fixed a couple of sparse warnings
>> - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
>>    instead of __raw_readl / __raw_writel
>>
>> Testing done:
>> - omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
>> - omap4-panda-es: boot / suspend-resume (RET)
>> - omap5-uevm: boot
>> - am335x-bone: boot
>> - dra7-evm: boot
>>
>> Maintainer friendly branches also available:
>>
>> tree: https://github.com/t-kristo/linux-pm.git
>>
>> clk driver only (Mike): clk-next-dt-clks-v13
>> DTS data only (Benoit): dts_for_3.14-dt-clks-v13
>> full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13
>
> I tested 3.13-rc7-dt-clks-v13 on top of a next branch I am working on
> with a OMAP4460 and it's working fine.
>
> A couple of things I noticed in the boot log:
> [ 0.000000] ti_dt_clocks_register: failed to lookup clock node bandgap_fclk
> [ 0.000000] smp_twd: clock not found -2
>
> I am get the bandgap_fclk clock lookup fail since it doesn't exist on
> 4460 and I guess the bandgap_ts_fclk clock will fail the same way on
> 4430. So maybe you need to differentiate between 4460 and 4430 in
> clk-44xx.c to get rid of this warning.

Yeah thats true. I was kind of lazy with the omap4 clk file (these are 
supposed to be temporary anyway until we can get rid of the clock 
aliases through proper driver DT mappings), and didn't separate omap4430 
vs omap4460 there. If this print needs to go away, we need to do this 
similarly to what was done with different omap3 versions (the clock data 
delta is much more larger there), but the additional code needed for 
this was rather large for the minimal impact... we would need separate 
board files, separate io.c setups, and logic within the clk-44xx.c file 
itself.

Just to re-phrase it, this doesn't impact functionality, the resultant 
clock nodes etc. are exactly the same before-and-after this set, the 
kernel just tries to register one additional clock alias which it can't 
find and prints the single line out.

-Tero

>
> As for the smp_twd clock I assume we can add "clocks =
> <&mpu_periphclk>" to local-timer@48240600 in omap4.dtsi to get rid of
> the warning. I can cook up a patch here if it is the right thing to
> do.
> I think the smp_twd warning existed before I applied this patch set.
>
> regards
> Joachim Eastwood
>