From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Lezcano Subject: Re: [PATCH v2 02/15] clocksource: orion: Use atomic access for shared registers Date: Tue, 21 Jan 2014 10:57:37 +0100 Message-ID: <52DE4491.2000505@linaro.org> References: <1390295561-3466-1-git-send-email-ezequiel.garcia@free-electrons.com> <1390295561-3466-3-git-send-email-ezequiel.garcia@free-electrons.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <1390295561-3466-3-git-send-email-ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Ezequiel Garcia , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Lior Amsalem , Thomas Petazzoni , Jason Cooper , Tawfik Bayouk , Andrew Lunn , Jason Gunthorpe , Wim Van Sebroeck , Gregory Clement , Sebastian Hesselbarth List-Id: devicetree@vger.kernel.org On 01/21/2014 10:12 AM, Ezequiel Garcia wrote: > Replace the driver-specific thread-safe shared register API > by the recently introduced atomic_io_clear_set(). > > Signed-off-by: Ezequiel Garcia Hi Ezequiel, in the future, put me in Cc when modifying files in clocksource that=20 will make my life easier to track the changes. Thanks. -- Daniel > --- > drivers/clocksource/time-orion.c | 28 ++++++++++------------------ > 1 file changed, 10 insertions(+), 18 deletions(-) > > diff --git a/drivers/clocksource/time-orion.c b/drivers/clocksource/t= ime-orion.c > index 9c7f018..3f14e56 100644 > --- a/drivers/clocksource/time-orion.c > +++ b/drivers/clocksource/time-orion.c > @@ -35,20 +35,6 @@ > #define ORION_ONESHOT_MAX 0xfffffffe > > static void __iomem *timer_base; > -static DEFINE_SPINLOCK(timer_ctrl_lock); > - > -/* > - * Thread-safe access to TIMER_CTRL register > - * (shared with watchdog timer) > - */ > -void orion_timer_ctrl_clrset(u32 clr, u32 set) > -{ > - spin_lock(&timer_ctrl_lock); > - writel((readl(timer_base + TIMER_CTRL) & ~clr) | set, > - timer_base + TIMER_CTRL); > - spin_unlock(&timer_ctrl_lock); > -} > -EXPORT_SYMBOL(orion_timer_ctrl_clrset); > /* > * Free-running clocksource handling. > @@ -68,7 +54,8 @@ static int orion_clkevt_next_event(unsigned long de= lta, > { > /* setup and enable one-shot timer */ > writel(delta, timer_base + TIMER1_VAL); > - orion_timer_ctrl_clrset(TIMER1_RELOAD_EN, TIMER1_EN); > + atomic_io_modify(timer_base + TIMER_CTRL, > + TIMER1_RELOAD_EN | TIMER1_EN, TIMER1_EN); I am not convinced this change is worth. Could you elaborate the race the spinlock should prevent ? > > return 0; > } > @@ -80,10 +67,13 @@ static void orion_clkevt_mode(enum clock_event_mo= de mode, > /* setup and enable periodic timer at 1/HZ intervals */ > writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD); > writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL); > - orion_timer_ctrl_clrset(0, TIMER1_RELOAD_EN | TIMER1_EN); > + atomic_io_modify(timer_base + TIMER_CTRL, > + TIMER1_RELOAD_EN | TIMER1_EN, > + TIMER1_RELOAD_EN | TIMER1_EN); > } else { > /* disable timer */ > - orion_timer_ctrl_clrset(TIMER1_RELOAD_EN | TIMER1_EN, 0); > + atomic_io_modify(timer_base + TIMER_CTRL, > + TIMER1_RELOAD_EN | TIMER1_EN, 0); > } > } > > @@ -131,7 +121,9 @@ static void __init orion_timer_init(struct device= _node *np) > /* setup timer0 as free-running clocksource */ > writel(~0, timer_base + TIMER0_VAL); > writel(~0, timer_base + TIMER0_RELOAD); > - orion_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | TIMER0_EN); > + atomic_io_modify(timer_base + TIMER_CTRL, > + TIMER0_RELOAD_EN | TIMER0_EN, > + TIMER0_RELOAD_EN | TIMER0_EN); > clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource"= , > clk_get_rate(clk), 300, 32, > clocksource_mmio_readl_down); > --=20 Linaro.org =E2=94=82 Open source software fo= r ARM SoCs =46ollow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe devicetree" i= n the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html