[PATCH v2 0/5] ARM: add omap3 INCOstartec board support

[PATCH v2 0/5] ARM: add omap3 INCOstartec board support

[Christoph Fritz]

This set of patches adds board support for an omap3 system from INCOstartec.
It's based on next-20140122.

Previously it was based on next-20140115. There, everything works as expected.

On branch git://git.linaro.org/people/ulf.hansson/clk.git linaro_clk/clk-next
which holdes all "clock DT conversion" commits, bootlog shows these abnormalities:

  [    0.559600] ------------[ cut here ]------------
  [    0.559631] WARNING: CPU: 0 PID: 1 at /home/honschu/media/linux/drivers/video/omap2/dss/dss.c:540 dss_set_clock_div+0xac/0xcc()
  [    0.559661] clk rate mismatch: 345600000 != 172800000
  [    0.559661] Modules linked in:
  [    0.559692] CPU: 0 PID: 1 Comm: swapper Not tainted 3.13.0-rc7+ 0
  [    0.559722] [<c0012fc4>] (unwind_backtrace+0x0/0xf8) from [<c0010e10>] (show_stack+0x10/0x14)
  [    0.559753] [<c0010e10>] (show_stack+0x10/0x14) from [<c0033fdc>] (warn_slowpath_common+0x64/0x84)
  [    0.559783] [<c0033fdc>] (warn_slowpath_common+0x64/0x84) from [<c0034090>] (warn_slowpath_fmt+0x30/0x40)
  [    0.559814] [<c0034090>] (warn_slowpath_fmt+0x30/0x40) from [<c02b23c0>] (dss_set_clock_div+0xac/0xcc)
  [    0.559844] [<c02b23c0>] (dss_set_clock_div+0xac/0xcc) from [<c0778f48>] (omap_dsshw_probe+0x1ec/0x2e0)
  [    0.559875] [<c0778f48>] (omap_dsshw_probe+0x1ec/0x2e0) from [<c02ff360>] (platform_drv_probe+0x18/0x48)
  [    0.559906] [<c02ff360>] (platform_drv_probe+0x18/0x48) from [<c02fdf84>] (driver_probe_device+0x110/0x230)
  [    0.559936] [<c02fdf84>] (driver_probe_device+0x110/0x230) from [<c02fe138>] (__driver_attach+0x94/0x98)
  [    0.559967] [<c02fe138>] (__driver_attach+0x94/0x98) from [<c02fc724>] (bus_for_each_dev+0x54/0x88)
  [    0.559997] [<c02fc724>] (bus_for_each_dev+0x54/0x88) from [<c02fd720>] (bus_add_driver+0xd4/0x1d0)
  [    0.559997] [<c02fd720>] (bus_add_driver+0xd4/0x1d0) from [<c02fe76c>] (driver_register+0x78/0xf4)
  [    0.560028] [<c02fe76c>] (driver_register+0x78/0xf4) from [<c02ff2c4>] (platform_driver_probe+0x20/0xa4)
  [    0.560058] [<c02ff2c4>] (platform_driver_probe+0x20/0xa4) from [<c0778ce0>] (omap_dss_init+0x1c/0x98)
  [    0.560089] [<c0778ce0>] (omap_dss_init+0x1c/0x98) from [<c0008828>] (do_one_initcall+0xe4/0x144)
  [    0.560119] [<c0008828>] (do_one_initcall+0xe4/0x144) from [<c075eadc>] (kernel_init_freeable+0xe8/0x1b0)
  [    0.560150] [<c075eadc>] (kernel_init_freeable+0xe8/0x1b0) from [<c05522bc>] (kernel_init+0x8/0x118)
  [    0.560180] [<c05522bc>] (kernel_init+0x8/0x118) from [<c000e4c8>] (ret_from_fork+0x14/0x2c)
  [    0.560302] ---[ end trace 187e8d9dd0655394 ]---
  [    0.560424] OMAP DSS rev 2.0
  --snip--
  [    2.601745] usb 1-1: new high-speed USB device number 2 using ehci-omap
  [    2.767059] usb 1-1: device descriptor read/64, error -71
  [    3.007934] usb 1-1: device descriptor read/64, error -71
  [    3.237091] usb 1-1: new high-speed USB device number 3 using ehci-omap
  [    3.387054] usb 1-1: device descriptor read/64, error -71
  [    3.637054] usb 1-1: device descriptor read/64, error -71
  [    3.867065] usb 1-1: new high-speed USB device number 4 using ehci-omap
  [    4.296966] usb 1-1: device not accepting address 4, error -71
  [    4.417053] usb 1-1: new high-speed USB device number 5 using ehci-omap
  [    4.846954] usb 1-1: device not accepting address 5, error -71
  [    4.853179] hub 1-0:1.0: unable to enumerate USB device on port 1
  [    5.217041] usb 2-1: new full-speed USB device number 2 using ohci-omap3
  [    5.407043] usb 2-1: device descriptor read/64, error -62
  [    5.697052] usb 2-1: device descriptor read/64, error -62
  [    5.987060] usb 2-1: new full-speed USB device number 3 using ohci-omap3
  [    6.066955] .[    6.177062] usb 2-1: device descriptor read/64, error -62
  [    6.467041] usb 2-1: device descriptor read/64, error -62
  [    6.757049] usb 2-1: new full-speed USB device number 4 using ohci-omap3
  [    7.176971] usb 2-1: device not accepting address 4, error -62
  [    7.357055] usb 2-1: new full-speed USB device number 5 using ohci-omap3
  [    7.776977] usb 2-1: device not accepting address 5, error -62
  [    7.783233] hub 2-0:1.0: unable to enumerate USB device on port 1

On next-20140122 the tps65930 (which should be compatible to twl4030) doesn't
set voltage on IO.1P8 any more which leads to a lot of external subsystem
failings like dss:

[    0.602264] omapdss_dss: probe of omapdss_dss failed with error -22
[    0.602691] omapdss CORE error: Failed to initialize DSS platform driver
[    0.603240] panel-dpi panel-dpi.0: failed to find video source 'dpi.0'

Changes compared to previous version:
 - rebased on next-20140122 from next-20140115
 - using omap36xx.dtsi instead of unsupported 1ghz omap37xx100

Christoph Fritz (5):
  ARM: dts: omap3: Add support for INCOstartec a83x module
  ARM: dts: omap3: Add support for INCOstartec DBB056 baseboard
  ARM: OMAP2+: add legacy display for omap3 DBB056
  ARM: OMAP2+: Add pdata quirk for sys_clkout2 for omap3 DBB056
  [RFC] omapdss: remove FEAT_DPI_USES_VDDS_DSI from omap3

 arch/arm/boot/dts/Makefile               |    1 +
 arch/arm/boot/dts/omap3-lilly-a83x.dtsi  |  445 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-lilly-dbb056.dts |  160 +++++++++++
 arch/arm/mach-omap2/dss-common.c         |   49 ++++
 arch/arm/mach-omap2/dss-common.h         |    1 +
 arch/arm/mach-omap2/pdata-quirks.c       |   44 ++-
 drivers/video/omap2/dss/dss_features.c   |    1 -
 7 files changed, 699 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap3-lilly-a83x.dtsi
 create mode 100644 arch/arm/boot/dts/omap3-lilly-dbb056.dts

-- 
1.7.10.4

[PATCH v2 1/5] ARM: dts: omap3: Add support for INCOstartec a83x module

[Christoph Fritz]

INCOstartec LILLY-A83X module is a TI DM3730xx100 (OMAP3) SoC
computer-on-module.

This patch adds device tree support for most of its features.

Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
 arch/arm/boot/dts/omap3-lilly-a83x.dtsi |  445 +++++++++++++++++++++++++++++++
 1 file changed, 445 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3-lilly-a83x.dtsi

diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
new file mode 100644
index 0000000..5e2137a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -0,0 +1,445 @@
+/*
+ * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "omap36xx.dtsi"
+
+/ {
+	model = "INCOstartec LILLY-A83X module (DM3730)";
+	compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+
+	chosen {
+			bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x8000000>;   /* 128 MB */
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		heartbeat1 {
+			label = "lilly-a83x::led1";
+			gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-on";
+		};
+
+	};
+
+	sound {
+		compatible = "ti,omap-twl4030";
+		ti,model = "lilly-a83x";
+
+		ti,mcbsp = <&mcbsp2>;
+		ti,codec = <&twl_audio>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		reg_vcc3: vcc3 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "VCC3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+		};
+	};
+
+	hsusb1_phy: hsusb1_phy {
+		compatible = "usb-nop-xceiv";
+		vcc-supply = <&reg_vcc3>;
+	};
+};
+
+&omap3_pmx_wkup {
+	pinctrl-names = "default";
+
+	lan9221_pins: pinmux_lan9221_pins {
+		pinctrl-single,pins = <
+			0x5A (PIN_INPUT | MUX_MODE4)   /* gpio_129 */
+		>;
+	};
+
+	tsc2048_pins: pinmux_tsc2048_pins {
+		pinctrl-single,pins = <
+			0x16 (PIN_INPUT_PULLUP | MUX_MODE4)   /* gpio_8 */
+		>;
+	};
+
+	mmc1cd_pins: pinmux_mmc1cd_pins {
+		pinctrl-single,pins = <
+			0x56 (PIN_INPUT | MUX_MODE4)   /* gpio_126 */
+		>;
+	};
+};
+
+&omap3_pmx_core {
+	pinctrl-names = "default";
+
+	gpio1_pins: pinmux_gpio1_pins {
+		pinctrl-single,pins = <
+			0x5ca (PIN_OUTPUT_PULLDOWN | MUX_MODE4)   /* gpio_29 */
+		>;
+	};
+
+	uart1_pins: pinmux_uart1_pins {
+		pinctrl-single,pins = <
+			0x14c (PIN_OUTPUT | MUX_MODE0)   /* uart1_tx.uart1_tx */
+			0x14e (PIN_OUTPUT | MUX_MODE0)   /* uart1_rts.uart1_rts */
+			0x150 (PIN_INPUT | MUX_MODE0)    /* uart1_cts.uart1_cts */
+			0x152 (PIN_INPUT | MUX_MODE0)    /* uart1_rx.uart1_rx */
+		>;
+	};
+
+	uart2_pins: pinmux_uart2_pins {
+		pinctrl-single,pins = <
+			0x140 (PIN_OUTPUT | MUX_MODE1)   /* mcbsp3_clkx.uart2_tx */
+			0x142 (PIN_INPUT | MUX_MODE1)    /* mcbsp3_fsx.uart2_rx */
+		>;
+	};
+
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			0x16e (PIN_INPUT | MUX_MODE0)    /* uart3_rx_irrx.uart3_rx_irrx */
+			0x170 (PIN_OUTPUT | MUX_MODE0)   /* uart3_tx_irtx.uart3_tx_irtx */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			0x18a (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl */
+			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda */
+		>;
+	};
+
+	i2c2_pins: pinmux_i2c2_pins {
+		pinctrl-single,pins = <
+			0x18e (PIN_INPUT | MUX_MODE0)   /* i2c2_scl.i2c2_scl */
+			0x190 (PIN_INPUT | MUX_MODE0)   /* i2c2_sda.i2c2_sda */
+		>;
+	};
+
+	i2c3_pins: pinmux_i2c3_pins {
+		pinctrl-single,pins = <
+			0x192 (PIN_INPUT | MUX_MODE0)   /* i2c3_scl.i2c3_scl */
+			0x194 (PIN_INPUT | MUX_MODE0)   /* i2c3_sda.i2c3_sda */
+		>;
+	};
+
+	hsusb1_pins: pinmux_hsusb1_pins {
+		pinctrl-single,pins = <
+			0x5a8 (PIN_OUTPUT | MUX_MODE3)  /* etk_clk.hsusb1_stp */
+			0x5aa (PIN_INPUT | MUX_MODE3)   /* etk_ctl.hsusb1_clk */
+			0x5ac (PIN_INPUT | MUX_MODE3)   /* etk_d0.hsusb1_data0 */
+			0x5ae (PIN_INPUT | MUX_MODE3)   /* etk_d1.hsusb1_data1 */
+			0x5b0 (PIN_INPUT | MUX_MODE3)   /* etk_d2.hsusb1_data2 */
+			0x5b2 (PIN_INPUT | MUX_MODE3)   /* etk_d3.hsusb1_data7 */
+			0x5b4 (PIN_INPUT | MUX_MODE3)   /* etk_d4.hsusb1_data4 */
+			0x5b6 (PIN_INPUT | MUX_MODE3)   /* etk_d5.hsusb1_data5 */
+			0x5b8 (PIN_INPUT | MUX_MODE3)   /* etk_d6.hsusb1_data6 */
+			0x5ba (PIN_INPUT | MUX_MODE3)   /* etk_d7.hsusb1_data3 */
+			0x5bc (PIN_INPUT | MUX_MODE3)   /* etk_d8.hsusb1_dir */
+			0x5be (PIN_INPUT | MUX_MODE3)   /* etk_d9.hsusb1_nxt */
+
+			/* GPIO 128 controls USB-Hub reset. But USB-Phy its
+			 * reset can't be controlled. So we clamp this GPIO to
+			 * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub.
+			 */
+
+			0x1ae (PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4)   /* gpio_182 */
+		>;
+	};
+
+	hsusb_otg_pins: pinmux_hsusb_otg_pins {
+		pinctrl-single,pins = <
+			0x172 (PIN_INPUT | MUX_MODE0)   /* hsusb0_clk.hsusb0_clk */
+			0x174 (PIN_OUTPUT | MUX_MODE0)  /* hsusb0_stp.hsusb0_stp */
+			0x176 (PIN_INPUT | MUX_MODE0)   /* hsusb0_dir.hsusb0_dir */
+			0x178 (PIN_INPUT | MUX_MODE0)   /* hsusb0_nxt.hsusb0_nxt */
+			0x17a (PIN_INPUT | MUX_MODE0)   /* hsusb0_data0.hsusb0_data0 */
+			0x17c (PIN_INPUT | MUX_MODE0)   /* hsusb0_data1.hsusb0_data1 */
+			0x17e (PIN_INPUT | MUX_MODE0)   /* hsusb0_data2.hsusb0_data2 */
+			0x180 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data3.hsusb0_data3 */
+			0x182 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data4.hsusb0_data4 */
+			0x184 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data5.hsusb0_data5 */
+			0x186 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data6.hsusb0_data6 */
+			0x188 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data7.hsusb0_data7 */
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			0x114 (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_clk.sdmmc1_clk */
+			0x116 (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_cmd.sdmmc1_cmd */
+			0x118 (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat0.sdmmc1_dat0 */
+			0x11a (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat1.sdmmc1_dat1 */
+			0x11c (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat2.sdmmc1_dat2 */
+			0x11e (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat3.sdmmc1_dat3 */
+		>;
+	};
+
+	spi2_pins: pinmux_spi2_pins {
+		pinctrl-single,pins = <
+			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_clk.mcspi2_clk */
+			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_simo.mcspi2_simo */
+			0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_somi.mcspi2_somi */
+			0x1ac (PIN_OUTPUT | MUX_MODE0)   /* mcspi2_cs0.mcspi2_cs0 */
+		>;
+	};
+};
+
+&gpio1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio1_pins>;
+};
+
+&i2c1 {
+	clock-frequency = <2600000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+
+	twl: twl@48 {
+		reg = <0x48>;
+		interrupts = <7>;   /* SYS_NIRQ cascaded to intc */
+		interrupt-parent = <&intc>;
+
+		twl_audio: audio {
+			compatible = "ti,twl4030-audio";
+			codec {
+			};
+		};
+	};
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&twl {
+	vmmc1: regulator-vmmc1 {
+		regulator-always-on;
+	};
+
+	vdd1: regulator-vdd1 {
+		regulator-always-on;
+	};
+
+	vdd2: regulator-vdd2 {
+		regulator-always-on;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <2600000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+};
+
+&i2c3 {
+	clock-frequency = <2600000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+		gpiom1: gpio@20 {
+			compatible = "mcp,mcp23017";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x20>;
+		};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
+
+&uart4 {
+	status = "disabled";
+};
+
+&mmc1 {
+	reg = <0x4809c000 0x400>;
+	cd-gpios = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
+	cd-inverted;
+	vmmc-supply = <&vmmc1>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins &mmc1cd_pins>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+};
+
+&mmc2 {
+	status = "disabled";
+};
+
+&mmc3 {
+	status = "disabled";
+};
+
+&mcspi2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_pins>;
+
+	tsc2046@0 {
+		reg = <0>;   /* CS0 */
+		compatible = "ti,tsc2046";
+		interrupt-parent = <&gpio1>;
+		interrupts = <8 0>;   /* boot6 / gpio_8 */
+		spi-max-frequency = <1000000>;
+		pendown-gpio = <&gpio1 8 0>;
+		vcc-supply = <&reg_vcc3>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&tsc2048_pins>;
+
+		ti,x-min = <300>;
+		ti,x-max = <3000>;
+		ti,y-min = <600>;
+		ti,y-max = <3600>;
+		ti,x-plate-ohms = <80>;
+		ti,pressure-max = <255>;
+		ti,swap-xy;
+
+		linux,wakeup;
+	};
+};
+
+&usbhsehci {
+	phys = <&hsusb1_phy>;
+};
+
+&usbhshost {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb1_pins>;
+	num-ports = <2>;
+	port1-mode = "ehci-phy";
+};
+
+&usb_otg_hs {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb_otg_pins>;
+	interface-type = <0>;
+	usb-phy = <&usb2_phy>;
+	phys = <&usb2_phy>;
+	phy-names = "usb2-phy";
+	mode = <3>;
+	power = <50>;
+};
+
+&gpmc {
+	ranges = <0 0 0x30000000 0x1000000>,
+		<7 0 0x15000000 0x01000000>;
+
+	nand@0,0 {
+		reg = <0 0 0x1000000>;
+		nand-bus-width = <16>;
+		ti,nand-ecc-opt = "bch8";
+		/* no elm on omap3 */
+
+		gpmc,mux-add-data = <0>;
+		gpmc,device-nand;
+		gpmc,device-width = <2>;
+		gpmc,wait-pin = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,burst-length= <4>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <100>;
+		gpmc,cs-wr-off-ns = <100>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <100>;
+		gpmc,adv-wr-off-ns = <100>;
+		gpmc,oe-on-ns = <5>;
+		gpmc,oe-off-ns = <75>;
+		gpmc,we-on-ns = <5>;
+		gpmc,we-off-ns = <75>;
+		gpmc,rd-cycle-ns = <100>;
+		gpmc,wr-cycle-ns = <100>;
+		gpmc,access-ns = <60>;
+		gpmc,page-burst-access-ns = <5>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-samecsen;
+		gpmc,cycle2cycle-delay-ns = <50>;
+		gpmc,wr-data-mux-bus-ns = <75>;
+		gpmc,wr-access-ns = <155>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "MLO";
+			reg = <0 0x80000>;
+		};
+
+		partition@0x80000 {
+			label = "u-boot";
+			reg = <0x80000 0x1e0000>;
+		};
+
+		partition@0x260000 {
+			label = "u-boot-environment";
+			reg = <0x260000 0x20000>;
+		};
+
+		partition@0x280000 {
+			label = "kernel";
+			reg = <0x280000 0x500000>;
+		};
+
+		partition@0x780000 {
+			label = "filesystem";
+			reg = <0x780000 0xf880000>;
+		};
+	};
+
+	ethernet@7,0 {
+		compatible = "smsc,lan9221", "smsc,lan9115";
+		bank-width = <2>;
+		gpmc,mux-add-data = <2>;
+		gpmc,cs-on-ns = <10>;
+		gpmc,cs-rd-off-ns = <60>;
+		gpmc,cs-wr-off-ns = <60>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <10>;
+		gpmc,adv-wr-off-ns = <10>;
+		gpmc,oe-on-ns = <10>;
+		gpmc,oe-off-ns = <60>;
+		gpmc,we-on-ns = <10>;
+		gpmc,we-off-ns = <60>;
+		gpmc,rd-cycle-ns = <100>;
+		gpmc,wr-cycle-ns = <100>;
+		gpmc,access-ns = <50>;
+		gpmc,page-burst-access-ns = <5>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <75>;
+		gpmc,wr-data-mux-bus-ns = <15>;
+		gpmc,wr-access-ns = <75>;
+		gpmc,cycle2cycle-samecsen;
+		gpmc,cycle2cycle-diffcsen;
+		vddvario-supply = <&reg_vcc3>;
+		vdd33a-supply = <&reg_vcc3>;
+		reg-io-width = <4>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <1 0x2>;
+		reg = <7 0 0xff>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lan9221_pins>;
+		phy-mode = "mii";
+	};
+};
-- 
1.7.10.4

[PATCH v2 2/5] ARM: dts: omap3: Add support for INCOstartec DBB056 baseboard

[Christoph Fritz]

INCOstartec LILLY-DBB056 is a carrier board (baseboard) for
computer-on-module LILLY-A83X.

This patch adds device-tree support for most of its features.

Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
 arch/arm/boot/dts/Makefile               |    1 +
 arch/arm/boot/dts/omap3-lilly-dbb056.dts |  160 ++++++++++++++++++++++++++++++
 2 files changed, 161 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3-lilly-dbb056.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cfd364d..b449161 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -215,6 +215,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
 	omap3-gta04.dtb \
 	omap3-igep0020.dtb \
 	omap3-igep0030.dtb \
+	omap3-lilly-dbb056.dtb \
 	omap3-zoom3.dtb \
 	omap4-panda.dtb \
 	omap4-panda-a4.dtb \
diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
new file mode 100644
index 0000000..a700b71
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+/dts-v1/;
+
+#include "omap3-lilly-a83x.dtsi"
+
+/ {
+	model = "INCOstartec LILLY-DBB056 (DM3730)";
+	compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+};
+
+&twl {
+	vaux2: regulator-vaux2 {
+		compatible = "ti,twl4030-vaux2";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		regulator-always-on;
+	};
+};
+
+&omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <&lcd_pins>;
+
+	lan9117_pins: pinmux_lan9117_pins {
+		pinctrl-single,pins = <
+			0xe4 (PIN_INPUT | MUX_MODE4)   /* gpio_98 */
+		>;
+	};
+
+	gpio4_pins: pinmux_gpio4_pins {
+		pinctrl-single,pins = <
+			0xfe (PIN_INPUT | MUX_MODE4)   /* gpio_111 -> sja1000 IRQ */
+		>;
+	};
+
+	lcd_pins: pinmux_lcd_pins {
+		pinctrl-single,pins = <
+			0x0a4 (PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+			0x0a6 (PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+			0x0a8 (PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+			0x0aa (PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+			0x0ac (PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
+			0x0ae (PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
+			0x0b0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
+			0x0b2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
+			0x0b4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
+			0x0b6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
+			0x0b8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
+			0x0ba (PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
+			0x0bc (PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
+			0x0be (PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
+			0x0c0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
+			0x0c2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
+			0x0c4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
+			0x0c6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
+			0x0c8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
+			0x0ca (PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
+			0x0cc (PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
+			0x0ce (PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
+			0x15c (PIN_OUTPUT | MUX_MODE4)   /* gpio_156 -> enable DSS */
+		>;
+	};
+
+	mmc2_pins: pinmux_mmc2_pins {
+		pinctrl-single,pins = <
+			0x128 (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_clk.sdmmc2_clk */
+			0x12a (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_cmd.sdmmc2_cmd */
+			0x12c (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_dat0.sdmmc2_dat0 */
+			0x12e (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_dat1.sdmmc2_dat1 */
+			0x130 (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_dat2.sdmmc2_dat2 */
+			0x132 (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_dat3.sdmmc2_dat3 */
+			0x134 (PIN_OUTPUT | MUX_MODE1)   /* sdmmc2_dat4.sdmmc2_dir_dat0 */
+			0x136 (PIN_OUTPUT | MUX_MODE1)   /* sdmmc2_dat5.sdmmc2_dir_dat1 */
+			0x138 (PIN_OUTPUT | MUX_MODE1)   /* sdmmc2_dat6.sdmmc2_dir_cmd */
+			0x13a (PIN_INPUT | MUX_MODE1)    /* sdmmc2_dat7.sdmmc2_clkin */
+			0x16a (PIN_INPUT_PULLUP | MUX_MODE4)   /* gpio_163 -> wp */
+			0x16c (PIN_INPUT_PULLUP | MUX_MODE4)   /* gpio_164 -> cd */
+		>;
+	};
+
+	spi1_pins: pinmux_spi1_pins {
+		pinctrl-single,pins = <
+			0x198 (PIN_INPUT | MUX_MODE0)   /* mcspi1_clk.mcspi1_clk */
+			0x19a (PIN_INPUT | MUX_MODE0)   /* mcspi1_simo.mcspi1_simo */
+			0x19c (PIN_INPUT | MUX_MODE0)   /* mcspi1_somi.mcspi1_somi */
+			0x19e (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi1_cs0.mcspi1_cs0 */
+		>;
+	};
+};
+
+&gpio4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio4_pins>;
+};
+
+&mmc2 {
+	status = "okay";
+	bus-width = <4>;
+	vmmc-supply = <&vmmc1>;
+	cd-gpios = <&gpio6 4 0>;   /* gpio_164 */
+	wp-gpios = <&gpio6 3 0>;   /* gpio_163 */
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+	ti,dual-volt;
+};
+
+&mcspi1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_pins>;
+};
+
+&gpmc {
+	ranges = <0 0 0x30000000 0x1000000>,   /* nand assigned by COM a83x */
+		<4 0 0x20000000 0x01000000>,
+		<7 0 0x15000000 0x01000000>;   /* eth assigend by COM a83x */
+
+	ethernet@4,0 {
+		compatible = "smsc,lan9117", "smsc,lan9115";
+		bank-width = <2>;
+		gpmc,mux-add-data = <2>;
+		gpmc,cs-on-ns = <10>;
+		gpmc,cs-rd-off-ns = <65>;
+		gpmc,cs-wr-off-ns = <65>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <10>;
+		gpmc,adv-wr-off-ns = <10>;
+		gpmc,oe-on-ns = <10>;
+		gpmc,oe-off-ns = <65>;
+		gpmc,we-on-ns = <10>;
+		gpmc,we-off-ns = <65>;
+		gpmc,rd-cycle-ns = <100>;
+		gpmc,wr-cycle-ns = <100>;
+		gpmc,access-ns = <60>;
+		gpmc,page-burst-access-ns = <5>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <75>;
+		gpmc,wr-data-mux-bus-ns = <15>;
+		gpmc,wr-access-ns = <75>;
+		gpmc,cycle2cycle-samecsen;
+		gpmc,cycle2cycle-diffcsen;
+		vddvario-supply = <&reg_vcc3>;
+		vdd33a-supply = <&reg_vcc3>;
+		reg-io-width = <4>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <2 0x2>;
+		reg = <4 0 0xff>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lan9117_pins>;
+		phy-mode = "mii";
+		smsc,force-internal-phy;
+	};
+};
-- 
1.7.10.4

[PATCH v2 3/5] ARM: OMAP2+: add legacy display for omap3 DBB056

[Christoph Fritz]

Full device tree support for omapdss is not yet accomplished. Until
then, init display by legacy platform code.

Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
 arch/arm/mach-omap2/dss-common.c   |   49 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/dss-common.h   |    1 +
 arch/arm/mach-omap2/pdata-quirks.c |    7 +++++-
 3 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index dadccc9..b8b4e39 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -257,3 +257,52 @@ void __init omap3_igep2_display_init_of(void)
 	platform_device_register(&omap3_igep2_tfp410_device);
 	platform_device_register(&omap3_igep2_dvi_connector_device);
 }
+
+/* OMAP3 dbb056 data */
+
+#define DBB056_DISPLAY_ENABLE_GPIO 156
+
+static const struct display_timing dbb056_lcd_videomode = {
+	.pixelclock = { 0, 19200000, 0 },
+
+	.hactive = { 0, 640, 0 },
+	.hfront_porch = { 0, 104, 0 },
+	.hback_porch = { 0, 8, 0 },
+	.hsync_len = { 0, 8, 0 },
+
+	.vactive = { 0, 480, 0 },
+	.vfront_porch = { 0, 104, 0 },
+	.vback_porch = { 0, 8, 0 },
+	.vsync_len = { 0, 8, 0 },
+
+	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
+		DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE,
+};
+
+static struct panel_dpi_platform_data dbb056_lcd_pdata = {
+	.name                   = "lcd",
+	.source                 = "dpi.0",
+
+	.data_lines             = 18,
+
+	.display_timing         = &dbb056_lcd_videomode,
+
+	.enable_gpio            = DBB056_DISPLAY_ENABLE_GPIO,
+	.backlight_gpio         = -1,
+};
+
+static struct platform_device dbb056_lcd_device = {
+	.name                   = "panel-dpi",
+	.id                     = 0,
+	.dev.platform_data      = &dbb056_lcd_pdata,
+};
+
+static struct omap_dss_board_info omap_dbb056_dss_data = {
+	.default_display_name = "lcd",
+};
+
+void __init omap3_dbb056_display_init_of(void)
+{
+	platform_device_register(&dbb056_lcd_device);
+	omap_display_init(&omap_dbb056_dss_data);
+}
diff --git a/arch/arm/mach-omap2/dss-common.h b/arch/arm/mach-omap2/dss-common.h
index a9becf0..a125b55 100644
--- a/arch/arm/mach-omap2/dss-common.h
+++ b/arch/arm/mach-omap2/dss-common.h
@@ -9,5 +9,6 @@
 void __init omap4_panda_display_init_of(void);
 void __init omap_4430sdp_display_init_of(void);
 void __init omap3_igep2_display_init_of(void);
+void __init omap3_dbb056_display_init_of(void);
 
 #endif
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 3d5b24d..a58590f 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -169,6 +169,10 @@ static void __init am3517_evm_legacy_init(void)
 	omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
 	omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
 }
+static void __init omap3_dbb056_legacy_init(void)
+{
+	omap3_dbb056_display_init_of();
+}
 #endif /* CONFIG_ARCH_OMAP3 */
 
 #ifdef CONFIG_ARCH_OMAP4
@@ -259,10 +263,11 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
 static struct pdata_init pdata_quirks[] __initdata = {
 #ifdef CONFIG_ARCH_OMAP3
 	{ "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, },
+	{ "incostartec,omap3-lilly-dbb056", omap3_dbb056_legacy_init, },
+	{ "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
 	{ "nokia,omap3-n900", hsmmc2_internal_input_clk, },
 	{ "nokia,omap3-n9", hsmmc2_internal_input_clk, },
 	{ "nokia,omap3-n950", hsmmc2_internal_input_clk, },
-	{ "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
 	{ "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
 	{ "ti,omap3-zoom3", omap3_zoom_legacy_init, },
 	{ "ti,am3517-evm", am3517_evm_legacy_init, },
-- 
1.7.10.4

[PATCH v2 4/5] ARM: OMAP2+: Add pdata quirk for sys_clkout2 for omap3 DBB056

[Christoph Fritz]

Full device tree support for clock control is not yet accomplished. Until
then, configure the 24Mhz of sys_clkout2 to feed an USB-Hub here.

Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
 arch/arm/mach-omap2/pdata-quirks.c |   37 ++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index a58590f..9ef7ca8 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -171,6 +171,43 @@ static void __init am3517_evm_legacy_init(void)
 }
 static void __init omap3_dbb056_legacy_init(void)
 {
+	struct clk *clkout2;
+	struct clk *cm96fck;
+
+	/* Reparent clkout2 to 96M_FCK */
+	pr_info("a83x-quirk: Late Reparent clkout2 to 96M_FCK\n");
+	clkout2 = clk_get(NULL, "clkout2_src_ck");
+	if(clkout2 < 0) {
+		pr_err("a83x-quirk: couldn't get clkout2_src_ck\n");
+		return;
+	}
+	cm96fck = clk_get(NULL, "cm_96m_fck");
+	if(cm96fck < 0) {
+		pr_err("a83x-quirk: couldn't get cm_96m_fck\n");
+		return;
+	}
+	if(clk_set_parent(clkout2, cm96fck) < 0) {
+		pr_err("a83x-quirk: couldn't reparent clkout2_src_ck\n");
+		return;
+	}
+
+	/* Set clkout2 to 24MHz for internal usb hub*/
+	pr_info("a83x-quirk: Set clkout2 to 24MHz for internal usb hub\n");
+	clkout2 = clk_get(NULL, "sys_clkout2");
+	if(clkout2 < 0) {
+		pr_err("a83x-quirk: couldn't get sys_clkout2\n");
+		return;
+	}
+	if(clk_set_rate(clkout2, 24000000) < 0) {
+		printk(KERN_ERR "board-omap3evm: couldn't set sys_clkout2 rate\n");
+		return;
+	}
+	if(clk_prepare_enable(clkout2) < 0) {
+		pr_err("a83x-quirk: couldn't enable sys_clkout2\n");
+		return;
+	}
+
+	/* Initialize display */
 	omap3_dbb056_display_init_of();
 }
 #endif /* CONFIG_ARCH_OMAP3 */
-- 
1.7.10.4

[PATCH v2 5/5] [RFC] omapdss: remove FEAT_DPI_USES_VDDS_DSI from omap3

[Christoph Fritz]

DBB056 doesn't use DSI for its display, but omap3 forces this
erroneously for all its boards:

  | OMAP DSS rev 2.0
  | omapdss DPI error: can't get VDDS_DSI regulator
  | omapfb omapfb: failed to connect default display
  | omapfb omapfb: failed to init overlay connections
  | omapfb omapfb: failed to setup omapfb
  | platform omapfb: Driver omapfb requests probe deferral

So this patch just disables it for omap3. Consider this as a hack!
Is there a proper fix for this issue?
---
 drivers/video/omap2/dss/dss_features.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index 7f89691..dbf5894 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -536,7 +536,6 @@ static const enum dss_feat_id omap3630_dss_feat_list[] = {
 	FEAT_ALPHA_FIXED_ZORDER,
 	FEAT_FIFO_MERGE,
 	FEAT_OMAP3_DSI_FIFO_BUG,
-	FEAT_DPI_USES_VDDS_DSI,
 };
 
 static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
-- 
1.7.10.4

Re: [PATCH v2 5/5] [RFC] omapdss: remove FEAT_DPI_USES_VDDS_DSI from omap3

[Javier Martinez Canillas]

Hello Christoph,

On 01/22/2014 04:04 PM, Christoph Fritz wrote:
> DBB056 doesn't use DSI for its display, but omap3 forces this
> erroneously for all its boards:
> 
>   | OMAP DSS rev 2.0
>   | omapdss DPI error: can't get VDDS_DSI regulator
>   | omapfb omapfb: failed to connect default display
>   | omapfb omapfb: failed to init overlay connections
>   | omapfb omapfb: failed to setup omapfb
>   | platform omapfb: Driver omapfb requests probe deferral
> 
> So this patch just disables it for omap3. Consider this as a hack!
> Is there a proper fix for this issue?

It is also a hack but I solved on the IGEPv2 board by adding a regulator-name =
"vdds_dsi" to the VPLL2 regulator as suggested by Tony.

Look at commit 2f2befd8 ("ARM: dts: omap3-igep0020: name twl4030 VPLL2 regulator
as vdds_dsi")

Having the workaround in the Device Tree is better IMHO since this is a
per-board configuration. That can be later removed once the DSS DT bindings are
added to mainline.

Thanks a lot and best regards,
Javier

Re: [PATCH v2 4/5] ARM: OMAP2+: Add pdata quirk for sys_clkout2 for omap3 DBB056

[Nishanth Menon]

On 01/22/2014 01:04 PM, Christoph Fritz wrote:
> Full device tree support for clock control is not yet accomplished. Until
> then, configure the 24Mhz of sys_clkout2 to feed an USB-Hub here.
> 
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> ---
>  arch/arm/mach-omap2/pdata-quirks.c |   37 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
> index a58590f..9ef7ca8 100644
> --- a/arch/arm/mach-omap2/pdata-quirks.c
> +++ b/arch/arm/mach-omap2/pdata-quirks.c
> @@ -171,6 +171,43 @@ static void __init am3517_evm_legacy_init(void)
>  }
>  static void __init omap3_dbb056_legacy_init(void)
>  {
> +	struct clk *clkout2;
> +	struct clk *cm96fck;
> +
> +	/* Reparent clkout2 to 96M_FCK */
> +	pr_info("a83x-quirk: Late Reparent clkout2 to 96M_FCK\n");
what'd be a83x?

> +	clkout2 = clk_get(NULL, "clkout2_src_ck");
> +	if(clkout2 < 0) {
> +		pr_err("a83x-quirk: couldn't get clkout2_src_ck\n");
> +		return;
> +	}
> +	cm96fck = clk_get(NULL, "cm_96m_fck");
> +	if(cm96fck < 0) {
> +		pr_err("a83x-quirk: couldn't get cm_96m_fck\n");
> +		return;
> +	}
> +	if(clk_set_parent(clkout2, cm96fck) < 0) {
> +		pr_err("a83x-quirk: couldn't reparent clkout2_src_ck\n");
> +		return;
> +	}
yep - we have bunch of similar code in drivers/clk/ti -> but we'd need
a generic property to handle this.
> +
> +	/* Set clkout2 to 24MHz for internal usb hub*/
> +	pr_info("a83x-quirk: Set clkout2 to 24MHz for internal usb hub\n");
> +	clkout2 = clk_get(NULL, "sys_clkout2");
> +	if(clkout2 < 0) {
> +		pr_err("a83x-quirk: couldn't get sys_clkout2\n");
> +		return;
> +	}
> +	if(clk_set_rate(clkout2, 24000000) < 0) {
same here.
> +		printk(KERN_ERR "board-omap3evm: couldn't set sys_clkout2 rate\n");
"board-omap3evm:" copy paste?
any reason why not pr_err?

> +		return;
> +	}
> +	if(clk_prepare_enable(clkout2) < 0) {
> +		pr_err("a83x-quirk: couldn't enable sys_clkout2\n");
> +		return;
> +	}
> +
> +	/* Initialize display */
>  	omap3_dbb056_display_init_of();
>  }
>  #endif /* CONFIG_ARCH_OMAP3 */
> 

looking at the coding style, I assume we'd missed running
checkpatch.pl --strict?

ERROR: space required before the open parenthesis '('
#44: FILE: arch/arm/mach-omap2/pdata-quirks.c:180:
+	if(clkout2 < 0) {

ERROR: space required before the open parenthesis '('
#49: FILE: arch/arm/mach-omap2/pdata-quirks.c:185:
+	if(cm96fck < 0) {

ERROR: space required before the open parenthesis '('
#53: FILE: arch/arm/mach-omap2/pdata-quirks.c:189:
+	if(clk_set_parent(clkout2, cm96fck) < 0) {

ERROR: space required before the open parenthesis '('
#61: FILE: arch/arm/mach-omap2/pdata-quirks.c:197:
+	if(clkout2 < 0) {

ERROR: space required before the open parenthesis '('
#65: FILE: arch/arm/mach-omap2/pdata-quirks.c:201:
+	if(clk_set_rate(clkout2, 24000000) < 0) {

WARNING: Prefer netdev_err(netdev, ... then dev_err(dev, ... then
pr_err(...  to printk(KERN_ERR ...
#66: FILE: arch/arm/mach-omap2/pdata-quirks.c:202:
+		printk(KERN_ERR "board-omap3evm: couldn't set sys_clkout2 rate\n");

ERROR: space required before the open parenthesis '('
#69: FILE: arch/arm/mach-omap2/pdata-quirks.c:205:
+	if(clk_prepare_enable(clkout2) < 0) {

total: 6 errors, 1 warnings, 0 checks, 43 lines checked

 has style problems, please review.

If any of these errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.

you might want to run something like aiaiai[1] or
kernel_patch_verify[2] or patman... etc.. to help you clean up for
minimum needs.

[1] https://lwn.net/Articles/488992/
[2] https://github.com/nmenon/kernel_patch_verify

-- 
Regards,
Nishanth Menon

Re: [PATCH v2 1/5] ARM: dts: omap3: Add support for INCOstartec a83x module

[Nishanth Menon]

On 01/22/2014 01:04 PM, Christoph Fritz wrote:
> INCOstartec LILLY-A83X module is a TI DM3730xx100 (OMAP3) SoC
> computer-on-module.
> 
> This patch adds device tree support for most of its features.
> 
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> ---
>  arch/arm/boot/dts/omap3-lilly-a83x.dtsi |  445 +++++++++++++++++++++++++++++++
>  1 file changed, 445 insertions(+)
>  create mode 100644 arch/arm/boot/dts/omap3-lilly-a83x.dtsi
> 
> diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
> new file mode 100644
> index 0000000..5e2137a
> --- /dev/null
> +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
> @@ -0,0 +1,445 @@
> +/*
> + * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include "omap36xx.dtsi"
> +
> +/ {
> +	model = "INCOstartec LILLY-A83X module (DM3730)";
> +	compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
> +
> +	chosen {
> +			bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x80000000 0x8000000>;   /* 128 MB */
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		heartbeat1 {
> +			label = "lilly-a83x::led1";
> +			gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
> +			linux,default-trigger = "default-on";
> +		};
> +
> +	};
> +
> +	sound {
> +		compatible = "ti,omap-twl4030";
> +		ti,model = "lilly-a83x";
> +
> +		ti,mcbsp = <&mcbsp2>;
> +		ti,codec = <&twl_audio>;
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
Shrug, just moving the fixed regulator to root also will do the job,
not sure simple-bus much sense here :(

> +		reg_vcc3: vcc3 {
> +                        compatible = "regulator-fixed";
> +                        regulator-name = "VCC3";
> +                        regulator-min-microvolt = <3300000>;
> +                        regulator-max-microvolt = <3300000>;
> +                        regulator-always-on;
> +		};
> +	};
> +
> +	hsusb1_phy: hsusb1_phy {
> +		compatible = "usb-nop-xceiv";
> +		vcc-supply = <&reg_vcc3>;
> +	};
> +};
> +
> +&omap3_pmx_wkup {
> +	pinctrl-names = "default";
> +
> +	lan9221_pins: pinmux_lan9221_pins {
> +		pinctrl-single,pins = <
> +			0x5A (PIN_INPUT | MUX_MODE4)   /* gpio_129 */
umm.. you might want to follow the convention as you followed later in
comments.
> +		>;
> +	};
> +
> +	tsc2048_pins: pinmux_tsc2048_pins {
> +		pinctrl-single,pins = <
> +			0x16 (PIN_INPUT_PULLUP | MUX_MODE4)   /* gpio_8 */
umm.. you might want to follow the convention as you followed later in
comments.
> +		>;
> +	};
> +
> +	mmc1cd_pins: pinmux_mmc1cd_pins {
> +		pinctrl-single,pins = <
> +			0x56 (PIN_INPUT | MUX_MODE4)   /* gpio_126 */
umm.. you might want to follow the convention as you followed later in
comments.
> +		>;
> +	};
> +};
> +
> +&omap3_pmx_core {
> +	pinctrl-names = "default";
> +
> +	gpio1_pins: pinmux_gpio1_pins {
> +		pinctrl-single,pins = <
> +			0x5ca (PIN_OUTPUT_PULLDOWN | MUX_MODE4)   /* gpio_29 */
umm.. you might want to follow the convention as you followed later in
comments.
> +		>;
> +	};
> +
> +	uart1_pins: pinmux_uart1_pins {
> +		pinctrl-single,pins = <
> +			0x14c (PIN_OUTPUT | MUX_MODE0)   /* uart1_tx.uart1_tx */
> +			0x14e (PIN_OUTPUT | MUX_MODE0)   /* uart1_rts.uart1_rts */
> +			0x150 (PIN_INPUT | MUX_MODE0)    /* uart1_cts.uart1_cts */
> +			0x152 (PIN_INPUT | MUX_MODE0)    /* uart1_rx.uart1_rx */
> +		>;
you may be interested in include/dt-bindings/pinctrl/omap.h
OMAP3_CORE1_IOPAD, OMAP3_CORE2_IOPAD as needed here.

> +	};
> +
> +	uart2_pins: pinmux_uart2_pins {
> +		pinctrl-single,pins = <
> +			0x140 (PIN_OUTPUT | MUX_MODE1)   /* mcbsp3_clkx.uart2_tx */
> +			0x142 (PIN_INPUT | MUX_MODE1)    /* mcbsp3_fsx.uart2_rx */
> +		>;
> +	};
> +
> +	uart3_pins: pinmux_uart3_pins {
> +		pinctrl-single,pins = <
> +			0x16e (PIN_INPUT | MUX_MODE0)    /* uart3_rx_irrx.uart3_rx_irrx */
> +			0x170 (PIN_OUTPUT | MUX_MODE0)   /* uart3_tx_irtx.uart3_tx_irtx */
> +		>;
> +	};
> +
> +	i2c1_pins: pinmux_i2c1_pins {
> +		pinctrl-single,pins = <
> +			0x18a (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl */
> +			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda */
umm.. you might want to follow the convention as you followed
elsewhere in comments.
> +		>;
> +	};
> +
> +	i2c2_pins: pinmux_i2c2_pins {
> +		pinctrl-single,pins = <
> +			0x18e (PIN_INPUT | MUX_MODE0)   /* i2c2_scl.i2c2_scl */
> +			0x190 (PIN_INPUT | MUX_MODE0)   /* i2c2_sda.i2c2_sda */
> +		>;
> +	};
> +
> +	i2c3_pins: pinmux_i2c3_pins {
> +		pinctrl-single,pins = <
> +			0x192 (PIN_INPUT | MUX_MODE0)   /* i2c3_scl.i2c3_scl */
> +			0x194 (PIN_INPUT | MUX_MODE0)   /* i2c3_sda.i2c3_sda */
> +		>;
> +	};
> +
> +	hsusb1_pins: pinmux_hsusb1_pins {
> +		pinctrl-single,pins = <
> +			0x5a8 (PIN_OUTPUT | MUX_MODE3)  /* etk_clk.hsusb1_stp */
&omap3_pmx_core2 and OMAP3_CORE2_IOPAD probably here. and probably see
similar usage in other board dtsi.
> +			0x5aa (PIN_INPUT | MUX_MODE3)   /* etk_ctl.hsusb1_clk */
> +			0x5ac (PIN_INPUT | MUX_MODE3)   /* etk_d0.hsusb1_data0 */
> +			0x5ae (PIN_INPUT | MUX_MODE3)   /* etk_d1.hsusb1_data1 */
> +			0x5b0 (PIN_INPUT | MUX_MODE3)   /* etk_d2.hsusb1_data2 */
> +			0x5b2 (PIN_INPUT | MUX_MODE3)   /* etk_d3.hsusb1_data7 */
> +			0x5b4 (PIN_INPUT | MUX_MODE3)   /* etk_d4.hsusb1_data4 */
> +			0x5b6 (PIN_INPUT | MUX_MODE3)   /* etk_d5.hsusb1_data5 */
> +			0x5b8 (PIN_INPUT | MUX_MODE3)   /* etk_d6.hsusb1_data6 */
> +			0x5ba (PIN_INPUT | MUX_MODE3)   /* etk_d7.hsusb1_data3 */
> +			0x5bc (PIN_INPUT | MUX_MODE3)   /* etk_d8.hsusb1_dir */
> +			0x5be (PIN_INPUT | MUX_MODE3)   /* etk_d9.hsusb1_nxt */
> +
> +			/* GPIO 128 controls USB-Hub reset. But USB-Phy its
> +			 * reset can't be controlled. So we clamp this GPIO to
> +			 * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub.
> +			 */
> +
> +			0x1ae (PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4)   /* gpio_182 */
> +		>;
> +	};
> +
> +	hsusb_otg_pins: pinmux_hsusb_otg_pins {
> +		pinctrl-single,pins = <
> +			0x172 (PIN_INPUT | MUX_MODE0)   /* hsusb0_clk.hsusb0_clk */
> +			0x174 (PIN_OUTPUT | MUX_MODE0)  /* hsusb0_stp.hsusb0_stp */
> +			0x176 (PIN_INPUT | MUX_MODE0)   /* hsusb0_dir.hsusb0_dir */
> +			0x178 (PIN_INPUT | MUX_MODE0)   /* hsusb0_nxt.hsusb0_nxt */
> +			0x17a (PIN_INPUT | MUX_MODE0)   /* hsusb0_data0.hsusb0_data0 */
> +			0x17c (PIN_INPUT | MUX_MODE0)   /* hsusb0_data1.hsusb0_data1 */
> +			0x17e (PIN_INPUT | MUX_MODE0)   /* hsusb0_data2.hsusb0_data2 */
> +			0x180 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data3.hsusb0_data3 */
> +			0x182 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data4.hsusb0_data4 */
> +			0x184 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data5.hsusb0_data5 */
> +			0x186 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data6.hsusb0_data6 */
> +			0x188 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data7.hsusb0_data7 */
> +		>;
> +	};
> +
> +	mmc1_pins: pinmux_mmc1_pins {
> +		pinctrl-single,pins = <
> +			0x114 (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_clk.sdmmc1_clk */
> +			0x116 (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_cmd.sdmmc1_cmd */
> +			0x118 (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat0.sdmmc1_dat0 */
> +			0x11a (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat1.sdmmc1_dat1 */
> +			0x11c (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat2.sdmmc1_dat2 */
> +			0x11e (PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat3.sdmmc1_dat3 */
> +		>;
> +	};
> +
> +	spi2_pins: pinmux_spi2_pins {
> +		pinctrl-single,pins = <
> +			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_clk.mcspi2_clk */
> +			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_simo.mcspi2_simo */
> +			0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_somi.mcspi2_somi */
> +			0x1ac (PIN_OUTPUT | MUX_MODE0)   /* mcspi2_cs0.mcspi2_cs0 */
> +		>;
> +	};
> +};
> +
> +&gpio1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gpio1_pins>;
> +};
> +
> +&i2c1 {
> +	clock-frequency = <2600000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c1_pins>;
> +
> +	twl: twl@48 {
> +		reg = <0x48>;
> +		interrupts = <7>;   /* SYS_NIRQ cascaded to intc */
> +		interrupt-parent = <&intc>;
> +
> +		twl_audio: audio {
> +			compatible = "ti,twl4030-audio";
> +			codec {
> +			};
> +		};
> +	};
> +};
> +
> +#include "twl4030.dtsi"
> +#include "twl4030_omap3.dtsi"
> +
> +&twl {
> +	vmmc1: regulator-vmmc1 {
> +		regulator-always-on;
> +	};
> +
> +	vdd1: regulator-vdd1 {
> +		regulator-always-on;
> +	};
> +
> +	vdd2: regulator-vdd2 {
> +		regulator-always-on;
> +	};
I hope you have covered all required regulators here including the
ones you might need for IO.1P8 perhaps?

> +};
> +
> +&i2c2 {
> +	clock-frequency = <2600000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c2_pins>;
> +};
> +
> +&i2c3 {
> +	clock-frequency = <2600000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c3_pins>;
> +		gpiom1: gpio@20 {
> +			compatible = "mcp,mcp23017";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0x20>;
> +		};
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart1_pins>;
> +};
> +
> +&uart2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart2_pins>;
> +};
> +
> +&uart3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart3_pins>;
> +};
> +
> +&uart4 {
> +	status = "disabled";
> +};
> +
> +&mmc1 {
> +	reg = <0x4809c000 0x400>;
little curious as to why this. is that to override length 0x200 to
0x400? that belongs to soc.dtsi then.

> +	cd-gpios = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
> +	cd-inverted;
> +	vmmc-supply = <&vmmc1>;
> +	bus-width = <4>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mmc1_pins &mmc1cd_pins>;
> +	cap-sdio-irq;
> +	cap-sd-highspeed;
> +	cap-mmc-highspeed;
> +};
> +
> +&mmc2 {
> +	status = "disabled";
> +};
> +
> +&mmc3 {
> +	status = "disabled";
> +};
> +
> +&mcspi2 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi2_pins>;
> +
> +	tsc2046@0 {
> +		reg = <0>;   /* CS0 */
> +		compatible = "ti,tsc2046";
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <8 0>;   /* boot6 / gpio_8 */
> +		spi-max-frequency = <1000000>;
> +		pendown-gpio = <&gpio1 8 0>;
> +		vcc-supply = <&reg_vcc3>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&tsc2048_pins>;
> +
> +		ti,x-min = <300>;
> +		ti,x-max = <3000>;
> +		ti,y-min = <600>;
> +		ti,y-max = <3600>;
> +		ti,x-plate-ohms = <80>;
> +		ti,pressure-max = <255>;
> +		ti,swap-xy;
> +
> +		linux,wakeup;
> +	};
> +};
> +
> +&usbhsehci {
> +	phys = <&hsusb1_phy>;
> +};
> +
> +&usbhshost {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&hsusb1_pins>;
> +	num-ports = <2>;
> +	port1-mode = "ehci-phy";
> +};
> +
> +&usb_otg_hs {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&hsusb_otg_pins>;
> +	interface-type = <0>;
> +	usb-phy = <&usb2_phy>;
> +	phys = <&usb2_phy>;
> +	phy-names = "usb2-phy";
> +	mode = <3>;
> +	power = <50>;
> +};
> +
> +&gpmc {
> +	ranges = <0 0 0x30000000 0x1000000>,
> +		<7 0 0x15000000 0x01000000>;
> +
> +	nand@0,0 {
> +		reg = <0 0 0x1000000>;
> +		nand-bus-width = <16>;
> +		ti,nand-ecc-opt = "bch8";
> +		/* no elm on omap3 */
> +
> +		gpmc,mux-add-data = <0>;
> +		gpmc,device-nand;
> +		gpmc,device-width = <2>;
> +		gpmc,wait-pin = <0>;
> +		gpmc,wait-monitoring-ns = <0>;
> +		gpmc,burst-length= <4>;
> +		gpmc,cs-on-ns = <0>;
> +		gpmc,cs-rd-off-ns = <100>;
> +		gpmc,cs-wr-off-ns = <100>;
> +		gpmc,adv-on-ns = <0>;
> +		gpmc,adv-rd-off-ns = <100>;
> +		gpmc,adv-wr-off-ns = <100>;
> +		gpmc,oe-on-ns = <5>;
> +		gpmc,oe-off-ns = <75>;
> +		gpmc,we-on-ns = <5>;
> +		gpmc,we-off-ns = <75>;
> +		gpmc,rd-cycle-ns = <100>;
> +		gpmc,wr-cycle-ns = <100>;
> +		gpmc,access-ns = <60>;
> +		gpmc,page-burst-access-ns = <5>;
> +		gpmc,bus-turnaround-ns = <0>;
> +		gpmc,cycle2cycle-samecsen;
> +		gpmc,cycle2cycle-delay-ns = <50>;
> +		gpmc,wr-data-mux-bus-ns = <75>;
> +		gpmc,wr-access-ns = <155>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		partition@0 {
> +			label = "MLO";
> +			reg = <0 0x80000>;
> +		};
> +
> +		partition@0x80000 {
> +			label = "u-boot";
> +			reg = <0x80000 0x1e0000>;
> +		};
> +
> +		partition@0x260000 {
> +			label = "u-boot-environment";
> +			reg = <0x260000 0x20000>;
> +		};
> +
> +		partition@0x280000 {
> +			label = "kernel";
> +			reg = <0x280000 0x500000>;
> +		};
> +
> +		partition@0x780000 {
> +			label = "filesystem";
> +			reg = <0x780000 0xf880000>;
> +		};
> +	};
> +
> +	ethernet@7,0 {
> +		compatible = "smsc,lan9221", "smsc,lan9115";
> +		bank-width = <2>;
> +		gpmc,mux-add-data = <2>;
> +		gpmc,cs-on-ns = <10>;
> +		gpmc,cs-rd-off-ns = <60>;
> +		gpmc,cs-wr-off-ns = <60>;
> +		gpmc,adv-on-ns = <0>;
> +		gpmc,adv-rd-off-ns = <10>;
> +		gpmc,adv-wr-off-ns = <10>;
> +		gpmc,oe-on-ns = <10>;
> +		gpmc,oe-off-ns = <60>;
> +		gpmc,we-on-ns = <10>;
> +		gpmc,we-off-ns = <60>;
> +		gpmc,rd-cycle-ns = <100>;
> +		gpmc,wr-cycle-ns = <100>;
> +		gpmc,access-ns = <50>;
> +		gpmc,page-burst-access-ns = <5>;
> +		gpmc,bus-turnaround-ns = <0>;
> +		gpmc,cycle2cycle-delay-ns = <75>;
> +		gpmc,wr-data-mux-bus-ns = <15>;
> +		gpmc,wr-access-ns = <75>;
> +		gpmc,cycle2cycle-samecsen;
> +		gpmc,cycle2cycle-diffcsen;
> +		vddvario-supply = <&reg_vcc3>;
> +		vdd33a-supply = <&reg_vcc3>;
> +		reg-io-width = <4>;
> +		interrupt-parent = <&gpio5>;
> +		interrupts = <1 0x2>;
> +		reg = <7 0 0xff>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&lan9221_pins>;
> +		phy-mode = "mii";
> +	};
> +};
> 


-- 
Regards,
Nishanth Menon

Re: [PATCH v2 4/5] ARM: OMAP2+: Add pdata quirk for sys_clkout2 for omap3 DBB056

[Christoph Fritz]

Hi Nishanth,

 thanks for reviewing this patch. Please see my comments below.

On Wed, Jan 22, 2014 at 01:33:21PM -0600, Nishanth Menon wrote:
> On 01/22/2014 01:04 PM, Christoph Fritz wrote:
> > Full device tree support for clock control is not yet accomplished. Until
> > then, configure the 24Mhz of sys_clkout2 to feed an USB-Hub here.
> > 
> > Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> > ---
> >  arch/arm/mach-omap2/pdata-quirks.c |   37 ++++++++++++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> > 
> > diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
> > index a58590f..9ef7ca8 100644
> > --- a/arch/arm/mach-omap2/pdata-quirks.c
> > +++ b/arch/arm/mach-omap2/pdata-quirks.c
> > @@ -171,6 +171,43 @@ static void __init am3517_evm_legacy_init(void)
> >  }
> >  static void __init omap3_dbb056_legacy_init(void)
> >  {
> > +	struct clk *clkout2;
> > +	struct clk *cm96fck;
> > +
> > +	/* Reparent clkout2 to 96M_FCK */
> > +	pr_info("a83x-quirk: Late Reparent clkout2 to 96M_FCK\n");
> what'd be a83x?

It's the computer-on-module name. Will get changed to __func__.

> > +	clkout2 = clk_get(NULL, "clkout2_src_ck");
> > +	if(clkout2 < 0) {
> > +		pr_err("a83x-quirk: couldn't get clkout2_src_ck\n");
> > +		return;
> > +	}
> > +	cm96fck = clk_get(NULL, "cm_96m_fck");
> > +	if(cm96fck < 0) {
> > +		pr_err("a83x-quirk: couldn't get cm_96m_fck\n");
> > +		return;
> > +	}
> > +	if(clk_set_parent(clkout2, cm96fck) < 0) {
> > +		pr_err("a83x-quirk: couldn't reparent clkout2_src_ck\n");
> > +		return;
> > +	}
> yep - we have bunch of similar code in drivers/clk/ti -> but we'd need
> a generic property to handle this.

This whole quirk of configuring sys_clkout2 in a platform file will
go away. Tero is planning to post some RFC patches to configure this
by DT.

> > +
> > +	/* Set clkout2 to 24MHz for internal usb hub*/
> > +	pr_info("a83x-quirk: Set clkout2 to 24MHz for internal usb hub\n");
> > +	clkout2 = clk_get(NULL, "sys_clkout2");
> > +	if(clkout2 < 0) {
> > +		pr_err("a83x-quirk: couldn't get sys_clkout2\n");
> > +		return;
> > +	}
> > +	if(clk_set_rate(clkout2, 24000000) < 0) {
> same here.
> > +		printk(KERN_ERR "board-omap3evm: couldn't set sys_clkout2 rate\n");
> "board-omap3evm:" copy paste?
> any reason why not pr_err?

will get fixed

> > +		return;
> > +	}
> > +	if(clk_prepare_enable(clkout2) < 0) {
> > +		pr_err("a83x-quirk: couldn't enable sys_clkout2\n");
> > +		return;
> > +	}
> > +
> > +	/* Initialize display */
> >  	omap3_dbb056_display_init_of();
> >  }
> >  #endif /* CONFIG_ARCH_OMAP3 */
> > 
> 
> looking at the coding style, I assume we'd missed running
> checkpatch.pl --strict?

Let me reroll this patch in a new v3 set.

Thanks
  -- Christoph

Re: [PATCH v2 1/5] ARM: dts: omap3: Add support for INCOstartec a83x module

[Christoph Fritz]

Hi Nishanth,

 thanks for reviewing this patch. Please see my comments below.

On Wed, Jan 22, 2014 at 01:48:14PM -0600, Nishanth Menon wrote:
> On 01/22/2014 01:04 PM, Christoph Fritz wrote:

> > +	regulators {
> > +		compatible = "simple-bus";
> Shrug, just moving the fixed regulator to root also will do the job,
> not sure simple-bus much sense here :(
> 

will get fixed

> > +		reg_vcc3: vcc3 {
> > +                        compatible = "regulator-fixed";
> > +                        regulator-name = "VCC3";
> > +                        regulator-min-microvolt = <3300000>;
> > +                        regulator-max-microvolt = <3300000>;
> > +                        regulator-always-on;
> > +		};
> > +	};
> > +
> > +	hsusb1_phy: hsusb1_phy {
> > +		compatible = "usb-nop-xceiv";
> > +		vcc-supply = <&reg_vcc3>;
> > +	};
> > +};
> > +
> > +&omap3_pmx_wkup {
> > +	pinctrl-names = "default";
> > +
> > +	lan9221_pins: pinmux_lan9221_pins {
> > +		pinctrl-single,pins = <
> > +			0x5A (PIN_INPUT | MUX_MODE4)   /* gpio_129 */
> umm.. you might want to follow the convention as you followed later in
> comments.

My convention was: If pin can be described unique with one name,
don't use two. But I'll change that to be uniform with all comments.

> > +		>;
> > +	};
> > +
> > +	tsc2048_pins: pinmux_tsc2048_pins {
> > +		pinctrl-single,pins = <
> > +			0x16 (PIN_INPUT_PULLUP | MUX_MODE4)   /* gpio_8 */
> umm.. you might want to follow the convention as you followed later in
> comments.

will get fixed

> > +		>;
> > +	};
> > +
> > +	mmc1cd_pins: pinmux_mmc1cd_pins {
> > +		pinctrl-single,pins = <
> > +			0x56 (PIN_INPUT | MUX_MODE4)   /* gpio_126 */
> umm.. you might want to follow the convention as you followed later in
> comments.

will get fixed

> > +		>;
> > +	};
> > +};
> > +
> > +&omap3_pmx_core {
> > +	pinctrl-names = "default";
> > +
> > +	gpio1_pins: pinmux_gpio1_pins {
> > +		pinctrl-single,pins = <
> > +			0x5ca (PIN_OUTPUT_PULLDOWN | MUX_MODE4)   /* gpio_29 */
> umm.. you might want to follow the convention as you followed later in
> comments.

will get fixed

> > +		>;
> > +	};
> > +
> > +	uart1_pins: pinmux_uart1_pins {
> > +		pinctrl-single,pins = <
> > +			0x14c (PIN_OUTPUT | MUX_MODE0)   /* uart1_tx.uart1_tx */
> > +			0x14e (PIN_OUTPUT | MUX_MODE0)   /* uart1_rts.uart1_rts */
> > +			0x150 (PIN_INPUT | MUX_MODE0)    /* uart1_cts.uart1_cts */
> > +			0x152 (PIN_INPUT | MUX_MODE0)    /* uart1_rx.uart1_rx */
> > +		>;
> you may be interested in include/dt-bindings/pinctrl/omap.h
> OMAP3_CORE1_IOPAD, OMAP3_CORE2_IOPAD as needed here.

will get fixed

> > +	};
> > +
> > +	uart2_pins: pinmux_uart2_pins {
> > +		pinctrl-single,pins = <
> > +			0x140 (PIN_OUTPUT | MUX_MODE1)   /* mcbsp3_clkx.uart2_tx */
> > +			0x142 (PIN_INPUT | MUX_MODE1)    /* mcbsp3_fsx.uart2_rx */
> > +		>;
> > +	};
> > +
> > +	uart3_pins: pinmux_uart3_pins {
> > +		pinctrl-single,pins = <
> > +			0x16e (PIN_INPUT | MUX_MODE0)    /* uart3_rx_irrx.uart3_rx_irrx */
> > +			0x170 (PIN_OUTPUT | MUX_MODE0)   /* uart3_tx_irtx.uart3_tx_irtx */
> > +		>;
> > +	};
> > +
> > +	i2c1_pins: pinmux_i2c1_pins {
> > +		pinctrl-single,pins = <
> > +			0x18a (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl */
> > +			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda */
> umm.. you might want to follow the convention as you followed
> elsewhere in comments.

will get fixed

> > +		>;
> > +	};
> > +
> > +	i2c2_pins: pinmux_i2c2_pins {
> > +		pinctrl-single,pins = <
> > +			0x18e (PIN_INPUT | MUX_MODE0)   /* i2c2_scl.i2c2_scl */
> > +			0x190 (PIN_INPUT | MUX_MODE0)   /* i2c2_sda.i2c2_sda */
> > +		>;
> > +	};
> > +
> > +	i2c3_pins: pinmux_i2c3_pins {
> > +		pinctrl-single,pins = <
> > +			0x192 (PIN_INPUT | MUX_MODE0)   /* i2c3_scl.i2c3_scl */
> > +			0x194 (PIN_INPUT | MUX_MODE0)   /* i2c3_sda.i2c3_sda */
> > +		>;
> > +	};
> > +
> > +	hsusb1_pins: pinmux_hsusb1_pins {
> > +		pinctrl-single,pins = <
> > +			0x5a8 (PIN_OUTPUT | MUX_MODE3)  /* etk_clk.hsusb1_stp */
> &omap3_pmx_core2 and OMAP3_CORE2_IOPAD probably here. and probably see
> similar usage in other board dtsi.

will get fixed

> > +
> > +#include "twl4030.dtsi"
> > +#include "twl4030_omap3.dtsi"
> > +
> > +&twl {
> > +	vmmc1: regulator-vmmc1 {
> > +		regulator-always-on;
> > +	};
> > +
> > +	vdd1: regulator-vdd1 {
> > +		regulator-always-on;
> > +	};
> > +
> > +	vdd2: regulator-vdd2 {
> > +		regulator-always-on;
> > +	};
> I hope you have covered all required regulators here including the
> ones you might need for IO.1P8 perhaps?

Yes, I rechecked all and it's fine now. IO.1P8 was low due to a
hardware error which is now fixed.

> > +
> > +&mmc1 {
> > +	reg = <0x4809c000 0x400>;
> little curious as to why this. is that to override length 0x200 to
> 0x400? that belongs to soc.dtsi then.

This is a remnant from last year and will get purged.

Let me reroll this patch in a new v3 set.

Thanks
  -- Christoph