[PATCH V2 00/10] exynos: add basic support for exynos5260 SoC

[PATCH V2 00/10] exynos: add basic support for exynos5260 SoC

[Rahul Sharma]

Add basic support for exynos5260 SoC.

This series is based on linux-next, Kukjin's for-next and
Mike's clk-for-linus-3.13 branches.

This patch is dependent on the following series from
Tomasz Figa <t.figa@samsung.com>:
http://www.spinics.net/lists/arm-kernel/msg280223.html

V2:
  1) Move suspend resume handling to Exynos5410 Clock file.
  2) Removed Unused Macros and Condition checks for Exynos5260.
  3) Add spin lock to clock provider context.
  4) Add clock provider context for Exynos5410.
  5) Uniform implementation for callbacks for PLL2550xx.
  6) Split Exynos5260 clock file patch to bring it under 100 Kb limit.
  7) Replace aclk/pclk/hclk gates with combined gates.
  8) Remove CLK_IGNORE_UNUSED flag for gate clocks.
  9) Split up DT patch into SoC and Board patch.

Pankaj Dubey (2):
  ARM: EXYNOS: initial board support for exynos5260 SoC
  clk/samsung: add support for pll2550xx

Rahul Sharma (7):
  clk/exynos5410: Move suspend/resume handling to SoC driver
  clk/samsung: add support for multuple clock providers
  clk/samsung: add support for pll2650xx
  clk/exynos5260: add macros and documentation for exynos5260
  clk/exynos5260: add clock file for exynos5260
  ARM: dts: add dts files for exynos5260 SoC
  ARM: dts: add dts files for xyref5260 board

Young-Gun Jang (1):
  pinctrl: exynos: add exynos5260 SoC specific data

 .../devicetree/bindings/clock/exynos5260-clock.txt |  299 +++
 .../bindings/pinctrl/samsung-pinctrl.txt           |    1 +
 arch/arm/boot/dts/Makefile                         |    1 +
 arch/arm/boot/dts/exynos5260-pinctrl.dtsi          |  572 ++++++
 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts    |  105 +
 arch/arm/boot/dts/exynos5260.dtsi                  |  317 +++
 arch/arm/mach-exynos/Kconfig                       |    9 +
 arch/arm/mach-exynos/common.c                      |   19 +-
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    1 +
 arch/arm/plat-samsung/include/plat/cpu.h           |    8 +
 arch/arm/plat-samsung/include/plat/map-s5p.h       |    1 +
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-exynos4.c                  |   47 +-
 drivers/clk/samsung/clk-exynos5250.c               |   26 +-
 drivers/clk/samsung/clk-exynos5260.c               | 2062 ++++++++++++++++++++
 drivers/clk/samsung/clk-exynos5260.h               |  496 +++++
 drivers/clk/samsung/clk-exynos5410.c               |   59 +-
 drivers/clk/samsung/clk-exynos5420.c               |   24 +-
 drivers/clk/samsung/clk-exynos5440.c               |   18 +-
 drivers/clk/samsung/clk-pll.c                      |  223 ++-
 drivers/clk/samsung/clk-pll.h                      |    3 +-
 drivers/clk/samsung/clk-s3c64xx.c                  |   44 +-
 drivers/clk/samsung/clk.c                          |  115 +-
 drivers/clk/samsung/clk.h                          |   72 +-
 drivers/pinctrl/pinctrl-exynos.c                   |   82 +
 drivers/pinctrl/pinctrl-samsung.c                  |    2 +
 drivers/pinctrl/pinctrl-samsung.h                  |    1 +
 include/dt-bindings/clk/exynos5260-clk.h           |  234 +++
 29 files changed, 4684 insertions(+), 159 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
 create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
 create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
 create mode 100644 drivers/clk/samsung/clk-exynos5260.c
 create mode 100644 drivers/clk/samsung/clk-exynos5260.h
 create mode 100644 include/dt-bindings/clk/exynos5260-clk.h

-- 
1.7.9.5

[PATCH V2 01/10] clk/exynos5410: move suspend/resume handling to SoC driver

[Rahul Sharma]

Suspend/resume handling is already moved for all other Exynos
SoCs other than Exynos5420 which is addressed in this patch.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 drivers/clk/samsung/clk-exynos5410.c |   49 ++++++++++++++++++++++++++++++----
 1 file changed, 44 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index 858b3ff..f94c493 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -16,6 +16,7 @@
 #include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/syscore_ops.h>
 
 #include "clk.h"
 
@@ -60,6 +61,11 @@ enum exynos5410_plls {
 	nr_plls			/* number of PLLs */
 };
 
+static void __iomem *reg_base;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos5410_save;
+
 /*
  * list of controller registers to be saved and restored during a
  * suspend/resume cycle.
@@ -89,6 +95,41 @@ static unsigned long exynos5410_clk_regs[] __initdata = {
 	DIV_KFC0,
 };
 
+static int exynos5410_clk_suspend(void)
+{
+	samsung_clk_save(reg_base, exynos5410_save,
+				ARRAY_SIZE(exynos5410_clk_regs));
+
+	return 0;
+}
+
+static void exynos5410_clk_resume(void)
+{
+	samsung_clk_restore(reg_base, exynos5410_save,
+				ARRAY_SIZE(exynos5410_clk_regs));
+}
+
+static struct syscore_ops exynos5410_clk_syscore_ops = {
+	.suspend = exynos5410_clk_suspend,
+	.resume = exynos5410_clk_resume,
+};
+
+static void exynos5410_clk_sleep_init(void)
+{
+	exynos5410_save = samsung_clk_alloc_reg_dump(exynos5410_clk_regs,
+					ARRAY_SIZE(exynos5410_clk_regs));
+	if (!exynos5410_save) {
+		pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
+			__func__);
+		return;
+	}
+
+	register_syscore_ops(&exynos5410_clk_syscore_ops);
+}
+#else
+static void exynos5410_clk_sleep_init(void) {}
+#endif
+
 /* list of all parent clocks */
 PNAME(apll_p)		= { "fin_pll", "fout_apll", };
 PNAME(bpll_p)		= { "fin_pll", "fout_bpll", };
@@ -214,15 +255,11 @@ static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
 /* register exynos5410 clocks */
 static void __init exynos5410_clk_init(struct device_node *np)
 {
-	void __iomem *reg_base;
-
 	reg_base = of_iomap(np, 0);
 	if (!reg_base)
 		panic("%s: failed to map registers\n", __func__);
 
-	samsung_clk_init(np, reg_base, CLK_NR_CLKS,
-			exynos5410_clk_regs, ARRAY_SIZE(exynos5410_clk_regs),
-			NULL, 0);
+	samsung_clk_init(np, reg_base, CLK_NR_CLKS);
 
 	samsung_clk_register_pll(exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
 					reg_base);
@@ -234,6 +271,8 @@ static void __init exynos5410_clk_init(struct device_node *np)
 	samsung_clk_register_gate(exynos5410_gate_clks,
 			ARRAY_SIZE(exynos5410_gate_clks));
 
+	exynos5410_clk_sleep_init();
+
 	pr_debug("Exynos5410: clock setup completed.\n");
 }
 CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
-- 
1.7.9.5

Re: [PATCH V2 01/10] clk/exynos5410: move suspend/resume handling to SoC driver

[Tomasz Figa]

On 07.01.2014 13:58, Rahul Sharma wrote:
> Suspend/resume handling is already moved for all other Exynos
> SoCs other than Exynos5420 which is addressed in this patch.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
>   drivers/clk/samsung/clk-exynos5410.c |   49 ++++++++++++++++++++++++++++++----
>   1 file changed, 44 insertions(+), 5 deletions(-)

Acked-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

[PATCH V2 02/10] ARM: EXYNOS: initial board support for exynos5260 SoC

[Rahul Sharma]

From: Pankaj Dubey <pankaj.dubey@samsung.com>

This patch add basic arch side support for exynos5260 SoC.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 arch/arm/mach-exynos/Kconfig                 |    9 +++++++++
 arch/arm/mach-exynos/common.c                |   19 ++++++++++++++++++-
 arch/arm/mach-exynos/include/mach/map.h      |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c       |    1 +
 arch/arm/plat-samsung/include/plat/cpu.h     |    8 ++++++++
 arch/arm/plat-samsung/include/plat/map-s5p.h |    1 +
 6 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 35c335d..60cbf03 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -101,6 +101,15 @@ config SOC_EXYNOS5410
 	help
 	  Enable EXYNOS5410 SoC support
 
+config SOC_EXYNOS5260
+	bool "SAMSUNG EXYNOS5260"
+	default y
+	depends on ARCH_EXYNOS5
+	select AUTO_ZRELADDR
+	select SAMSUNG_DMADEV
+	help
+	  Enable EXYNOS5260 SoC support
+
 config SOC_EXYNOS5420
 	bool "SAMSUNG EXYNOS5420"
 	default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 09e6898..e0c7108 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
 static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5260[] = "EXYNOS5260";
 static const char name_exynos5410[] = "EXYNOS5410";
 static const char name_exynos5420[] = "EXYNOS5420";
 static const char name_exynos5440[] = "EXYNOS5440";
@@ -92,6 +93,12 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.init		= exynos_init,
 		.name		= name_exynos5410,
 	}, {
+		.idcode		= EXYNOS5260_SOC_ID,
+		.idmask		= EXYNOS5_SOC_MASK,
+		.map_io		= exynos5_map_io,
+		.init		= exynos_init,
+		.name		= name_exynos5260,
+	}, {
 		.idcode		= EXYNOS5420_SOC_ID,
 		.idmask		= EXYNOS5_SOC_MASK,
 		.map_io		= exynos5_map_io,
@@ -279,6 +286,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
 	},
 };
 
+static struct map_desc exynos5260_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
+		.pfn		= __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
 void exynos4_restart(enum reboot_mode mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
@@ -387,9 +403,10 @@ static void __init exynos4_map_io(void)
 static void __init exynos5_map_io(void)
 {
 	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
-
 	if (soc_is_exynos5250())
 		iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+	if (soc_is_exynos5260())
+		iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
 	if (soc_is_exynos5410())
 		iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
 }
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 894f431..188bb78 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -30,6 +30,7 @@
 #define EXYNOS4x12_PA_SYSRAM_NS		0x0204F000
 #define EXYNOS5250_PA_SYSRAM_NS		0x0204F000
 #define EXYNOS5410_PA_SYSRAM_NS		0x02073000
+#define EXYNOS5260_PA_SYSRAM_NS		0x02073000
 
 #define EXYNOS_PA_CHIPID		0x10000000
 
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 9bb6eac..7d3838a 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
 
 static char const *exynos5_dt_compat[] __initdata = {
 	"samsung,exynos5250",
+	"samsung,exynos5260",
 	"samsung,exynos5410",
 	"samsung,exynos5420",
 	"samsung,exynos5440",
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 8f09488..4daa9b3 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4_CPU_MASK	0xFFFE0000
 
 #define EXYNOS5250_SOC_ID	0x43520000
+#define EXYNOS5260_SOC_ID	0xE5260000
 #define EXYNOS5410_SOC_ID	0xE5410000
 #define EXYNOS5420_SOC_ID	0xE5420000
 #define EXYNOS5440_SOC_ID	0xE5440000
@@ -69,6 +70,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5260, EXYNOS5260_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
@@ -156,6 +158,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_exynos5410()	0
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5260)
+# define soc_is_exynos5260()	is_samsung_exynos5260()
+#else
+# define soc_is_exynos5260()	0
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5420)
 # define soc_is_exynos5420()	is_samsung_exynos5420()
 #else
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index 31cac97..13c802b 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -23,6 +23,7 @@
 
 #define S5P_VA_SYSRAM		S3C_ADDR(0x02400000)
 #define S5P_VA_SYSRAM_NS	S3C_ADDR(0x02410000)
+
 #define S5P_VA_DMC0		S3C_ADDR(0x02440000)
 #define S5P_VA_DMC1		S3C_ADDR(0x02480000)
 #define S5P_VA_SROMC		S3C_ADDR(0x024C0000)
-- 
1.7.9.5

Re: [PATCH V2 02/10] ARM: EXYNOS: initial board support for exynos5260 SoC

[Arnd Bergmann]

On Tuesday 07 January 2014 18:29:00 Rahul Sharma wrote:
> From: Pankaj Dubey <pankaj.dubey@samsung.com>
> 
> This patch add basic arch side support for exynos5260 SoC.
> 
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 09e6898..e0c7108 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
>  static const char name_exynos4212[] = "EXYNOS4212";
>  static const char name_exynos4412[] = "EXYNOS4412";
>  static const char name_exynos5250[] = "EXYNOS5250";
> +static const char name_exynos5260[] = "EXYNOS5260";
>  static const char name_exynos5410[] = "EXYNOS5410";
>  static const char name_exynos5420[] = "EXYNOS5420";
>  static const char name_exynos5440[] = "EXYNOS5440";
> @@ -92,6 +93,12 @@ static struct cpu_table cpu_ids[] __initdata = {
>  		.init		= exynos_init,
>  		.name		= name_exynos5410,
>  	}, {
> +		.idcode		= EXYNOS5260_SOC_ID,
> +		.idmask		= EXYNOS5_SOC_MASK,
> +		.map_io		= exynos5_map_io,
> +		.init		= exynos_init,
> +		.name		= name_exynos5260,
> +	}, {
>  		.idcode		= EXYNOS5420_SOC_ID,
>  		.idmask		= EXYNOS5_SOC_MASK,
>  		.map_io		= exynos5_map_io,

I think we've seen enough of these. Please generalize it enough
so we won't need to add any more entries whenever a new SoC
comes up. It's probably fine for now to have to tell the difference
between EXYNOS4 and EXYNOS5, but not new chips within some family.

According to rumors on the web, EXYNOS6 is going to be released
soon with a 64-bit CPU in it, and since we don't allow platform
specific code for arm64 like this any more, you should just
drop it for arm32 as well.

> @@ -279,6 +286,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
>  	},
>  };
>  
> +static struct map_desc exynos5260_iodesc[] __initdata = {
> +	{
> +		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
> +		.pfn		= __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE,
> +	},
> +};
> +
>  void exynos4_restart(enum reboot_mode mode, const char *cmd)
>  {
>  	__raw_writel(0x1, S5P_SWRESET);

The only difference you have is the map descriptor, and that should
go away if you only add a proper DT binding for SYSRAM. Try to get
rid of the remaining map_desc entries while you're at it.

> diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
> index 31cac97..13c802b 100644
> --- a/arch/arm/plat-samsung/include/plat/map-s5p.h
> +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
> @@ -23,6 +23,7 @@
>  
>  #define S5P_VA_SYSRAM		S3C_ADDR(0x02400000)
>  #define S5P_VA_SYSRAM_NS	S3C_ADDR(0x02410000)
> +
>  #define S5P_VA_DMC0		S3C_ADDR(0x02440000)
>  #define S5P_VA_DMC1		S3C_ADDR(0x02480000)
>  #define S5P_VA_SROMC		S3C_ADDR(0x024C0000)
> 

This hunk doesn't really belong in the patch at all.

	Arnd

Re: [PATCH V2 02/10] ARM: EXYNOS: initial board support for exynos5260 SoC

[Rahul Sharma]

Thanks Arnd,

On 7 January 2014 18:54, Arnd Bergmann <arnd@arndb.de> wrote:
> On Tuesday 07 January 2014 18:29:00 Rahul Sharma wrote:
>> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>>
>> This patch add basic arch side support for exynos5260 SoC.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> ---
>> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
>> index 09e6898..e0c7108 100644
>> --- a/arch/arm/mach-exynos/common.c
>> +++ b/arch/arm/mach-exynos/common.c
>> @@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
>>  static const char name_exynos4212[] = "EXYNOS4212";
>>  static const char name_exynos4412[] = "EXYNOS4412";
>>  static const char name_exynos5250[] = "EXYNOS5250";
>> +static const char name_exynos5260[] = "EXYNOS5260";
>>  static const char name_exynos5410[] = "EXYNOS5410";
>>  static const char name_exynos5420[] = "EXYNOS5420";
>>  static const char name_exynos5440[] = "EXYNOS5440";
>> @@ -92,6 +93,12 @@ static struct cpu_table cpu_ids[] __initdata = {
>>               .init           = exynos_init,
>>               .name           = name_exynos5410,
>>       }, {
>> +             .idcode         = EXYNOS5260_SOC_ID,
>> +             .idmask         = EXYNOS5_SOC_MASK,
>> +             .map_io         = exynos5_map_io,
>> +             .init           = exynos_init,
>> +             .name           = name_exynos5260,
>> +     }, {
>>               .idcode         = EXYNOS5420_SOC_ID,
>>               .idmask         = EXYNOS5_SOC_MASK,
>>               .map_io         = exynos5_map_io,
>
> I think we've seen enough of these. Please generalize it enough
> so we won't need to add any more entries whenever a new SoC
> comes up. It's probably fine for now to have to tell the difference
> between EXYNOS4 and EXYNOS5, but not new chips within some family.
>
> According to rumors on the web, EXYNOS6 is going to be released
> soon with a 64-bit CPU in it, and since we don't allow platform
> specific code for arm64 like this any more, you should just
> drop it for arm32 as well.

I agree with you. Let me explore options to optimize this part of the
code. I prefer
to add code here (along with legacy ) to accept DT bindings for Exynos5 family
SoCs and use them for Exynos5260. Next, I will migrate the rest of the existing
platforms and get rid of existing platform code.

>
>> @@ -279,6 +286,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
>>       },
>>  };
>>
>> +static struct map_desc exynos5260_iodesc[] __initdata = {
>> +     {
>> +             .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
>> +             .pfn            = __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
>> +             .length         = SZ_4K,
>> +             .type           = MT_DEVICE,
>> +     },
>> +};
>> +
>>  void exynos4_restart(enum reboot_mode mode, const char *cmd)
>>  {
>>       __raw_writel(0x1, S5P_SWRESET);
>
> The only difference you have is the map descriptor, and that should
> go away if you only add a proper DT binding for SYSRAM. Try to get
> rid of the remaining map_desc entries while you're at it.
>

Ok. let me check this.

>> diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
>> index 31cac97..13c802b 100644
>> --- a/arch/arm/plat-samsung/include/plat/map-s5p.h
>> +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
>> @@ -23,6 +23,7 @@
>>
>>  #define S5P_VA_SYSRAM                S3C_ADDR(0x02400000)
>>  #define S5P_VA_SYSRAM_NS     S3C_ADDR(0x02410000)
>> +
>>  #define S5P_VA_DMC0          S3C_ADDR(0x02440000)
>>  #define S5P_VA_DMC1          S3C_ADDR(0x02480000)
>>  #define S5P_VA_SROMC         S3C_ADDR(0x024C0000)
>>
>
> This hunk doesn't really belong in the patch at all.

I will move it to correct patch.

Regards,
Rahul Sharma

>
>         Arnd

[PATCH V2 03/10] pinctrl: exynos: add exynos5260 SoC specific data

[Rahul Sharma]

From: Young-Gun Jang <yg1004.jang@samsung.com>

Add Samsung Exynos5260 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5260.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Young-Gun Jang <yg1004.jang@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
 .../bindings/pinctrl/samsung-pinctrl.txt           |    1 +
 drivers/pinctrl/pinctrl-exynos.c                   |   82 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.c                  |    2 +
 drivers/pinctrl/pinctrl-samsung.h                  |    1 +
 4 files changed, 86 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 257677d..2b32783 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -16,6 +16,7 @@ Required Properties:
   - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
   - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
   - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
+  - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
   - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
 
 - reg: Base address of the pin controller hardware module and length of
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 155b1b3..07c8130 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 	},
 };
 
+/* pin banks of exynos5260 pin-controller 0 */
+static struct samsung_pin_bank exynos5260_pin_banks0[] = {
+	EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
+	EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
+	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+	EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
+	EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
+	EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
+	EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
+	EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
+	EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
+	EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
+	EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
+	EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
+	EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
+	EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
+	EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
+	EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
+	EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
+};
+
+/* pin banks of exynos5260 pin-controller 1 */
+static struct samsung_pin_bank exynos5260_pin_banks1[] = {
+	EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
+	EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
+	EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
+	EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
+	EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
+};
+
+/* pin banks of exynos5260 pin-controller 2 */
+static struct samsung_pin_bank exynos5260_pin_banks2[] = {
+	EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
+	EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
+ * three gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
+	{
+		/* pin-controller instance 0 data */
+		.pin_banks	= exynos5260_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos5260_pin_banks0),
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.weint_con	= EXYNOS_WKUP_ECON_OFFSET,
+		.weint_mask	= EXYNOS_WKUP_EMASK_OFFSET,
+		.weint_pend	= EXYNOS_WKUP_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.eint_wkup_init = exynos_eint_wkup_init,
+		.label		= "exynos5260-gpio-ctrl0",
+	}, {
+		/* pin-controller instance 1 data */
+		.pin_banks	= exynos5260_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos5260_pin_banks1),
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.label		= "exynos5260-gpio-ctrl1",
+	}, {
+		/* pin-controller instance 2 data */
+		.pin_banks	= exynos5260_pin_banks2,
+		.nr_banks	= ARRAY_SIZE(exynos5260_pin_banks2),
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.label		= "exynos5260-gpio-ctrl2",
+	},
+};
+
 /* pin banks of exynos5420 pin-controller 0 */
 static struct samsung_pin_bank exynos5420_pin_banks0[] = {
 	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 47ec2e8..0324d4c 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1120,6 +1120,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
 		.data = (void *)exynos4x12_pin_ctrl },
 	{ .compatible = "samsung,exynos5250-pinctrl",
 		.data = (void *)exynos5250_pin_ctrl },
+	{ .compatible = "samsung,exynos5260-pinctrl",
+		.data = (void *)exynos5260_pin_ctrl },
 	{ .compatible = "samsung,exynos5420-pinctrl",
 		.data = (void *)exynos5420_pin_ctrl },
 	{ .compatible = "samsung,s5pv210-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 30622d9..bab9c21 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -254,6 +254,7 @@ struct samsung_pmx_func {
 extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
+extern struct samsung_pin_ctrl exynos5260_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];
 extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
 extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
-- 
1.7.9.5

Re: [PATCH V2 03/10] pinctrl: exynos: add exynos5260 SoC specific data

[Arnd Bergmann]

On Tuesday 07 January 2014 18:29:01 Rahul Sharma wrote:
> From: Young-Gun Jang <yg1004.jang@samsung.com>
> 
> Add Samsung Exynos5260 SoC specific data to enable pinctrl
> support for all platforms based on EXYNOS5260.
> 
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Signed-off-by: Young-Gun Jang <yg1004.jang@samsung.com>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>

On a similar note to the comment about the platform patch, I think
it would be good to extend the DT binding in a way that allows
you to describe the differences between the SoCs without having
to change the driver every time a new model comes out.

We still have to maintain backwards compatibility with the
existing bindings I suppose, but I'd rather not see new ones
added like this. I realize that there is a tradeoff between
having too much information in DT when it is always fixed, and
having too much hardcoded in the driver, and at some point there
was a conscious decision to do it like this, but I fear the
tradeoff has changed with the number of EXYNOS implementations
that really only differ in their pin banks.

	Arnd

Re: [PATCH V2 03/10] pinctrl: exynos: add exynos5260 SoC specific data

[Tomasz Figa]

On 07.01.2014 14:31, Arnd Bergmann wrote:
> On Tuesday 07 January 2014 18:29:01 Rahul Sharma wrote:
>> From: Young-Gun Jang <yg1004.jang@samsung.com>
>>
>> Add Samsung Exynos5260 SoC specific data to enable pinctrl
>> support for all platforms based on EXYNOS5260.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Signed-off-by: Young-Gun Jang <yg1004.jang@samsung.com>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
>
> On a similar note to the comment about the platform patch, I think
> it would be good to extend the DT binding in a way that allows
> you to describe the differences between the SoCs without having
> to change the driver every time a new model comes out.
>
> We still have to maintain backwards compatibility with the
> existing bindings I suppose, but I'd rather not see new ones
> added like this. I realize that there is a tradeoff between
> having too much information in DT when it is always fixed, and
> having too much hardcoded in the driver, and at some point there
> was a conscious decision to do it like this, but I fear the
> tradeoff has changed with the number of EXYNOS implementations
> that really only differ in their pin banks.

There isn't really too much data being added to the driver on per-SoC 
basis. Anyway, I remember that when I was trying to move all the data to 
DT long time ago when refactoring the driver, after a long discussion on 
the ML it was decided that it is not really a good idea and so we have 
the end result as we can see now.

Personally I'd prefer all the static data of struct samsung_pin_bank to 
be located in DT, with each bank having a compatible string that would 
translate to appropriate struct samsung_pin_bank_type, which is common 
across multiple SoCs (basically all >= S5PV210), and parameters such as 
pin-count, control-base, and geint-/weint-base (which would also imply 
interrupt type) - name (which is used only for human readable text) 
could be implied by node names. However that would mean quite 
significant effort (and churn), especially considering the fact that we 
need to maintain compatibility with existing bindings, due to "ABI 
stability" (which I'm slowly losing my faith in), so I don't think it's 
worth it.

So, from me:

Acked-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

[PATCH V2 04/10] clk/samsung: add support for multiple clock providers

[Rahul Sharma]

Samsung CCF helper functions do not provide support to
register multiple Clock Providers for a given SoC. Due to
this limitation SoC platforms are not able to use these
helpers for registering multiple clock providers and are
forced to bypass this layer.

This layer is modified accordingly to enable the support.

Clock file for exynos4, exynos5250, exynos5420, exynos5440
and S3c64xx are also modified as per changed helper functions.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c    |   47 +++++++-------
 drivers/clk/samsung/clk-exynos5250.c |   26 +++++---
 drivers/clk/samsung/clk-exynos5410.c |   14 +++--
 drivers/clk/samsung/clk-exynos5420.c |   24 ++++---
 drivers/clk/samsung/clk-exynos5440.c |   18 +++---
 drivers/clk/samsung/clk-pll.c        |   14 +++--
 drivers/clk/samsung/clk-s3c64xx.c    |   44 +++++++------
 drivers/clk/samsung/clk.c            |  115 +++++++++++++++++++---------------
 drivers/clk/samsung/clk.h            |   72 ++++++++++++++-------
 9 files changed, 220 insertions(+), 154 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 50f6e00..5e47abf 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1094,7 +1094,7 @@ static unsigned long exynos4_get_xom(void)
 	return xom;
 }
 
-static void __init exynos4_clk_register_finpll(void)
+static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
 {
 	struct samsung_fixed_rate_clock fclk;
 	struct clk *clk;
@@ -1117,7 +1117,7 @@ static void __init exynos4_clk_register_finpll(void)
 	fclk.parent_name = NULL;
 	fclk.flags = CLK_IS_ROOT;
 	fclk.fixed_rate = finpll_f;
-	samsung_clk_register_fixed_rate(&fclk, 1);
+	samsung_clk_register_fixed_rate(ctx, &fclk, 1);
 
 }
 
@@ -1227,22 +1227,25 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
 static void __init exynos4_clk_init(struct device_node *np,
 				    enum exynos4_soc soc)
 {
+	struct samsung_clk_provider *ctx;
 	exynos4_soc = soc;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base)
 		panic("%s: failed to map registers\n", __func__);
 
-	samsung_clk_init(np, reg_base, nr_clks);
+	ctx = samsung_clk_init(np, reg_base, nr_clks);
+	if (!ctx)
+		panic("%s: unable to allocate context.\n", __func__);
 
-	samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
+	samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
 			ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
 			ext_clk_match);
 
-	exynos4_clk_register_finpll();
+	exynos4_clk_register_finpll(ctx);
 
 	if (exynos4_soc == EXYNOS4210) {
-		samsung_clk_register_mux(exynos4210_mux_early,
+		samsung_clk_register_mux(ctx, exynos4210_mux_early,
 					ARRAY_SIZE(exynos4210_mux_early));
 
 		if (_get_rate("fin_pll") == 24000000) {
@@ -1256,7 +1259,7 @@ static void __init exynos4_clk_init(struct device_node *np,
 			exynos4210_plls[vpll].rate_table =
 							exynos4210_vpll_rates;
 
-		samsung_clk_register_pll(exynos4210_plls,
+		samsung_clk_register_pll(ctx, exynos4210_plls,
 					ARRAY_SIZE(exynos4210_plls), reg_base);
 	} else {
 		if (_get_rate("fin_pll") == 24000000) {
@@ -1268,42 +1271,42 @@ static void __init exynos4_clk_init(struct device_node *np,
 							exynos4x12_vpll_rates;
 		}
 
-		samsung_clk_register_pll(exynos4x12_plls,
+		samsung_clk_register_pll(ctx, exynos4x12_plls,
 					ARRAY_SIZE(exynos4x12_plls), reg_base);
 	}
 
-	samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
+	samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
 			ARRAY_SIZE(exynos4_fixed_rate_clks));
-	samsung_clk_register_mux(exynos4_mux_clks,
+	samsung_clk_register_mux(ctx, exynos4_mux_clks,
 			ARRAY_SIZE(exynos4_mux_clks));
-	samsung_clk_register_div(exynos4_div_clks,
+	samsung_clk_register_div(ctx, exynos4_div_clks,
 			ARRAY_SIZE(exynos4_div_clks));
-	samsung_clk_register_gate(exynos4_gate_clks,
+	samsung_clk_register_gate(ctx, exynos4_gate_clks,
 			ARRAY_SIZE(exynos4_gate_clks));
 
 	if (exynos4_soc == EXYNOS4210) {
-		samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
+		samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
 			ARRAY_SIZE(exynos4210_fixed_rate_clks));
-		samsung_clk_register_mux(exynos4210_mux_clks,
+		samsung_clk_register_mux(ctx, exynos4210_mux_clks,
 			ARRAY_SIZE(exynos4210_mux_clks));
-		samsung_clk_register_div(exynos4210_div_clks,
+		samsung_clk_register_div(ctx, exynos4210_div_clks,
 			ARRAY_SIZE(exynos4210_div_clks));
-		samsung_clk_register_gate(exynos4210_gate_clks,
+		samsung_clk_register_gate(ctx, exynos4210_gate_clks,
 			ARRAY_SIZE(exynos4210_gate_clks));
-		samsung_clk_register_alias(exynos4210_aliases,
+		samsung_clk_register_alias(ctx, exynos4210_aliases,
 			ARRAY_SIZE(exynos4210_aliases));
 	} else {
-		samsung_clk_register_mux(exynos4x12_mux_clks,
+		samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
 			ARRAY_SIZE(exynos4x12_mux_clks));
-		samsung_clk_register_div(exynos4x12_div_clks,
+		samsung_clk_register_div(ctx, exynos4x12_div_clks,
 			ARRAY_SIZE(exynos4x12_div_clks));
-		samsung_clk_register_gate(exynos4x12_gate_clks,
+		samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
 			ARRAY_SIZE(exynos4x12_gate_clks));
-		samsung_clk_register_alias(exynos4x12_aliases,
+		samsung_clk_register_alias(ctx, exynos4x12_aliases,
 			ARRAY_SIZE(exynos4x12_aliases));
 	}
 
-	samsung_clk_register_alias(exynos4_aliases,
+	samsung_clk_register_alias(ctx, exynos4_aliases,
 			ARRAY_SIZE(exynos4_aliases));
 
 	exynos4_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 82f14e1..af4f7fd 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -583,6 +583,8 @@ static struct of_device_id ext_clk_match[] __initdata = {
 /* register exynox5250 clocks */
 static void __init exynos5250_clk_init(struct device_node *np)
 {
+	struct samsung_clk_provider *ctx;
+
 	if (np) {
 		reg_base = of_iomap(np, 0);
 		if (!reg_base)
@@ -591,11 +593,14 @@ static void __init exynos5250_clk_init(struct device_node *np)
 		panic("%s: unable to determine soc\n", __func__);
 	}
 
-	samsung_clk_init(np, reg_base, nr_clks);
-	samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
+	ctx = samsung_clk_init(np, reg_base, nr_clks);
+	if (!ctx)
+		panic("%s: unable to allocate context.\n", __func__);
+
+	samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
 			ext_clk_match);
-	samsung_clk_register_mux(exynos5250_pll_pmux_clks,
+	samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
 				ARRAY_SIZE(exynos5250_pll_pmux_clks));
 
 	if (_get_rate("fin_pll") == 24 * MHZ)
@@ -604,17 +609,18 @@ static void __init exynos5250_clk_init(struct device_node *np)
 	if (_get_rate("mout_vpllsrc") == 24 * MHZ)
 		exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;
 
-	samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),
-					reg_base);
-	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
+	samsung_clk_register_pll(ctx, exynos5250_plls,
+			ARRAY_SIZE(exynos5250_plls),
+			reg_base);
+	samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
-	samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
+	samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
 			ARRAY_SIZE(exynos5250_fixed_factor_clks));
-	samsung_clk_register_mux(exynos5250_mux_clks,
+	samsung_clk_register_mux(ctx, exynos5250_mux_clks,
 			ARRAY_SIZE(exynos5250_mux_clks));
-	samsung_clk_register_div(exynos5250_div_clks,
+	samsung_clk_register_div(ctx, exynos5250_div_clks,
 			ARRAY_SIZE(exynos5250_div_clks));
-	samsung_clk_register_gate(exynos5250_gate_clks,
+	samsung_clk_register_gate(ctx, exynos5250_gate_clks,
 			ARRAY_SIZE(exynos5250_gate_clks));
 
 	exynos5250_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index f94c493..c761e9d 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -255,20 +255,24 @@ static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
 /* register exynos5410 clocks */
 static void __init exynos5410_clk_init(struct device_node *np)
 {
+	struct samsung_clk_provider *ctx;
+
 	reg_base = of_iomap(np, 0);
 	if (!reg_base)
 		panic("%s: failed to map registers\n", __func__);
 
-	samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+	if (!ctx)
+		panic("%s: unable to allocate context.\n", __func__);
 
-	samsung_clk_register_pll(exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
+	samsung_clk_register_pll(ctx, exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
 					reg_base);
 
-	samsung_clk_register_mux(exynos5410_mux_clks,
+	samsung_clk_register_mux(ctx, exynos5410_mux_clks,
 			ARRAY_SIZE(exynos5410_mux_clks));
-	samsung_clk_register_div(exynos5410_div_clks,
+	samsung_clk_register_div(ctx, exynos5410_div_clks,
 			ARRAY_SIZE(exynos5410_div_clks));
-	samsung_clk_register_gate(exynos5410_gate_clks,
+	samsung_clk_register_gate(ctx, exynos5410_gate_clks,
 			ARRAY_SIZE(exynos5410_gate_clks));
 
 	exynos5410_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9de5bfd..e5493cf 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -808,6 +808,8 @@ static struct of_device_id ext_clk_match[] __initdata = {
 /* register exynos5420 clocks */
 static void __init exynos5420_clk_init(struct device_node *np)
 {
+	struct samsung_clk_provider *ctx;
+
 	if (np) {
 		reg_base = of_iomap(np, 0);
 		if (!reg_base)
@@ -816,21 +818,25 @@ static void __init exynos5420_clk_init(struct device_node *np)
 		panic("%s: unable to determine soc\n", __func__);
 	}
 
-	samsung_clk_init(np, reg_base, nr_clks);
-	samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
+	ctx = samsung_clk_init(np, reg_base, nr_clks);
+	if (!ctx)
+		panic("%s: unable to allocate context.\n", __func__);
+
+	samsung_clk_of_register_fixed_ext(ctx, exynos5420_fixed_rate_ext_clks,
 			ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
 			ext_clk_match);
-	samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls),
-					reg_base);
-	samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
+	samsung_clk_register_pll(ctx, exynos5420_plls,
+			ARRAY_SIZE(exynos5420_plls),
+			reg_base);
+	samsung_clk_register_fixed_rate(ctx, exynos5420_fixed_rate_clks,
 			ARRAY_SIZE(exynos5420_fixed_rate_clks));
-	samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
+	samsung_clk_register_fixed_factor(ctx, exynos5420_fixed_factor_clks,
 			ARRAY_SIZE(exynos5420_fixed_factor_clks));
-	samsung_clk_register_mux(exynos5420_mux_clks,
+	samsung_clk_register_mux(ctx, exynos5420_mux_clks,
 			ARRAY_SIZE(exynos5420_mux_clks));
-	samsung_clk_register_div(exynos5420_div_clks,
+	samsung_clk_register_div(ctx, exynos5420_div_clks,
 			ARRAY_SIZE(exynos5420_div_clks));
-	samsung_clk_register_gate(exynos5420_gate_clks,
+	samsung_clk_register_gate(ctx, exynos5420_gate_clks,
 			ARRAY_SIZE(exynos5420_gate_clks));
 
 	exynos5420_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index e3e460a..c2f5d3c 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -106,6 +106,7 @@ static struct of_device_id ext_clk_match[] __initdata = {
 static void __init exynos5440_clk_init(struct device_node *np)
 {
 	void __iomem *reg_base;
+	struct samsung_clk_provider *ctx;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -114,22 +115,25 @@ static void __init exynos5440_clk_init(struct device_node *np)
 		return;
 	}
 
-	samsung_clk_init(np, reg_base, nr_clks);
-	samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
+	ctx = samsung_clk_init(np, reg_base, nr_clks);
+	if (!ctx)
+		panic("%s: unable to allocate context.\n", __func__);
+
+	samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,
 		ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
 
 	samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
 	samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
 
-	samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
+	samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks,
 			ARRAY_SIZE(exynos5440_fixed_rate_clks));
-	samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
+	samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks,
 			ARRAY_SIZE(exynos5440_fixed_factor_clks));
-	samsung_clk_register_mux(exynos5440_mux_clks,
+	samsung_clk_register_mux(ctx, exynos5440_mux_clks,
 			ARRAY_SIZE(exynos5440_mux_clks));
-	samsung_clk_register_div(exynos5440_div_clks,
+	samsung_clk_register_div(ctx, exynos5440_div_clks,
 			ARRAY_SIZE(exynos5440_div_clks));
-	samsung_clk_register_gate(exynos5440_gate_clks,
+	samsung_clk_register_gate(ctx, exynos5440_gate_clks,
 			ARRAY_SIZE(exynos5440_gate_clks));
 
 	pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 529e11d..e8e8953 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -710,8 +710,9 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
 	return clk;
 }
 
-static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
-						void __iomem *base)
+static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+				struct samsung_pll_clock *pll_clk,
+				void __iomem *base)
 {
 	struct samsung_clk_pll *pll;
 	struct clk *clk;
@@ -804,7 +805,7 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
 		return;
 	}
 
-	samsung_clk_add_lookup(clk, pll_clk->id);
+	samsung_clk_add_lookup(ctx, clk, pll_clk->id);
 
 	if (!pll_clk->alias)
 		return;
@@ -815,11 +816,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
 			__func__, pll_clk->name, ret);
 }
 
-void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
-				unsigned int nr_pll, void __iomem *base)
+void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+			struct samsung_pll_clock *pll_list,
+			unsigned int nr_pll, void __iomem *base)
 {
 	int cnt;
 
 	for (cnt = 0; cnt < nr_pll; cnt++)
-		_samsung_clk_register_pll(&pll_list[cnt], base);
+		_samsung_clk_register_pll(ctx, &pll_list[cnt], base);
 }
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
index a43cbde..b7d06ae 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -442,12 +442,14 @@ static struct samsung_clock_alias s3c6410_clock_aliases[] = {
 	ALIAS(MEM0_SROM, NULL, "srom"),
 };
 
-static void __init s3c64xx_clk_register_fixed_ext(unsigned long fin_pll_f,
-							unsigned long xusbxti_f)
+static void __init s3c64xx_clk_register_fixed_ext(
+				struct samsung_clk_provider *ctx,
+				unsigned long fin_pll_f,
+				unsigned long xusbxti_f)
 {
 	s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
 	s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
-	samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_ext_clks,
+	samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks,
 				ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
 }
 
@@ -456,6 +458,8 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
 			     unsigned long xusbxti_f, bool s3c6400,
 			     void __iomem *base)
 {
+	struct samsung_clk_provider *ctx;
+
 	reg_base = base;
 	is_s3c6400 = s3c6400;
 
@@ -465,48 +469,50 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
 			panic("%s: failed to map registers\n", __func__);
 	}
 
-	samsung_clk_init(np, reg_base, NR_CLKS);
+	ctx = samsung_clk_init(np, reg_base, NR_CLKS);
+	if (!ctx)
+		panic("%s: unable to allocate context.\n", __func__);
 
 	/* Register external clocks. */
 	if (!np)
-		s3c64xx_clk_register_fixed_ext(xtal_f, xusbxti_f);
+		s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);
 
 	/* Register PLLs. */
-	samsung_clk_register_pll(s3c64xx_pll_clks,
+	samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
 				ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
 
 	/* Register common internal clocks. */
-	samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_clks,
+	samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
 					ARRAY_SIZE(s3c64xx_fixed_rate_clks));
-	samsung_clk_register_mux(s3c64xx_mux_clks,
+	samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
 					ARRAY_SIZE(s3c64xx_mux_clks));
-	samsung_clk_register_div(s3c64xx_div_clks,
+	samsung_clk_register_div(ctx, s3c64xx_div_clks,
 					ARRAY_SIZE(s3c64xx_div_clks));
-	samsung_clk_register_gate(s3c64xx_gate_clks,
+	samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
 					ARRAY_SIZE(s3c64xx_gate_clks));
 
 	/* Register SoC-specific clocks. */
 	if (is_s3c6400) {
-		samsung_clk_register_mux(s3c6400_mux_clks,
+		samsung_clk_register_mux(ctx, s3c6400_mux_clks,
 					ARRAY_SIZE(s3c6400_mux_clks));
-		samsung_clk_register_div(s3c6400_div_clks,
+		samsung_clk_register_div(ctx, s3c6400_div_clks,
 					ARRAY_SIZE(s3c6400_div_clks));
-		samsung_clk_register_gate(s3c6400_gate_clks,
+		samsung_clk_register_gate(ctx, s3c6400_gate_clks,
 					ARRAY_SIZE(s3c6400_gate_clks));
-		samsung_clk_register_alias(s3c6400_clock_aliases,
+		samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
 					ARRAY_SIZE(s3c6400_clock_aliases));
 	} else {
-		samsung_clk_register_mux(s3c6410_mux_clks,
+		samsung_clk_register_mux(ctx, s3c6410_mux_clks,
 					ARRAY_SIZE(s3c6410_mux_clks));
-		samsung_clk_register_div(s3c6410_div_clks,
+		samsung_clk_register_div(ctx, s3c6410_div_clks,
 					ARRAY_SIZE(s3c6410_div_clks));
-		samsung_clk_register_gate(s3c6410_gate_clks,
+		samsung_clk_register_gate(ctx, s3c6410_gate_clks,
 					ARRAY_SIZE(s3c6410_gate_clks));
-		samsung_clk_register_alias(s3c6410_clock_aliases,
+		samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
 					ARRAY_SIZE(s3c6410_clock_aliases));
 	}
 
-	samsung_clk_register_alias(s3c64xx_clock_aliases,
+	samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
 					ARRAY_SIZE(s3c64xx_clock_aliases));
 	s3c64xx_clk_sleep_init();
 
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 91bec3e..c75eb11 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -14,13 +14,6 @@
 #include <linux/syscore_ops.h>
 #include "clk.h"
 
-static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
-static void __iomem *reg_base;
-#ifdef CONFIG_OF
-static struct clk_onecell_data clk_data;
-#endif
-
 void samsung_clk_save(void __iomem *base,
 				    struct samsung_clk_reg_dump *rd,
 				    unsigned int num_regs)
@@ -55,40 +48,54 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
 }
 
 /* setup the essentials required to support clock lookup using ccf */
-void __init samsung_clk_init(struct device_node *np, void __iomem *base,
-			     unsigned long nr_clks)
+struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
+			void __iomem *base, unsigned long nr_clks)
 {
-	reg_base = base;
+	struct samsung_clk_provider *ctx;
+	struct clk **clk_table;
+	int ret;
+
+	ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
+	if (!ctx)
+		panic("could not allocate clock provider context.\n");
 
 	clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
 	if (!clk_table)
 		panic("could not allocate clock lookup table\n");
 
+	ctx->reg_base = base;
+	ctx->clk_data.clks = clk_table;
+	ctx->clk_data.clk_num = nr_clks;
+	ctx->lock = __SPIN_LOCK_UNLOCKED(lock);
+
 	if (!np)
-		return;
+		return ctx;
 
-#ifdef CONFIG_OF
-	clk_data.clks = clk_table;
-	clk_data.clk_num = nr_clks;
-	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-#endif
+	ret = of_clk_add_provider(np, of_clk_src_onecell_get,
+			&ctx->clk_data);
+	if (ret)
+		panic("could not register clock provide\n");
+
+	return ctx;
 }
 
 /* add a clock instance to the clock lookup table used for dt based lookup */
-void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
+void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
+				unsigned int id)
 {
-	if (clk_table && id)
-		clk_table[id] = clk;
+	if (ctx->clk_data.clks && id)
+		ctx->clk_data.clks[id] = clk;
 }
 
 /* register a list of aliases */
-void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
-					unsigned int nr_clk)
+void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
+				struct samsung_clock_alias *list,
+				unsigned int nr_clk)
 {
 	struct clk *clk;
 	unsigned int idx, ret;
 
-	if (!clk_table) {
+	if (!ctx->clk_data.clks) {
 		pr_err("%s: clock table missing\n", __func__);
 		return;
 	}
@@ -100,7 +107,7 @@ void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
 			continue;
 		}
 
-		clk = clk_table[list->id];
+		clk = ctx->clk_data.clks[list->id];
 		if (!clk) {
 			pr_err("%s: failed to find clock %d\n", __func__,
 				list->id);
@@ -115,7 +122,7 @@ void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
 }
 
 /* register a list of fixed clocks */
-void __init samsung_clk_register_fixed_rate(
+void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
 		struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
 {
 	struct clk *clk;
@@ -130,7 +137,7 @@ void __init samsung_clk_register_fixed_rate(
 			continue;
 		}
 
-		samsung_clk_add_lookup(clk, list->id);
+		samsung_clk_add_lookup(ctx, clk, list->id);
 
 		/*
 		 * Unconditionally add a clock lookup for the fixed rate clocks.
@@ -144,7 +151,7 @@ void __init samsung_clk_register_fixed_rate(
 }
 
 /* register a list of fixed factor clocks */
-void __init samsung_clk_register_fixed_factor(
+void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx,
 		struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
 {
 	struct clk *clk;
@@ -159,28 +166,30 @@ void __init samsung_clk_register_fixed_factor(
 			continue;
 		}
 
-		samsung_clk_add_lookup(clk, list->id);
+		samsung_clk_add_lookup(ctx, clk, list->id);
 	}
 }
 
 /* register a list of mux clocks */
-void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
-					unsigned int nr_clk)
+void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
+				struct samsung_mux_clock *list,
+				unsigned int nr_clk)
 {
 	struct clk *clk;
 	unsigned int idx, ret;
 
 	for (idx = 0; idx < nr_clk; idx++, list++) {
 		clk = clk_register_mux(NULL, list->name, list->parent_names,
-			list->num_parents, list->flags, reg_base + list->offset,
-			list->shift, list->width, list->mux_flags, &lock);
+			list->num_parents, list->flags,
+			ctx->reg_base + list->offset,
+			list->shift, list->width, list->mux_flags, &ctx->lock);
 		if (IS_ERR(clk)) {
 			pr_err("%s: failed to register clock %s\n", __func__,
 				list->name);
 			continue;
 		}
 
-		samsung_clk_add_lookup(clk, list->id);
+		samsung_clk_add_lookup(ctx, clk, list->id);
 
 		/* register a clock lookup only if a clock alias is specified */
 		if (list->alias) {
@@ -194,8 +203,9 @@ void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
 }
 
 /* register a list of div clocks */
-void __init samsung_clk_register_div(struct samsung_div_clock *list,
-					unsigned int nr_clk)
+void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
+				struct samsung_div_clock *list,
+				unsigned int nr_clk)
 {
 	struct clk *clk;
 	unsigned int idx, ret;
@@ -203,22 +213,22 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list,
 	for (idx = 0; idx < nr_clk; idx++, list++) {
 		if (list->table)
 			clk = clk_register_divider_table(NULL, list->name,
-					list->parent_name, list->flags,
-					reg_base + list->offset, list->shift,
-					list->width, list->div_flags,
-					list->table, &lock);
+				list->parent_name, list->flags,
+				ctx->reg_base + list->offset,
+				list->shift, list->width, list->div_flags,
+				list->table, &ctx->lock);
 		else
 			clk = clk_register_divider(NULL, list->name,
-					list->parent_name, list->flags,
-					reg_base + list->offset, list->shift,
-					list->width, list->div_flags, &lock);
+				list->parent_name, list->flags,
+				ctx->reg_base + list->offset, list->shift,
+				list->width, list->div_flags, &ctx->lock);
 		if (IS_ERR(clk)) {
 			pr_err("%s: failed to register clock %s\n", __func__,
 				list->name);
 			continue;
 		}
 
-		samsung_clk_add_lookup(clk, list->id);
+		samsung_clk_add_lookup(ctx, clk, list->id);
 
 		/* register a clock lookup only if a clock alias is specified */
 		if (list->alias) {
@@ -232,16 +242,17 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list,
 }
 
 /* register a list of gate clocks */
-void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
-						unsigned int nr_clk)
+void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
+				struct samsung_gate_clock *list,
+				unsigned int nr_clk)
 {
 	struct clk *clk;
 	unsigned int idx, ret;
 
 	for (idx = 0; idx < nr_clk; idx++, list++) {
 		clk = clk_register_gate(NULL, list->name, list->parent_name,
-				list->flags, reg_base + list->offset,
-				list->bit_idx, list->gate_flags, &lock);
+				list->flags, ctx->reg_base + list->offset,
+				list->bit_idx, list->gate_flags, &ctx->lock);
 		if (IS_ERR(clk)) {
 			pr_err("%s: failed to register clock %s\n", __func__,
 				list->name);
@@ -257,7 +268,7 @@ void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
 					__func__, list->alias);
 		}
 
-		samsung_clk_add_lookup(clk, list->id);
+		samsung_clk_add_lookup(ctx, clk, list->id);
 	}
 }
 
@@ -266,21 +277,21 @@ void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
  * tree and register it
  */
 #ifdef CONFIG_OF
-void __init samsung_clk_of_register_fixed_ext(
+void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
 			struct samsung_fixed_rate_clock *fixed_rate_clk,
 			unsigned int nr_fixed_rate_clk,
 			struct of_device_id *clk_matches)
 {
 	const struct of_device_id *match;
-	struct device_node *np;
+	struct device_node *clk_np;
 	u32 freq;
 
-	for_each_matching_node_and_match(np, clk_matches, &match) {
-		if (of_property_read_u32(np, "clock-frequency", &freq))
+	for_each_matching_node_and_match(clk_np, clk_matches, &match) {
+		if (of_property_read_u32(clk_np, "clock-frequency", &freq))
 			continue;
 		fixed_rate_clk[(u32)match->data].fixed_rate = freq;
 	}
-	samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk);
+	samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
 }
 #endif
 
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index c7141ba..9693b80 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -22,6 +22,18 @@
 #include "clk-pll.h"
 
 /**
+ * struct samsung_clk_provider: information about clock provider
+ * @reg_base: virtual address for the register base.
+ * @clk_data: holds clock related data like clk* and number of clocks.
+ * @lock: maintains exclusion bwtween callbacks for a given clock-provider.
+ */
+struct samsung_clk_provider {
+	void __iomem *reg_base;
+	struct clk_onecell_data clk_data;
+	spinlock_t lock;
+};
+
+/**
  * struct samsung_clock_alias: information about mux clock
  * @id: platform specific id of the clock.
  * @dev_name: name of the device to which this clock belongs.
@@ -312,40 +324,52 @@ struct samsung_pll_clock {
 	__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,	\
 		_lock, _con, _rtable, _alias)
 
-extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
-				    unsigned long nr_clks);
+extern struct samsung_clk_provider *__init samsung_clk_init(
+			struct device_node *np, void __iomem *base,
+			unsigned long nr_clks);
 extern void __init samsung_clk_of_register_fixed_ext(
-		struct samsung_fixed_rate_clock *fixed_rate_clk,
-		unsigned int nr_fixed_rate_clk,
-		struct of_device_id *clk_matches);
+			struct samsung_clk_provider *ctx,
+			struct samsung_fixed_rate_clock *fixed_rate_clk,
+			unsigned int nr_fixed_rate_clk,
+			struct of_device_id *clk_matches);
 
-extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
+extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
+			struct clk *clk, unsigned int id);
 
-extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
-		unsigned int nr_clk);
+extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx,
+			struct samsung_clock_alias *list,
+			unsigned int nr_clk);
 extern void __init samsung_clk_register_fixed_rate(
-		struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
+			struct samsung_clk_provider *ctx,
+			struct samsung_fixed_rate_clock *clk_list,
+			unsigned int nr_clk);
 extern void __init samsung_clk_register_fixed_factor(
-		struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
-extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
-		unsigned int nr_clk);
-extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
-		unsigned int nr_clk);
-extern void __init samsung_clk_register_gate(
-		struct samsung_gate_clock *clk_list, unsigned int nr_clk);
-extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
-		unsigned int nr_clk, void __iomem *base);
+			struct samsung_clk_provider *ctx,
+			struct samsung_fixed_factor_clock *list,
+			unsigned int nr_clk);
+extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
+			struct samsung_mux_clock *clk_list,
+			unsigned int nr_clk);
+extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
+			struct samsung_div_clock *clk_list,
+			unsigned int nr_clk);
+extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
+			struct samsung_gate_clock *clk_list,
+			unsigned int nr_clk);
+extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+			struct samsung_pll_clock *pll_list,
+			unsigned int nr_clk, void __iomem *base);
 
 extern unsigned long _get_rate(const char *clk_name);
 
 extern void samsung_clk_save(void __iomem *base,
-			     struct samsung_clk_reg_dump *rd,
-			     unsigned int num_regs);
+			struct samsung_clk_reg_dump *rd,
+			unsigned int num_regs);
 extern void samsung_clk_restore(void __iomem *base,
-				const struct samsung_clk_reg_dump *rd,
-				unsigned int num_regs);
+			const struct samsung_clk_reg_dump *rd,
+			unsigned int num_regs);
 extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
-						const unsigned long *rdump,
-						unsigned long nr_rdump);
+			const unsigned long *rdump,
+			unsigned long nr_rdump);
 
 #endif /* __SAMSUNG_CLK_H */
-- 
1.7.9.5

Re: [PATCH V2 04/10] clk/samsung: add support for multiple clock providers

[Tomasz Figa]

Hi Rahul,

The patch looks mostly fine now, but I still have one inline comment.

On 07.01.2014 13:59, Rahul Sharma wrote:
> Samsung CCF helper functions do not provide support to
> register multiple Clock Providers for a given SoC. Due to
> this limitation SoC platforms are not able to use these
> helpers for registering multiple clock providers and are
> forced to bypass this layer.
>
> This layer is modified accordingly to enable the support.
>
> Clock file for exynos4, exynos5250, exynos5420, exynos5440
[snip]
>   /* setup the essentials required to support clock lookup using ccf */
> -void __init samsung_clk_init(struct device_node *np, void __iomem *base,
> -			     unsigned long nr_clks)
> +struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
> +			void __iomem *base, unsigned long nr_clks)
>   {
> -	reg_base = base;
> +	struct samsung_clk_provider *ctx;
> +	struct clk **clk_table;
> +	int ret;
> +
> +	ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
> +	if (!ctx)
> +		panic("could not allocate clock provider context.\n");
>
>   	clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
>   	if (!clk_table)
>   		panic("could not allocate clock lookup table\n");
>
> +	ctx->reg_base = base;
> +	ctx->clk_data.clks = clk_table;
> +	ctx->clk_data.clk_num = nr_clks;
> +	ctx->lock = __SPIN_LOCK_UNLOCKED(lock);

spin_lock_init(&ctx->lock);

Best regards,
Tomasz

[PATCH V2 05/10] clk/samsung: add support for pll2550xx

[Rahul Sharma]

From: Pankaj Dubey <pankaj.dubey@samsung.com>

exynos5260 use pll2550xx and it has different bit fields
for P,M,S values as compared to pll2550. Support for
pll2550xx is added here.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
 drivers/clk/samsung/clk-pll.c |  108 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-pll.h |    1 +
 2 files changed, 109 insertions(+)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index e8e8953..08f85ae 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -710,6 +710,108 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
 	return clk;
 }
 
+/*
+ * PLL2550xx Clock Type
+ */
+
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL2550XX_LOCK_FACTOR 270
+
+#define PLL2550XX_M_MASK		0x3FF
+#define PLL2550XX_P_MASK		0x3F
+#define PLL2550XX_S_MASK		0x7
+#define PLL2550XX_LOCK_STAT_MASK	0x1
+#define PLL2550XX_M_SHIFT		9
+#define PLL2550XX_P_SHIFT		3
+#define PLL2550XX_S_SHIFT		0
+#define PLL2550XX_LOCK_STAT_SHIFT	21
+
+static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 mdiv, pdiv, sdiv, pll_con;
+	u64 fvco = parent_rate;
+
+	pll_con = __raw_readl(pll->con_reg);
+	mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
+	pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
+	sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
+
+	fvco *= mdiv;
+	do_div(fvco, (pdiv << sdiv));
+
+	return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+	u32 old_mdiv, old_pdiv;
+
+	old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
+	old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
+
+	return mdiv != old_mdiv || pdiv != old_pdiv;
+}
+
+static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long prate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	const struct samsung_pll_rate_table *rate;
+	u32 tmp;
+
+	/* Get required rate settings from table */
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	tmp = __raw_readl(pll->con_reg);
+
+	if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
+		/* If only s change, change just s value only*/
+		tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
+		tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
+		__raw_writel(tmp, pll->con_reg);
+
+		return 0;
+	}
+
+	/* Set PLL lock time. */
+	__raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
+
+	/* Change PLL PMS values */
+	tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
+			(PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) |
+			(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT));
+	tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
+			(rate->pdiv << PLL2550XX_P_SHIFT) |
+			(rate->sdiv << PLL2550XX_S_SHIFT);
+	__raw_writel(tmp, pll->con_reg);
+
+	/* wait_lock_time */
+	do {
+		cpu_relax();
+		tmp = __raw_readl(pll->con_reg);
+	} while (!(tmp & (PLL2550XX_LOCK_STAT_MASK
+			<< PLL2550XX_LOCK_STAT_SHIFT)));
+
+	return 0;
+}
+
+static const struct clk_ops samsung_pll2550xx_clk_ops = {
+	.recalc_rate = samsung_pll2550xx_recalc_rate,
+	.round_rate = samsung_pll_round_rate,
+	.set_rate = samsung_pll2550xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
+	.recalc_rate = samsung_pll2550xx_recalc_rate,
+};
+
 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 				struct samsung_pll_clock *pll_clk,
 				void __iomem *base)
@@ -787,6 +889,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 		else
 			init.ops = &samsung_pll46xx_clk_ops;
 		break;
+	case pll_2550xx:
+		if (!pll->rate_table)
+			init.ops = &samsung_pll2550xx_clk_min_ops;
+		else
+			init.ops = &samsung_pll2550xx_clk_ops;
+		break;
 	default:
 		pr_warn("%s: Unknown pll type for pll clk %s\n",
 			__func__, pll_clk->name);
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 6c39030..e106470 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -25,6 +25,7 @@ enum samsung_pll_type {
 	pll_4650c,
 	pll_6552,
 	pll_6553,
+	pll_2550xx,
 };
 
 #define PLL_35XX_RATE(_rate, _m, _p, _s)			\
-- 
1.7.9.5

Re: [PATCH V2 05/10] clk/samsung: add support for pll2550xx

[Tomasz Figa]

On 07.01.2014 13:59, Rahul Sharma wrote:
> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>
> exynos5260 use pll2550xx and it has different bit fields
> for P,M,S values as compared to pll2550. Support for
> pll2550xx is added here.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
> ---
>   drivers/clk/samsung/clk-pll.c |  108 +++++++++++++++++++++++++++++++++++++++++
>   drivers/clk/samsung/clk-pll.h |    1 +
>   2 files changed, 109 insertions(+)

Acked-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

[PATCH V2 06/10] clk/samsung: add support for pll2650xx

[Rahul Sharma]

Add support for pll2650xx in samsung pll file. This pll variant
is close to pll36xx but uses CON2 registers instead of CON1.

Aud_pll in Exynos5260 is pll2650xx and uses this code.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 drivers/clk/samsung/clk-pll.c |  101 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-pll.h |    2 +-
 2 files changed, 102 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 08f85ae..35cbc60 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -812,6 +812,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
 	.recalc_rate = samsung_pll2550xx_recalc_rate,
 };
 
+/*
+ * PLL2650XX Clock Type
+ */
+
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL2650XX_LOCK_FACTOR (3000)
+
+#define PLL2650XX_MDIV_SHIFT		(9)
+#define PLL2650XX_PDIV_SHIFT		(3)
+#define PLL2650XX_SDIV_SHIFT		(0)
+#define PLL2650XX_KDIV_SHIFT		(0)
+#define PLL2650XX_MDIV_MASK		(0x1ff)
+#define PLL2650XX_PDIV_MASK		(0x3f)
+#define PLL2650XX_SDIV_MASK		(0x7)
+#define PLL2650XX_KDIV_MASK		(0xffff)
+#define PLL2650XX_PLL_ENABLE_SHIFT	(23)
+#define PLL2650XX_PLL_LOCKTIME_SHIFT	(21)
+#define PLL2650XX_PLL_FOUTMASK_SHIFT	(31)
+
+static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
+	s16 kdiv;
+	u64 fvco = parent_rate;
+
+	pll_con0 = __raw_readl(pll->con_reg);
+	pll_con2 = __raw_readl(pll->con_reg + 8);
+	mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
+	kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
+
+	fvco *= (mdiv << 16) + kdiv;
+	do_div(fvco, (pdiv << sdiv));
+	fvco >>= 16;
+
+	return (unsigned long)fvco;
+}
+
+static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 tmp, pll_con0, pll_con2;
+	const struct samsung_pll_rate_table *rate;
+
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	pll_con0 = __raw_readl(pll->con_reg);
+	pll_con2 = __raw_readl(pll->con_reg + 8);
+
+	 /* Change PLL PMS values */
+	pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
+			PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
+			PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
+	pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
+	pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
+	pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
+	pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
+	pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
+
+	pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
+	pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
+			<< PLL2650XX_KDIV_SHIFT;
+
+	/* Set PLL lock time. */
+	__raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
+
+	__raw_writel(pll_con0, pll->con_reg);
+	__raw_writel(pll_con2, pll->con_reg + 8);
+
+	do {
+		tmp = __raw_readl(pll->con_reg);
+	} while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
+
+	return 0;
+}
+
+static const struct clk_ops samsung_pll2650xx_clk_ops = {
+	.recalc_rate = samsung_pll2650xx_recalc_rate,
+	.set_rate = samsung_pll2650xx_set_rate,
+	.round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
+	.recalc_rate = samsung_pll2650xx_recalc_rate,
+};
+
 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 				struct samsung_pll_clock *pll_clk,
 				void __iomem *base)
@@ -895,6 +990,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 		else
 			init.ops = &samsung_pll2550xx_clk_ops;
 		break;
+	case pll_2650xx:
+		if (!pll->rate_table)
+			init.ops = &samsung_pll2650xx_clk_min_ops;
+		else
+			init.ops = &samsung_pll2650xx_clk_ops;
+		break;
 	default:
 		pr_warn("%s: Unknown pll type for pll clk %s\n",
 			__func__, pll_clk->name);
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index e106470..b326e94 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -26,6 +26,7 @@ enum samsung_pll_type {
 	pll_6552,
 	pll_6553,
 	pll_2550xx,
+	pll_2650xx,
 };
 
 #define PLL_35XX_RATE(_rate, _m, _p, _s)			\
@@ -93,5 +94,4 @@ struct samsung_pll_rate_table {
 extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
 			const char *pname, const void __iomem *reg_base,
 			const unsigned long offset);
-
 #endif /* __SAMSUNG_CLK_PLL_H */
-- 
1.7.9.5

Re: [PATCH V2 06/10] clk/samsung: add support for pll2650xx

[Tomasz Figa]

Hi Rahul,

On 07.01.2014 13:59, Rahul Sharma wrote:
> Add support for pll2650xx in samsung pll file. This pll variant
> is close to pll36xx but uses CON2 registers instead of CON1.
>
> Aud_pll in Exynos5260 is pll2650xx and uses this code.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
>   drivers/clk/samsung/clk-pll.c |  101 +++++++++++++++++++++++++++++++++++++++++
>   drivers/clk/samsung/clk-pll.h |    2 +-
>   2 files changed, 102 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 08f85ae..35cbc60 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -812,6 +812,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
>   	.recalc_rate = samsung_pll2550xx_recalc_rate,
>   };
>
> +/*
> + * PLL2650XX Clock Type
> + */
> +
> +/* Maximum lock time can be 3000 * PDIV cycles */
> +#define PLL2650XX_LOCK_FACTOR (3000)
> +
> +#define PLL2650XX_MDIV_SHIFT		(9)
> +#define PLL2650XX_PDIV_SHIFT		(3)
> +#define PLL2650XX_SDIV_SHIFT		(0)
> +#define PLL2650XX_KDIV_SHIFT		(0)
> +#define PLL2650XX_MDIV_MASK		(0x1ff)
> +#define PLL2650XX_PDIV_MASK		(0x3f)
> +#define PLL2650XX_SDIV_MASK		(0x7)
> +#define PLL2650XX_KDIV_MASK		(0xffff)
> +#define PLL2650XX_PLL_ENABLE_SHIFT	(23)
> +#define PLL2650XX_PLL_LOCKTIME_SHIFT	(21)
> +#define PLL2650XX_PLL_FOUTMASK_SHIFT	(31)

For single bit fields it would be better to use simple definitions, 
using BIT() macro, such as

#define PLL2650XX_PLL_ENABLE		BIT(23)

and then using it with | or & ~ operators directly.

Also there is no need for parentheses around simple integers.

> +
> +static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
> +				unsigned long parent_rate)
> +{
> +	struct samsung_clk_pll *pll = to_clk_pll(hw);
> +	u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
> +	s16 kdiv;
> +	u64 fvco = parent_rate;
> +
> +	pll_con0 = __raw_readl(pll->con_reg);
> +	pll_con2 = __raw_readl(pll->con_reg + 8);
> +	mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
> +	pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
> +	sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
> +	kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
> +
> +	fvco *= (mdiv << 16) + kdiv;
> +	do_div(fvco, (pdiv << sdiv));
> +	fvco >>= 16;
> +
> +	return (unsigned long)fvco;
> +}
> +
> +static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
> +					unsigned long parent_rate)
> +{
> +	struct samsung_clk_pll *pll = to_clk_pll(hw);
> +	u32 tmp, pll_con0, pll_con2;
> +	const struct samsung_pll_rate_table *rate;
> +
> +	rate = samsung_get_pll_settings(pll, drate);
> +	if (!rate) {
> +		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
> +			drate, __clk_get_name(hw->clk));
> +		return -EINVAL;
> +	}
> +
> +	pll_con0 = __raw_readl(pll->con_reg);
> +	pll_con2 = __raw_readl(pll->con_reg + 8);
> +
> +	 /* Change PLL PMS values */
> +	pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
> +			PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
> +			PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
> +	pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
> +	pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
> +	pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
> +	pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
> +	pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
> +
> +	pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
> +	pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
> +			<< PLL2650XX_KDIV_SHIFT;

Huh? This looks suspiciously. Why KDIV needs to be negated and increased 
by 1?

> +
> +	/* Set PLL lock time. */
> +	__raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
> +
> +	__raw_writel(pll_con0, pll->con_reg);
> +	__raw_writel(pll_con2, pll->con_reg + 8);
> +
> +	do {
> +		tmp = __raw_readl(pll->con_reg);
> +	} while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));

Is the right bit being checked here? On other PLLs it's 29th bit named 
LOCK_STAT. Could you confirm this?

> +
> +	return 0;
> +}
> +
> +static const struct clk_ops samsung_pll2650xx_clk_ops = {
> +	.recalc_rate = samsung_pll2650xx_recalc_rate,
> +	.set_rate = samsung_pll2650xx_set_rate,
> +	.round_rate = samsung_pll_round_rate,
> +};
> +
> +static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
> +	.recalc_rate = samsung_pll2650xx_recalc_rate,
> +};
> +
>   static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>   				struct samsung_pll_clock *pll_clk,
>   				void __iomem *base)
> @@ -895,6 +990,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>   		else
>   			init.ops = &samsung_pll2550xx_clk_ops;
>   		break;
> +	case pll_2650xx:
> +		if (!pll->rate_table)
> +			init.ops = &samsung_pll2650xx_clk_min_ops;
> +		else
> +			init.ops = &samsung_pll2650xx_clk_ops;
> +		break;
>   	default:
>   		pr_warn("%s: Unknown pll type for pll clk %s\n",
>   			__func__, pll_clk->name);
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index e106470..b326e94 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -26,6 +26,7 @@ enum samsung_pll_type {
>   	pll_6552,
>   	pll_6553,
>   	pll_2550xx,
> +	pll_2650xx,
>   };
>
>   #define PLL_35XX_RATE(_rate, _m, _p, _s)			\
> @@ -93,5 +94,4 @@ struct samsung_pll_rate_table {
>   extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
>   			const char *pname, const void __iomem *reg_base,
>   			const unsigned long offset);
> -

Not a part of this change.

Best regards,
Tomasz

[PATCH V2 07/10] clk/exynos5260: add macros and documentation for exynos5260

[Rahul Sharma]

Add macros which are used as Clock IDs in DT and clock file.
It also adds the documentation for the exynos5260 clocks.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 .../devicetree/bindings/clock/exynos5260-clock.txt |  299 ++++++++++++++++++++
 include/dt-bindings/clk/exynos5260-clk.h           |  234 +++++++++++++++
 2 files changed, 533 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
 create mode 100644 include/dt-bindings/clk/exynos5260-clk.h

diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
new file mode 100644
index 0000000..ec180c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
@@ -0,0 +1,299 @@
+* Samsung Exynos5260 Clock Controller
+
+The Exynos5260 clock controller encalsulate all CMUs which are
+instantiaited independently from the device-tree. As a whole,
+these CMUs generates and supplies clocks to various controllers
+within the Exynos5260 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - First compatible should be one of the following
+		"exynos5260-cmu-top"
+		"exynos5260-cmu-peri"
+		"exynos5260-cmu-egl"
+		"exynos5260-cmu-kfc"
+		"exynos5260-cmu-g2d"
+		"exynos5260-cmu-mif"
+		"exynos5260-cmu-mfc"
+		"exynos5260-cmu-g3d"
+		"exynos5260-cmu-fsys"
+		"exynos5260-cmu-aud"
+		"exynos5260-cmu-isp"
+		"exynos5260-cmu-gscl"
+		"exynos5260-cmu-disp"
+  - Second compatible should be "samsung,exynos5260-clock".
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the each controller. Each
+clock is assigned a MACRO constant. These constants are defined in
+"dt-bindings/clk/exynos5260-clk.h". DT client nodes use this MACRO to specify
+the clock which they consume.
+
+-----------------------
+  CMU_TOP clocks
+-----------------------
+
+  FIN_PLL
+  TOP_FOUT_DISP_PLL
+  TOP_FOUT_AUD_PLL
+  TOP_SCLK_MMC0
+  TOP_SCLK_MMC1
+  TOP_SCLK_MMC2
+  TOP_SCLK_HDMIPHY
+  TOP_SCLK_FIMD1
+  TOP_MOUT_FIMD1
+  TOP_MOUT_DISP_PLL
+
+-----------------------
+  CMU_EGL clocks
+-----------------------
+
+  EGL_FOUT_EGL_PLL
+  EGL_FOUT_EGL_DPLL
+
+-----------------------
+  CMU_KFC clocks
+-----------------------
+
+  KFC_FOUT_KFC_PLL
+
+-----------------------
+  CMU_MIF clocks
+-----------------------
+
+  MIF_FOUT_MEM_PLL
+  MIF_FOUT_BUS_PLL
+  MIF_FOUT_MEDIA_PLL
+
+-----------------------
+  CMU_G3D clocks
+-----------------------
+
+  G3D_FOUT_G3D_PLL
+  G3D_CLK_G3D_HPM
+  G3D_CLK_G3D
+
+-----------------------
+  CMU_AUD clocks
+-----------------------
+
+  AUD_CLK_AUD_UART
+  AUD_CLK_PCM
+  AUD_CLK_I2S
+  AUD_CLK_DMAC
+  AUD_SCLK_AUD_UART
+  AUD_SCLK_PCM
+  AUD_SCLK_I2S
+  AUD_NR_CLK
+
+-----------------------
+  CMU_MFC clocks
+-----------------------
+
+  MFC_CLK_MFC
+  MFC_CLK_SMMU2_MFCM1
+  MFC_CLK_SMMU2_MFCM0
+
+-----------------------
+  CMU_GSCL clocks
+-----------------------
+
+  GSCL_CLK_PIXEL_GSCL1
+  GSCL_CLK_PIXEL_GSCL0
+  GSCL_CLK_MSCL1
+  GSCL_CLK_MSCL0
+  GSCL_CLK_GSCL1
+  GSCL_CLK_GSCL0
+  GSCL_CLK_FIMC_LITE_D
+  GSCL_CLK_FIMC_LITE_B
+  GSCL_CLK_FIMC_LITE_A
+  GSCL_CLK_CSIS1
+  GSCL_CLK_CSIS0
+  GSCL_CLK_SMMU3_LITE_D
+  GSCL_CLK_SMMU3_LITE_B
+  GSCL_CLK_SMMU3_LITE_A
+  GSCL_CLK_SMMU3_GSCL0
+  GSCL_CLK_SMMU3_GSCL1
+  GSCL_CLK_SMMU3_MSCL0
+  GSCL_CLK_SMMU3_MSCL1
+  GSCL_SCLK_CSIS1_WRAP
+  GSCL_SCLK_CSIS0_WRAP
+
+-----------------------
+  CMU_FSYS clocks
+-----------------------
+
+  FSYS_CLK_TSI
+  FSYS_CLK_USBLINK
+  FSYS_CLK_USBHOST20
+  FSYS_CLK_USBDRD30
+  FSYS_CLK_SROMC
+  FSYS_CLK_PDMA
+  FSYS_CLK_MMC2
+  FSYS_CLK_MMC1
+  FSYS_CLK_MMC0
+  FSYS_CLK_RTIC
+  FSYS_CLK_SMMU_RTIC
+  FSYS_PHYCLK_USBDRD30
+  FSYS_PHYCLK_USBHOST20
+  FSYS_NR_CLK
+
+-----------------------
+  CMU_PERI clocks
+-----------------------
+
+  PERI_CLK_WDT_KFC
+  PERI_CLK_WDT_EGL
+  PERI_CLK_HSIC3
+  PERI_CLK_HSIC2
+  PERI_CLK_HSIC1
+  PERI_CLK_HSIC0
+  PERI_CLK_PCM
+  PERI_CLK_MCT
+  PERI_CLK_I2S
+  PERI_CLK_I2CHDMI
+  PERI_CLK_I2C7
+  PERI_CLK_I2C6
+  PERI_CLK_I2C5
+  PERI_CLK_I2C4
+  PERI_CLK_I2C9
+  PERI_CLK_I2C8
+  PERI_CLK_I2C11
+  PERI_CLK_I2C10
+  PERI_CLK_HDMICEC
+  PERI_CLK_EFUSE_WRITER
+  PERI_CLK_ABB
+  PERI_CLK_UART2
+  PERI_CLK_UART1
+  PERI_CLK_UART0
+  PERI_CLK_ADC
+  PERI_CLK_TMU4
+  PERI_CLK_TMU3
+  PERI_CLK_TMU2
+  PERI_CLK_TMU1
+  PERI_CLK_TMU0
+  PERI_CLK_SPI2
+  PERI_CLK_SPI1
+  PERI_CLK_SPI0
+  PERI_CLK_SPDIF
+  PERI_CLK_PWM
+  PERI_CLK_UART4
+  PERI_CLK_CHIPID
+  PERI_CLK_PROVKEY0
+  PERI_CLK_PROVKEY1
+  PERI_CLK_SECKEY
+  PERI_CLK_TOP_RTC
+  PERI_CLK_TZPC10
+  PERI_CLK_TZPC9
+  PERI_CLK_TZPC8
+  PERI_CLK_TZPC7
+  PERI_CLK_TZPC6
+  PERI_CLK_TZPC5
+  PERI_CLK_TZPC4
+  PERI_CLK_TZPC3
+  PERI_CLK_TZPC2
+  PERI_CLK_TZPC1
+  PERI_CLK_TZPC0
+  PERI_SCLK_SPI2
+  PERI_SCLK_SPI1
+  PERI_SCLK_SPI0
+  PERI_SCLK_SPDIF
+  PERI_SCLK_I2S
+  PERI_SCLK_PCM1
+  PERI_SCLK_UART2
+  PERI_SCLK_UART1
+  PERI_SCLK_UART0
+
+-----------------------
+  CMU_DISP clocks
+-----------------------
+
+  DISP_CLK_SMMU_TV
+  DISP_CLK_SMMU_FIMD1M1
+  DISP_CLK_SMMU_FIMD1M0
+  DISP_CLK_MIXER
+  DISP_CLK_MIPIPHY
+  DISP_CLK_HDMIPHY
+  DISP_CLK_HDMI
+  DISP_CLK_FIMD1
+  DISP_CLK_DSIM1
+  DISP_CLK_DPPHY
+  DISP_CLK_DP
+  DISP_SCLK_PIXEL
+  DISP_SCLK_HDMI
+  DISP_MOUT_HDMI_PHY_PIXEL
+  DISP_NR_CLK
+
+-----------------------
+  CMU_G2D clocks
+-----------------------
+
+  G2D_CLK_SMMU3_JPEG
+  G2D_CLK_MDMA
+  G2D_CLK_JPEG
+  G2D_CLK_G2D
+  G2D_CLK_SSS
+  G2D_CLK_SLIM_SSS
+  G2D_CLK_SMMU_SLIM_SSS
+  G2D_CLK_SMMU_SSS
+  G2D_CLK_SMMU_MDMA
+  G2D_CLK_SMMU3_G2D
+
+-----------------------
+  CMU_ISP clocks
+-----------------------
+
+  ISP_CLK_GIC
+  ISP_CLK_WDT
+  ISP_CLK_UART
+  ISP_CLK_SPI1
+  ISP_CLK_SPI0
+  ISP_CLK_SMMU_SCALERP
+  ISP_CLK_SMMU_SCALERC
+  ISP_CLK_SMMU_ISPCX
+  ISP_CLK_SMMU_ISP
+  ISP_CLK_SMMU_FD
+  ISP_CLK_SMMU_DRC
+  ISP_CLK_PWM
+  ISP_CLK_MTCADC
+  ISP_CLK_MPWM
+  ISP_CLK_MCUCTL
+  ISP_CLK_I2C1
+  ISP_CLK_I2C0
+  ISP_CLK_FIMC_SCALERP
+  ISP_CLK_FIMC_SCALERC
+  ISP_CLK_FIMC
+  ISP_CLK_FIMC_FD
+  ISP_CLK_FIMC_DRC
+  ISP_CLK_CA5
+  ISP_SCLK_SPI0_EXT
+  ISP_SCLK_SPI1_EXT
+  ISP_SCLK_UART_EXT
+
+
+Example 1: An example of a clock controller node is listed below.
+
+	cmu_disp: clock-controller@0x14550000 {
+		compatible = "exynos5260-cmu-disp", "samsung,exynos5260-clock";
+		reg = <0x14550000 0x10000>;
+		#clock-cells = <1>;
+	};
+
+Example 2: UART controller node that consumes the clock generated by the
+		peri clock controller. Refer to the standard clock bindings for
+		information about 'clocks' and 'clock-names' property.
+
+	serial@12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 146 0>;
+		clocks = <&cmu_peri PERI_PCLK_UART0>, <&cmu_peri PERI_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
+
diff --git a/include/dt-bindings/clk/exynos5260-clk.h b/include/dt-bindings/clk/exynos5260-clk.h
new file mode 100644
index 0000000..d2fb7fa
--- /dev/null
+++ b/include/dt-bindings/clk/exynos5260-clk.h
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+#define	ID_NONE		0
+
+/*
+ * Clock names: XXXXXX_YYYYY_ZZZZZ
+ *                    |------| |----| |----|
+ *                       cmu       type      IP
+*/
+
+/* list of clocks for CMU_TOP */
+#define	FIN_PLL			1
+#define	TOP_FOUT_DISP_PLL	2
+#define	TOP_FOUT_AUD_PLL	3
+#define	TOP_SCLK_MMC0		4
+#define	TOP_SCLK_MMC1		5
+#define	TOP_SCLK_MMC2		6
+#define	TOP_SCLK_HDMIPHY	7
+#define	TOP_SCLK_FIMD1		8
+#define	TOP_MOUT_FIMD1		9
+#define	TOP_MOUT_DISP_PLL	10
+#define	TOP_NR_CLK		11
+
+/* list of clocks for CMU_EGL */
+#define	EGL_FOUT_EGL_PLL	1
+#define	EGL_FOUT_EGL_DPLL	2
+#define	EGL_NR_CLK		3
+
+/* list of clocks for CMU_KFC */
+#define	KFC_FOUT_KFC_PLL	1
+#define	KFC_NR_CLK		2
+
+/* list of clocks for CMU_MIF */
+#define	MIF_FOUT_MEM_PLL	1
+#define	MIF_FOUT_BUS_PLL	2
+#define	MIF_FOUT_MEDIA_PLL	3
+#define	MIF_NR_CLK		4
+
+/* list of clocks for CMU_G3D */
+#define	G3D_FOUT_G3D_PLL	1
+#define	G3D_CLK_G3D_HPM		2
+#define	G3D_CLK_G3D		3
+#define	G3D_NR_CLK		4
+
+/* list of clocks for CMU_AUD */
+#define	AUD_CLK_AUD_UART	1
+#define	AUD_CLK_PCM		2
+#define	AUD_CLK_I2S		3
+#define	AUD_CLK_DMAC		4
+#define	AUD_SCLK_AUD_UART	5
+#define	AUD_SCLK_PCM		6
+#define	AUD_SCLK_I2S		7
+#define	AUD_NR_CLK		8
+
+/* list of clocks for CMU_MFC */
+#define	MFC_CLK_MFC		1
+#define	MFC_CLK_SMMU2_MFCM1	2
+#define	MFC_CLK_SMMU2_MFCM0	3
+#define	MFC_NR_CLK		4
+
+/* list of clocks for CMU_GSCL */
+#define	GSCL_CLK_PIXEL_GSCL1	1
+#define	GSCL_CLK_PIXEL_GSCL0	2
+#define	GSCL_CLK_MSCL1		3
+#define	GSCL_CLK_MSCL0		4
+#define	GSCL_CLK_GSCL1		5
+#define	GSCL_CLK_GSCL0		6
+#define	GSCL_CLK_FIMC_LITE_D	7
+#define	GSCL_CLK_FIMC_LITE_B	8
+#define	GSCL_CLK_FIMC_LITE_A	9
+#define	GSCL_CLK_CSIS1		10
+#define	GSCL_CLK_CSIS0		11
+#define	GSCL_CLK_SMMU3_LITE_D	12
+#define	GSCL_CLK_SMMU3_LITE_B	13
+#define	GSCL_CLK_SMMU3_LITE_A	14
+#define	GSCL_CLK_SMMU3_GSCL0	15
+#define	GSCL_CLK_SMMU3_GSCL1	16
+#define	GSCL_CLK_SMMU3_MSCL0	17
+#define	GSCL_CLK_SMMU3_MSCL1	18
+#define	GSCL_SCLK_CSIS1_WRAP	19
+#define	GSCL_SCLK_CSIS0_WRAP	20
+#define	GSCL_NR_CLK		21
+
+/* list of clocks for CMU_FSYS */
+#define	FSYS_CLK_TSI		1
+#define	FSYS_CLK_USBLINK	2
+#define	FSYS_CLK_USBHOST20	3
+#define	FSYS_CLK_USBDRD30	4
+#define	FSYS_CLK_SROMC		5
+#define	FSYS_CLK_PDMA		6
+#define	FSYS_CLK_MMC2		7
+#define	FSYS_CLK_MMC1		8
+#define	FSYS_CLK_MMC0		9
+#define	FSYS_CLK_RTIC		10
+#define	FSYS_CLK_SMMU_RTIC	11
+#define	FSYS_PHYCLK_USBDRD30	12
+#define	FSYS_PHYCLK_USBHOST20	13
+#define	FSYS_NR_CLK		14
+
+/* list of clocks for CMU_PERI */
+#define	PERI_CLK_WDT_KFC	1
+#define	PERI_CLK_WDT_EGL	2
+#define	PERI_CLK_HSIC3		3
+#define	PERI_CLK_HSIC2		4
+#define	PERI_CLK_HSIC1		5
+#define	PERI_CLK_HSIC0		6
+#define	PERI_CLK_PCM		7
+#define	PERI_CLK_MCT		8
+#define	PERI_CLK_I2S		9
+#define	PERI_CLK_I2CHDMI	10
+#define	PERI_CLK_I2C7		11
+#define	PERI_CLK_I2C6		12
+#define	PERI_CLK_I2C5		13
+#define	PERI_CLK_I2C4		14
+#define	PERI_CLK_I2C9		15
+#define	PERI_CLK_I2C8		16
+#define	PERI_CLK_I2C11		17
+#define	PERI_CLK_I2C10		18
+#define	PERI_CLK_HDMICEC	19
+#define	PERI_CLK_EFUSE_WRITER	20
+#define	PERI_CLK_ABB		21
+#define	PERI_CLK_UART2		22
+#define	PERI_CLK_UART1		23
+#define	PERI_CLK_UART0		24
+#define	PERI_CLK_ADC		25
+#define	PERI_CLK_TMU4		26
+#define	PERI_CLK_TMU3		27
+#define	PERI_CLK_TMU2		28
+#define	PERI_CLK_TMU1		29
+#define	PERI_CLK_TMU0		30
+#define	PERI_CLK_SPI2		31
+#define	PERI_CLK_SPI1		32
+#define	PERI_CLK_SPI0		33
+#define	PERI_CLK_SPDIF		34
+#define	PERI_CLK_PWM		35
+#define	PERI_CLK_UART4		36
+#define	PERI_CLK_CHIPID		37
+#define	PERI_CLK_PROVKEY0	38
+#define	PERI_CLK_PROVKEY1	39
+#define	PERI_CLK_SECKEY		40
+#define	PERI_CLK_TOP_RTC	41
+#define	PERI_CLK_TZPC10		42
+#define	PERI_CLK_TZPC9		43
+#define	PERI_CLK_TZPC8		44
+#define	PERI_CLK_TZPC7		45
+#define	PERI_CLK_TZPC6		46
+#define	PERI_CLK_TZPC5		47
+#define	PERI_CLK_TZPC4		48
+#define	PERI_CLK_TZPC3		49
+#define	PERI_CLK_TZPC2		50
+#define	PERI_CLK_TZPC1		51
+#define	PERI_CLK_TZPC0		52
+#define	PERI_SCLK_SPI2		53
+#define	PERI_SCLK_SPI1		54
+#define	PERI_SCLK_SPI0		55
+#define	PERI_SCLK_SPDIF		56
+#define	PERI_SCLK_I2S		57
+#define	PERI_SCLK_PCM1		58
+#define	PERI_SCLK_UART2		59
+#define	PERI_SCLK_UART1		60
+#define	PERI_SCLK_UART0		61
+#define	PERI_NR_CLK		62
+
+/* list of clocks for CMU_DISP */
+#define	DISP_CLK_SMMU_TV	1
+#define	DISP_CLK_SMMU_FIMD1M1	2
+#define	DISP_CLK_SMMU_FIMD1M0	3
+#define	DISP_CLK_MIXER		4
+#define	DISP_CLK_MIPIPHY	5
+#define	DISP_CLK_HDMIPHY	6
+#define	DISP_CLK_HDMI		7
+#define	DISP_CLK_FIMD1		8
+#define	DISP_CLK_DSIM1		9
+#define	DISP_CLK_DPPHY		10
+#define	DISP_CLK_DP		11
+#define	DISP_SCLK_PIXEL		12
+#define	DISP_SCLK_HDMI		13
+#define	DISP_MOUT_HDMI_PHY_PIXEL	14
+#define	DISP_NR_CLK		15
+
+/* list of clocks for CMU_G2D */
+#define	G2D_CLK_SMMU3_JPEG	1
+#define	G2D_CLK_MDMA		2
+#define	G2D_CLK_JPEG		3
+#define	G2D_CLK_G2D		4
+#define	G2D_CLK_SSS		5
+#define	G2D_CLK_SLIM_SSS	6
+#define	G2D_CLK_SMMU_SLIM_SSS	7
+#define	G2D_CLK_SMMU_SSS	8
+#define	G2D_CLK_SMMU_MDMA	9
+#define	G2D_CLK_SMMU3_G2D	10
+#define	G2D_NR_CLK		11
+
+/* list of clocks for CMU_ISP */
+#define	ISP_CLK_GIC		1
+#define	ISP_CLK_WDT		2
+#define	ISP_CLK_UART		3
+#define	ISP_CLK_SPI1		4
+#define	ISP_CLK_SPI0		5
+#define	ISP_CLK_SMMU_SCALERP	6
+#define	ISP_CLK_SMMU_SCALERC	7
+#define	ISP_CLK_SMMU_ISPCX	8
+#define	ISP_CLK_SMMU_ISP	9
+#define	ISP_CLK_SMMU_FD		10
+#define	ISP_CLK_SMMU_DRC	11
+#define	ISP_CLK_PWM		12
+#define	ISP_CLK_MTCADC		13
+#define	ISP_CLK_MPWM		14
+#define	ISP_CLK_MCUCTL		15
+#define	ISP_CLK_I2C1		16
+#define	ISP_CLK_I2C0		17
+#define	ISP_CLK_FIMC_SCALERP	18
+#define	ISP_CLK_FIMC_SCALERC	19
+#define	ISP_CLK_FIMC		20
+#define	ISP_CLK_FIMC_FD		21
+#define	ISP_CLK_FIMC_DRC	22
+#define	ISP_CLK_CA5		23
+#define	ISP_SCLK_SPI0_EXT	24
+#define	ISP_SCLK_SPI1_EXT	25
+#define	ISP_SCLK_UART_EXT	26
+#define	ISP_NR_CLK		27
+
+#endif
-- 
1.7.9.5

[PATCH V2 08/10] clk/exynos5260: add clock file for exynos5260

[Rahul Sharma]

Add support for exynos5260 clocks in clock driver.

Signed-off-by: Rahul Sharma <rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 drivers/clk/samsung/Makefile         |    1 +
 drivers/clk/samsung/clk-exynos5260.c | 2062 ++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-exynos5260.h |  496 ++++++++
 3 files changed, 2559 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-exynos5260.c
 create mode 100644 drivers/clk/samsung/clk-exynos5260.h

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b572dd7..557d940 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5260)	+= clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5410)	+= clk-exynos5410.o
 obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
new file mode 100644
index 0000000..c0c458b
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -0,0 +1,2062 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5260 SoC.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include "clk-exynos5260.h"
+#include "clk.h"
+#include "clk-pll.h"
+
+#include <dt-bindings/clk/exynos5260-clk.h>
+
+static LIST_HEAD(clock_reg_cache_list);
+static bool syscore_ops_registered;
+
+struct exynos5260_clock_reg_cache {
+	struct list_head node;
+	void __iomem *reg_base;
+	struct samsung_clk_reg_dump *rdump;
+	unsigned int rd_num;
+};
+
+#ifdef CONFIG_PM_SLEEP
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+*/
+
+static unsigned long exynos5260_aud_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_AUD
+*/
+	MUX_SEL_AUD,
+	DIV_AUD0,
+	DIV_AUD1,
+	EN_ACLK_AUD,
+	EN_PCLK_AUD,
+	EN_SCLK_AUD,
+	EN_IP_AUD,
+};
+
+static unsigned long exynos5260_disp_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_DISP
+*/
+	MUX_SEL_DISP0,
+	MUX_SEL_DISP1,
+	MUX_SEL_DISP2,
+	MUX_SEL_DISP3,
+	MUX_SEL_DISP4,
+	DIV_DISP,
+	EN_ACLK_DISP,
+	EN_PCLK_DISP,
+	EN_SCLK_DISP0,
+	EN_SCLK_DISP1,
+	EN_IP_DISP,
+	EN_IP_DISP_BUS,
+};
+
+static unsigned long exynos5260_egl_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_EGL
+*/
+	EGL_PLL_LOCK,
+	EGL_PLL_CON0,
+	EGL_PLL_CON1,
+	EGL_PLL_FREQ_DET,
+	MUX_SEL_EGL,
+	MUX_ENABLE_EGL,
+	DIV_EGL,
+	DIV_EGL_PLL_FDET,
+	EN_ACLK_EGL,
+	EN_PCLK_EGL,
+	EN_SCLK_EGL,
+};
+
+static unsigned long exynos5260_fsys_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_FSYS
+*/
+	MUX_SEL_FSYS0,
+	MUX_SEL_FSYS1,
+	EN_ACLK_FSYS,
+	EN_ACLK_FSYS_SECURE_RTIC,
+	EN_ACLK_FSYS_SECURE_SMMU_RTIC,
+	EN_SCLK_FSYS,
+	EN_IP_FSYS,
+	EN_IP_FSYS_SECURE_RTIC,
+	EN_IP_FSYS_SECURE_SMMU_RTIC,
+};
+
+static unsigned long exynos5260_g2d_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_G2D
+*/
+	MUX_SEL_G2D,
+	MUX_STAT_G2D,
+	DIV_G2D,
+	EN_ACLK_G2D,
+	EN_ACLK_G2D_SECURE_SSS,
+	EN_ACLK_G2D_SECURE_SLIM_SSS,
+	EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS,
+	EN_ACLK_G2D_SECURE_SMMU_SSS,
+	EN_ACLK_G2D_SECURE_SMMU_MDMA,
+	EN_ACLK_G2D_SECURE_SMMU_G2D,
+	EN_PCLK_G2D,
+	EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS,
+	EN_PCLK_G2D_SECURE_SMMU_SSS,
+	EN_PCLK_G2D_SECURE_SMMU_MDMA,
+	EN_PCLK_G2D_SECURE_SMMU_G2D,
+	EN_IP_G2D,
+	EN_IP_G2D_SECURE_SSS,
+	EN_IP_G2D_SECURE_SLIM_SSS,
+	EN_IP_G2D_SECURE_SMMU_SLIM_SSS,
+	EN_IP_G2D_SECURE_SMMU_SSS,
+	EN_IP_G2D_SECURE_SMMU_MDMA,
+	EN_IP_G2D_SECURE_SMMU_G2D,
+};
+
+static unsigned long exynos5260_g3d_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_G3D
+*/
+	G3D_PLL_LOCK,
+	G3D_PLL_CON0,
+	G3D_PLL_CON1,
+	G3D_PLL_FDET,
+	MUX_SEL_G3D,
+	DIV_G3D,
+	DIV_G3D_PLL_FDET,
+	EN_ACLK_G3D,
+	EN_PCLK_G3D,
+	EN_SCLK_G3D,
+	EN_IP_G3D,
+};
+
+static unsigned long exynos5260_gscl_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_GSCL
+*/
+	MUX_SEL_GSCL,
+	DIV_GSCL,
+	EN_ACLK_GSCL,
+	EN_ACLK_GSCL_FIMC,
+	EN_ACLK_GSCL_SECURE_SMMU_GSCL0,
+	EN_ACLK_GSCL_SECURE_SMMU_GSCL1,
+	EN_ACLK_GSCL_SECURE_SMMU_MSCL0,
+	EN_ACLK_GSCL_SECURE_SMMU_MSCL1,
+	EN_PCLK_GSCL,
+	EN_PCLK_GSCL_FIMC,
+	EN_PCLK_GSCL_SECURE_SMMU_GSCL0,
+	EN_PCLK_GSCL_SECURE_SMMU_GSCL1,
+	EN_PCLK_GSCL_SECURE_SMMU_MSCL0,
+	EN_PCLK_GSCL_SECURE_SMMU_MSCL1,
+	EN_SCLK_GSCL,
+	EN_SCLK_GSCL_FIMC,
+	EN_IP_GSCL,
+	EN_IP_GSCL_FIMC,
+	EN_IP_GSCL_SECURE_SMMU_GSCL0,
+	EN_IP_GSCL_SECURE_SMMU_GSCL1,
+	EN_IP_GSCL_SECURE_SMMU_MSCL0,
+	EN_IP_GSCL_SECURE_SMMU_MSCL1,
+};
+
+static unsigned long exynos5260_isp_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_ISP
+*/
+	MUX_SEL_ISP0,
+	MUX_SEL_ISP1,
+	DIV_ISP,
+	EN_ACLK_ISP0,
+	EN_ACLK_ISP1,
+	EN_PCLK_ISP0,
+	EN_PCLK_ISP1,
+	EN_SCLK_ISP,
+	EN_IP_ISP0,
+	EN_IP_ISP1,
+};
+
+static unsigned long exynos5260_kfc_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_KFC
+*/
+	KFC_PLL_LOCK,
+	KFC_PLL_CON0,
+	KFC_PLL_CON1,
+	KFC_PLL_FDET,
+	MUX_SEL_KFC0,
+	MUX_SEL_KFC2,
+	DIV_KFC,
+	DIV_KFC_PLL_FDET,
+	EN_ACLK_KFC,
+	EN_PCLK_KFC,
+	EN_SCLK_KFC,
+	EN_IP_KFC,
+};
+
+static unsigned long exynos5260_mfc_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_MFC
+*/
+	MUX_SEL_MFC,
+	DIV_MFC,
+	EN_ACLK_MFC,
+	EN_ACLK_SECURE_SMMU2_MFC,
+	EN_PCLK_MFC,
+	EN_PCLK_SECURE_SMMU2_MFC,
+	EN_IP_MFC,
+	EN_IP_MFC_SECURE_SMMU2_MFC,
+};
+
+static unsigned long exynos5260_mif_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_MIF
+*/
+	MEM_PLL_LOCK,
+	BUS_PLL_LOCK,
+	MEDIA_PLL_LOCK,
+	MEM_PLL_CON0,
+	MEM_PLL_CON1,
+	MEM_PLL_FDET,
+	BUS_PLL_CON0,
+	BUS_PLL_CON1,
+	BUS_PLL_FDET,
+	MEDIA_PLL_CON0,
+	MEDIA_PLL_CON1,
+	MEDIA_PLL_FDET,
+	MUX_SEL_MIF,
+	DIV_MIF,
+	DIV_MIF_PLL_FDET,
+	EN_ACLK_MIF,
+	EN_ACLK_MIF_SECURE_DREX1_TZ,
+	EN_ACLK_MIF_SECURE_DREX0_TZ,
+	EN_ACLK_MIF_SECURE_INTMEM,
+	EN_PCLK_MIF,
+	EN_PCLK_MIF_SECURE_MONOCNT,
+	EN_PCLK_MIF_SECURE_RTC_APBIF,
+	EN_PCLK_MIF_SECURE_DREX1_TZ,
+	EN_PCLK_MIF_SECURE_DREX0_TZ,
+	EN_SCLK_MIF,
+	EN_IP_MIF,
+	EN_IP_MIF_SECURE_MONOCNT,
+	EN_IP_MIF_SECURE_RTC_APBIF,
+	EN_IP_MIF_SECURE_DREX1_TZ,
+	EN_IP_MIF_SECURE_DREX0_TZ,
+	EN_IP_MIF_SECURE_INTEMEM,
+};
+
+static unsigned long exynos5260_peri_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_PERI
+*/
+	MUX_SEL_PERI,
+	MUX_SEL_PERI1,
+	DIV_PERI,
+	EN_PCLK_PERI0,
+	EN_PCLK_PERI1,
+	EN_PCLK_PERI2,
+	EN_PCLK_PERI3,
+	EN_PCLK_PERI_SECURE_CHIPID,
+	EN_PCLK_PERI_SECURE_PROVKEY0,
+	EN_PCLK_PERI_SECURE_PROVKEY1,
+	EN_PCLK_PERI_SECURE_SECKEY,
+	EN_PCLK_PERI_SECURE_ANTIRBKCNT,
+	EN_PCLK_PERI_SECURE_TOP_RTC,
+	EN_PCLK_PERI_SECURE_TZPC,
+	EN_SCLK_PERI,
+	EN_SCLK_PERI_SECURE_TOP_RTC,
+	EN_IP_PERI0,
+	EN_IP_PERI1,
+	EN_IP_PERI2,
+	EN_IP_PERI_SECURE_CHIPID,
+	EN_IP_PERI_SECURE_PROVKEY0,
+	EN_IP_PERI_SECURE_PROVKEY1,
+	EN_IP_PERI_SECURE_SECKEY,
+	EN_IP_PERI_SECURE_ANTIRBKCNT,
+	EN_IP_PERI_SECURE_TOP_RTC,
+	EN_IP_PERI_SECURE_TZPC,
+};
+
+static unsigned long exynos5260_top_clk_regs[] __initdata = {
+/*
+ *Registers for CMU_TOP
+*/
+	DISP_PLL_LOCK,
+	AUD_PLL_LOCK,
+	DISP_PLL_CON0,
+	DISP_PLL_CON1,
+	DISP_PLL_FDET,
+	AUD_PLL_CON0,
+	AUD_PLL_CON1,
+	AUD_PLL_CON2,
+	AUD_PLL_FDET,
+	MUX_SEL_TOP_PLL0,
+	MUX_SEL_TOP_MFC,
+	MUX_SEL_TOP_G2D,
+	MUX_SEL_TOP_GSCL,
+	MUX_SEL_TOP_ISP10,
+	MUX_SEL_TOP_ISP11,
+	MUX_SEL_TOP_DISP0,
+	MUX_SEL_TOP_DISP1,
+	MUX_SEL_TOP_BUS,
+	MUX_SEL_TOP_PERI0,
+	MUX_SEL_TOP_PERI1,
+	MUX_SEL_TOP_FSYS,
+	DIV_TOP_G2D_MFC,
+	DIV_TOP_GSCL_ISP0,
+	DIV_TOP_ISP10,
+	DIV_TOP_ISP11,
+	DIV_TOP_DISP,
+	DIV_TOP_BUS,
+	DIV_TOP_PERI0,
+	DIV_TOP_PERI1,
+	DIV_TOP_PERI2,
+	DIV_TOP_FSYS0,
+	DIV_TOP_FSYS1,
+	DIV_TOP_HPM,
+	DIV_TOP_PLL_FDET,
+	EN_ACLK_TOP,
+	EN_SCLK_TOP,
+	EN_IP_TOP,
+};
+
+static int exynos5260_clk_suspend(void)
+{
+	struct exynos5260_clock_reg_cache *cache;
+
+	list_for_each_entry(cache, &clock_reg_cache_list, node)
+		samsung_clk_save(cache->reg_base, cache->rdump,
+				cache->rd_num);
+
+	return 0;
+}
+
+static void exynos5260_clk_resume(void)
+{
+	struct exynos5260_clock_reg_cache *cache;
+
+	list_for_each_entry(cache, &clock_reg_cache_list, node)
+		samsung_clk_restore(cache->reg_base, cache->rdump,
+				cache->rd_num);
+}
+
+static struct syscore_ops exynos5260_clk_syscore_ops = {
+	.suspend = exynos5260_clk_suspend,
+	.resume = exynos5260_clk_resume,
+};
+
+static void exynos5260_clk_sleep_init(void __iomem *reg_base,
+			unsigned long *rdump,
+			unsigned long nr_rdump)
+{
+	struct exynos5260_clock_reg_cache *reg_cache;
+
+	reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
+			GFP_KERNEL);
+	if (!reg_cache)
+		panic("could not allocate register cache.\n");
+
+	reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
+
+	if (!reg_cache->rdump)
+		panic("could not allocate register dump storage.\n");
+
+	reg_cache->rd_num = nr_rdump;
+	reg_cache->reg_base = reg_base;
+	list_add_tail(&reg_cache->node, &clock_reg_cache_list);
+
+	if (!syscore_ops_registered) {
+		register_syscore_ops(&exynos5260_clk_syscore_ops);
+		syscore_ops_registered = true;
+	}
+
+	exynos5260_clk_suspend();
+}
+
+#else
+static void exynos5260_clk_sleep_init(void) {}
+#endif
+
+/*
+ * List of parent clocks for muses in CMU_AUD
+*/
+PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
+PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_audcdclk0_user"};
+PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_audcdclk0_user"};
+
+/*
+ * List of parent clocks for muses in CMU_DISP
+*/
+PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
+			"phyclk_dptx_phy_ch3_txd_clk"};
+PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
+			"phyclk_dptx_phy_ch2_txd_clk"};
+PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
+			"phyclk_dptx_phy_ch1_txd_clk"};
+PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
+			"phyclk_dptx_phy_ch0_txd_clk"};
+
+PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
+PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
+PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
+PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
+			"phyclk_hdmi_phy_tmds_clko"};
+PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
+			"phyclk_hdmi_phy_ref_clko"};
+PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll",
+			"phyclk_hdmi_phy_pixel_clko"};
+PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll",
+			"phyclk_hdmi_link_o_tmds_clkhi"};
+PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll",
+			"phyclk_mipi_dphy_4l_m_txbyte_clkhs"};
+PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll",
+			"phyclk_dptx_phy_o_ref_clk_24m"};
+PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll",
+			"phyclk_dptx_phy_clk_div2"};
+PNAME(mout_sclk_dsim1_tx_clk_esc_clk_user_p) = {"fin_pll",
+			"sclk_dsim1_txclkescclk"};
+PNAME(mout_sclk_dsim1_tx_clk_esc3_user_p) = {"fin_pll",
+			"sclk_dsim1_txclkesc3"};
+PNAME(mout_sclk_dsim1_tx_clk_esc2_user_p) = {"fin_pll",
+			"sclk_dsim1_txclkesc2"};
+PNAME(mout_sclk_dsim1_tx_clk_esc1_user_p) = {"fin_pll",
+			"sclk_dsim1_txclkesc1"};
+PNAME(mout_sclk_dsim1_tx_clk_esc0_user_p) = {"fin_pll",
+			"sclk_dsim1_txclkesc0"};
+PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user",
+			"mout_aclk_disp_222_user"};
+PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll",
+			"phyclk_mipi_dphy_4l_m_rxclkesc0"};
+PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk",
+			"dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
+
+/*
+ * List of parent clocks for muses in CMU_EGL
+*/
+PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"};
+PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"};
+
+/*
+ * List of parent clocks for muses in CMU_FSYS
+*/
+PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll",
+			"phyclk_usbhost20_phy_phyclock"};
+PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll",
+			"phyclk_usbhost20_phy_freeclk"};
+PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll",
+			"phyclk_usbhost20_phy_clk48mohci"};
+PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll",
+			"phyclk_usbdrd30_udrd30_pipe_pclk"};
+PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll",
+			"phyclk_usbdrd30_udrd30_phyclock"};
+
+/*
+ * List of parent clocks for muses in CMU_G2D
+*/
+PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"};
+
+/*
+ * List of parent clocks for muses in CMU_G3D
+*/
+PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"};
+
+/*
+ * List of parent clocks for muses in CMU_GSCL
+*/
+PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "fout_aud_pll"};
+PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
+PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
+PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
+
+/*
+ * List of parent clocks for muses in CMU_ISP
+*/
+PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"};
+PNAME(mout_isp_266_user_p)	 = {"fin_pll", "dout_aclk_isp1_266"};
+
+/*
+ * List of parent clocks for muses in CMU_KFC
+*/
+PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"};
+PNAME(mout_kfc_p)	 = {"mout_kfc_pll", "dout_media_pll"};
+
+/*
+ * List of parent clocks for muses in CMU_MFC
+*/
+PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"};
+
+/*
+ * List of parent clocks for muses in CMU_MIF
+*/
+PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"};
+PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"};
+PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"};
+PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"};
+PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"};
+PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"};
+PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"};
+
+/*
+ * List of parent clocks for muses in CMU_PERI
+*/
+PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud",
+			"phyclk_hdmi_phy_ref_cko"};
+PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
+			"phyclk_hdmi_phy_ref_cko"};
+PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extlk", "fin_pll",
+			"dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
+
+/*
+ * List of parent clocks for muses in CMU_TOP
+*/
+PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};
+PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"};
+PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"};
+PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"};
+PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"};
+PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"};
+
+PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"};
+
+PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"};
+
+PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user",
+			"mout_gscl_bustop_333"};
+PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user",
+			"mout_m2m_mediatop_400"};
+PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user",
+			"mout_gscl_bustop_fimc"};
+
+PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user",
+			"mout_memtop_pll_user"};
+PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"};
+PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"};
+
+PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"};
+
+PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
+PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"};
+PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
+PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"};
+PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user",
+			"mout_bustop_pll_user"};
+PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"};
+
+PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
+PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
+
+PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"};
+
+PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a",
+			"mout_mediatop_pll_user"};
+PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a",
+			"mout_mediatop_pll_user"};
+PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a",
+			"mout_mediatop_pll_user"};
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos5260_fixed_rate_ext_clks[] __initdata = {
+	FRATE(FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 24000000),
+	FRATE(ID_NONE, "xrtcxti", NULL, CLK_IS_ROOT, 32768),
+
+	FRATE(ID_NONE, "ioclk_audcdclk0_user", NULL, CLK_IS_ROOT, 0),
+
+	FRATE(ID_NONE, "ioclk_pcm_extclk", NULL, CLK_IS_ROOT, 2048000),
+	FRATE(ID_NONE, "ioclk_aud_i2s_bclk", NULL, CLK_IS_ROOT, 2048000),
+	FRATE(ID_NONE, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 49152000),
+	FRATE(ID_NONE, "ioclk_i2s_cdclk", NULL, CLK_IS_ROOT, 0),
+	FRATE(ID_NONE, "ioclk_spdif_extlk", NULL, CLK_IS_ROOT, 0),
+
+	FRATE(ID_NONE, "ioclk_i2s_sclk", NULL, CLK_IS_ROOT, 0),
+	FRATE(ID_NONE, "ioclk_spi0_clkin", NULL, CLK_IS_ROOT, 0),
+	FRATE(ID_NONE, "ioclk_spi1_clkin", NULL, CLK_IS_ROOT, 0),
+	FRATE(ID_NONE, "ioclk_spi2_clkin", NULL, CLK_IS_ROOT, 0),
+
+	FRATE(ID_NONE, "ioclk_mmc0_sdrdqs_in", NULL, CLK_IS_ROOT, 200000000),
+
+	FRATE(ID_NONE, "ioclk_spi0_isp_spi_clk_in", NULL,
+			CLK_IS_ROOT, 50000000),
+	FRATE(ID_NONE, "ioclk_spi1_isp_spi_clk_in", NULL,
+			CLK_IS_ROOT, 50000000),
+	FRATE(ID_NONE, "ioclk_spi0_isp_spi_clk_out", NULL,
+			CLK_IS_ROOT, 50000000),
+	FRATE(ID_NONE, "ioclk_spi1_isp_spi_clk_out", NULL,
+			CLK_IS_ROOT, 50000000),
+};
+
+/* fixed rate clocks generated inside the soc */
+struct samsung_fixed_rate_clock exynos5260_fixed_rate_clks[] __initdata = {
+	FRATE(ID_NONE, "phyclk_dptx_phy_ch3_txd_clk", NULL,
+			CLK_IS_ROOT, 270000000),
+	FRATE(ID_NONE, "phyclk_dptx_phy_ch2_txd_clk", NULL,
+			CLK_IS_ROOT, 270000000),
+	FRATE(ID_NONE, "phyclk_dptx_phy_ch1_txd_clk", NULL,
+			CLK_IS_ROOT, 270000000),
+	FRATE(ID_NONE, "phyclk_dptx_phy_ch0_txd_clk", NULL,
+			CLK_IS_ROOT, 270000000),
+	FRATE(ID_NONE, "phyclk_hdmi_phy_tmds_clko", NULL,
+			CLK_IS_ROOT, 250000000),
+	FRATE(TOP_SCLK_HDMIPHY, "phyclk_hdmi_phy_pixel_clko", NULL,
+			CLK_IS_ROOT, 1660000000),
+	FRATE(ID_NONE, "phyclk_hdmi_link_o_tmds_clkhi", NULL,
+			CLK_IS_ROOT, 125000000),
+	FRATE(ID_NONE, "phyclk_mipi_dphy_4l_m_txbyteclkhs", NULL,
+			CLK_IS_ROOT, 187500000),
+	FRATE(ID_NONE, "phyclk_dptx_phy_o_ref_clk_24m", NULL,
+			CLK_IS_ROOT, 24000000),
+	FRATE(ID_NONE, "phyclk_dptx_phy_clk_div2", NULL,
+			CLK_IS_ROOT, 135000000),
+	FRATE(ID_NONE, "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL,
+			CLK_IS_ROOT, 20000000),
+	FRATE(ID_NONE, "phyclk_usbhost20_phy_phyclock", NULL,
+			CLK_IS_ROOT, 60000000),
+	FRATE(ID_NONE, "phyclk_usbhost20_phy_freeclk", NULL,
+			CLK_IS_ROOT, 60000000),
+	FRATE(ID_NONE, "phyclk_usbhost20_phy_clk48mohci", NULL,
+			CLK_IS_ROOT, 48000000),
+	FRATE(ID_NONE, "phyclk_usbdrd30_udrd30_pipe_pclk", NULL,
+			CLK_IS_ROOT, 125000000),
+	FRATE(ID_NONE, "phyclk_usbdrd30_udrd30_phyclock", NULL,
+			CLK_IS_ROOT, 60000000),
+};
+
+struct samsung_fixed_factor_clock exynos5260_fixed_factor_clks[] __initdata = {
+};
+
+/* MULITPLEXER CLOCKS */
+
+/*
+ * List of Mux clocks for CMU_AUD
+*/
+struct samsung_mux_clock exynos5260_aud_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
+			MUX_SEL_AUD, 8, 1),
+	MUX(ID_NONE, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
+			MUX_SEL_AUD, 4, 1),
+	MUX(ID_NONE, "mout_aud_pll_user", mout_aud_pll_user_p,
+			MUX_SEL_AUD, 0, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_DISP
+*/
+struct samsung_mux_clock exynos5260_disp_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_sclk_hdmi_spdif", mout_sclk_hdmi_spdif_p,
+			MUX_SEL_DISP4, 4, 2),
+
+	MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc_clk_user",
+			mout_sclk_dsim1_tx_clk_esc_clk_user_p,
+			MUX_SEL_DISP2, 28, 1),
+	MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc3_user",
+			mout_sclk_dsim1_tx_clk_esc3_user_p,
+			MUX_SEL_DISP2, 24, 1),
+	MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc2_user",
+			mout_sclk_dsim1_tx_clk_esc2_user_p,
+			MUX_SEL_DISP2, 20, 1),
+	MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc1_user",
+			mout_sclk_dsim1_tx_clk_esc1_user_p,
+			MUX_SEL_DISP2, 16, 1),
+	MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc0_user",
+			mout_sclk_dsim1_tx_clk_esc0_user_p,
+			MUX_SEL_DISP2, 12, 1),
+	MUX(ID_NONE, "mout_sclk_hdmi_pixel", mout_sclk_hdmi_pixel_p,
+			MUX_SEL_DISP2, 4, 1),
+	MUX(ID_NONE, "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user",
+			mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p,
+			MUX_SEL_DISP2, 0, 1),
+
+	MUX(ID_NONE, "mout_phyclk_hdmi_phy_tmds_clko_user",
+			mout_phyclk_hdmi_phy_tmds_clko_user_p,
+			MUX_SEL_DISP1, 28, 1),
+	MUX(ID_NONE, "mout_phyclk_hdmi_phy_ref_clko_user",
+			mout_phyclk_hdmi_phy_ref_clko_user_p,
+			MUX_SEL_DISP1, 24, 1),
+	MUX(DISP_MOUT_HDMI_PHY_PIXEL, "mout_phyclk_hdmi_phy_pixel_clko_user",
+			mout_phyclk_hdmi_phy_pixel_clko_user_p,
+			MUX_SEL_DISP1, 20, 1),
+	MUX(ID_NONE, "mout_phyclk_hdmi_link_o_tmds_clkhi_user",
+			mout_phyclk_hdmi_link_o_tmds_clkhi_user_p,
+			MUX_SEL_DISP1, 16, 1),
+	MUX(ID_NONE, "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs",
+			mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p,
+			MUX_SEL_DISP1, 8, 1),
+	MUX(ID_NONE, "mout_phyclk_dptx_phy_o_ref_clk_24m_user",
+			mout_phyclk_dptx_phy_o_ref_clk_24m_user_p,
+			MUX_SEL_DISP1, 4, 1),
+	MUX(ID_NONE, "mout_phyclk_dptx_phy_clk_div2_user",
+			mout_phyclk_dptx_phy_clk_div2_user_p,
+			MUX_SEL_DISP1, 0, 1),
+
+	MUX(ID_NONE, "mout_phyclk_dptx_phy_ch3_txd_clk_user",
+			mout_phyclk_dptx_phy_ch3_txd_clk_user_p,
+			MUX_SEL_DISP0, 28, 1),
+	MUX(ID_NONE, "mout_phyclk_dptx_phy_ch2_txd_clk_user",
+			mout_phyclk_dptx_phy_ch2_txd_clk_user_p,
+			MUX_SEL_DISP0, 24, 1),
+	MUX(ID_NONE, "mout_phyclk_dptx_phy_ch1_txd_clk_user",
+			mout_phyclk_dptx_phy_ch1_txd_clk_user_p,
+			MUX_SEL_DISP0, 20, 1),
+	MUX(ID_NONE, "mout_phyclk_dptx_phy_ch0_txd_clk_user",
+			mout_phyclk_dptx_phy_ch0_txd_clk_user_p,
+			MUX_SEL_DISP0, 16, 1),
+	MUX(ID_NONE, "mout_aclk_disp_222_user", mout_aclk_disp_222_user_p,
+			MUX_SEL_DISP0, 8, 1),
+	MUX(ID_NONE, "mout_sclk_disp_pixel_user", mout_sclk_disp_pixel_user_p,
+			MUX_SEL_DISP0, 4, 1),
+	MUX(ID_NONE, "mout_aclk_disp_333_user", mout_aclk_disp_333_user_p,
+			MUX_SEL_DISP0, 0, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_EGL
+*/
+struct samsung_mux_clock exynos5260_egl_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1),
+	MUX(ID_NONE, "mout_egl_pll", mout_egl_pll_p, MUX_SEL_EGL, 4, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_FSYS
+*/
+struct samsung_mux_clock exynos5260_fsys_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_phyclk_usbhost20_phyclk_user",
+			mout_phyclk_usbhost20_phyclk_user_p,
+			MUX_SEL_FSYS1, 16, 1),
+	MUX(ID_NONE, "mout_phyclk_usbhost20_freeclk_user",
+			mout_phyclk_usbhost20_freeclk_user_p,
+			MUX_SEL_FSYS1, 12, 1),
+	MUX(ID_NONE, "mout_phyclk_usbhost20_clk48mohci_user",
+			mout_phyclk_usbhost20_clk48mohci_user_p,
+			MUX_SEL_FSYS1, 8, 1),
+	MUX(ID_NONE, "mout_phyclk_usbdrd30_pipe_pclk_user",
+			mout_phyclk_usbdrd30_pipe_pclk_user_p,
+			MUX_SEL_FSYS1, 4, 1),
+	MUX(ID_NONE, "mout_phyclk_usbdrd30_phyclock_user",
+			mout_phyclk_usbdrd30_phyclock_user_p,
+			MUX_SEL_FSYS1, 0, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_G2D
+*/
+struct samsung_mux_clock exynos5260_g2d_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_aclk_g2d_333_user", mout_aclk_g2d_333_user_p,
+			MUX_SEL_G2D, 0, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_G3D
+*/
+struct samsung_mux_clock exynos5260_g3d_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_g3d_pll", mout_g3d_pll_p, MUX_SEL_G3D, 0, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_GSCL
+*/
+struct samsung_mux_clock exynos5260_gscl_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_aclk_csis", mout_aclk_csis_p, MUX_SEL_GSCL, 24, 1),
+	MUX(ID_NONE, "mout_aclk_gscl_fimc_user", mout_aclk_gscl_fimc_user_p,
+			MUX_SEL_GSCL, 8, 1),
+	MUX(ID_NONE, "mout_aclk_m2m_400_user", mout_aclk_m2m_400_user_p,
+			MUX_SEL_GSCL, 4, 1),
+	MUX(ID_NONE, "mout_aclk_gscl_333_user", mout_aclk_gscl_333_user_p,
+			MUX_SEL_GSCL, 0, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_ISP
+*/
+struct samsung_mux_clock exynos5260_isp_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_isp_400_user", mout_isp_400_user_p,
+			MUX_SEL_ISP0, 4, 1),
+	MUX(ID_NONE, "mout_isp_266_user", mout_isp_266_user_p,
+			MUX_SEL_ISP0, 0, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_KFC
+*/
+struct samsung_mux_clock exynos5260_kfc_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_kfc_pll", mout_kfc_pll_p, MUX_SEL_KFC0, 0, 1),
+	MUX(ID_NONE, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_MFC
+*/
+struct samsung_mux_clock exynos5260_mfc_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_aclk_mfc_333_user", mout_aclk_mfc_333_user_p,
+			MUX_SEL_MFC, 0, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_MIF
+*/
+struct samsung_mux_clock exynos5260_mif_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_clk2x_phy", mout_clk2x_phy_p, MUX_SEL_MIF, 24, 1),
+	MUX(ID_NONE, "mout_mif_drex2x", mout_mif_drex2x_p, MUX_SEL_MIF, 20, 1),
+	MUX(ID_NONE, "mout_clkm_phy", mout_clkm_phy_p, MUX_SEL_MIF, 16, 1),
+	MUX(ID_NONE, "mout_mif_drex", mout_mif_drex_p, MUX_SEL_MIF, 12, 1),
+	MUX(ID_NONE, "mout_media_pll", mout_media_pll_p, MUX_SEL_MIF, 8, 1),
+	MUX(ID_NONE, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF, 4, 1),
+	MUX(ID_NONE, "mout_mem_pll", mout_mem_pll_p, MUX_SEL_MIF, 0, 1),
+};
+
+/*
+ * List of Mux clocks for CMU_PERI
+*/
+struct samsung_mux_clock exynos5260_peri_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_sclk_spdif", mout_sclk_spdif_p,
+			MUX_SEL_PERI1, 20, 2),
+	MUX(ID_NONE, "mout_sclk_i2scod", mout_sclk_i2scod_p,
+			MUX_SEL_PERI1, 12, 2),
+	MUX(ID_NONE, "mout_sclk_pcm", mout_sclk_pcm_p,
+			MUX_SEL_PERI1, 4, 2),
+};
+
+/*
+ * List of Mux clocks for CMU_TOP
+*/
+struct samsung_mux_clock exynos5260_top_mux_clks[] __initdata = {
+	MUX(ID_NONE, "mout_audtop_pll_user", mout_audtop_pll_user_p,
+			MUX_SEL_TOP_PLL0, 24, 1),
+	MUX(ID_NONE, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP_PLL0, 16, 1),
+	MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
+			MUX_SEL_TOP_PLL0, 12, 1),
+	MUX(ID_NONE, "mout_bustop_pll_user", mout_bustop_pll_user_p,
+			MUX_SEL_TOP_PLL0, 8, 1),
+	MUX(ID_NONE, "mout_memtop_pll_user", mout_memtop_pll_user_p,
+			MUX_SEL_TOP_PLL0, 4, 1),
+	MUX(ID_NONE, "mout_mediatop_pll_user", mout_mediatop_pll_user_p,
+			MUX_SEL_TOP_PLL0, 0, 1),
+
+
+	MUX(ID_NONE, "mout_disp_disp_333", mout_disp_disp_333_p,
+			MUX_SEL_TOP_DISP0, 0, 1),
+	MUX(ID_NONE, "mout_aclk_disp_333", mout_aclk_disp_333_p,
+			MUX_SEL_TOP_DISP0, 8, 1),
+	MUX(ID_NONE, "mout_disp_disp_222", mout_disp_disp_222_p,
+			MUX_SEL_TOP_DISP0, 12, 1),
+	MUX(ID_NONE, "mout_aclk_disp_222", mout_aclk_disp_222_p,
+			MUX_SEL_TOP_DISP0, 20, 1),
+	MUX(ID_NONE, "mout_disp_media_pixel", mout_disp_media_pixel_p,
+			MUX_SEL_TOP_DISP1, 8, 1),
+	MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p,
+			MUX_SEL_TOP_DISP1, 0, 1),
+
+	MUX(ID_NONE, "mout_sclk_peri_spi0_clk", mout_sclk_peri_spi_clk_p,
+			MUX_SEL_TOP_PERI1, 8, 1),
+	MUX(ID_NONE, "mout_sclk_peri_spi1_clk", mout_sclk_peri_spi_clk_p,
+			MUX_SEL_TOP_PERI1, 4, 1),
+	MUX(ID_NONE, "mout_sclk_peri_spi2_clk", mout_sclk_peri_spi_clk_p,
+			MUX_SEL_TOP_PERI1, 0, 1),
+	MUX(ID_NONE, "mout_sclk_peri_uart0_uclk", mout_sclk_peri_uart_uclk_p,
+			MUX_SEL_TOP_PERI1, 20, 1),
+	MUX(ID_NONE, "mout_sclk_peri_uart2_uclk", mout_sclk_peri_uart_uclk_p,
+			MUX_SEL_TOP_PERI1, 16, 1),
+	MUX(ID_NONE, "mout_sclk_peri_uart1_uclk", mout_sclk_peri_uart_uclk_p,
+			MUX_SEL_TOP_PERI1, 12, 1),
+
+	MUX(ID_NONE, "mout_bus4_bustop_100", mout_bus_bustop_100_p,
+			MUX_SEL_TOP_BUS, 28, 1),
+	MUX(ID_NONE, "mout_bus4_bustop_400", mout_bus_bustop_400_p,
+			MUX_SEL_TOP_BUS, 24, 1),
+	MUX(ID_NONE, "mout_bus3_bustop_100", mout_bus_bustop_100_p,
+			MUX_SEL_TOP_BUS, 20, 1),
+	MUX(ID_NONE, "mout_bus3_bustop_400", mout_bus_bustop_400_p,
+			MUX_SEL_TOP_BUS, 16, 1),
+	MUX(ID_NONE, "mout_bus2_bustop_400", mout_bus_bustop_400_p,
+			MUX_SEL_TOP_BUS, 12, 1),
+	MUX(ID_NONE, "mout_bus2_bustop_100", mout_bus_bustop_100_p,
+			MUX_SEL_TOP_BUS, 8, 1),
+	MUX(ID_NONE, "mout_bus1_bustop_100", mout_bus_bustop_100_p,
+			MUX_SEL_TOP_BUS, 4, 1),
+	MUX(ID_NONE, "mout_bus1_bustop_400", mout_bus_bustop_400_p,
+			MUX_SEL_TOP_BUS, 0, 1),
+
+	MUX(ID_NONE, "mout_sclk_fsys_usb", mout_sclk_fsys_usb_p,
+			MUX_SEL_TOP_FSYS, 0, 1),
+	MUX(ID_NONE, "mout_sclk_fsys_mmc0_sdclkin_a",
+			mout_sclk_fsys_mmc_sdclkin_a_p,
+			MUX_SEL_TOP_FSYS, 20, 1),
+	MUX(ID_NONE, "mout_sclk_fsys_mmc1_sdclkin_a",
+			mout_sclk_fsys_mmc_sdclkin_a_p,
+			MUX_SEL_TOP_FSYS, 12, 1),
+	MUX(ID_NONE, "mout_sclk_fsys_mmc2_sdclkin_a",
+			mout_sclk_fsys_mmc_sdclkin_a_p,
+			MUX_SEL_TOP_FSYS, 4, 1),
+	MUX(ID_NONE, "mout_sclk_fsys_mmc0_sdclkin_b",
+			mout_sclk_fsys_mmc0_sdclkin_b_p,
+			MUX_SEL_TOP_FSYS, 24, 1),
+	MUX(ID_NONE, "mout_sclk_fsys_mmc1_sdclkin_b",
+			mout_sclk_fsys_mmc1_sdclkin_b_p,
+			MUX_SEL_TOP_FSYS, 16, 1),
+	MUX(ID_NONE, "mout_sclk_fsys_mmc2_sdclkin_b",
+			mout_sclk_fsys_mmc2_sdclkin_b_p,
+			MUX_SEL_TOP_FSYS, 8, 1),
+
+	MUX(ID_NONE, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
+			MUX_SEL_TOP_ISP10, 20, 1),
+	MUX(ID_NONE, "mout_isp1_media_266", mout_isp1_media_266_p,
+			MUX_SEL_TOP_ISP10, 16, 1),
+	MUX(ID_NONE, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
+			MUX_SEL_TOP_ISP10, 8 , 1),
+	MUX(ID_NONE, "mout_isp1_media_400", mout_isp1_media_400_p,
+			MUX_SEL_TOP_ISP10, 4, 1),
+
+	MUX(ID_NONE, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
+			MUX_SEL_TOP_ISP11, 4, 1),
+	MUX(ID_NONE, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p,
+			MUX_SEL_TOP_ISP11, 8, 1),
+	MUX(ID_NONE, "mout_sclk_isp1_uart", mout_sclk_isp_uart_p,
+			MUX_SEL_TOP_ISP11, 12, 1),
+	MUX(ID_NONE, "mout_sclk_isp1_sensor2", mout_sclk_isp_sensor_p,
+			MUX_SEL_TOP_ISP11, 24, 1),
+	MUX(ID_NONE, "mout_sclk_isp1_sensor1", mout_sclk_isp_sensor_p,
+			MUX_SEL_TOP_ISP11, 20, 1),
+	MUX(ID_NONE, "mout_sclk_isp1_sensor0", mout_sclk_isp_sensor_p,
+			MUX_SEL_TOP_ISP11, 16, 1),
+
+	MUX(ID_NONE, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
+			MUX_SEL_TOP_MFC, 8, 1),
+	MUX(ID_NONE, "mout_mfc_bustop_333", mout_mfc_bustop_333_p,
+			MUX_SEL_TOP_MFC, 4, 1),
+
+	MUX(ID_NONE, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
+			MUX_SEL_TOP_G2D, 8, 1),
+	MUX(ID_NONE, "mout_g2d_bustop_333", mout_g2d_bustop_333_p,
+			MUX_SEL_TOP_G2D, 4, 1),
+
+	MUX(ID_NONE, "mout_aclk_gscl_fimc", mout_aclk_gscl_fimc_p,
+			MUX_SEL_TOP_GSCL, 20, 1),
+	MUX(ID_NONE, "mout_gscl_bustop_fimc", mout_gscl_bustop_fimc_p,
+			MUX_SEL_TOP_GSCL, 16, 1),
+	MUX(ID_NONE, "mout_aclk_gscl_333", mout_aclk_gscl_333_p,
+			MUX_SEL_TOP_GSCL, 12, 1),
+	MUX(ID_NONE, "mout_gscl_bustop_333", mout_gscl_bustop_333_p,
+			MUX_SEL_TOP_GSCL, 8, 1),
+	MUX(ID_NONE, "mout_aclk_gscl_400", mout_aclk_gscl_400_p,
+			MUX_SEL_TOP_GSCL, 4, 1),
+	MUX(ID_NONE, "mout_m2m_mediatop_400", mout_m2m_mediatop_400_p,
+			MUX_SEL_TOP_GSCL, 0, 1),
+};
+
+/* DIVIDER CLOCKS */
+
+/*
+ * List of Divider clocks for CMU_AUD
+*/
+struct samsung_div_clock exynos5260_aud_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_aclk_aud_131", "mout_aud_pll_user",
+			DIV_AUD0, 0, 4),
+	DIV(ID_NONE, "dout_sclk_aud_uart", "mout_aud_pll_user",
+			DIV_AUD1, 12, 4),
+	DIV(ID_NONE, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm",
+			DIV_AUD1, 4, 8),
+	DIV(ID_NONE, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s",
+			DIV_AUD1, 0, 4),
+};
+
+/*
+ * List of Divider clocks for CMU_DISP
+*/
+struct samsung_div_clock exynos5260_disp_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_sclk_hdmi_phy_pixel_clki", "mout_sclk_hdmi_pixel",
+			DIV_DISP, 16, 4),
+	DIV(ID_NONE, "dout_sclk_fimd1_extclkpll", "mout_sclk_disp_pixel_user",
+			DIV_DISP, 12, 4),
+	DIV(ID_NONE, "dout_pclk_disp_111", "mout_aclk_disp_222_user",
+			DIV_DISP, 8, 4),
+};
+
+/*
+ * List of Divider clocks for CMU_EGL
+*/
+struct samsung_div_clock exynos5260_egl_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3),
+	DIV(ID_NONE, "dout_egl_pclk_dbg", "dout_egl_atclk", DIV_EGL, 20, 3),
+	DIV(ID_NONE, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3),
+	DIV(ID_NONE, "dout_pclk_egl", "dout_egl_atclk", DIV_EGL, 12, 3),
+	DIV(ID_NONE, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3),
+	DIV(ID_NONE, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3),
+	DIV(ID_NONE, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3),
+};
+
+/*
+ * List of Divider clocks for CMU_G2D
+*/
+struct samsung_div_clock exynos5260_g2d_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
+			DIV_G2D, 0, 3),
+};
+
+/*
+ * List of Divider clocks for CMU_G3D
+*/
+
+struct samsung_div_clock exynos5260_g3d_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3),
+	DIV(ID_NONE, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3),
+};
+
+/*
+ * List of Divider clocks for CMU_GSCL
+*/
+struct samsung_div_clock exynos5260_gscl_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_aclk_csis_200", "mout_aclk_m2m_400_user",
+			DIV_GSCL, 4, 3),
+	DIV(ID_NONE, "dout_pclk_m2m_100", "mout_aclk_m2m_400_user",
+			DIV_GSCL, 0, 3),
+};
+
+/*
+ * List of Divider clocks for CMU_ISP
+*/
+
+struct samsung_div_clock exynos5260_isp_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2),
+	DIV(ID_NONE, "dout_ca5_pclkdbg", "mout_kfc", DIV_ISP, 16, 4),
+	DIV(ID_NONE, "dout_ca5_atclkin", "mout_kfc", DIV_ISP, 12, 3),
+	DIV(ID_NONE, "dout_pclk_isp_133", "mout_kfc", DIV_ISP, 4, 4),
+	DIV(ID_NONE, "dout_pclk_isp_66", "mout_kfc", DIV_ISP, 0, 3),
+};
+
+/*
+ * List of Divider clocks for CMU_KFC
+*/
+struct samsung_div_clock exynos5260_kfc_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3),
+	DIV(ID_NONE, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3),
+	DIV(ID_NONE, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3),
+	DIV(ID_NONE, "dout_kfc_pclk_dbg", "dout_kfc2", DIV_KFC, 12, 3),
+	DIV(ID_NONE, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3),
+	DIV(ID_NONE, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3),
+	DIV(ID_NONE, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3),
+};
+
+/*
+ * List of Divider clocks for CMU_MFC
+*/
+struct samsung_div_clock exynos5260_mfc_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
+			DIV_MFC, 0, 3),
+};
+
+/*
+ * List of Divider clocks for CMU_MIF
+*/
+struct samsung_div_clock exynos5260_mif_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_aclk_bus_100", "dout_bus_pll", DIV_MIF, 28, 4),
+	DIV(ID_NONE, "dout_aclk_bus_200", "dout_bus_pll", DIV_MIF, 24, 3),
+	DIV(ID_NONE, "dout_aclk_mif_466", "dout_clk2x_phy", DIV_MIF, 20, 3),
+	DIV(ID_NONE, "dout_clk2x_phy", "mout_clk2x_phy", DIV_MIF, 16, 4),
+	DIV(ID_NONE, "dout_clkm_phy", "mout_clkm_phy", DIV_MIF, 12, 3),
+	DIV(ID_NONE, "dout_bus_pll", "mout_bus_pll", DIV_MIF, 8, 3),
+	DIV(ID_NONE, "dout_mem_pll", "mout_mem_pll", DIV_MIF, 4, 3),
+	DIV(ID_NONE, "dout_media_pll", "mout_media_pll", DIV_MIF, 0, 3),
+};
+
+/*
+ * List of Divider clocks for CMU_peri
+*/
+struct samsung_div_clock exynos5260_peri_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 0, 6),
+	DIV(ID_NONE, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8),
+};
+
+/*
+ * List of Divider clocks for CMU_TOP
+*/
+struct samsung_div_clock exynos5260_top_div_clks[] __initdata = {
+	DIV(ID_NONE, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
+			DIV_TOP_G2D_MFC, 4, 3),
+
+	DIV(ID_NONE, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
+			DIV_TOP_GSCL_ISP0, 0, 3),
+
+	DIV(ID_NONE, "dout_sclk_isp1_sensor2_a", "mout_aclk_gscl_fimc",
+			DIV_TOP_GSCL_ISP0, 24, 4),
+	DIV(ID_NONE, "dout_sclk_isp1_sensor1_a", "mout_aclk_gscl_400",
+			DIV_TOP_GSCL_ISP0, 20, 4),
+	DIV(ID_NONE, "dout_sclk_isp1_sensor0_a", "mout_aclk_gscl_fimc",
+			DIV_TOP_GSCL_ISP0, 16, 4),
+	DIV(ID_NONE, "dout_aclk_gscl_fimc", "mout_aclk_gscl_fimc",
+			DIV_TOP_GSCL_ISP0, 8, 3),
+	DIV(ID_NONE, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
+			DIV_TOP_GSCL_ISP0, 4, 3),
+	DIV(ID_NONE, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
+			DIV_TOP_GSCL_ISP0, 0, 3),
+
+	DIV(ID_NONE, "dout_sclk_isp1_spi0_b", "dout_sclk_isp1_spi0_a",
+			DIV_TOP_ISP10, 16, 8),
+	DIV(ID_NONE, "dout_sclk_isp1_spi0_a", "mout_sclk_isp1_spi0",
+			DIV_TOP_ISP10, 12, 4),
+	DIV(ID_NONE, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
+			DIV_TOP_ISP10, 4, 3),
+	DIV(ID_NONE, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
+			DIV_TOP_ISP10, 0, 3),
+	DIV(ID_NONE, "dout_sclk_isp1_uart", "mout_sclk_isp1_uart",
+			DIV_TOP_ISP11, 12, 4),
+	DIV(ID_NONE, "dout_sclk_isp1_spi1_b", "dout_sclk_isp1_spi1_a",
+			DIV_TOP_ISP11, 4, 8),
+	DIV(ID_NONE, "dout_sclk_isp1_spi1_a", "mout_sclk_isp1_spi1",
+			DIV_TOP_ISP11, 0, 4),
+	DIV(ID_NONE, "dout_sclk_isp1_sensor2_b", "dout_sclk_isp1_sensor2_a",
+			DIV_TOP_ISP11, 24, 4),
+	DIV(ID_NONE, "dout_sclk_isp1_sensor1_b", "dout_sclk_isp1_sensor1_a",
+			DIV_TOP_ISP11, 20, 4),
+	DIV(ID_NONE, "dout_sclk_isp1_sensor0_b", "dout_sclk_isp1_sensor0_a",
+			DIV_TOP_ISP11, 16, 4),
+
+	DIV(ID_NONE, "dout_sclk_hpm_targetclk", "mout_bustop_pll_user",
+			DIV_TOP_HPM, 0, 3),
+
+	DIV(ID_NONE, "dout_sclk_disp_pixel", "mout_sclk_disp_pixel",
+			DIV_TOP_DISP, 8, 3),
+	DIV(ID_NONE, "dout_aclk_disp_222", "mout_aclk_disp_222",
+			DIV_TOP_DISP, 4, 3),
+	DIV(ID_NONE, "dout_aclk_disp_333", "mout_aclk_disp_333",
+			DIV_TOP_DISP, 0, 3),
+
+	DIV(ID_NONE, "dout_aclk_bus4_100", "mout_bus4_bustop_100",
+			DIV_TOP_BUS, 28, 4),
+	DIV(ID_NONE, "dout_aclk_bus4_400", "mout_bus4_bustop_400",
+			DIV_TOP_BUS, 24, 3),
+	DIV(ID_NONE, "dout_aclk_bus3_100", "mout_bus3_bustop_100",
+			DIV_TOP_BUS, 20, 4),
+	DIV(ID_NONE, "dout_aclk_bus3_400", "mout_bus3_bustop_400",
+			DIV_TOP_BUS, 16, 3),
+	DIV(ID_NONE, "dout_aclk_bus2_100", "mout_bus2_bustop_100",
+			DIV_TOP_BUS, 12, 4),
+	DIV(ID_NONE, "dout_aclk_bus2_400", "mout_bus2_bustop_400",
+			DIV_TOP_BUS, 8, 3),
+	DIV(ID_NONE, "dout_aclk_bus1_100", "mout_bus1_bustop_100",
+			DIV_TOP_BUS, 4, 4),
+	DIV(ID_NONE, "dout_aclk_bus1_400", "mout_bus1_bustop_400",
+			DIV_TOP_BUS, 0, 3),
+
+	DIV(ID_NONE, "dout_sclk_peri_spi1_b", "dout_sclk_peri_spi1_a",
+			DIV_TOP_PERI0, 20, 8),
+	DIV(ID_NONE, "dout_sclk_peri_spi1_a", "mout_sclk_peri_spi1_clk",
+			DIV_TOP_PERI0, 16, 4),
+	DIV(ID_NONE, "dout_sclk_peri_spi0_b", "dout_sclk_peri_spi0_a",
+			DIV_TOP_PERI0, 8, 8),
+	DIV(ID_NONE, "dout_sclk_peri_spi0_a", "mout_sclk_peri_spi0_clk",
+			DIV_TOP_PERI0, 4, 4),
+	DIV(ID_NONE, "dout_sclk_peri_uart0", "mout_sclk_peri_uart0_uclk",
+			DIV_TOP_PERI1, 24, 4),
+	DIV(ID_NONE, "dout_sclk_peri_uart2", "mout_sclk_peri_uart2_uclk",
+			DIV_TOP_PERI1, 20, 4),
+	DIV(ID_NONE, "dout_sclk_peri_uart1", "mout_sclk_peri_uart1_uclk",
+			DIV_TOP_PERI1, 16, 4),
+	DIV(ID_NONE, "dout_sclk_peri_spi2_b", "dout_sclk_peri_spi2_a",
+			DIV_TOP_PERI1, 4, 8),
+	DIV(ID_NONE, "dout_sclk_peri_spi2_a", "mout_sclk_peri_spi2_clk",
+			DIV_TOP_PERI1, 0, 4),
+	DIV(ID_NONE, "dout_aclk_peri_aud", "mout_audtop_pll_user",
+			DIV_TOP_PERI2, 24, 3),
+	DIV(ID_NONE, "dout_aclk_peri_66", "mout_bustop_pll_user",
+			DIV_TOP_PERI2, 20, 4),
+
+	DIV(ID_NONE, "dout_sclk_fsys_mmc0_sdclkin_b",
+			"dout_sclk_fsys_mmc0_sdclkin_a",
+			DIV_TOP_FSYS0, 16, 8),
+	DIV(ID_NONE, "dout_sclk_fsys_mmc0_sdclkin_a",
+			"mout_sclk_fsys_mmc0_sdclkin_b",
+			DIV_TOP_FSYS0, 12, 4),
+	DIV(ID_NONE, "dout_sclk_fsys_usbdrd30_suspend_clk",
+			"mout_sclk_fsys_usb",
+			DIV_TOP_FSYS0, 4, 4),
+	DIV(ID_NONE, "dout_aclk_fsys_200", "mout_bustop_pll_user",
+			DIV_TOP_FSYS0, 0, 3),
+
+	DIV(ID_NONE, "dout_sclk_fsys_mmc2_sdclkin_b",
+			"dout_sclk_fsys_mmc2_sdclkin_a",
+			DIV_TOP_FSYS1, 16, 8),
+	DIV(ID_NONE, "dout_sclk_fsys_mmc2_sdclkin_a",
+			"mout_sclk_fsys_mmc2_sdclkin_b",
+			DIV_TOP_FSYS1, 12, 4),
+	DIV(ID_NONE, "dout_sclk_fsys_mmc1_sdclkin_b",
+			"dout_sclk_fsys_mmc1_sdclkin_a",
+			DIV_TOP_FSYS1, 4, 8),
+	DIV(ID_NONE, "dout_sclk_fsys_mmc1_sdclkin_a",
+			"mout_sclk_fsys_mmc1_sdclkin_b",
+			DIV_TOP_FSYS1, 0, 4),
+};
+
+/* GATE CLOCKS */
+
+/*
+ * List of Gate clocks for CMU_AUD
+*/
+struct samsung_gate_clock exynos5260_aud_gate_clks[] __initdata = {
+	GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
+			EN_IP_AUD, 4, 0, 0),
+	GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
+	GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),
+	GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
+			EN_IP_AUD, 1, 0, 0),
+	GATE(ID_NONE, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD, 0, 0, 0),
+
+	GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
+			EN_SCLK_AUD, 2, 0, 0),
+	GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
+			EN_SCLK_AUD, 1, 0, 0),
+	GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
+			EN_SCLK_AUD, 0, 0, 0),
+};
+
+/*
+ * List of Gate clocks for CMU_DISP
+*/
+struct samsung_gate_clock exynos5260_disp_gate_clks[] __initdata = {
+	GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 25, 0, 0),
+	GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
+			"mout_aclk_disp_222_user",
+			EN_IP_DISP, 23, 0, 0),
+	GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
+			"mout_aclk_disp_222_user",
+			EN_IP_DISP, 22, 0, 0),
+	GATE(ID_NONE, "clk_pixel_mixer", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
+	GATE(ID_NONE, "clk_pixel_disp", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 11, 0, 0),
+	GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 10, 0, 0),
+	GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 9, 0, 0),
+	GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 8, 0, 0),
+	GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 7, 0, 0),
+	GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 6, 0, 0),
+	GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 5, 0, 0),
+	GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 4, 0, 0),
+
+	GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
+			"dout_sclk_hdmi_phy_pixel_clki",
+			EN_SCLK_DISP0, 29, 0, 0),
+	GATE(DISP_SCLK_HDMI, "sclk_hdmi_link_i_pixel",
+			"mout_phyclk_hdmi_phy_pixel_clko_user",
+			EN_SCLK_DISP0, 26, 0, 0),
+};
+
+/*
+ * List of Gate clocks for CMU_EGL
+*/
+struct samsung_gate_clock exynos5260_egl_gate_clks[] __initdata = {
+};
+
+/*
+ * List of Gate clocks for CMU_FSYS
+*/
+struct samsung_gate_clock exynos5260_fsys_gate_clks[] __initdata = {
+	GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 20, 0, 0),
+	GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 18, 0, 0),
+	GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 15, 0, 0),
+	GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 14, 0, 0),
+	GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 13, 0, 0),
+	GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 9, 0, 0),
+	GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 8, 0, 0),
+	GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 7, 0, 0),
+	GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 6, 0, 0),
+
+	GATE(FSYS_CLK_RTIC, "clk_rtic", "mout_bustop_pll_user",
+			EN_IP_FSYS_SECURE_RTIC, 11, 0, 0),
+	GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "mout_bustop_pll_user",
+			EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
+
+
+	GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g",
+			"mout_phyclk_usbdrd30_phyclock_user",
+			EN_SCLK_FSYS, 7, 0, 0),
+	GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
+			"mout_phyclk_usbdrd30_phyclock_user",
+			EN_SCLK_FSYS, 1, 0, 0),
+};
+
+/*
+ * List of Gate clocks for CMU_G2D
+*/
+struct samsung_gate_clock exynos5260_g2d_gate_clks[] __initdata = {
+	GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user",
+			EN_IP_G2D, 16, 0, 0),
+	GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user",
+			EN_IP_G2D, 6, 0, 0),
+	GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user",
+			EN_IP_G2D, 5, 0, 0),
+	GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user",
+			EN_IP_G2D, 4, 0, 0),
+
+	GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user",
+			EN_IP_G2D_SECURE_SSS, 17, 0, 0),
+	GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user",
+			EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0),
+	GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss",
+			"mout_aclk_g2d_333_user",
+			EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0),
+	GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user",
+			EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0),
+	GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user",
+			EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0),
+	GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user",
+			EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0),
+};
+
+/*
+ * List of Gate clocks for CMU_G3D
+*/
+struct samsung_gate_clock exynos5260_g3d_gate_clks[] __initdata = {
+	GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d",
+			EN_IP_G3D, 3, 0, 0),
+	GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0),
+};
+
+/*
+ * List of Gate clocks for CMU_GSCL
+*/
+struct samsung_gate_clock exynos5260_gscl_gate_clks[] __initdata = {
+	GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 9, 0, 0),
+	GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 8, 0, 0),
+	GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 5, 0, 0),
+	GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 4, 0, 0),
+	GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 3, 0, 0),
+	GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 2, 0, 0),
+	GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 12, 0, 0),
+	GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 11, 0, 0),
+	GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 10, 0, 0),
+	GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 9, 0, 0),
+	GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 8, 0, 0),
+	GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 7, 0, 0),
+	GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 6, 0, 0),
+	GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 5, 0, 0),
+	GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
+			"mout_aclk_gscl_333",
+			EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
+	GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333",
+			EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),
+	GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
+			"mout_aclk_m2m_400_user",
+			EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0),
+	GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
+			"mout_aclk_m2m_400_user",
+			EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
+
+	GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200",
+			EN_SCLK_GSCL_FIMC, 1, 0, 0),
+	GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200",
+			EN_SCLK_GSCL_FIMC, 0, 0, 0),
+};
+
+/*
+ * List of Gate clocks for CMU_ISP
+*/
+struct samsung_gate_clock exynos5260_isp_gate_clks[] __initdata = {
+	GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
+			EN_IP_ISP0, 15, 0, 0),
+
+	GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 31, 0, 0),
+	GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 30, 0, 0),
+	GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 28, 0, 0),
+	GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 27, 0, 0),
+
+	GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
+			"mout_aclk_isp1_266",
+			EN_IP_ISP1, 26, 0, 0),
+	GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
+			"mout_aclk_isp1_266",
+			EN_IP_ISP1, 25, 0, 0),
+	GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 24, 0, 0),
+	GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 23, 0, 0),
+	GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 22, 0, 0),
+	GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 21, 0, 0),
+	GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 14, 0, 0),
+	GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 11, 0, 0),
+	GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 10, 0, 0),
+	GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 9, 0, 0),
+	GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 8, 0, 0),
+	GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 7, 0, 0),
+	GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
+			"mout_aclk_isp1_266",
+			EN_IP_ISP1, 6, 0, 0),
+	GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
+			"mout_aclk_isp1_266",
+			EN_IP_ISP1, 5, 0, 0),
+	GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 4, 0, 0),
+	GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 3, 0, 0),
+	GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 2, 0, 0),
+	GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 1, 0, 0),
+
+	GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll",
+			EN_SCLK_ISP, 9, 0, 0),
+	GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll",
+			EN_SCLK_ISP, 8, 0, 0),
+	GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll",
+			EN_SCLK_ISP, 7, 0, 0),
+};
+
+/*
+ * List of Gate clocks for CMU_KFC
+*/
+struct samsung_gate_clock exynos5260_kfc_gate_clks[] __initdata = {
+};
+
+/*
+ * List of Gate clocks for CMU_MFC
+*/
+struct samsung_gate_clock exynos5260_mfc_gate_clks[] __initdata = {
+	GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user",
+			EN_IP_MFC, 1, 0, 0),
+
+	GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user",
+			EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0),
+	GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
+			EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0),
+};
+
+/*
+ * List of Gate clocks for CMU_MIF
+*/
+struct samsung_gate_clock exynos5260_mif_gate_clks[] __initdata = {
+	GATE(ID_NONE, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
+			EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
+	GATE(ID_NONE, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
+			EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(ID_NONE, "clk_monocnt", "dout_aclk_bus_100",
+			EN_IP_MIF_SECURE_MONOCNT, 22,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(ID_NONE, "clk_mif_rtc", "dout_aclk_bus_100",
+			EN_IP_MIF_SECURE_RTC_APBIF, 23,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(ID_NONE, "clk_drex1", "dout_aclk_mif_466",
+			EN_IP_MIF_SECURE_DREX1_TZ, 9,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(ID_NONE, "clk_drex0", "dout_aclk_mif_466",
+			EN_IP_MIF_SECURE_DREX0_TZ, 9,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(ID_NONE, "clk_intmem", "dout_aclk_bus_200",
+			EN_IP_MIF_SECURE_INTEMEM, 11,
+			CLK_IGNORE_UNUSED, 0),
+
+	GATE(ID_NONE, "sclk_lpddr3phy_wrap_u1", "dout_clkm_phy",
+			EN_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
+	GATE(ID_NONE, "sclk_lpddr3phy_wrap_u0", "dout_clkm_phy",
+			EN_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+/*
+ * List of Gate clocks for CMU_PERI
+*/
+struct samsung_gate_clock exynos5260_peri_gate_clks[] __initdata = {
+	GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66",
+		EN_IP_PERI0, 25, 0, 0),
+	GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66",
+		EN_IP_PERI0, 24, 0, 0),
+	GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66",
+		EN_IP_PERI0, 23, 0, 0),
+	GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66",
+		EN_IP_PERI0, 22, 0, 0),
+	GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66",
+		EN_IP_PERI0, 21, 0, 0),
+	GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66",
+		EN_IP_PERI0, 20, 0, 0),
+	GATE(PERI_CLK_PCM, "clk_pcm", "dout_aclk_peri_66",
+		EN_IP_PERI0, 18, 0, 0),
+	GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66",
+		EN_IP_PERI0, 17, 0, 0),
+	GATE(PERI_CLK_I2S, "clk_i2s", "dout_aclk_peri_66",
+		EN_IP_PERI0, 16, 0, 0),
+	GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66",
+		EN_IP_PERI0, 15, 0, 0),
+	GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66",
+		EN_IP_PERI0, 14, 0, 0),
+	GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66",
+		EN_IP_PERI0, 13, 0, 0),
+	GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66",
+		EN_IP_PERI0, 12, 0, 0),
+	GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66",
+		EN_IP_PERI0, 11, 0, 0),
+	GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66",
+		EN_IP_PERI0, 10, 0, 0),
+	GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66",
+		EN_IP_PERI0, 9, 0, 0),
+	GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66",
+		EN_IP_PERI0, 8, 0, 0),
+	GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66",
+		EN_IP_PERI0, 7, 0, 0),
+	GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66",
+		EN_IP_PERI0, 6, 0, 0),
+	GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66",
+		EN_IP_PERI0, 5, 0, 0),
+	GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66",
+		EN_IP_PERI0, 1, 0, 0),
+
+	GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66",
+		EN_IP_PERI2, 21, 0, 0),
+	GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66",
+		EN_IP_PERI2, 20, 0, 0),
+	GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66",
+		EN_IP_PERI2, 19, 0, 0),
+	GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66",
+		EN_IP_PERI2, 18, 0, 0),
+	GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66",
+		EN_IP_PERI2, 14, 0, 0),
+	GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66",
+		EN_IP_PERI2, 13, 0, 0),
+	GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66",
+		EN_IP_PERI2, 12, 0, 0),
+	GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66",
+		EN_IP_PERI2, 11, 0, 0),
+	GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66",
+		EN_IP_PERI2, 10, 0, 0),
+	GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66",
+		EN_IP_PERI2, 9, 0, 0),
+	GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66",
+		EN_IP_PERI2, 8, 0, 0),
+	GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66",
+		EN_IP_PERI2, 7, 0, 0),
+	GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66",
+		EN_IP_PERI2, 6, 0, 0),
+	GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66",
+		EN_IP_PERI2, 3, 0, 0),
+	GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66",
+		EN_IP_PERI2, 0, 0, 0),
+
+	GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_CHIPID, 2, 0, 0),
+	GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0),
+	GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0),
+	GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_SECKEY, 5, 0, 0),
+	GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0),
+
+	GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 20, 0, 0),
+	GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 19, 0, 0),
+	GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 18, 0, 0),
+	GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 17, 0, 0),
+	GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 16, 0, 0),
+	GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 15, 0, 0),
+	GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 14, 0, 0),
+	GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
+	GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
+	GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
+	GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
+
+	GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
+			EN_SCLK_PERI, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
+			EN_SCLK_PERI, 11, CLK_IGNORE_UNUSED, 0),
+	GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
+			EN_SCLK_PERI, 10, CLK_IGNORE_UNUSED, 0),
+	GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
+			EN_SCLK_PERI, 9, 0, 0),
+	GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b",
+			EN_SCLK_PERI, 8, 0, 0),
+	GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b",
+			EN_SCLK_PERI, 7, 0, 0),
+	GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b",
+			EN_SCLK_PERI, 2, 0, 0),
+	GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1, 0, 0),
+	GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0, 0, 0),
+};
+
+/*
+ * List of Gate clocks for CMU_TOP
+*/
+struct samsung_gate_clock exynos5260_top_gate_clks[] __initdata = {
+	GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel",
+			EN_ACLK_TOP, 10, 0, 0),
+	GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin",
+			"dout_sclk_fsys_mmc2_sdclkin_b",
+			EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0),
+	GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
+			"dout_sclk_fsys_mmc1_sdclkin_b",
+			EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT,
+			0),
+	GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
+			"dout_sclk_fsys_mmc0_sdclkin_b",
+			EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
+};
+
+/*
+* Applicable for all 2550 Type PLLS for Exynos5260, listed below
+* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL,
+* BUS_PLL, MEDIA_PLL, G3D_PLL.
+*/
+static const struct samsung_pll_rate_table exynos5260_pll2550_24mhz_tbl[] = {
+	PLL_35XX_RATE(1700000000, 425, 6, 0),
+	PLL_35XX_RATE(1600000000, 200, 3, 0),
+	PLL_35XX_RATE(1500000000, 250, 4, 0),
+	PLL_35XX_RATE(1400000000, 175, 3, 0),
+	PLL_35XX_RATE(1300000000, 325, 6, 0),
+	PLL_35XX_RATE(1200000000, 400, 4, 1),
+	PLL_35XX_RATE(1100000000, 275, 3, 1),
+	PLL_35XX_RATE(1000000000, 250, 3, 1),
+	PLL_35XX_RATE(933000000, 311, 4, 1),
+	PLL_35XX_RATE(900000000, 300, 4, 1),
+	PLL_35XX_RATE(800000000, 200, 3, 1),
+	PLL_35XX_RATE(733000000, 733, 12, 1),
+	PLL_35XX_RATE(700000000, 175, 3, 1),
+	PLL_35XX_RATE(667000000, 667, 12, 1),
+	PLL_35XX_RATE(633000000, 211, 4, 1),
+	PLL_35XX_RATE(620000000, 310, 3, 2),
+	PLL_35XX_RATE(600000000, 400, 4, 2),
+	PLL_35XX_RATE(543000000, 362, 4, 2),
+	PLL_35XX_RATE(533000000, 533, 6, 2),
+	PLL_35XX_RATE(500000000, 250, 3, 2),
+	PLL_35XX_RATE(450000000, 300, 4, 2),
+	PLL_35XX_RATE(400000000, 200, 3, 2),
+	PLL_35XX_RATE(350000000, 175, 3, 2),
+	PLL_35XX_RATE(300000000, 400, 4, 3),
+	PLL_35XX_RATE(266000000, 266, 3, 3),
+	PLL_35XX_RATE(200000000, 200, 3, 3),
+	PLL_35XX_RATE(160000000, 160, 3, 3),
+};
+
+/*
+* Applicable for 2650 Type PLL for AUD_PLL.
+*/
+static const struct samsung_pll_rate_table exynos5260_pll2650_24mhz_tbl[] = {
+	PLL_36XX_RATE(1600000000, 200, 3, 0, 0),
+	PLL_36XX_RATE(1200000000, 100, 2, 0, 0),
+	PLL_36XX_RATE(1000000000, 250, 3, 1, 0),
+	PLL_36XX_RATE(800000000, 200, 3, 1, 0),
+	PLL_36XX_RATE(600000000, 100, 2, 1, 0),
+	PLL_36XX_RATE(532000000, 266, 3, 2, 0),
+	PLL_36XX_RATE(480000000, 160, 2, 2, 0),
+	PLL_36XX_RATE(432000000, 144, 2, 2, 0),
+	PLL_36XX_RATE(400000000, 200, 3, 2, 0),
+	PLL_36XX_RATE(394216000, 459, 7, 2, 49282),
+	PLL_36XX_RATE(333000000, 111, 2, 2, 0),
+	PLL_36XX_RATE(300000000, 100, 2, 2, 0),
+	PLL_36XX_RATE(266000000, 266, 3, 3, 0),
+	PLL_36XX_RATE(200000000, 200, 3, 3, 0),
+	PLL_36XX_RATE(166000000, 166, 3, 3, 0),
+	PLL_36XX_RATE(133000000, 266, 3, 4, 0),
+	PLL_36XX_RATE(100000000, 200, 3, 4, 0),
+	PLL_36XX_RATE(66000000, 176, 2, 5, 0),
+};
+
+static struct of_device_id cmu_subtype_match_table[] = {
+	{
+		.compatible = "exynos5260-cmu-top",
+		.data	= (void	*)CMU_TYPE_TOP,
+	}, {
+		.compatible = "exynos5260-cmu-peri",
+		.data	= (void	*)CMU_TYPE_PERI,
+	}, {
+		.compatible = "exynos5260-cmu-egl",
+		.data	= (void	*)CMU_TYPE_EGL,
+	}, {
+		.compatible = "exynos5260-cmu-kfc",
+		.data	= (void	*)CMU_TYPE_KFC,
+	}, {
+		.compatible = "exynos5260-cmu-g2d",
+		.data	= (void	*)CMU_TYPE_G2D,
+	}, {
+		.compatible = "exynos5260-cmu-mif",
+		.data	= (void	*)CMU_TYPE_MIF,
+	}, {
+		.compatible = "exynos5260-cmu-mfc",
+		.data	= (void	*)CMU_TYPE_MFC,
+	}, {
+		.compatible = "exynos5260-cmu-g3d",
+		.data	= (void	*)CMU_TYPE_G3D,
+	}, {
+		.compatible = "exynos5260-cmu-fsys",
+		.data	= (void	*)CMU_TYPE_FSYS,
+	}, {
+		.compatible = "exynos5260-cmu-aud",
+		.data	= (void	*)CMU_TYPE_AUD,
+	}, {
+		.compatible = "exynos5260-cmu-isp",
+		.data	= (void	*)CMU_TYPE_ISP,
+	}, {
+		.compatible = "exynos5260-cmu-gscl",
+		.data	= (void	*)CMU_TYPE_GSCL,
+	}, {
+		.compatible = "exynos5260-cmu-disp",
+		.data	= (void	*)CMU_TYPE_DISP,
+	}, {
+		/* end node */
+	}
+};
+
+static struct samsung_pll_clock exynos5260_top_pll_clks[] __initdata = {
+	PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
+		DISP_PLL_LOCK, DISP_PLL_CON0,
+		exynos5260_pll2550_24mhz_tbl),
+	PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
+		AUD_PLL_LOCK, AUD_PLL_CON0,
+		exynos5260_pll2650_24mhz_tbl),
+};
+
+static struct samsung_pll_clock exynos5260_egl_pll_clks[] __initdata = {
+	PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
+		EGL_PLL_LOCK, EGL_PLL_CON0,
+		exynos5260_pll2550_24mhz_tbl),
+};
+
+static struct samsung_pll_clock exynos5260_kfc_pll_clks[] __initdata = {
+	PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
+		KFC_PLL_LOCK, KFC_PLL_CON0,
+		exynos5260_pll2550_24mhz_tbl),
+};
+
+static struct samsung_pll_clock exynos5260_mif_pll_clks[] __initdata = {
+	PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
+		MEM_PLL_LOCK, MEM_PLL_CON0,
+		exynos5260_pll2550_24mhz_tbl),
+	PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
+		BUS_PLL_LOCK, BUS_PLL_CON0,
+		exynos5260_pll2550_24mhz_tbl),
+	PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
+		MEDIA_PLL_LOCK, MEDIA_PLL_CON0,
+		exynos5260_pll2550_24mhz_tbl),
+};
+
+static struct samsung_pll_clock exynos5260_g3d_pll_clks[] __initdata = {
+	PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
+		G3D_PLL_LOCK, G3D_PLL_CON0,
+		exynos5260_pll2550_24mhz_tbl),
+};
+
+void __init exynos5260_clk_init(struct device_node *np)
+{
+	void __iomem *reg_base;
+	const struct of_device_id *match;
+	static unsigned long *rdump;
+	struct samsung_clk_provider *ctx;
+	unsigned long nr_rdump;
+
+	if (!np)
+		panic("%s: unable to determine soc\n", __func__);
+
+	match = of_match_node(cmu_subtype_match_table, np);
+
+	if (!match)
+		panic("%s: cmu type (%s) is not supported.\n", __func__,
+		np->name);
+
+	reg_base = of_iomap(np, 0);
+	if (!reg_base)
+		panic("%s: failed to map registers\n", __func__);
+
+	if ((int)match->data == CMU_TYPE_AUD) {
+		rdump = exynos5260_aud_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_aud_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, AUD_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_mux(ctx, exynos5260_aud_mux_clks,
+			ARRAY_SIZE(exynos5260_aud_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_aud_div_clks,
+			ARRAY_SIZE(exynos5260_aud_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_aud_gate_clks,
+			ARRAY_SIZE(exynos5260_aud_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_DISP) {
+		rdump = exynos5260_disp_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_disp_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, DISP_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_mux(ctx, exynos5260_disp_mux_clks,
+			ARRAY_SIZE(exynos5260_disp_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_disp_div_clks,
+			ARRAY_SIZE(exynos5260_disp_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_disp_gate_clks,
+			ARRAY_SIZE(exynos5260_disp_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_EGL) {
+		rdump = exynos5260_egl_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_egl_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, EGL_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_pll(ctx, exynos5260_egl_pll_clks,
+			ARRAY_SIZE(exynos5260_egl_pll_clks),
+			reg_base);
+
+		samsung_clk_register_mux(ctx, exynos5260_egl_mux_clks,
+			ARRAY_SIZE(exynos5260_egl_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_egl_div_clks,
+			ARRAY_SIZE(exynos5260_egl_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_egl_gate_clks,
+			ARRAY_SIZE(exynos5260_egl_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_FSYS) {
+		rdump = exynos5260_fsys_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_fsys_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, FSYS_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_mux(ctx, exynos5260_fsys_mux_clks,
+			ARRAY_SIZE(exynos5260_fsys_mux_clks));
+		samsung_clk_register_gate(ctx, exynos5260_fsys_gate_clks,
+			ARRAY_SIZE(exynos5260_fsys_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_G2D) {
+		rdump = exynos5260_g2d_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_g2d_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, G2D_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_mux(ctx, exynos5260_g2d_mux_clks,
+			ARRAY_SIZE(exynos5260_g2d_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_g2d_div_clks,
+			ARRAY_SIZE(exynos5260_g2d_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_g2d_gate_clks,
+			ARRAY_SIZE(exynos5260_g2d_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_G3D) {
+		rdump = exynos5260_g3d_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_g3d_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, G3D_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+		samsung_clk_register_pll(ctx, exynos5260_g3d_pll_clks,
+			ARRAY_SIZE(exynos5260_g3d_pll_clks),
+			reg_base);
+		samsung_clk_register_mux(ctx, exynos5260_g3d_mux_clks,
+			ARRAY_SIZE(exynos5260_g3d_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_g3d_div_clks,
+			ARRAY_SIZE(exynos5260_g3d_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_g3d_gate_clks,
+			ARRAY_SIZE(exynos5260_g3d_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_GSCL) {
+		rdump = exynos5260_gscl_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_gscl_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, GSCL_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_mux(ctx, exynos5260_gscl_mux_clks,
+			ARRAY_SIZE(exynos5260_gscl_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_gscl_div_clks,
+			ARRAY_SIZE(exynos5260_gscl_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_gscl_gate_clks,
+			ARRAY_SIZE(exynos5260_gscl_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_ISP) {
+		rdump = exynos5260_isp_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_isp_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, ISP_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_mux(ctx, exynos5260_isp_mux_clks,
+			ARRAY_SIZE(exynos5260_isp_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_isp_div_clks,
+			ARRAY_SIZE(exynos5260_isp_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_isp_gate_clks,
+			ARRAY_SIZE(exynos5260_isp_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_KFC) {
+		rdump = exynos5260_kfc_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_kfc_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, KFC_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_pll(ctx, exynos5260_kfc_pll_clks,
+			ARRAY_SIZE(exynos5260_kfc_pll_clks),
+			reg_base);
+		samsung_clk_register_mux(ctx, exynos5260_kfc_mux_clks,
+			ARRAY_SIZE(exynos5260_kfc_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_kfc_div_clks,
+			ARRAY_SIZE(exynos5260_kfc_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_kfc_gate_clks,
+			ARRAY_SIZE(exynos5260_kfc_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_MFC) {
+		rdump = exynos5260_mfc_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_mfc_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, MFC_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_mux(ctx, exynos5260_mfc_mux_clks,
+			ARRAY_SIZE(exynos5260_mfc_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_mfc_div_clks,
+			ARRAY_SIZE(exynos5260_mfc_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_mfc_gate_clks,
+			ARRAY_SIZE(exynos5260_mfc_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_MIF) {
+		rdump = exynos5260_mif_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_mif_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, MIF_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_pll(ctx, exynos5260_mif_pll_clks,
+			ARRAY_SIZE(exynos5260_mif_pll_clks),
+			reg_base);
+		samsung_clk_register_mux(ctx, exynos5260_mif_mux_clks,
+			ARRAY_SIZE(exynos5260_mif_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_mif_div_clks,
+			ARRAY_SIZE(exynos5260_mif_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_mif_gate_clks,
+			ARRAY_SIZE(exynos5260_mif_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_PERI) {
+		rdump = exynos5260_peri_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_peri_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, PERI_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_mux(ctx, exynos5260_peri_mux_clks,
+			ARRAY_SIZE(exynos5260_peri_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_peri_div_clks,
+			ARRAY_SIZE(exynos5260_peri_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_peri_gate_clks,
+			ARRAY_SIZE(exynos5260_peri_gate_clks));
+
+	} else if ((int)match->data == CMU_TYPE_TOP) {
+		rdump = exynos5260_top_clk_regs;
+		nr_rdump = ARRAY_SIZE(exynos5260_top_clk_regs);
+
+		ctx = samsung_clk_init(np, reg_base, TOP_NR_CLK);
+		if (!ctx)
+			panic("%s: unable to alllocate ctx\n", __func__);
+
+		samsung_clk_register_fixed_rate(ctx,
+			exynos5260_fixed_rate_ext_clks,
+			ARRAY_SIZE(
+			exynos5260_fixed_rate_ext_clks));
+
+		samsung_clk_register_fixed_rate(ctx,
+			exynos5260_fixed_rate_clks,
+			ARRAY_SIZE(exynos5260_fixed_rate_clks));
+
+		samsung_clk_register_pll(ctx, exynos5260_top_pll_clks,
+			ARRAY_SIZE(exynos5260_top_pll_clks),
+			reg_base);
+
+		samsung_clk_register_mux(ctx, exynos5260_top_mux_clks,
+			ARRAY_SIZE(exynos5260_top_mux_clks));
+		samsung_clk_register_div(ctx, exynos5260_top_div_clks,
+			ARRAY_SIZE(exynos5260_top_div_clks));
+		samsung_clk_register_gate(ctx, exynos5260_top_gate_clks,
+			ARRAY_SIZE(exynos5260_top_gate_clks));
+		} else {
+			panic("%s: invalid cmu sub-type.\n", __func__);
+	};
+
+	exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump);
+}
+
+CLK_OF_DECLARE(exynos5260_clk, "samsung,exynos5260-clock", exynos5260_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5260.h b/drivers/clk/samsung/clk-exynos5260.h
new file mode 100644
index 0000000..32063d1
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5260.h
@@ -0,0 +1,496 @@
+#ifndef __CLK_EXYNOS5260_H
+#define __CLK_EXYNOS5260_H
+
+#define CMU_TYPE_AUD	1
+#define CMU_TYPE_DISP	2
+#define CMU_TYPE_EGL	3
+#define CMU_TYPE_FSYS	4
+#define CMU_TYPE_G2D	5
+#define CMU_TYPE_G3D	6
+#define CMU_TYPE_GSCL	7
+#define CMU_TYPE_ISP	8
+#define CMU_TYPE_KFC	9
+#define CMU_TYPE_MFC	10
+#define CMU_TYPE_MIF	11
+#define CMU_TYPE_PERI	12
+#define CMU_TYPE_TOP	13
+
+#define CMU_TYPE_ALL	14
+
+/*
+*Base address for different CMUs
+*TODO: All Bases should be removed at earliest.
+*/
+#define CMU_AUD_BASE	0x128C0000
+#define CMU_DISP_BASE	0x14550000
+#define CMU_EGL_BASE	0x10600000
+#define CMU_FSYS_BASE	0x122E0000
+#define CMU_G2D_BASE	0x10A00000
+#define CMU_G3D_BASE	0x11830000
+#define CMU_GSCL_BASE	0x13F00000
+#define CMU_ISP_BASE	0x133C0000
+#define CMU_KFC_BASE	0x10700000
+#define CMU_MFC_BASE	0x11090000
+#define CMU_MIF_BASE	0x10CE0000
+#define CMU_PERI_BASE	0x10200000
+#define CMU_TOP_BASE	0x10010000
+
+#define AUD_REG(x)		(x)
+#define DISP_REG(x)		(x)
+#define EGL_REG(x)		(x)
+#define FSYS_REG(x)		(x)
+#define G2D_REG(x)		(x)
+#define G3D_REG(x)		(x)
+#define GSCL_REG(x)		(x)
+#define ISP_REG(x)		(x)
+#define KFC_REG(x)		(x)
+#define MFC_REG(x)		(x)
+#define MIF_REG(x)		(x)
+#define PERI_REG(x)		(x)
+#define TOP_REG(x)		(x)
+
+/*
+*Registers for CMU_AUD
+*/
+#define MUX_SEL_AUD		AUD_REG(0x0200)
+#define MUX_ENABLE_AUD		AUD_REG(0x0300)
+#define MUX_STAT_AUD		AUD_REG(0x0400)
+#define MUX_IGNORE_AUD		AUD_REG(0x0500)
+#define DIV_AUD0		AUD_REG(0x0600)
+#define DIV_AUD1		AUD_REG(0x0604)
+#define DIV_STAT_AUD0		AUD_REG(0x0700)
+#define DIV_STAT_AUD1		AUD_REG(0x0704)
+#define EN_ACLK_AUD		AUD_REG(0x0800)
+#define EN_PCLK_AUD		AUD_REG(0x0900)
+#define EN_SCLK_AUD		AUD_REG(0x0a00)
+#define EN_IP_AUD		AUD_REG(0x0b00)
+
+/*
+*Registers for CMU_DISP
+*/
+#define MUX_SEL_DISP0		DISP_REG(0x0200)
+#define MUX_SEL_DISP1		DISP_REG(0x0204)
+#define MUX_SEL_DISP2		DISP_REG(0x0208)
+#define MUX_SEL_DISP3		DISP_REG(0x020C)
+#define MUX_SEL_DISP4		DISP_REG(0x0210)
+#define MUX_ENABLE_DISP0	DISP_REG(0x0300)
+#define MUX_ENABLE_DISP1	DISP_REG(0x0304)
+#define MUX_ENABLE_DISP2	DISP_REG(0x0308)
+#define MUX_ENABLE_DISP3	DISP_REG(0x030c)
+#define MUX_ENABLE_DISP4	DISP_REG(0x0310)
+#define MUX_STAT_DISP0		DISP_REG(0x0400)
+#define MUX_STAT_DISP1		DISP_REG(0x0404)
+#define MUX_STAT_DISP2		DISP_REG(0x0408)
+#define MUX_STAT_DISP3		DISP_REG(0x040c)
+#define MUX_STAT_DISP4		DISP_REG(0x0410)
+#define MUX_IGNORE_DISP0	DISP_REG(0x0500)
+#define MUX_IGNORE_DISP1	DISP_REG(0x0504)
+#define MUX_IGNORE_DISP2	DISP_REG(0x0508)
+#define MUX_IGNORE_DISP3	DISP_REG(0x050c)
+#define MUX_IGNORE_DISP4	DISP_REG(0x0510)
+#define DIV_DISP		DISP_REG(0x0600)
+#define DIV_STAT_DISP		DISP_REG(0x0700)
+#define EN_ACLK_DISP		DISP_REG(0x0800)
+#define EN_PCLK_DISP		DISP_REG(0x0900)
+#define EN_SCLK_DISP0		DISP_REG(0x0a00)
+#define EN_SCLK_DISP1		DISP_REG(0x0a04)
+#define EN_IP_DISP		DISP_REG(0x0b00)
+#define EN_IP_DISP_BUS		DISP_REG(0x0b04)
+
+
+/*
+*Registers for CMU_EGL
+*/
+#define EGL_PLL_LOCK		EGL_REG(0x0000)
+#define EGL_DPLL_LOCK		EGL_REG(0x0004)
+#define EGL_PLL_CON0		EGL_REG(0x0100)
+#define EGL_PLL_CON1		EGL_REG(0x0104)
+#define EGL_PLL_FREQ_DET	EGL_REG(0x010c)
+#define EGL_DPLL_CON0		EGL_REG(0x0110)
+#define EGL_DPLL_CON1		EGL_REG(0x0114)
+#define EGL_DPLL_FREQ_DET	EGL_REG(0x011c)
+#define MUX_SEL_EGL		EGL_REG(0x0200)
+#define MUX_ENABLE_EGL		EGL_REG(0x0300)
+#define MUX_STAT_EGL		EGL_REG(0x0400)
+#define DIV_EGL			EGL_REG(0x0600)
+#define DIV_EGL_PLL_FDET	EGL_REG(0x0604)
+#define DIV_STAT_EGL		EGL_REG(0x0700)
+#define DIV_STAT_EGL_PLL_FDET	EGL_REG(0x0704)
+#define EN_ACLK_EGL		EGL_REG(0x0800)
+#define EN_PCLK_EGL		EGL_REG(0x0900)
+#define EN_SCLK_EGL		EGL_REG(0x0a00)
+#define EN_IP_EGL		EGL_REG(0x0b00)
+#define CLKOUT_CMU_EGL		EGL_REG(0x0c00)
+#define CLKOUT_CMU_EGL_DIV_STAT	EGL_REG(0x0c04)
+#define ARMCLK_STOPCTRL		EGL_REG(0x1000)
+#define EAGLE_EMA_CTRL		EGL_REG(0x1008)
+#define EAGLE_EMA_STATUS	EGL_REG(0x100c)
+#define PWR_CTRL		EGL_REG(0x1020)
+#define PWR_CTRL2		EGL_REG(0x1024)
+#define CLKSTOP_CTRL		EGL_REG(0x1028)
+#define INTR_SPREAD_EN		EGL_REG(0x1080)
+#define INTR_SPREAD_USE_STANDBYWFI	EGL_REG(0x1084)
+#define INTR_SPREAD_BLOCKING_DURATION	EGL_REG(0x1088)
+#define CMU_EGL_SPARE0		EGL_REG(0x2000)
+#define CMU_EGL_SPARE1		EGL_REG(0x2004)
+#define CMU_EGL_SPARE2		EGL_REG(0x2008)
+#define CMU_EGL_SPARE3		EGL_REG(0x200c)
+#define CMU_EGL_SPARE4		EGL_REG(0x2010)
+
+/*
+*Registers for CMU_FSYS
+*/
+
+#define MUX_SEL_FSYS0		FSYS_REG(0x0200)
+#define MUX_SEL_FSYS1		FSYS_REG(0x0204)
+#define MUX_ENABLE_FSYS0	FSYS_REG(0x0300)
+#define MUX_ENABLE_FSYS1	FSYS_REG(0x0304)
+#define MUX_STAT_FSYS0		FSYS_REG(0x0400)
+#define MUX_STAT_FSYS1		FSYS_REG(0x0404)
+#define MUX_IGNORE_FSYS0	FSYS_REG(0x0500)
+#define MUX_IGNORE_FSYS1	FSYS_REG(0x0504)
+#define EN_ACLK_FSYS		FSYS_REG(0x0800)
+#define EN_ACLK_FSYS_SECURE_RTIC		FSYS_REG(0x0804)
+#define EN_ACLK_FSYS_SECURE_SMMU_RTIC		FSYS_REG(0x0808)
+#define EN_PCLK_FSYS		FSYS_REG(0x0900)
+#define EN_SCLK_FSYS		FSYS_REG(0x0a00)
+#define EN_IP_FSYS		FSYS_REG(0x0b00)
+#define EN_IP_FSYS_SECURE_RTIC	FSYS_REG(0x0b04)
+#define EN_IP_FSYS_SECURE_SMMU_RTIC	FSYS_REG(0x0b08)
+
+/*
+*Registers for CMU_G2D
+*/
+
+#define MUX_SEL_G2D		G2D_REG(0x0200)
+#define MUX_ENABLE_G2D		G2D_REG(0x0300)
+#define MUX_STAT_G2D		G2D_REG(0x0400)
+#define DIV_G2D			G2D_REG(0x0600)
+#define DIV_STAT_G2D		G2D_REG(0x0700)
+#define EN_ACLK_G2D		G2D_REG(0x0800)
+#define EN_ACLK_G2D_SECURE_SSS			G2D_REG(0x0804)
+#define EN_ACLK_G2D_SECURE_SLIM_SSS		G2D_REG(0x0808)
+#define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS	G2D_REG(0x080c)
+#define EN_ACLK_G2D_SECURE_SMMU_SSS		G2D_REG(0x0810)
+#define EN_ACLK_G2D_SECURE_SMMU_MDMA		G2D_REG(0x0814)
+#define EN_ACLK_G2D_SECURE_SMMU_G2D		G2D_REG(0x0818)
+#define EN_PCLK_G2D				G2D_REG(0x0900)
+#define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS	G2D_REG(0x0904)
+#define EN_PCLK_G2D_SECURE_SMMU_SSS		G2D_REG(0x0908)
+#define EN_PCLK_G2D_SECURE_SMMU_MDMA		G2D_REG(0x090c)
+#define EN_PCLK_G2D_SECURE_SMMU_G2D		G2D_REG(0x0910)
+#define EN_IP_G2D				G2D_REG(0x0b00)
+#define EN_IP_G2D_SECURE_SSS			G2D_REG(0x0b04)
+#define EN_IP_G2D_SECURE_SLIM_SSS		G2D_REG(0x0b08)
+#define EN_IP_G2D_SECURE_SMMU_SLIM_SSS		G2D_REG(0x0b0c)
+#define EN_IP_G2D_SECURE_SMMU_SSS		G2D_REG(0x0b10)
+#define EN_IP_G2D_SECURE_SMMU_MDMA		G2D_REG(0x0b14)
+#define EN_IP_G2D_SECURE_SMMU_G2D		G2D_REG(0x0b18)
+
+/*
+*Registers for CMU_G3D
+*/
+
+#define G3D_PLL_LOCK		G3D_REG(0x0000)
+#define G3D_PLL_CON0		G3D_REG(0x0100)
+#define G3D_PLL_CON1		G3D_REG(0x0104)
+#define G3D_PLL_FDET		G3D_REG(0x010c)
+#define MUX_SEL_G3D		G3D_REG(0x0200)
+#define MUX_EN_G3D		G3D_REG(0x0300)
+#define MUX_STAT_G3D		G3D_REG(0x0400)
+#define MUX_IGNORE_G3D		G3D_REG(0x0500)
+#define DIV_G3D			G3D_REG(0x0600)
+#define DIV_G3D_PLL_FDET	G3D_REG(0x0604)
+#define DIV_STAT_G3D		G3D_REG(0x0700)
+#define DIV_STAT_G3D_PLL_FDET	G3D_REG(0x0704)
+#define EN_ACLK_G3D		G3D_REG(0x0800)
+#define EN_PCLK_G3D		G3D_REG(0x0900)
+#define EN_SCLK_G3D		G3D_REG(0x0a00)
+#define EN_IP_G3D		G3D_REG(0x0b00)
+#define CLKOUT_CMU_G3D		G3D_REG(0x0c00)
+#define CLKOUT_CMU_G3D_DIV_STAT		G3D_REG(0x0c04)
+#define G3DCLK_STOPCTRL		G3D_REG(0x1000)
+#define G3D_EMA_CTRL		G3D_REG(0x1008)
+#define G3D_EMA_STATUS		G3D_REG(0x100c)
+
+/*
+*Registers for CMU_GSCL
+*/
+
+#define MUX_SEL_GSCL		GSCL_REG(0x0200)
+#define MUX_EN_GSCL		GSCL_REG(0x0300)
+#define MUX_STAT_GSCL		GSCL_REG(0x0400)
+#define MUX_IGNORE_GSCL		GSCL_REG(0x0500)
+#define DIV_GSCL		GSCL_REG(0x0600)
+#define DIV_STAT_GSCL		GSCL_REG(0x0700)
+#define EN_ACLK_GSCL		GSCL_REG(0x0800)
+#define EN_ACLK_GSCL_FIMC	GSCL_REG(0x0804)
+#define EN_ACLK_GSCL_SECURE_SMMU_GSCL0		GSCL_REG(0x0808)
+#define EN_ACLK_GSCL_SECURE_SMMU_GSCL1		GSCL_REG(0x080c)
+#define EN_ACLK_GSCL_SECURE_SMMU_MSCL0		GSCL_REG(0x0810)
+#define EN_ACLK_GSCL_SECURE_SMMU_MSCL1		GSCL_REG(0x0814)
+#define EN_PCLK_GSCL				GSCL_REG(0x0900)
+#define EN_PCLK_GSCL_FIMC			GSCL_REG(0x0904)
+#define EN_PCLK_GSCL_SECURE_SMMU_GSCL0		GSCL_REG(0x0908)
+#define EN_PCLK_GSCL_SECURE_SMMU_GSCL1		GSCL_REG(0x090c)
+#define EN_PCLK_GSCL_SECURE_SMMU_MSCL0		GSCL_REG(0x0910)
+#define EN_PCLK_GSCL_SECURE_SMMU_MSCL1		GSCL_REG(0x0914)
+#define EN_SCLK_GSCL		GSCL_REG(0x0a00)
+#define EN_SCLK_GSCL_FIMC	GSCL_REG(0x0a04)
+#define EN_IP_GSCL		GSCL_REG(0x0b00)
+#define EN_IP_GSCL_FIMC		GSCL_REG(0x0b04)
+#define EN_IP_GSCL_SECURE_SMMU_GSCL0		GSCL_REG(0x0b08)
+#define EN_IP_GSCL_SECURE_SMMU_GSCL1		GSCL_REG(0x0b0c)
+#define EN_IP_GSCL_SECURE_SMMU_MSCL0		GSCL_REG(0x0b10)
+#define EN_IP_GSCL_SECURE_SMMU_MSCL1		GSCL_REG(0x0b14)
+
+/*
+*Registers for CMU_ISP
+*/
+#define MUX_SEL_ISP0		ISP_REG(0x0200)
+#define MUX_SEL_ISP1		ISP_REG(0x0204)
+#define MUX_ENABLE_ISP0		ISP_REG(0x0300)
+#define MUX_ENABLE_ISP1		ISP_REG(0x0304)
+#define MUX_STAT_ISP0		ISP_REG(0x0400)
+#define MUX_STAT_ISP1		ISP_REG(0x0404)
+#define MUX_IGNORE_ISP0		ISP_REG(0x0500)
+#define MUX_IGNORE_ISP1		ISP_REG(0x0504)
+#define DIV_ISP			ISP_REG(0x0600)
+#define DIV_STAT_ISP		ISP_REG(0x0700)
+#define EN_ACLK_ISP0		ISP_REG(0x0800)
+#define EN_ACLK_ISP1		ISP_REG(0x0804)
+#define EN_PCLK_ISP0		ISP_REG(0x0900)
+#define EN_PCLK_ISP1		ISP_REG(0x0904)
+#define EN_SCLK_ISP		ISP_REG(0x0a00)
+#define EN_IP_ISP0		ISP_REG(0x0b00)
+#define EN_IP_ISP1		ISP_REG(0x0b04)
+
+/*
+*Registers for CMU_KFC
+*/
+#define KFC_PLL_LOCK		KFC_REG(0x0000)
+#define KFC_PLL_CON0		KFC_REG(0x0100)
+#define KFC_PLL_CON1		KFC_REG(0x0104)
+#define KFC_PLL_FDET		KFC_REG(0x010c)
+#define MUX_SEL_KFC0		KFC_REG(0x0200)
+#define MUX_SEL_KFC2		KFC_REG(0x0208)
+#define MUX_ENABLE_KFC0		KFC_REG(0x0300)
+#define MUX_ENABLE_KFC2		KFC_REG(0x0308)
+#define MUX_STAT_KFC0		KFC_REG(0x0400)
+#define MUX_STAT_KFC2		KFC_REG(0x0408)
+#define DIV_KFC			KFC_REG(0x0600)
+#define DIV_KFC_PLL_FDET	KFC_REG(0x0604)
+#define DIV_STAT_KFC		KFC_REG(0x0700)
+#define DIV_STAT_KFC_PLL_FDET	KFC_REG(0x0704)
+#define EN_ACLK_KFC		KFC_REG(0x0800)
+#define EN_PCLK_KFC		KFC_REG(0x0900)
+#define EN_SCLK_KFC		KFC_REG(0x0a00)
+#define EN_IP_KFC		KFC_REG(0x0b00)
+#define CLKOUT_CMU_KFC		KFC_REG(0x0c00)
+#define CLKOUT_CMU_KFC_DIV_STAT		KFC_REG(0x0c04)
+#define ARMCLK_STOPCTRL_KFC	KFC_REG(0x1000)
+#define ARM_EMA_CTRL		KFC_REG(0x1008)
+#define ARM_EMA_STATUS		KFC_REG(0x100c)
+#define PWR_CTRL_KFC		KFC_REG(0x1020)
+#define PWR_CTRL2_KFC		KFC_REG(0x1024)
+#define CLKSTOP_CTRL_KFC	KFC_REG(0x1028)
+#define INTR_SPREAD_ENABLE_KFC			KFC_REG(0x1080)
+#define INTR_SPREAD_USE_STANDBYWFI_KFC		KFC_REG(0x1084)
+#define INTR_SPREAD_BLOCKING_DURATION_KFC	KFC_REG(0x1088)
+#define CMU_KFC_SPARE0		KFC_REG(0x2000)
+#define CMU_KFC_SPARE1		KFC_REG(0x2004)
+#define CMU_KFC_SPARE2		KFC_REG(0x2008)
+#define CMU_KFC_SPARE3		KFC_REG(0x200c)
+#define CMU_KFC_SPARE4		KFC_REG(0x2010)
+
+/*
+*Registers for CMU_MFC
+*/
+#define MUX_SEL_MFC		MFC_REG(0x0200)
+#define MUX_ENABLE_MFC		MFC_REG(0x0300)
+#define MUX_STAT_MFC		MFC_REG(0x0400)
+#define DIV_MFC			MFC_REG(0x0600)
+#define DIV_STAT_MFC		MFC_REG(0x0700)
+#define EN_ACLK_MFC		MFC_REG(0x0800)
+#define EN_ACLK_SECURE_SMMU2_MFC	MFC_REG(0x0804)
+#define EN_PCLK_MFC		MFC_REG(0x0900)
+#define EN_PCLK_SECURE_SMMU2_MFC	MFC_REG(0x0904)
+#define EN_IP_MFC			MFC_REG(0x0b00)
+#define EN_IP_MFC_SECURE_SMMU2_MFC		MFC_REG(0x0b04)
+
+/*
+*Registers for CMU_MIF
+*/
+#define MEM_PLL_LOCK		MIF_REG(0x0000)
+#define BUS_PLL_LOCK		MIF_REG(0x0004)
+#define MEDIA_PLL_LOCK		MIF_REG(0x0008)
+#define MEM_PLL_CON0		MIF_REG(0x0100)
+#define MEM_PLL_CON1		MIF_REG(0x0104)
+#define MEM_PLL_FDET		MIF_REG(0x010c)
+#define BUS_PLL_CON0		MIF_REG(0x0110)
+#define BUS_PLL_CON1		MIF_REG(0x0114)
+#define BUS_PLL_FDET		MIF_REG(0x011c)
+#define MEDIA_PLL_CON0		MIF_REG(0x0120)
+#define MEDIA_PLL_CON1		MIF_REG(0x0124)
+#define MEDIA_PLL_FDET		MIF_REG(0x012c)
+#define MUX_SEL_MIF		MIF_REG(0x0200)
+#define MUX_ENABLE_MIF		MIF_REG(0x0300)
+#define MUX_STAT_MIF		MIF_REG(0x0400)
+#define MUX_IGNORE_MIF		MIF_REG(0x0500)
+#define DIV_MIF			MIF_REG(0x0600)
+#define DIV_MIF_PLL_FDET	MIF_REG(0x0604)
+#define DIV_STAT_MIF		MIF_REG(0x0700)
+#define DIV_STAT_MIF_PLL_FDET	MIF_REG(0x0704)
+#define EN_ACLK_MIF		MIF_REG(0x0800)
+#define EN_ACLK_MIF_SECURE_DREX1_TZ	MIF_REG(0x0804)
+#define EN_ACLK_MIF_SECURE_DREX0_TZ	MIF_REG(0x0808)
+#define EN_ACLK_MIF_SECURE_INTMEM	MIF_REG(0x080c)
+#define EN_PCLK_MIF			MIF_REG(0x0900)
+#define EN_PCLK_MIF_SECURE_MONOCNT	MIF_REG(0x0904)
+#define EN_PCLK_MIF_SECURE_RTC_APBIF	MIF_REG(0x0908)
+#define EN_PCLK_MIF_SECURE_DREX1_TZ	MIF_REG(0x090c)
+#define EN_PCLK_MIF_SECURE_DREX0_TZ	MIF_REG(0x0910)
+#define EN_SCLK_MIF			MIF_REG(0x0a00)
+#define EN_IP_MIF			MIF_REG(0x0b00)
+#define EN_IP_MIF_SECURE_MONOCNT	MIF_REG(0x0b04)
+#define EN_IP_MIF_SECURE_RTC_APBIF	MIF_REG(0x0b08)
+#define EN_IP_MIF_SECURE_DREX1_TZ	MIF_REG(0x0b0c)
+#define EN_IP_MIF_SECURE_DREX0_TZ	MIF_REG(0x0b10)
+#define EN_IP_MIF_SECURE_INTEMEM	MIF_REG(0x0b14)
+#define CLKOUT_CMU_MIF_DIV_STAT		MIF_REG(0x0c04)
+#define DREX_FREQ_CTRL			MIF_REG(0x1000)
+#define PAUSE				MIF_REG(0x1004)
+#define DDRPHY_LOCK_CTRL		MIF_REG(0x1008)
+#define CLKOUT_CMU_MIF		MIF_REG(0xcb00)
+
+/*
+*Registers for CMU_PERI
+*/
+#define MUX_SEL_PERI		PERI_REG(0x0200)
+#define MUX_SEL_PERI1		PERI_REG(0x0204)
+#define MUX_ENABLE_PERI		PERI_REG(0x0300)
+#define MUX_ENABLE_PERI1	PERI_REG(0x0304)
+#define MUX_STAT_PERI		PERI_REG(0x0400)
+#define MUX_STAT_PERI1		PERI_REG(0x0404)
+#define MUX_IGNORE_PERI		PERI_REG(0x0500)
+#define MUX_IGNORE_PERI1	PERI_REG(0x0504)
+#define DIV_PERI		PERI_REG(0x0600)
+#define DIV_STAT_PERI		PERI_REG(0x0700)
+#define EN_PCLK_PERI0		PERI_REG(0x0800)
+#define EN_PCLK_PERI1		PERI_REG(0x0804)
+#define EN_PCLK_PERI2		PERI_REG(0x0808)
+#define EN_PCLK_PERI3		PERI_REG(0x080c)
+#define EN_PCLK_PERI_SECURE_CHIPID	PERI_REG(0x0810)
+#define EN_PCLK_PERI_SECURE_PROVKEY0	PERI_REG(0x0814)
+#define EN_PCLK_PERI_SECURE_PROVKEY1	PERI_REG(0x0818)
+#define EN_PCLK_PERI_SECURE_SECKEY	PERI_REG(0x081c)
+#define EN_PCLK_PERI_SECURE_ANTIRBKCNT	PERI_REG(0x0820)
+#define EN_PCLK_PERI_SECURE_TOP_RTC	PERI_REG(0x0824)
+#define EN_PCLK_PERI_SECURE_TZPC	PERI_REG(0x0828)
+#define EN_SCLK_PERI			PERI_REG(0x0a00)
+#define EN_SCLK_PERI_SECURE_TOP_RTC	PERI_REG(0x0a04)
+#define EN_IP_PERI0			PERI_REG(0x0b00)
+#define EN_IP_PERI1			PERI_REG(0x0b04)
+#define EN_IP_PERI2			PERI_REG(0x0b08)
+#define EN_IP_PERI_SECURE_CHIPID	PERI_REG(0x0b0c)
+#define EN_IP_PERI_SECURE_PROVKEY0	PERI_REG(0x0b10)
+#define EN_IP_PERI_SECURE_PROVKEY1	PERI_REG(0x0b14)
+#define EN_IP_PERI_SECURE_SECKEY	PERI_REG(0x0b18)
+#define EN_IP_PERI_SECURE_ANTIRBKCNT	PERI_REG(0x0b1c)
+#define EN_IP_PERI_SECURE_TOP_RTC	PERI_REG(0x0b20)
+#define EN_IP_PERI_SECURE_TZPC		PERI_REG(0x0b24)
+
+/*
+*Registers for CMU_TOP
+*/
+#define DISP_PLL_LOCK		TOP_REG(0x0000)
+#define AUD_PLL_LOCK		TOP_REG(0x0004)
+#define DISP_PLL_CON0		TOP_REG(0x0100)
+#define DISP_PLL_CON1		TOP_REG(0x0104)
+#define DISP_PLL_FDET		TOP_REG(0x0108)
+#define AUD_PLL_CON0		TOP_REG(0x0110)
+#define AUD_PLL_CON1		TOP_REG(0x0114)
+#define AUD_PLL_CON2		TOP_REG(0x0118)
+#define AUD_PLL_FDET		TOP_REG(0x011c)
+#define MUX_SEL_TOP_PLL0	TOP_REG(0x0200)
+#define MUX_SEL_TOP_MFC		TOP_REG(0x0204)
+#define MUX_SEL_TOP_G2D		TOP_REG(0x0208)
+#define MUX_SEL_TOP_GSCL	TOP_REG(0x020c)
+#define MUX_SEL_TOP_ISP10	TOP_REG(0x0214)
+#define MUX_SEL_TOP_ISP11	TOP_REG(0x0218)
+#define MUX_SEL_TOP_DISP0	TOP_REG(0x021c)
+#define MUX_SEL_TOP_DISP1	TOP_REG(0x0220)
+#define MUX_SEL_TOP_BUS		TOP_REG(0x0224)
+#define MUX_SEL_TOP_PERI0	TOP_REG(0x0228)
+#define MUX_SEL_TOP_PERI1	TOP_REG(0x022c)
+#define MUX_SEL_TOP_FSYS	TOP_REG(0x0230)
+#define MUX_ENABLE_TOP_PLL0	TOP_REG(0x0300)
+#define MUX_ENABLE_TOP_MFC	TOP_REG(0x0304)
+#define MUX_ENABLE_TOP_G2D	TOP_REG(0x0308)
+#define MUX_ENABLE_TOP_GSCL	TOP_REG(0x030c)
+#define MUX_ENABLE_TOP_ISP10	TOP_REG(0x0314)
+#define MUX_ENABLE_TOP_ISP11	TOP_REG(0x0318)
+#define MUX_ENABLE_TOP_DISP0	TOP_REG(0x031c)
+#define MUX_ENABLE_TOP_DISP1	TOP_REG(0x0320)
+#define MUX_ENABLE_TOP_BUS	TOP_REG(0x0324)
+#define MUX_ENABLE_TOP_PERI0	TOP_REG(0x0328)
+#define MUX_ENABLE_TOP_PERI1	TOP_REG(0x032c)
+#define MUX_ENABLE_TOP_FSYS	TOP_REG(0x0330)
+#define MUX_STAT_TOP_PLL0	TOP_REG(0x0400)
+#define MUX_STAT_TOP_MFC	TOP_REG(0x0404)
+#define MUX_STAT_TOP_G2D	TOP_REG(0x0408)
+#define MUX_STAT_TOP_GSCL	TOP_REG(0x040c)
+#define MUX_STAT_TOP_ISP10	TOP_REG(0x0414)
+#define MUX_STAT_TOP_ISP11	TOP_REG(0x0418)
+#define MUX_STAT_TOP_DISP0	TOP_REG(0x041c)
+#define MUX_STAT_TOP_DISP1	TOP_REG(0x0420)
+#define MUX_STAT_TOP_BUS	TOP_REG(0x0424)
+#define MUX_STAT_TOP_PERI0	TOP_REG(0x0428)
+#define MUX_STAT_TOP_PERI1	TOP_REG(0x042c)
+#define MUX_STAT_TOP_FSYS	TOP_REG(0x0430)
+#define MUX_IGNORE_TOP_PLL0	TOP_REG(0x0500)
+#define MUX_IGNORE_TOP_MFC	TOP_REG(0x0504)
+#define MUX_IGNORE_TOP_G2D	TOP_REG(0x0508)
+#define MUX_IGNORE_TOP_GSCL	TOP_REG(0x050c)
+#define MUX_IGNORE_TOP_ISP10	TOP_REG(0x0514)
+#define MUX_IGNORE_TOP_ISP11	TOP_REG(0x0518)
+#define MUX_IGNORE_TOP_DISP0	TOP_REG(0x051c)
+#define MUX_IGNORE_TOP_DISP1	TOP_REG(0x0520)
+#define MUX_IGNORE_TOP_BUS	TOP_REG(0x0524)
+#define MUX_IGNORE_TOP_PERI0	TOP_REG(0x0528)
+#define MUX_IGNORE_TOP_PERI1	TOP_REG(0x052c)
+#define MUX_IGNORE_TOP_FSYS	TOP_REG(0x0530)
+#define DIV_TOP_G2D_MFC		TOP_REG(0x0600)
+#define DIV_TOP_GSCL_ISP0	TOP_REG(0x0604)
+#define DIV_TOP_ISP10		TOP_REG(0x0608)
+#define DIV_TOP_ISP11		TOP_REG(0x060c)
+#define DIV_TOP_DISP		TOP_REG(0x0610)
+#define DIV_TOP_BUS		TOP_REG(0x0614)
+#define DIV_TOP_PERI0		TOP_REG(0x0618)
+#define DIV_TOP_PERI1		TOP_REG(0x061c)
+#define DIV_TOP_PERI2		TOP_REG(0x0620)
+#define DIV_TOP_FSYS0		TOP_REG(0x0624)
+#define DIV_TOP_FSYS1		TOP_REG(0x0628)
+#define DIV_TOP_HPM		TOP_REG(0x062c)
+#define DIV_TOP_PLL_FDET	TOP_REG(0x0630)
+#define DIV_STAT_TOP_G2D_MFC	TOP_REG(0x0700)
+#define DIV_STAT_TOP_GSCL_ISP0	TOP_REG(0x0704)
+#define DIV_STAT_TOP_ISP10	TOP_REG(0x0708)
+#define DIV_STAT_TOP_ISP11	TOP_REG(0x070c)
+#define DIV_STAT_TOP_DISP	TOP_REG(0x0710)
+#define DIV_STAT_TOP_BUS	TOP_REG(0x0714)
+#define DIV_STAT_TOP_PERI0	TOP_REG(0x0718)
+#define DIV_STAT_TOP_PERI1	TOP_REG(0x071c)
+#define DIV_STAT_TOP_PERI2	TOP_REG(0x0720)
+#define DIV_STAT_TOP_FSYS0	TOP_REG(0x0724)
+#define DIV_STAT_TOP_FSYS1	TOP_REG(0x0728)
+#define DIV_STAT_TOP_HPM	TOP_REG(0x072c)
+#define DIV_STAT_TOP_PLL_FDET	TOP_REG(0x0730)
+#define EN_ACLK_TOP		TOP_REG(0x0800)
+#define EN_SCLK_TOP		TOP_REG(0x0a00)
+#define EN_IP_TOP		TOP_REG(0x0b00)
+#define CLKOUT_CMU_TOP		TOP_REG(0x0c00)
+#define CLKOUT_CMU_TOP_DIV_STAT	TOP_REG(0x0c04)
+
+#endif /*__CLK_EXYNOS5260_H */
+
-- 
1.7.9.5

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[PATCH V2 09/10] ARM: dts: add dts files for exynos5260 SoC

[Rahul Sharma]

The patch adds the dts files for exynos5260.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
 arch/arm/boot/dts/exynos5260-pinctrl.dtsi |  572 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos5260.dtsi         |  317 ++++++++++++++++
 2 files changed, 889 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/exynos5260.dtsi

diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
new file mode 100644
index 0000000..3f2c5c4
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -0,0 +1,572 @@
+/*
+ * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+	pinctrl@11600000 {
+		gpa0: gpa0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpa1: gpa1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpa2: gpa2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb0: gpb0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb1: gpb1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb2: gpb2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb3: gpb3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb4: gpb4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb5: gpb5 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd0: gpd0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd1: gpd1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd2: gpd2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpe0: gpe0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpe1: gpe1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf0: gpf0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf1: gpf1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpk0: gpk0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx0: gpx0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx1: gpx1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx2: gpx2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx3: gpx3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		uart0_data: uart0-data {
+			samsung,pins = "gpa0-0", "gpa0-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart0_fctl: uart0-fctl {
+			samsung,pins = "gpa0-2", "gpa0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_data: uart1-data {
+			samsung,pins = "gpa1-0", "gpa1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_fctl: uart1-fctl {
+			samsung,pins = "gpa1-2", "gpa1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart2_data: uart2-data {
+			samsung,pins = "gpa1-4", "gpa1-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi0_bus: spi0-bus {
+			samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi1_bus: spi1-bus {
+			samsung,pins = "gpa2-5", "gpa2-6", "gpa2-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		usb3_vbus0_en: usb3-vbus0-en {
+			samsung,pins = "gpa2-4";
+			samsung,pin-function = <1>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2s1_bus: i2s1-bus {
+			samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+					"gpb0-4";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		pcm1_bus: pcm1-bus {
+			samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+					"gpb0-4";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		spdif1_bus: spdif1-bus {
+			samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi2_bus: spi2-bus {
+			samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c0_hs_bus: i2c0-hs-bus {
+			samsung,pins = "gpb3-0", "gpb3-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c1_hs_bus: i2c1-hs-bus {
+			samsung,pins = "gpb3-2", "gpb3-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c2_hs_bus: i2c2-hs-bus {
+			samsung,pins = "gpb3-4", "gpb3-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c3_hs_bus: i2c3-hs-bus {
+			samsung,pins = "gpb3-6", "gpb3-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c4_bus: i2c4-bus {
+			samsung,pins = "gpb4-0", "gpb4-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c5_bus: i2c5-bus {
+			samsung,pins = "gpb4-2", "gpb4-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c6_bus: i2c6-bus {
+			samsung,pins = "gpb4-4", "gpb4-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c7_bus: i2c7-bus {
+			samsung,pins = "gpb4-6", "gpb4-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c8_bus: i2c8-bus {
+			samsung,pins = "gpb5-0", "gpb5-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c9_bus: i2c9-bus {
+			samsung,pins = "gpb5-2", "gpb5-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c10_bus: i2c10-bus {
+			samsung,pins = "gpb5-4", "gpb5-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c11_bus: i2c11-bus {
+			samsung,pins = "gpb5-6", "gpb5-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		cam_gpio_a: cam-gpio-a {
+			samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
+				"gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
+				"gpe1-0", "gpe1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		cam_gpio_b: cam-gpio-b {
+			samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
+				"gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		cam_i2c1_bus: cam-i2c1-bus {
+			samsung,pins = "gpf0-2", "gpf0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		cam_i2c0_bus: cam-i2c0-bus {
+			samsung,pins = "gpf0-0", "gpf0-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		cam_spi0_bus: cam-spi0-bus {
+			samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		cam_spi1_bus: cam-spi1-bus {
+			samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+	};
+
+	pinctrl@12290000 {
+		gpc0: gpc0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc1: gpc1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc2: gpc2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc3: gpc3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc4: gpc4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		sd0_clk: sd0-clk {
+			samsung,pins = "gpc0-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_cmd: sd0-cmd {
+			samsung,pins = "gpc0-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_bus1: sd0-bus-width1 {
+			samsung,pins = "gpc0-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_bus4: sd0-bus-width4 {
+			samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_bus8: sd0-bus-width8 {
+			samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_rdqs: sd0-rdqs {
+			samsung,pins = "gpc0-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd1_clk: sd1-clk {
+			samsung,pins = "gpc1-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd1_cmd: sd1-cmd {
+			samsung,pins = "gpc1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd1_bus1: sd1-bus-width1 {
+			samsung,pins = "gpc1-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd1_bus4: sd1-bus-width4 {
+			samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd1_bus8: sd1-bus-width8 {
+			samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd2_clk: sd2-clk {
+			samsung,pins = "gpc2-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd2_cmd: sd2-cmd {
+			samsung,pins = "gpc2-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd2_cd: sd2-cd {
+			samsung,pins = "gpc2-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd2_bus1: sd2-bus-width1 {
+			samsung,pins = "gpc2-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd2_bus4: sd2-bus-width4 {
+			samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+	};
+
+	pinctrl@128B0000 {
+		gpz0: gpz0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpz1: gpz1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
new file mode 100644
index 0000000..32a95c7
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -0,0 +1,317 @@
+/*
+ * SAMSUNG EXYNOS5260 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "skeleton.dtsi"
+#include "exynos5260-pinctrl.dtsi"
+
+#include <dt-bindings/clk/exynos5260-clk.h>
+
+/ {
+	compatible = "samsung,exynos5260";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		pinctrl0 = &pinctrl_0;
+		pinctrl1 = &pinctrl_1;
+		pinctrl2 = &pinctrl_2;
+	};
+
+	chipid@10000000 {
+		compatible = "samsung,exynos4210-chipid";
+		reg = <0x10000000 0x100>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0>;
+			cci-control-port = <&cci_control1>;
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+			cci-control-port = <&cci_control1>;
+		};
+		cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x100>;
+			cci-control-port = <&cci_control0>;
+		};
+		cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x101>;
+			cci-control-port = <&cci_control0>;
+		};
+		cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x102>;
+			cci-control-port = <&cci_control0>;
+		};
+		cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x103>;
+			cci-control-port = <&cci_control0>;
+		};
+	};
+
+	cmus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		cmu_top: clock-controller@10010000 {
+			compatible = "exynos5260-cmu-top", "samsung,exynos5260-clock";
+			reg = <0x10010000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_peri: clock-controller@10200000 {
+			compatible = "exynos5260-cmu-peri", "samsung,exynos5260-clock";
+			reg = <0x10200000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_egl: clock-controller@10600000 {
+			compatible = "exynos5260-cmu-egl", "samsung,exynos5260-clock";
+			reg = <0x10600000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_kfc: clock-controller@10700000 {
+			compatible = "exynos5260-cmu-kfc", "samsung,exynos5260-clock";
+			reg = <0x10700000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_g2d: clock-controller@10A00000 {
+			compatible = "exynos5260-cmu-g2d", "samsung,exynos5260-clock";
+			reg = <0x10A00000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_mif: clock-controller@10CE0000 {
+			compatible = "exynos5260-cmu-mif", "samsung,exynos5260-clock";
+			reg = <0x10CE0000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_mfc: clock-controller@11090000 {
+			compatible = "exynos5260-cmu-mfc", "samsung,exynos5260-clock";
+			reg = <0x11090000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_g3d: clock-controller@11830000 {
+			compatible = "exynos5260-cmu-g3d", "samsung,exynos5260-clock";
+			reg = <0x11830000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_fsys: clock-controller@122E0000 {
+			compatible = "exynos5260-cmu-fsys", "samsung,exynos5260-clock";
+			reg = <0x122E0000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_aud: clock-controller@128C0000 {
+			compatible = "exynos5260-cmu-aud", "samsung,exynos5260-clock";
+			reg = <0x128C0000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_isp: clock-controller@133C0000 {
+			compatible = "exynos5260-cmu-isp", "samsung,exynos5260-clock";
+			reg = <0x133C0000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_gscl: clock-controller@13F00000 {
+			compatible = "exynos5260-cmu-gscl", "samsung,exynos5260-clock";
+			reg = <0x13F00000 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		cmu_disp: clock-controller@14550000 {
+			compatible = "exynos5260-cmu-disp", "samsung,exynos5260-clock";
+			reg = <0x14550000 0x10000>;
+			#clock-cells = <1>;
+		};
+	};
+
+	gic: interrupt-controller@10481000 {
+		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		interrupt-controller;
+		reg = <0x10481000 0x1000>,
+			<0x10482000 0x1000>,
+			<0x10484000 0x2000>,
+			<0x10486000 0x2000>;
+		interrupts = <1 9 0xf04>;
+	};
+
+	mct@100B0000 {
+		compatible = "samsung,exynos4210-mct";
+		reg = <0x100B0000 0x1000>;
+		interrupt-controller;
+		#interrups-cells = <1>;
+		interrupt-parent = <&mct_map>;
+		interrupts = <0>, <1>, <2>, <3>,
+				<4>, <5>, <6>, <7>,
+				<8>, <9>, <10>, <11>;
+		clocks = <&cmu_top FIN_PLL>, <&cmu_peri PERI_CLK_MCT>;
+		clock-names = "fin_pll", "mct";
+
+		mct_map: mct-map {
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-map = <0 &gic 0 104 0>,
+					<1 &gic 0 105 0>,
+					<2 &gic 0 106 0>,
+					<3 &gic 0 107 0>,
+					<4 &gic 0 122 0>,
+					<5 &gic 0 123 0>,
+					<6 &gic 0 124 0>,
+					<7 &gic 0 125 0>,
+					<8 &gic 0 126 0>,
+					<9 &gic 0 127 0>,
+					<10 &gic 0 128 0>,
+					<11 &gic 0 129 0>;
+		};
+	};
+
+	cci@10F00000 {
+		compatible = "arm,cci-400";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x10F00000 0x1000>;
+		ranges = <0x0 0x10F00000 0x6000>;
+
+		cci_control0: slave-if@4000 {
+			compatible = "arm,cci-400-ctrl-if";
+			interface-type = "ace";
+			reg = <0x4000 0x1000>;
+		};
+
+		cci_control1: slave-if@5000 {
+			compatible = "arm,cci-400-ctrl-if";
+			interface-type = "ace";
+			reg = <0x5000 0x1000>;
+		};
+	};
+
+	pinctrl_0: pinctrl@11600000 {
+		compatible = "samsung,exynos5260-pinctrl";
+		reg = <0x11600000 0x1000>;
+		interrupts = <0 79 0>;
+
+		wakeup-interrupt-controller {
+			compatible = "samsung,exynos4210-wakeup-eint";
+			interrupt-parent = <&gic>;
+			interrupts = <0 32 0>;
+		};
+	};
+
+	pinctrl_1: pinctrl@12290000 {
+		compatible = "samsung,exynos5260-pinctrl";
+		reg = <0x12290000 0x1000>;
+		interrupts = <0 157 0>;
+	};
+
+	pinctrl_2: pinctrl@128B0000 {
+		compatible = "samsung,exynos5260-pinctrl";
+		reg = <0x128B0000 0x1000>;
+		interrupts = <0 243 0>;
+	};
+
+	serial@12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 146 0>;
+		clocks = <&cmu_peri PERI_CLK_UART0>, <&cmu_peri PERI_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
+
+	serial@12C10000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C10000 0x100>;
+		interrupts = <0 147 0>;
+		clocks = <&cmu_peri PERI_CLK_UART1>, <&cmu_peri PERI_SCLK_UART1>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
+
+	serial@12C20000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C20000 0x100>;
+		interrupts = <0 148 0>;
+		clocks = <&cmu_peri PERI_CLK_UART2>, <&cmu_peri PERI_SCLK_UART2>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
+
+	serial@12860000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12860000 0x100>;
+		interrupts = <0 145 0>;
+		clocks = <&cmu_aud AUD_CLK_AUD_UART>, <&cmu_aud AUD_SCLK_AUD_UART>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
+
+	mmc_0: mmc0@12140000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12140000 0x2000>;
+		interrupts = <0 156 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cmu_fsys FSYS_CLK_MMC0>, <&cmu_top TOP_SCLK_MMC0>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x40>;
+		status = "disabled";
+	};
+
+	mmc_1: mmc1@12150000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12150000 0x2000>;
+		interrupts = <0 158 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cmu_fsys FSYS_CLK_MMC1>, <&cmu_top TOP_SCLK_MMC1>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x40>;
+		status = "disabled";
+	};
+
+	mmc_2: mmc2@12160000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12160000 0x2000>;
+		interrupts = <0 159 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cmu_fsys FSYS_CLK_MMC2>, <&cmu_top TOP_SCLK_MMC2>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x40>;
+		status = "disabled";
+	};
+};
-- 
1.7.9.5

[PATCH V2 10/10] ARM: dts: add dts files for xyref5260 board

[Rahul Sharma]

The patch adds the dts files for xyref5260 board which
is based on Exynos5260 Evt0 sample.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
 arch/arm/boot/dts/Makefile                      |    1 +
 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts |  105 +++++++++++++++++++++++
 2 files changed, 106 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cfee1ef..dbba98c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -64,6 +64,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 	exynos5250-arndale.dtb \
 	exynos5250-smdk5250.dtb \
 	exynos5250-snow.dtb \
+	exynos5260-xyref5260-evt0.dtb \
 	exynos5410-smdk5410.dtb \
 	exynos5420-arndale-octa.dtb \
 	exynos5420-smdk5420.dtb \
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
new file mode 100644
index 0000000..b4c9c35
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
@@ -0,0 +1,105 @@
+/*
+ * SAMSUNG XYREF5260 EVT0 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5260.dtsi"
+
+/ {
+	model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260";
+	compatible = "samsung,xyref5260", "samsung,exynos5260";
+
+	memory {
+		reg = <0x20000000 0x80000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttySAC2,115200";
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fin_pll: oscillator@0 {
+			compatible = "fixed-clock";
+			reg = <0>;
+			clock-frequency = <24000000>;
+			clock-output-names = "fin_pll";
+			#clock-cells = <0>;
+		};
+	};
+
+	pinctrl@11600000 {
+		hdmi_hpd_irq: hdmi-hpd-irq {
+			samsung,pins = "gpx3-7";
+			samsung,pin-function = <0>;
+			samsung,pin-pud = <1>;
+			samsung,pin-drv = <0>;
+		};
+	};
+
+	serial@12C00000 {
+		status = "okay";
+	};
+
+	serial@12C10000 {
+		status = "okay";
+	};
+
+	serial@12C20000 {
+		status = "okay";
+	};
+
+	serial@12860000 {
+		status = "okay";
+	};
+
+	mmc0@12140000 {
+		status = "okay";
+		num-slots = <1>;
+		broken-cd;
+		bypass-smu;
+		supports-highspeed;
+		supports-hs200-mode; /* 200 Mhz */
+		fifo-depth = <0x40>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-ciu-div = <3>;
+		samsung,dw-mshc-sdr-timing = <0 4>;
+		samsung,dw-mshc-ddr-timing = <0 2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+
+		slot@0 {
+			reg = <0>;
+			bus-width = <8>;
+		};
+	};
+
+	mmc2@12160000 {
+		status = "okay";
+		num-slots = <1>;
+		supports-highspeed;
+		fifo-depth = <0x40>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-ciu-div = <3>;
+		samsung,dw-mshc-sdr-timing = <2 3>;
+		samsung,dw-mshc-ddr-timing = <1 2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+
+		slot@0 {
+			reg = <0>;
+			bus-width = <4>;
+			disable-wp;
+		};
+	};
+};
-- 
1.7.9.5