From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee Suthikulanit Subject: Re: [PATCH v2 08/11] of: Increase MAX_PHANDLE_ARGS Date: Thu, 30 Jan 2014 16:53:35 -0600 Message-ID: <52EAD7EF.3040305@amd.com> References: <1389876263-25759-1-git-send-email-andreas.herrmann@calxeda.com> <1389876263-25759-9-git-send-email-andreas.herrmann@calxeda.com> <20140117110830.GW3471@alberich> <52E92842.3000001@amd.com> <52E93360.1000904@amd.com> <20140129171611.GB13543@alberich> <52E939CB.1020705@amd.com> <20140129172932.GQ26622@mudshark.cambridge.arm.com> <52E940FC.9050602@amd.com> <20140129180350.GS26622@mudshark.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20140129180350.GS26622-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Will Deacon Cc: "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , Rob Herring , Rob Herring , Andreas Herrmann , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: devicetree@vger.kernel.org On 1/29/2014 12:03 PM, Will Deacon wrote: > On Wed, Jan 29, 2014 at 05:57:16PM +0000, Suravee Suthikulanit wrote: >> On 1/29/2014 11:29 AM, Will Deacon wrote: >>> On Wed, Jan 29, 2014 at 05:26:35PM +0000, Suravee Suthikulanit wrote: >>>> On 1/29/2014 11:16 AM, Andreas Herrmann wrote: >>>>> On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit wrote: >>>>>> Actually, we are using 32 on the AMD system. So, do you think we can set >>>>>> this to 32 instead? >>>>> >>>>> I think that's ok. >>>>> >>>>> But are we really talking about number of SMRs or number of StreamIDs >>>>> per master device here? Ie. are you just having 32 SMRs for an SMMU on >>>>> your AMD system or do you have master devices which have 32 StreamIDs? >>>>> >>>>> If it's just number of SMRs we don't need to modify this macro. >>>>> >>>> >>>> I am referring to the case where each mmu-master can have upto 32 streamID. >>> >>> Crikey, how many SMRs do you have? Andreas and I have been struggling to >>> write a decent allocator for those, so if you have any algorithms that don't >>> require a quantum computer, we'd love to hear from you :)! >>> >>> Will >>> >> >> Are you talking about the __arm_smmu_alloc_bitmap()? >> >> Currently, we have configured the each SMMU to have 32 SMRs and using >> 15-bit streamID. However, we mostly have upto 32 streamID for each >> master, and most of the SMMU only have one master. So it looks like the >> current logic should be ok. > > Interesting... how does that work for PCI? Do you force all devices behind a > given RC into the same address space? > > Will > For PCI devices, we are using the bus, device, and function id to make up the 15-bit SID for devices behind a particular PCI root complex. I also notice that we are currently not supporting the streamID mask in the SMR. Is this something planed for the future? Suravee