From mboxrd@z Thu Jan 1 00:00:00 1970 From: srinivas kandagatla Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support Date: Fri, 31 Jan 2014 12:27:39 +0000 Message-ID: <52EB96BB.6070800@st.com> References: <1391093744-19905-1-git-send-email-patrice.chotard@st.com> <1391093744-19905-2-git-send-email-patrice.chotard@st.com> <201401301935.16463.arnd@arndb.de> <201401301939.08302.arnd@arndb.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <201401301939.08302.arnd@arndb.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Arnd Bergmann , linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, Russell King , kernel@stlinux.com, Linus Walleij , linux-kernel@vger.kernel.org, Patrice CHOTARD , Stuart Menefy , alexandre.torgue@st.com, Rob Herring , Grant Likely , Giuseppe Cavallaro , maxime.coquelin@st.com List-Id: devicetree@vger.kernel.org Hi Arnd, On 30/01/14 18:39, Arnd Bergmann wrote: > Actually reading the code in this file shows that the L2 cache > initialization is the only nonstandard thing in there. We should > really find a way to get rid of the entire function. I think this will get rid of lot of code left in board-dt. > > Sorry if I missed the initial review, but can you explain > why this is needed to start with? On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set the way-size explicit here. Thanks, srini