[parent not found: <1391093744-19905-1-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>]
* [PATCH 1/4] ARM: STi: add stid127 soc support
[not found] ` <1391093744-19905-1-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
@ 2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 18:35 ` Arnd Bergmann
2014-02-27 12:23 ` Maxime Coquelin
0 siblings, 2 replies; 20+ messages in thread
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-F5mvAk5X5gdBDgjK7y7TUQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Linus Walleij, Grant Likely,
Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: maxime.coquelin-qxv4g6HH51o, alexandre.torgue-qxv4g6HH51o,
patrice.chotard-qxv4g6HH51o, Giuseppe Cavallaro
From: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
This patch adds support to STiD127 SoC.
The main adaptation is the L2 cache way size compare to STiH41x SoCs.
Signed-off-by: alexandre torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
---
arch/arm/mach-sti/board-dt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index 1217fb5..be018a9 100644
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -9,6 +9,7 @@
#include <linux/irq.h>
#include <linux/of_platform.h>
+#include <linux/of.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
@@ -18,6 +19,10 @@ void __init stih41x_l2x0_init(void)
{
u32 way_size = 0x4;
u32 aux_ctrl;
+
+ if (of_machine_is_compatible("st,stid127"))
+ way_size = 0x3;
+
/* may be this can be encoded in macros like BIT*() */
aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
@@ -36,6 +41,7 @@ static void __init stih41x_machine_init(void)
static const char *stih41x_dt_match[] __initdata = {
"st,stih415",
"st,stih416",
+ "st,stid127",
NULL
};
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 1/4] ARM: STi: add stid127 soc support
2014-01-30 14:55 ` [PATCH 1/4] ARM: STi: add stid127 soc support Patrice CHOTARD
@ 2014-01-30 18:35 ` Arnd Bergmann
[not found] ` <201401301935.16463.arnd-r2nGTMty4D4@public.gmane.org>
2014-02-27 12:23 ` Maxime Coquelin
1 sibling, 1 reply; 20+ messages in thread
From: Arnd Bergmann @ 2014-01-30 18:35 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, Russell King, kernel, Srinivas Kandagatla,
Linus Walleij, Patrice CHOTARD, linux-kernel, Stuart Menefy,
Rob Herring, Grant Likely, Giuseppe Cavallaro, maxime.coquelin,
alexandre.torgue
On Thursday 30 January 2014, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <alexandre.torgue@st.com>
>
> This patch adds support to STiD127 SoC.
> The main adaptation is the L2 cache way size compare to STiH41x SoCs.
>
> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
> arch/arm/mach-sti/board-dt.c | 6 ++++++
> 1 file changed, 6 insertions(+)
Wouldn't it be better to read this value from the l2 cache
controller node? I'd assume there might be more SoCs that
will need a similar change, so it's better to come up with
a solution that doesn't involve changing the kernel every
time.
Arnd
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 1/4] ARM: STi: add stid127 soc support
2014-01-30 14:55 ` [PATCH 1/4] ARM: STi: add stid127 soc support Patrice CHOTARD
2014-01-30 18:35 ` Arnd Bergmann
@ 2014-02-27 12:23 ` Maxime Coquelin
2014-02-27 12:27 ` Patrice Chotard
1 sibling, 1 reply; 20+ messages in thread
From: Maxime Coquelin @ 2014-02-27 12:23 UTC (permalink / raw)
To: Patrice CHOTARD, Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel, kernel, linux-kernel, Linus Walleij,
Grant Likely, Rob Herring, devicetree
Cc: Giuseppe Cavallaro, alexandre.torgue
Hi Patrice,
Could you add an overview documentation as it has been done for other
STi platforms?
See Documentation/arm/sti/stih416-overview.txt
Thanks,
Maxime
On 01/30/2014 03:55 PM, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <alexandre.torgue@st.com>
>
> This patch adds support to STiD127 SoC.
> The main adaptation is the L2 cache way size compare to STiH41x SoCs.
>
> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
> arch/arm/mach-sti/board-dt.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
> index 1217fb5..be018a9 100644
> --- a/arch/arm/mach-sti/board-dt.c
> +++ b/arch/arm/mach-sti/board-dt.c
> @@ -9,6 +9,7 @@
>
> #include <linux/irq.h>
> #include <linux/of_platform.h>
> +#include <linux/of.h>
> #include <asm/hardware/cache-l2x0.h>
> #include <asm/mach/arch.h>
>
> @@ -18,6 +19,10 @@ void __init stih41x_l2x0_init(void)
> {
> u32 way_size = 0x4;
> u32 aux_ctrl;
> +
> + if (of_machine_is_compatible("st,stid127"))
> + way_size = 0x3;
> +
> /* may be this can be encoded in macros like BIT*() */
> aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
> (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
> @@ -36,6 +41,7 @@ static void __init stih41x_machine_init(void)
> static const char *stih41x_dt_match[] __initdata = {
> "st,stih415",
> "st,stih416",
> + "st,stid127",
> NULL
> };
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 1/4] ARM: STi: add stid127 soc support
2014-02-27 12:23 ` Maxime Coquelin
@ 2014-02-27 12:27 ` Patrice Chotard
0 siblings, 0 replies; 20+ messages in thread
From: Patrice Chotard @ 2014-02-27 12:27 UTC (permalink / raw)
To: Maxime Coquelin, Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel, kernel, linux-kernel, Linus Walleij,
Grant Likely, Rob Herring, devicetree
Cc: Giuseppe Cavallaro, alexandre.torgue
Hi Maxime
Thanks for reviewing.
Yes for sure, i will add additional board informations.
Patrice
On 02/27/2014 01:23 PM, Maxime Coquelin wrote:
> Hi Patrice,
>
> Could you add an overview documentation as it has been done for other
> STi platforms?
>
> See Documentation/arm/sti/stih416-overview.txt
>
> Thanks,
> Maxime
>
> On 01/30/2014 03:55 PM, Patrice CHOTARD wrote:
>> From: Alexandre TORGUE <alexandre.torgue@st.com>
>>
>> This patch adds support to STiD127 SoC.
>> The main adaptation is the L2 cache way size compare to STiH41x SoCs.
>>
>> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> ---
>> arch/arm/mach-sti/board-dt.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
>> index 1217fb5..be018a9 100644
>> --- a/arch/arm/mach-sti/board-dt.c
>> +++ b/arch/arm/mach-sti/board-dt.c
>> @@ -9,6 +9,7 @@
>>
>> #include <linux/irq.h>
>> #include <linux/of_platform.h>
>> +#include <linux/of.h>
>> #include <asm/hardware/cache-l2x0.h>
>> #include <asm/mach/arch.h>
>>
>> @@ -18,6 +19,10 @@ void __init stih41x_l2x0_init(void)
>> {
>> u32 way_size = 0x4;
>> u32 aux_ctrl;
>> +
>> + if (of_machine_is_compatible("st,stid127"))
>> + way_size = 0x3;
>> +
>> /* may be this can be encoded in macros like BIT*() */
>> aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
>> (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
>> @@ -36,6 +41,7 @@ static void __init stih41x_machine_init(void)
>> static const char *stih41x_dt_match[] __initdata = {
>> "st,stih415",
>> "st,stih416",
>> + "st,stid127",
>> NULL
>> };
>>
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 2/4] pinctrl: st: add stid127 support
2014-01-30 14:55 [PATCH 0/4] ARM:sti: Add STiD127 platform and board support Patrice CHOTARD
[not found] ` <1391093744-19905-1-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
@ 2014-01-30 14:55 ` Patrice CHOTARD
2014-01-31 12:30 ` srinivas kandagatla
2014-02-04 20:54 ` Linus Walleij
2014-01-30 14:55 ` [PATCH 3/4] ARM: dts: Add support of STid127 Soc Patrice CHOTARD
2014-01-30 14:55 ` [PATCH 4/4] ARM: dts: add B2112 board support Patrice CHOTARD
3 siblings, 2 replies; 20+ messages in thread
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel, kernel, linux-kernel, Linus Walleij,
Grant Likely, Rob Herring, devicetree
Cc: Giuseppe Cavallaro, patrice.chotard, alexandre.torgue,
maxime.coquelin
From: Alexandre TORGUE <alexandre.torgue@st.com>
Add STid127 PIOs (psouth, pwest, peast) in pinctrl.
Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
---
drivers/pinctrl/pinctrl-st.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 9cadc68..01227de 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -336,6 +336,27 @@ static const struct st_pctl_data stih416_data = {
.alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
};
+/* STid127 data */
+static const struct st_pctl_data stid127_data = {
+ .rt_style = st_retime_style_dedicated,
+ /* reuse stih416 delays as they are identical */
+ .input_delays = stih416_delays,
+ .ninput_delays = 14,
+ /* reuse stih416 delays as they are identical */
+ .output_delays = stih416_delays,
+ .noutput_delays = 14,
+ .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 14,
+};
+
+static const struct st_pctl_data stid127_psouth_data = {
+ .rt_style = st_retime_style_dedicated,
+ .input_delays = stid127_delays,
+ .ninput_delays = 14,
+ .output_delays = stid127_delays,
+ .noutput_delays = 14,
+ .alt = 0, .oe = 7, .pu = 9, .od = 11, .rt = 13,
+};
+
/* Low level functions.. */
static inline int st_gpio_bank(int gpio)
{
@@ -1264,6 +1285,10 @@ static struct of_device_id st_pctl_of_match[] = {
{ .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data},
{ .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data},
{ .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data},
+ { .compatible = "st,stid127-pwest-pinctrl", .data = &stid127_data },
+ { .compatible = "st,stid127-psouth-pinctrl",
+ .data = &stid127_psouth_data },
+ { .compatible = "st,stid127-peast-pinctrl", .data = &stid127_data },
{ /* sentinel */ }
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 2/4] pinctrl: st: add stid127 support
2014-01-30 14:55 ` [PATCH 2/4] pinctrl: st: add stid127 support Patrice CHOTARD
@ 2014-01-31 12:30 ` srinivas kandagatla
2014-02-04 20:54 ` Linus Walleij
1 sibling, 0 replies; 20+ messages in thread
From: srinivas kandagatla @ 2014-01-31 12:30 UTC (permalink / raw)
To: Patrice CHOTARD, Stuart Menefy, Russell King, linux-arm-kernel,
kernel, linux-kernel, Linus Walleij, Grant Likely, Rob Herring,
devicetree
Cc: Giuseppe Cavallaro, alexandre.torgue, maxime.coquelin
Looks good for me.
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
On 30/01/14 14:55, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <alexandre.torgue@st.com>
>
> Add STid127 PIOs (psouth, pwest, peast) in pinctrl.
>
> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> ---
> drivers/pinctrl/pinctrl-st.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
> index 9cadc68..01227de 100644
> --- a/drivers/pinctrl/pinctrl-st.c
> +++ b/drivers/pinctrl/pinctrl-st.c
> @@ -336,6 +336,27 @@ static const struct st_pctl_data stih416_data = {
> .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
> };
>
> +/* STid127 data */
> +static const struct st_pctl_data stid127_data = {
> + .rt_style = st_retime_style_dedicated,
> + /* reuse stih416 delays as they are identical */
> + .input_delays = stih416_delays,
> + .ninput_delays = 14,
> + /* reuse stih416 delays as they are identical */
> + .output_delays = stih416_delays,
> + .noutput_delays = 14,
> + .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 14,
> +};
> +
> +static const struct st_pctl_data stid127_psouth_data = {
> + .rt_style = st_retime_style_dedicated,
> + .input_delays = stid127_delays,
> + .ninput_delays = 14,
> + .output_delays = stid127_delays,
> + .noutput_delays = 14,
> + .alt = 0, .oe = 7, .pu = 9, .od = 11, .rt = 13,
> +};
> +
> /* Low level functions.. */
> static inline int st_gpio_bank(int gpio)
> {
> @@ -1264,6 +1285,10 @@ static struct of_device_id st_pctl_of_match[] = {
> { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data},
> { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data},
> { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data},
> + { .compatible = "st,stid127-pwest-pinctrl", .data = &stid127_data },
> + { .compatible = "st,stid127-psouth-pinctrl",
> + .data = &stid127_psouth_data },
> + { .compatible = "st,stid127-peast-pinctrl", .data = &stid127_data },
> { /* sentinel */ }
> };
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 2/4] pinctrl: st: add stid127 support
2014-01-30 14:55 ` [PATCH 2/4] pinctrl: st: add stid127 support Patrice CHOTARD
2014-01-31 12:30 ` srinivas kandagatla
@ 2014-02-04 20:54 ` Linus Walleij
1 sibling, 0 replies; 20+ messages in thread
From: Linus Walleij @ 2014-02-04 20:54 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel@lists.infradead.org, kernel,
linux-kernel@vger.kernel.org, Grant Likely, Rob Herring,
devicetree@vger.kernel.org, Maxime Coquelin, Alexandre TORGUE,
Giuseppe Cavallaro
On Thu, Jan 30, 2014 at 3:55 PM, Patrice CHOTARD <patrice.chotard@st.com> wrote:
> From: Alexandre TORGUE <alexandre.torgue@st.com>
>
> Add STid127 PIOs (psouth, pwest, peast) in pinctrl.
>
> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
Patch applied with Srinivas ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/4] ARM: dts: Add support of STid127 Soc.
2014-01-30 14:55 [PATCH 0/4] ARM:sti: Add STiD127 platform and board support Patrice CHOTARD
[not found] ` <1391093744-19905-1-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
2014-01-30 14:55 ` [PATCH 2/4] pinctrl: st: add stid127 support Patrice CHOTARD
@ 2014-01-30 14:55 ` Patrice CHOTARD
2014-01-31 12:50 ` srinivas kandagatla
2014-01-30 14:55 ` [PATCH 4/4] ARM: dts: add B2112 board support Patrice CHOTARD
3 siblings, 1 reply; 20+ messages in thread
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel, kernel, linux-kernel, Linus Walleij,
Grant Likely, Rob Herring, devicetree
Cc: Giuseppe Cavallaro, patrice.chotard, alexandre.torgue,
maxime.coquelin
From: Alexandre TORGUE <alexandre.torgue@st.com>
The STid127 integrates all harware components to function as a cable modem
or, in combination with a back end device, as a Gateway set top boxe.
Supported devices:
-UART0
-UART2
Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stid127-clock.dtsi | 31 ++++
arch/arm/boot/dts/stid127-pinctrl.dtsi | 245 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stid127.dtsi | 130 +++++++++++++++++
3 files changed, 406 insertions(+)
create mode 100644 arch/arm/boot/dts/stid127-clock.dtsi
create mode 100644 arch/arm/boot/dts/stid127-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stid127.dtsi
diff --git a/arch/arm/boot/dts/stid127-clock.dtsi b/arch/arm/boot/dts/stid127-clock.dtsi
new file mode 100644
index 0000000..c6cafa9
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-clock.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ * Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+ clocks {
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: arm_periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+ /*
+ * Bootloader initialized system infrastructure clock for
+ * serial devices.
+ */
+ CLK_IC_LP_HD: clockgenA0@29 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "CLK_IC_LP_HD";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stid127-pinctrl.dtsi b/arch/arm/boot/dts/stid127-pinctrl.dtsi
new file mode 100644
index 0000000..3fa66f3
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-pinctrl.dtsi
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2012 STMicroelectronics Limited.
+ * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ * Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+ aliases {
+ gpio0 = &PIO0;
+ gpio1 = &PIO1;
+ gpio2 = &PIO2;
+ gpio3 = &PIO3;
+ gpio4 = &PIO4;
+ gpio5 = &PIO5;
+ gpio6 = &PIO6;
+ gpio7 = &PIO7;
+ gpio8 = &PIO8;
+ gpio9 = &PIO9;
+ gpio10 = &PIO10;
+ gpio11 = &PIO11;
+ gpio12 = &PIO12;
+ gpio13 = &PIO13;
+ gpio14 = &PIO14;
+ gpio15 = &PIO15;
+ gpio16 = &PIO16;
+ gpio17 = &PIO17;
+ gpio18 = &PIO18;
+ gpio19 = &PIO19;
+ gpio20 = &PIO20;
+ gpio21 = &PIO21;
+ gpio22 = &PIO22;
+
+ };
+
+ soc {
+ pin-controller-pwest {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-pwest-pinctrl";
+ st,syscfg = <&syscfg_pwest>;
+ ranges = <0 0xfebe0000 0x8000>;
+
+ PIO0: gpio@febe0000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ interrupts = <0 149 0>;
+ st,bank-name = "PIO0";
+ };
+ PIO1: gpio@febe1000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 150 0>;
+ st,bank-name = "PIO1";
+ };
+ PIO2: gpio@febe2000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 151 0>;
+ st,bank-name = "PIO2";
+ };
+ PIO3: gpio@febe3000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 152 0>;
+ st,bank-name = "PIO3";
+ };
+ PIO4: gpio@febe4000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 153 0>;
+ st,bank-name = "PIO4";
+ };
+ PIO5: gpio@febe5000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 154 0>;
+ st,bank-name = "PIO5";
+ };
+ PIO6: gpio@febe6000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 155 0>;
+ st,bank-name = "PIO6";
+ };
+ PIO7: gpio@febe7000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x7000 0x100>;
+ interrupts = <0 156 0>;
+ st,bank-name = "PIO7";
+ };
+ uart0 {
+ pinctrl_uart0: uart0 {
+ st,pins {
+ tx = <&PIO3 2 ALT2 OUT>;
+ rx = <&PIO3 0 ALT2 IN>;
+ };
+ };
+ };
+
+ };
+
+ pin-controller-psouth {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-psouth-pinctrl";
+ st,syscfg = <&syscfg_psouth>;
+ ranges = <0 0xfef70000 0x7000>;
+
+ PIO8: gpio@fef70000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ interrupts = <0 157 0>;
+ st,bank-name = "PIO8";
+ };
+ PIO9: gpio@fef71000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 158 0>;
+ st,bank-name = "PIO9";
+ };
+ PIO10: gpio@fef72000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 159 0>;
+ st,bank-name = "PIO10";
+ };
+ PIO11: gpio@fef73000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 160 0>;
+ st,bank-name = "PIO11";
+ };
+ PIO12: gpio@fef74000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 161 0>;
+ st,bank-name = "PIO12";
+ };
+ PIO13: gpio@fef75000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 162 0>;
+ st,bank-name = "PIO13";
+ };
+ PIO14: gpio@fef76000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 163 0>;
+ st,bank-name = "PIO14";
+ };
+ };
+
+ pin-controller-peast {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-peast-pinctrl";
+ st,syscfg = <&syscfg_peast>;
+ ranges = <0 0xfebc0000 0x8000>;
+
+ PIO15: gpio@febc0000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = < 0 0x100>;
+ interrupts = <0 164 0>;
+ st,bank-name = "PIO15";
+ };
+ PIO16: gpio@febc1000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 165 0>;
+ st,bank-name = "PIO16";
+ };
+ PIO17: gpio@febc2000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 166 0>;
+ st,bank-name = "PIO17";
+ };
+ PIO18: gpio@febc3000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 167 0>;
+ st,bank-name = "PIO18";
+ };
+ PIO19: gpio@febc4000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 168 0>;
+ st,bank-name = "PIO19";
+ };
+ PIO20: gpio@febc5000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 169 0>;
+ st,bank-name = "PIO20";
+ };
+ PIO21: gpio@febc6000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 170 0>;
+ st,bank-name = "PIO21";
+ };
+ PIO22: gpio@febc7000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x7000 0x100>;
+ interrupts = <0 171 0>;
+ st,bank-name = "PIO22";
+ };
+ uart2 {
+ pinctrl_uart2: uart2-0 {
+ st,pins {
+ tx = <&PIO20 1 ALT3 OUT>;
+ rx = <&PIO20 2 ALT3 IN>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stid127.dtsi b/arch/arm/boot/dts/stid127.dtsi
new file mode 100644
index 0000000..a6f0b8fe
--- /dev/null
+++ b/arch/arm/boot/dts/stid127.dtsi
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ * Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stid127-pinctrl.dtsi"
+#include "stid127-clock.dtsi"
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ intc: interrupt-controller@fffe1000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xfffe1000 0x1000>,
+ <0xfffe0100 0x100>;
+ };
+
+ scu@fffe0000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xfffe0000 0x1000>;
+ };
+
+ timer@fffe0200 {
+ interrupt-parent = <&intc>;
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xfffe0200 0x100>;
+ interrupts = <1 11 0x04>;
+ clocks = <&arm_periph_clk>;
+ };
+
+ L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xfffe2000 0x1000>;
+ arm,data-latency = <3 2 2>;
+ arm,tag-latency = <1 1 1>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ compatible = "simple-bus";
+
+ syscfg_west:west-syscfg@febf0000{
+ compatible = "st,stid127-west-syscfg", "syscon";
+ reg = <0xfebf0000 0x1000>;
+ };
+
+ syscfg_south:south-syscfg@fefa0000{
+ compatible = "st,stid127-south-syscfg", "syscon";
+ reg = <0xfefa0000 0x1000>;
+ };
+
+ syscfg_docsis:docsis-syscfg@fef90000{
+ compatible = "st,stid127-docsys-syscfg", "syscon";
+ reg = <0xfef90000 0x1000>;
+ };
+
+ syscfg_cpu:cpu-syscfg@fe9a0000{
+ compatible = "st,stid127-cpu-syscfg", "syscon";
+ reg = <0xfe9a0000 0x1000>;
+ };
+
+ syscfg_hd:hd-syscfg@fe930000{
+ compatible = "st,stid127-hd-syscfg", "syscon";
+ reg = <0xfe930000 0x1000>;
+ };
+
+ syscfg_pwest:pwest-syscfg@fec00000{
+ compatible = "st,stid127-pwest-syscfg", "syscon";
+ reg = <0xfec00000 0x1000>;
+ };
+
+ syscfg_psouth:psouth-syscfg@fefd0000{
+ compatible = "st,stid127-psouth-syscfg", "syscon";
+ reg = <0xfefd0000 0x1000>;
+ };
+
+ syscfg_peast:peast-syscfg@febd0000{
+ compatible = "st,stid127-peast-syscfg", "syscon";
+ reg = <0xfebd0000 0x1000>;
+ };
+
+ /* Comms block ASCs in SASG2 */
+ uart0: serial@fe530000{
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfe530000 0x2c>;
+ interrupts = <0 25 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&CLK_IC_LP_HD>;
+ };
+
+ uart2: serial@fe532000{
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfe532000 0x2c>;
+ interrupts = <0 27 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&CLK_IC_LP_HD>;
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 3/4] ARM: dts: Add support of STid127 Soc.
2014-01-30 14:55 ` [PATCH 3/4] ARM: dts: Add support of STid127 Soc Patrice CHOTARD
@ 2014-01-31 12:50 ` srinivas kandagatla
[not found] ` <52EB9C03.70009-qxv4g6HH51o@public.gmane.org>
0 siblings, 1 reply; 20+ messages in thread
From: srinivas kandagatla @ 2014-01-31 12:50 UTC (permalink / raw)
To: Patrice CHOTARD, Stuart Menefy, Russell King, linux-arm-kernel,
kernel, linux-kernel, Linus Walleij, Grant Likely, Rob Herring,
devicetree
Cc: Giuseppe Cavallaro, alexandre.torgue, maxime.coquelin
Hi Patrice,
On 30/01/14 14:55, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <alexandre.torgue@st.com>
>
> The STid127 integrates all harware components to function as a cable modem
s/harware/hardware/
s/STid127/STiD127
Please fix other instances too.
> or, in combination with a back end device, as a Gateway set top boxe.
s/boxe/box/
>
> Supported devices:
> -UART0
> -UART2
>
> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> ---
> arch/arm/boot/dts/stid127-clock.dtsi | 31 ++++
> arch/arm/boot/dts/stid127-pinctrl.dtsi | 245 ++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/stid127.dtsi | 130 +++++++++++++++++
> 3 files changed, 406 insertions(+)
> create mode 100644 arch/arm/boot/dts/stid127-clock.dtsi
> create mode 100644 arch/arm/boot/dts/stid127-pinctrl.dtsi
> create mode 100644 arch/arm/boot/dts/stid127.dtsi
>
> diff --git a/arch/arm/boot/dts/stid127-clock.dtsi b/arch/arm/boot/dts/stid127-clock.dtsi
> new file mode 100644
> index 0000000..c6cafa9
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127-clock.dtsi
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited
2014
> + * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
> + * Alexandre Torgue <alexandre.torgue@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +/ {Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
> + clocks {
> + /*
> + * ARM Peripheral clock for timers
> + */
> + arm_periph_clk: arm_periph_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <100000000>;
> + };
> + /*
> + * Bootloader initialized system infrastructure clock for
> + * serial devices.
> + */
> + CLK_IC_LP_HD: clockgenA0@29 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <100000000>;
> + clock-output-names = "CLK_IC_LP_HD";
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/stid127-pinctrl.dtsi b/arch/arm/boot/dts/stid127-pinctrl.dtsi
> new file mode 100644
> index 0000000..3fa66f3
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127-pinctrl.dtsi
> @@ -0,0 +1,245 @@
> +/*
> + * Copyright (C) 2012 STMicroelectronics Limited.
2014
> + * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
> + * Alexandre Torgue <alexandre.torgue@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
s/publishhed/published/
> + */
> +#include "st-pincfg.h"
> +/ {
> + aliases {
> + gpio0 = &PIO0;
> + gpio1 = &PIO1;
> + gpio2 = &PIO2;
> + gpio3 = &PIO3;
> + gpio4 = &PIO4;
> + gpio5 = &PIO5;
> + gpio6 = &PIO6;
> + gpio7 = &PIO7;
> + gpio8 = &PIO8;
> + gpio9 = &PIO9;
> + gpio10 = &PIO10;
> + gpio11 = &PIO11;
> + gpio12 = &PIO12;
> + gpio13 = &PIO13;
> + gpio14 = &PIO14;
> + gpio15 = &PIO15;
> + gpio16 = &PIO16;
> + gpio17 = &PIO17;
> + gpio18 = &PIO18;
> + gpio19 = &PIO19;
> + gpio20 = &PIO20;
> + gpio21 = &PIO21;
> + gpio22 = &PIO22;
> +
> + };
> +
> + soc {
> + pin-controller-pwest {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "st,stid127-pwest-pinctrl";
> + st,syscfg = <&syscfg_pwest>;
> + ranges = <0 0xfebe0000 0x8000>;
Can you add interrupt controller support to the pin controller.
Patches are in : https://lkml.org/lkml/2014/1/16/342
All these patches are due to be in v3.15.
> +
> + PIO0: gpio@febe0000 {
> + gpio-controller;
> + #gpio-cells = <1>;
> + reg = <0 0x100>;
> + interrupts = <0 149 0>;
> + st,bank-name = "PIO0";
> + };
> + rx = <&PIO3 0 ALT2 IN>;
> + };
> + };
> + };
> +
> + };
unnecessary empty line here.
> diff --git a/arch/arm/boot/dts/stid127.dtsi b/arch/arm/boot/dts/stid127.dtsi
> new file mode 100644
> index 0000000..a6f0b8fe
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127.dtsi
> @@ -0,0 +1,130 @@
> +/*
> + * Copyright (C) 2013 STMicroelectronics Limited.
2014
> + * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
> + * Alexandre Torgue <alexandre.torgue@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
s/publishhed/published/
> + */
> +#include "stid127-pinctrl.dtsi"
> +#include "stid127-clock.dtsi"
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <0>;
> + };
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <1>;
> + };
> + };
> +
> + intc: interrupt-controller@fffe1000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0xfffe1000 0x1000>,
> + <0xfffe0100 0x100>;
> + };
> +
> + scu@fffe0000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0xfffe0000 0x1000>;
> + };
> +
> + timer@fffe0200 {
> + interrupt-parent = <&intc>;
> + compatible = "arm,cortex-a9-global-timer";
> + reg = <0xfffe0200 0x100>;
> + interrupts = <1 11 0x04>;
> + clocks = <&arm_periph_clk>;
Fix the tab spacing here.
Thanks,
srini
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 4/4] ARM: dts: add B2112 board support
2014-01-30 14:55 [PATCH 0/4] ARM:sti: Add STiD127 platform and board support Patrice CHOTARD
` (2 preceding siblings ...)
2014-01-30 14:55 ` [PATCH 3/4] ARM: dts: Add support of STid127 Soc Patrice CHOTARD
@ 2014-01-30 14:55 ` Patrice CHOTARD
2014-01-31 12:51 ` srinivas kandagatla
3 siblings, 1 reply; 20+ messages in thread
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel, kernel, linux-kernel, Linus Walleij,
Grant Likely, Rob Herring, devicetree
Cc: maxime.coquelin, alexandre.torgue, patrice.chotard,
Giuseppe Cavallaro
From: Alexandre TORGUE <alexandre.torgue@st.com>
Add support for B2112 board based on STiD127 SoC.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/stid127-b2112.dts | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stid127-b2112.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..7173dca 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -247,7 +247,8 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
stih416-b2000.dtb \
stih415-b2020.dtb \
- stih416-b2020.dtb
+ stih416-b2020.dtb \
+ stid127-b2112.dtb
dtb-$(CONFIG_ARCH_SUNXI) += \
sun4i-a10-a1000.dtb \
sun4i-a10-cubieboard.dtb \
diff --git a/arch/arm/boot/dts/stid127-b2112.dts b/arch/arm/boot/dts/stid127-b2112.dts
new file mode 100644
index 0000000..b4507e3
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-b2112.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stid127.dtsi"
+
+/ {
+ model = "STiD127 B2112 Board";
+ compatible = "st,stid127", "st,stid127-b2112";
+
+ memory{
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyAS0,115200";
+ linux,stdout-path = &uart2;
+ };
+
+ aliases {
+ ttyAS0 = &uart2;
+ };
+
+ soc {
+ uart2: serial@fe532000{
+ status = "okay";
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 4/4] ARM: dts: add B2112 board support
2014-01-30 14:55 ` [PATCH 4/4] ARM: dts: add B2112 board support Patrice CHOTARD
@ 2014-01-31 12:51 ` srinivas kandagatla
0 siblings, 0 replies; 20+ messages in thread
From: srinivas kandagatla @ 2014-01-31 12:51 UTC (permalink / raw)
To: Patrice CHOTARD, Stuart Menefy, Russell King, linux-arm-kernel,
kernel, linux-kernel, Linus Walleij, Grant Likely, Rob Herring,
devicetree
Cc: Giuseppe Cavallaro, alexandre.torgue, maxime.coquelin
On 30/01/14 14:55, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <alexandre.torgue@st.com>
>
> Add support for B2112 board based on STiD127 SoC.
>
> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
> ---
> arch/arm/boot/dts/Makefile | 3 ++-
> arch/arm/boot/dts/stid127-b2112.dts | 35 +++++++++++++++++++++++++++++++++++
> 2 files changed, 37 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/stid127-b2112.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index d57c1a6..7173dca 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -247,7 +247,8 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
> dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
> stih416-b2000.dtb \
> stih415-b2020.dtb \
> - stih416-b2020.dtb
> + stih416-b2020.dtb \
> + stid127-b2112.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += \
> sun4i-a10-a1000.dtb \
> sun4i-a10-cubieboard.dtb \
> diff --git a/arch/arm/boot/dts/stid127-b2112.dts b/arch/arm/boot/dts/stid127-b2112.dts
> new file mode 100644
> index 0000000..b4507e3
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127-b2112.dts
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright (C) 2013 STMicroelectronics Limited.
2014
> + * Author: Alexandre Torgue <alexandre.torgue@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
s/publishhed/published/
> + */
> +/dts-v1/;
> +#include "stid127.dtsi"
> +
> +/ {
> + model = "STiD127 B2112 Board";
> + compatible = "st,stid127", "st,stid127-b2112";
> +
> + memory{
> + device_type = "memory";
> + reg = <0x40000000 0x10000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyAS0,115200";
> + linux,stdout-path = &uart2;
> + };
> +
> + aliases {
> + ttyAS0 = &uart2;
> + };
> +
> + soc {
> + uart2: serial@fe532000{
> + status = "okay";
> + };
> + };
> +};
>
^ permalink raw reply [flat|nested] 20+ messages in thread