[PATCH 0/4] OMAP IOMMU DTS nodes

[PATCH 0/4] OMAP IOMMU DTS nodes

[Suman Anna]

Hi,

This series includes patches that adds the iommu DT nodes on
OMAP3 (IVA), and OMAP4 and OMAP5 SoCs. It also includes an
updated OMAP3 ISP iommu DT node patch posted previously [1].

Posting the series separately from the driver DT adapation
changes [2]. The series adds the DTS patches in line with the
new OMAP IOMMU bindings [3] posted alongside the DT adaptation.

[1] http://marc.info/?l=linux-omap&m=138728486000628&w=2
[2] http://marc.info/?l=linux-omap&m=139231544416973&w=2
[3] http://marc.info/?l=linux-omap&m=139231545116981&w=2

Florian Vaussard (3):
  ARM: dts: OMAP3: Update ISP IOMMU node
  ARM: dts: OMAP3: Add IVA IOMMU node
  ARM: dts: OMAP4: Add IOMMU nodes

Suman Anna (1):
  ARM: dts: OMAP5: Add IOMMU nodes

 arch/arm/boot/dts/omap3.dtsi | 17 ++++++++++++++---
 arch/arm/boot/dts/omap4.dtsi | 17 +++++++++++++++++
 arch/arm/boot/dts/omap5.dtsi | 17 +++++++++++++++++
 3 files changed, 48 insertions(+), 3 deletions(-)

-- 
1.8.5.3

[PATCH 1/4] ARM: dts: OMAP3: Update ISP IOMMU node

[Suman Anna]

From: Florian Vaussard <florian.vaussard-p8DiymsW2f8@public.gmane.org>

Update the IOMMU node for the camera subsystem as per the
OMAP IOMMU bindings.

Signed-off-by: Florian Vaussard <florian.vaussard-p8DiymsW2f8@public.gmane.org>
[s-anna-l0cyMroinI0@public.gmane.org: corrected interrupt number]
Signed-off-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/omap3.dtsi | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index a5fc83b..ac91cc3 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -411,10 +411,12 @@
 		};
 
 		mmu_isp: mmu@480bd400 {
-			compatible = "ti,omap3-mmu-isp";
-			ti,hwmods = "mmu_isp";
+			compatible = "ti,omap2-iommu";
 			reg = <0x480bd400 0x80>;
-			interrupts = <8>;
+			interrupts = <24>;
+			ti,hwmods = "mmu_isp";
+			ti,#tlb-entries = <8>;
+			dma-window = <0 0xfffff000>;
 		};
 
 		wdt2: wdt@48314000 {
-- 
1.8.5.3

[PATCH 2/4] ARM: dts: OMAP3: Add IVA IOMMU node

[Suman Anna]

From: Florian Vaussard <florian.vaussard-p8DiymsW2f8@public.gmane.org>

Add the DT node for the IOMMU within the DSP subsystem. The entry
is disabled to keep in line with the current hwmod usage.

Signed-off-by: Florian Vaussard <florian.vaussard-p8DiymsW2f8@public.gmane.org>
[s-anna-l0cyMroinI0@public.gmane.org: split the entry and disable the node]
Signed-off-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/omap3.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index ac91cc3..9607187 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -419,6 +419,15 @@
 			dma-window = <0 0xfffff000>;
 		};
 
+		mmu_iva: mmu@5d000000 {
+			compatible = "ti,omap2-iommu";
+			reg = <0x5d000000 0x80>;
+			interrupts = <28>;
+			ti,hwmods = "mmu_iva";
+			dma-window = <0x11000000 0xeefff000>;
+			status = "disabled";
+		};
+
 		wdt2: wdt@48314000 {
 			compatible = "ti,omap3-wdt";
 			reg = <0x48314000 0x80>;
-- 
1.8.5.3

[PATCH 3/4] ARM: dts: OMAP4: Add IOMMU nodes

[Suman Anna]

From: Florian Vaussard <florian.vaussard-p8DiymsW2f8@public.gmane.org>

Add the IOMMU nodes for the DSP and IPU subsystems. The external
address space for DSP starts at 0x20000000 in OMAP4 compared to
0x11000000 in OMAP3, and the addresses beyond 0xE0000000 are
private address space for the Cortex-M3 cores in the IPU subsystem.
The MMU within the IPU sub-system also supports a bus error back
capability, not available on the DSP MMU.

Signed-off-by: Florian Vaussard <florian.vaussard-p8DiymsW2f8@public.gmane.org>
[s-anna-l0cyMroinI0@public.gmane.org: dma-window updates and bus error back addition]
Signed-off-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/omap4.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index d3f8a6e..1885f90 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -461,6 +461,23 @@
 			dma-names = "tx", "rx";
 		};
 
+		mmu_dsp: mmu@4a066000 {
+			compatible = "ti,omap4-iommu";
+			reg = <0x4a066000 0xff>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "mmu_dsp";
+			dma-window = <0x20000000 0xdffff000>;
+		};
+
+		mmu_ipu: mmu@55082000 {
+			compatible = "ti,omap4-iommu";
+			reg = <0x55082000 0xff>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "mmu_ipu";
+			dma-window = <0 0xdffff000>;
+			ti,iommu-bus-err-back;
+		};
+
 		wdt2: wdt@4a314000 {
 			compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 			reg = <0x4a314000 0x80>;
-- 
1.8.5.3

[PATCH 4/4] ARM: dts: OMAP5: Add IOMMU nodes

[Suman Anna]

The IOMMU DT nodes have been added for the DSP and IPU
subsystems. The MMUs in OMAP5 are identical to those in
OMAP4, including the bus error back capability on IPU.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index a72813a..a78fdaa 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -513,6 +513,23 @@
 			dma-names = "tx", "rx";
 		};
 
+		mmu_dsp: mmu@4a066000 {
+			compatible = "ti,omap4-iommu";
+			reg = <0x4a066000 0xff>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "mmu_dsp";
+			dma-window = <0x20000000 0xdffff000>;
+		};
+
+		mmu_ipu: mmu@55082000 {
+			compatible = "ti,omap4-iommu";
+			reg = <0x55082000 0xff>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "mmu_ipu";
+			dma-window = <0 0xdffff000>;
+			ti,iommu-bus-err-back;
+		};
+
 		keypad: keypad@4ae1c000 {
 			compatible = "ti,omap4-keypad";
 			reg = <0x4ae1c000 0x400>;
-- 
1.8.5.3

Re: [PATCH 3/4] ARM: dts: OMAP4: Add IOMMU nodes

[Laurent Pinchart]

Hi Suman,

Thank you for the patch.

On Thursday 13 February 2014 12:22:55 Suman Anna wrote:
> From: Florian Vaussard <florian.vaussard@epfl.ch>
> 
> Add the IOMMU nodes for the DSP and IPU subsystems. The external
> address space for DSP starts at 0x20000000 in OMAP4 compared to
> 0x11000000 in OMAP3, and the addresses beyond 0xE0000000 are
> private address space for the Cortex-M3 cores in the IPU subsystem.
> The MMU within the IPU sub-system also supports a bus error back
> capability, not available on the DSP MMU.
> 
> Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
> [s-anna@ti.com: dma-window updates and bus error back addition]
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  arch/arm/boot/dts/omap4.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index d3f8a6e..1885f90 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -461,6 +461,23 @@
>  			dma-names = "tx", "rx";
>  		};
> 
> +		mmu_dsp: mmu@4a066000 {
> +			compatible = "ti,omap4-iommu";
> +			reg = <0x4a066000 0xff>;
> +			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "mmu_dsp";
> +			dma-window = <0x20000000 0xdffff000>;
> +		};
> +
> +		mmu_ipu: mmu@55082000 {
> +			compatible = "ti,omap4-iommu";
> +			reg = <0x55082000 0xff>;
> +			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "mmu_ipu";
> +			dma-window = <0 0xdffff000>;

I'm not too familiar with the M3 MPU in the OMAP4, but doesn't its memory map 
also include other reserved regions, such as 0x55040000- 0x5505ffff to access 
the ISS ?

> +			ti,iommu-bus-err-back;
> +		};
> +
>  		wdt2: wdt@4a314000 {
>  			compatible = "ti,omap4-wdt", "ti,omap3-wdt";
>  			reg = <0x4a314000 0x80>;

-- 
Regards,

Laurent Pinchart

Re: [PATCH 3/4] ARM: dts: OMAP4: Add IOMMU nodes

[Suman Anna]

Hi Laurent,

On 02/26/2014 03:05 PM, Laurent Pinchart wrote:
> Hi Suman,
>
> Thank you for the patch.
>
> On Thursday 13 February 2014 12:22:55 Suman Anna wrote:
>> From: Florian Vaussard <florian.vaussard-p8DiymsW2f8@public.gmane.org>
>>
>> Add the IOMMU nodes for the DSP and IPU subsystems. The external
>> address space for DSP starts at 0x20000000 in OMAP4 compared to
>> 0x11000000 in OMAP3, and the addresses beyond 0xE0000000 are
>> private address space for the Cortex-M3 cores in the IPU subsystem.
>> The MMU within the IPU sub-system also supports a bus error back
>> capability, not available on the DSP MMU.
>>
>> Signed-off-by: Florian Vaussard <florian.vaussard-p8DiymsW2f8@public.gmane.org>
>> [s-anna-l0cyMroinI0@public.gmane.org: dma-window updates and bus error back addition]
>> Signed-off-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
>> ---
>>   arch/arm/boot/dts/omap4.dtsi | 17 +++++++++++++++++
>>   1 file changed, 17 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index d3f8a6e..1885f90 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -461,6 +461,23 @@
>>   			dma-names = "tx", "rx";
>>   		};
>>
>> +		mmu_dsp: mmu@4a066000 {
>> +			compatible = "ti,omap4-iommu";
>> +			reg = <0x4a066000 0xff>;
>> +			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
>> +			ti,hwmods = "mmu_dsp";
>> +			dma-window = <0x20000000 0xdffff000>;
>> +		};
>> +
>> +		mmu_ipu: mmu@55082000 {
>> +			compatible = "ti,omap4-iommu";
>> +			reg = <0x55082000 0xff>;
>> +			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
>> +			ti,hwmods = "mmu_ipu";
>> +			dma-window = <0 0xdffff000>;
>
> I'm not too familiar with the M3 MPU in the OMAP4, but doesn't its memory map
> also include other reserved regions, such as 0x55040000- 0x5505ffff to access
> the ISS ?

The MMU integration into the M3 MPU subsystem is actually slightly 
different to that seen on DSP in OMAP3. The M3 MPU subsystem actually 
has one additional type of MMU, called the Attribute MMU/Unicache MMU 
immediately after the M3 processor. It is programmed completely from the 
M3, and is used mainly for setting the cache attributes and valid 
address ranges and translations for accessing address ranges like the 
ISS space. The L2 MMU interprets the remaining addresses, so yes, there 
are certain other address ranges that never go through the L2MMU. The 
dma-window values are used by omap-iovmm, but OMAP4 does not make use of 
omap-iovmm.

regards
Suman

>
>> +			ti,iommu-bus-err-back;
>> +		};
>> +
>>   		wdt2: wdt@4a314000 {
>>   			compatible = "ti,omap4-wdt", "ti,omap3-wdt";
>>   			reg = <0x4a314000 0x80>;
>