* [PATCH 01/12] ARM: OMAP2: convert sys_ck and osc_ck to standard clock types
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
@ 2014-02-28 9:22 ` Tero Kristo
[not found] ` <1393579384-23440-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
` (10 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:22 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, mturquette; +Cc: linux-arm-kernel, devicetree
osc_ck can be simply defined as a multiplexer clock, and the sys_ck
can be a simple divider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/Makefile | 3 +-
arch/arm/mach-omap2/cclock2420_data.c | 52 +++++++++++++------------
arch/arm/mach-omap2/cclock2430_data.c | 60 +++++++++++++++-------------
arch/arm/mach-omap2/clkt2xxx_osc.c | 69 ---------------------------------
arch/arm/mach-omap2/clkt2xxx_sys.c | 47 ----------------------
arch/arm/mach-omap2/clock2xxx.h | 2 -
arch/arm/mach-omap2/cm-regbits-24xx.h | 1 +
arch/arm/mach-omap2/pm24xx.c | 4 ++
8 files changed, 67 insertions(+), 171 deletions(-)
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_osc.c
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_sys.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e6eec6f..2c40cc3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -173,10 +173,9 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
+obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
index 3662f4d..3e46ac1 100644
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -57,40 +57,39 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
-static struct clk osc_ck;
+DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
-static const struct clk_ops osc_ck_ops = {
- .recalc_rate = &omap2_osc_clk_recalc,
-};
+DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
-static struct clk_hw_omap osc_ck_hw = {
- .hw = {
- .clk = &osc_ck,
- },
-};
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0);
-static struct clk osc_ck = {
- .name = "osc_ck",
- .ops = &osc_ck_ops,
- .hw = &osc_ck_hw.hw,
- .flags = CLK_IS_ROOT,
+/* 26M ck is a dummy, added to fill the hole in the aplls_clkin parent list */
+static const char *aplls_clkin_ck_parent_names[] = {
+ "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck",
};
+DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0,
+ OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT,
+ OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL);
+
DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-static struct clk sys_ck;
+DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck,
+ 0x0, 2, 1);
-static const char *sys_ck_parent_names[] = {
- "osc_ck",
+static const char *osc_ck_parent_names[] = {
+ "aplls_clkin_ck", "aplls_clkin_x2_ck",
};
-static const struct clk_ops sys_ck_ops = {
- .init = &omap2_init_clk_clkdm,
- .recalc_rate = &omap2xxx_sys_clk_recalc,
-};
+DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0,
+ OMAP2420_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
+ OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
-DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2420_PRCM_CLKSRC_CTRL,
+ OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
static struct dpll_data dpll_dd = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -1741,6 +1740,12 @@ static struct omap_clk omap2420_clks[] = {
/* external root sources */
CLK(NULL, "func_32k_ck", &func_32k_ck),
CLK(NULL, "secure_32k_ck", &secure_32k_ck),
+ CLK(NULL, "virt_12m_ck", &virt_12m_ck),
+ CLK(NULL, "virt_13m_ck", &virt_13m_ck),
+ CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
+ CLK(NULL, "virt_26m_ck", &virt_26m_ck),
+ CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck),
+ CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck),
CLK(NULL, "osc_ck", &osc_ck),
CLK(NULL, "sys_ck", &sys_ck),
CLK(NULL, "alt_ck", &alt_ck),
@@ -1904,7 +1909,6 @@ static const char *enable_init_clks[] = {
int __init omap2420_clk_init(void)
{
- prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_242X;
rate_table = omap2420_rate_table;
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index 5e4b037..582abc2 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -55,42 +55,39 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
-static struct clk osc_ck;
+DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
-static const struct clk_ops osc_ck_ops = {
- .enable = &omap2_enable_osc_ck,
- .disable = omap2_disable_osc_ck,
- .recalc_rate = &omap2_osc_clk_recalc,
-};
+DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
-static struct clk_hw_omap osc_ck_hw = {
- .hw = {
- .clk = &osc_ck,
- },
-};
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-static struct clk osc_ck = {
- .name = "osc_ck",
- .ops = &osc_ck_ops,
- .hw = &osc_ck_hw.hw,
- .flags = CLK_IS_ROOT,
+DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0);
+
+/* 26M ck is a dummy, added to filla hole in the aplls_clkin parent list */
+static const char *aplls_clkin_ck_parent_names[] = {
+ "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck",
};
+DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0,
+ OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT,
+ OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL);
+
DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-static struct clk sys_ck;
+DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck,
+ 0x0, 2, 1);
-static const char *sys_ck_parent_names[] = {
- "osc_ck",
+static const char *osc_ck_parent_names[] = {
+ "aplls_clkin_ck", "aplls_clkin_x2_ck",
};
-static const struct clk_ops sys_ck_ops = {
- .init = &omap2_init_clk_clkdm,
- .recalc_rate = &omap2xxx_sys_clk_recalc,
-};
+DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0,
+ OMAP2430_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
+ OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
-DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2430_PRCM_CLKSRC_CTRL,
+ OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
static struct dpll_data dpll_dd = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -1308,7 +1305,11 @@ static struct clk_hw_omap mdm_osc_ck_hw = {
.clkdm_name = "mdm_clkdm",
};
-DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops);
+static const char *mdm_osc_ck_parent_names[] = {
+ "osc_ck",
+};
+
+DEFINE_STRUCT_CLK(mdm_osc_ck, mdm_osc_ck_parent_names, aes_ick_ops);
static struct clk mmchs1_fck;
@@ -1842,6 +1843,12 @@ static struct omap_clk omap2430_clks[] = {
/* external root sources */
CLK(NULL, "func_32k_ck", &func_32k_ck),
CLK(NULL, "secure_32k_ck", &secure_32k_ck),
+ CLK(NULL, "virt_12m_ck", &virt_12m_ck),
+ CLK(NULL, "virt_13m_ck", &virt_13m_ck),
+ CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
+ CLK(NULL, "virt_26m_ck", &virt_26m_ck),
+ CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck),
+ CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck),
CLK(NULL, "osc_ck", &osc_ck),
CLK("twl", "fck", &osc_ck),
CLK(NULL, "sys_ck", &sys_ck),
@@ -2021,7 +2028,6 @@ static const char *enable_init_clks[] = {
int __init omap2430_clk_init(void)
{
- prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_243X;
rate_table = omap2430_rate_table;
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
deleted file mode 100644
index 19f54d4..0000000
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * OMAP2xxx osc_clk-specific clock code
- *
- * Copyright (C) 2005-2008 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
- *
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
- *
- * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- * Gordon McNutt and RidgeRun, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#undef DEBUG
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "clock.h"
-#include "clock2xxx.h"
-#include "prm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
-
-/*
- * XXX This does not actually enable the osc_ck, since the osc_ck must
- * be running for this function to be called. Instead, this function
- * is used to disable an autoidle mode on the osc_ck. The existing
- * clk_enable/clk_disable()-based usecounting for osc_ck should be
- * replaced with autoidle-based usecounting.
- */
-int omap2_enable_osc_ck(struct clk_hw *clk)
-{
- u32 pcc;
-
- pcc = __raw_readl(prcm_clksrc_ctrl);
-
- __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-
- return 0;
-}
-
-/*
- * XXX This does not actually disable the osc_ck, since doing so would
- * immediately halt the system. Instead, this function is used to
- * enable an autoidle mode on the osc_ck. The existing
- * clk_enable/clk_disable()-based usecounting for osc_ck should be
- * replaced with autoidle-based usecounting.
- */
-void omap2_disable_osc_ck(struct clk_hw *clk)
-{
- u32 pcc;
-
- pcc = __raw_readl(prcm_clksrc_ctrl);
-
- __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-}
-
-unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
- unsigned long parent_rate)
-{
- return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
-}
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
deleted file mode 100644
index f467d07..0000000
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * OMAP2xxx sys_clk-specific clock code
- *
- * Copyright (C) 2005-2008 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
- *
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
- *
- * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- * Gordon McNutt and RidgeRun, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "clock.h"
-#include "clock2xxx.h"
-#include "prm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
-
-void __iomem *prcm_clksrc_ctrl;
-
-u32 omap2xxx_get_sysclkdiv(void)
-{
- u32 div;
-
- div = __raw_readl(prcm_clksrc_ctrl);
- div &= OMAP_SYSCLKDIV_MASK;
- div >>= OMAP_SYSCLKDIV_SHIFT;
-
- return div;
-}
-
-unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
- unsigned long parent_rate)
-{
- return parent_rate / omap2xxx_get_sysclkdiv();
-}
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index 539dc08..8d52a0c 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -49,8 +49,6 @@ int omap2430_clk_init(void);
#define omap2430_clk_init() do { } while(0)
#endif
-extern void __iomem *prcm_clksrc_ctrl;
-
extern struct clk_hw *dclk_hw;
int omap2_enable_osc_ck(struct clk_hw *hw);
void omap2_disable_osc_ck(struct clk_hw *hw);
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 8538669..d7a5d11 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -107,6 +107,7 @@
#define OMAP24XX_AUTO_DPLL_SHIFT 0
#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
#define OMAP24XX_APLLS_CLKIN_SHIFT 23
+#define OMAP24XX_APLLS_CLKIN_WIDTH 3
#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 8c07594..2dbc30c 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -251,6 +251,10 @@ static void __init prcm_setup_regs(void)
/* Enable wake-up events */
omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
WKUP_MOD, PM_WKEN);
+
+ /* Enable SYS_CLKEN control when all domains idle */
+ omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
+ OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
}
int __init omap2_pm_init(void)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread[parent not found: <1393579384-23440-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>]
* [PATCH 02/12] ARM: OMAP2420: clock: get rid of fixed-div property use
[not found] ` <1393579384-23440-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
@ 2014-02-28 9:22 ` Tero Kristo
2014-02-28 9:22 ` [PATCH 05/12] CLK: TI: APLL: add support for omap2 aplls Tero Kristo
1 sibling, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:22 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cleans up the code a bit and is useful for clock data DT conversion.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/cclock2420_data.c | 15 ++++-----------
arch/arm/mach-omap2/clock.c | 21 ---------------------
arch/arm/mach-omap2/clock.h | 3 ---
3 files changed, 4 insertions(+), 35 deletions(-)
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
index 3e46ac1..3b0beea 100644
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -1025,18 +1025,12 @@ DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
dsp_fck_parent_names, dsp_fck_ops);
+DEFINE_CLK_FIXED_FACTOR(iva1_ifck_div, "iva1_ifck", &iva1_ifck, 0x0, 1, 2);
+
static struct clk iva1_mpu_int_ifck;
static const char *iva1_mpu_int_ifck_parent_names[] = {
- "iva1_ifck",
-};
-
-static const struct clk_ops iva1_mpu_int_ifck_ops = {
- .init = &omap2_init_clk_clkdm,
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
- .recalc_rate = &omap_fixed_divisor_recalc,
+ "iva1_ifck_div",
};
static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
@@ -1047,11 +1041,10 @@ static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
.clkdm_name = "iva1_clkdm",
- .fixed_div = 2,
};
DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
- iva1_mpu_int_ifck_ops);
+ aes_ick_ops);
static struct clk mailboxes_ick;
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 591581a..4ac6e3d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -82,27 +82,6 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
}
/*
- * Used for clocks that have the same value as the parent clock,
- * divided by some factor
- */
-unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct clk_hw_omap *oclk;
-
- if (!hw) {
- pr_warn("%s: hw is NULL\n", __func__);
- return -EINVAL;
- }
-
- oclk = to_clk_hw_omap(hw);
-
- WARN_ON(!oclk->fixed_div);
-
- return parent_rate / oclk->fixed_div;
-}
-
-/*
* OMAP2+ specific clock functions
*/
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index bda767a..3843c9f 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -189,9 +189,6 @@ struct clk_hw_omap_ops {
void (*deny_idle)(struct clk_hw_omap *oclk);
};
-unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
- unsigned long parent_rate);
-
/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
#define CORE_CLK_SRC_32K 0x0
#define CORE_CLK_SRC_DPLL 0x1
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 05/12] CLK: TI: APLL: add support for omap2 aplls
[not found] ` <1393579384-23440-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
2014-02-28 9:22 ` [PATCH 02/12] ARM: OMAP2420: clock: get rid of fixed-div property use Tero Kristo
@ 2014-02-28 9:22 ` Tero Kristo
2014-02-28 19:14 ` Nishanth Menon
1 sibling, 1 reply; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:22 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, nm-l0cyMroinI0,
mturquette-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
This patch adds support for omap2 type aplls, which have gating and
autoidle functionality.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
.../devicetree/bindings/clock/ti/apll.txt | 21 ++-
arch/arm/mach-omap2/clock.h | 11 --
drivers/clk/ti/apll.c | 180 ++++++++++++++++++++
include/linux/clk/ti.h | 21 ++-
4 files changed, 216 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt
index 7faf5a6..61ecd30 100644
--- a/Documentation/devicetree/bindings/clock/ti/apll.txt
+++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
@@ -14,18 +14,29 @@ a subtype of a DPLL [2], although a simplified one at that.
[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
Required properties:
-- compatible : shall be "ti,dra7-apll-clock"
+- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
- reg : address and length of the register set for controlling the APLL.
It contains the information of registers in the following order:
- "control" - contains the control register base address
- "idlest" - contains the idlest register base address
+ "control" - contains the control register offset
+ "idlest" - contains the idlest register offset
+ "autoidle" - contains the autoidle register offset (OMAP2 only)
Examples:
- apll_pcie_ck: apll_pcie_ck@4a008200 {
+ apll_pcie_ck: apll_pcie_ck {
#clock-cells = <0>;
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
- reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
+ reg = <0x021c>, <0x0220>;
compatible = "ti,dra7-apll-clock";
};
+
+ apll96_ck: apll96_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap2-apll-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <2>;
+ ti,idlest-shift = <8>;
+ ti,clock-frequency = <96000000>;
+ reg = <0x0500>, <0x0530>, <0x0520>;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7057f37..7b7a03c 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -178,17 +178,6 @@ struct clksel {
const struct clksel_rate *rates;
};
-struct clk_hw_omap_ops {
- void (*find_idlest)(struct clk_hw_omap *oclk,
- void __iomem **idlest_reg,
- u8 *idlest_bit, u8 *idlest_val);
- void (*find_companion)(struct clk_hw_omap *oclk,
- void __iomem **other_reg,
- u8 *other_bit);
- void (*allow_idle)(struct clk_hw_omap *oclk);
- void (*deny_idle)(struct clk_hw_omap *oclk);
-};
-
/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
#define CORE_CLK_SRC_32K 0x0
#define CORE_CLK_SRC_DPLL 0x1
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index b986f61..60b2427 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -221,3 +221,183 @@ cleanup:
kfree(init);
}
CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
+
+#define OMAP2_EN_APLL_LOCKED 0x3
+#define OMAP2_EN_APLL_STOPPED 0x0
+
+static int omap2_apll_is_enabled(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ struct dpll_data *ad = clk->dpll_data;
+ u32 v;
+
+ v = ti_clk_ll_ops->clk_readl(ad->control_reg);
+ v &= ad->enable_mask;
+
+ v >>= __ffs(ad->enable_mask);
+
+ return v == OMAP2_EN_APLL_LOCKED ? 1 : 0;
+}
+
+static unsigned long omap2_apll_recalc(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+
+ if (omap2_apll_is_enabled(hw))
+ return clk->fixed_rate;
+
+ return 0;
+}
+
+static int omap2_apll_enable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ struct dpll_data *ad = clk->dpll_data;
+ u32 v;
+ int i = 0;
+
+ v = ti_clk_ll_ops->clk_readl(ad->control_reg);
+ v &= ~ad->enable_mask;
+ v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
+ ti_clk_ll_ops->clk_writel(v, ad->control_reg);
+
+ while (1) {
+ v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
+ if (v & ad->idlest_mask)
+ break;
+ if (i > MAX_APLL_WAIT_TRIES)
+ break;
+ i++;
+ udelay(1);
+ }
+
+ if (i == MAX_APLL_WAIT_TRIES) {
+ pr_warn("%s failed to transition to locked\n",
+ __clk_get_name(clk->hw.clk));
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static void omap2_apll_disable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ struct dpll_data *ad = clk->dpll_data;
+ u32 v;
+
+ v = ti_clk_ll_ops->clk_readl(ad->control_reg);
+ v &= ~ad->enable_mask;
+ v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
+ ti_clk_ll_ops->clk_writel(v, ad->control_reg);
+}
+
+static struct clk_ops omap2_apll_ops = {
+ .enable = &omap2_apll_enable,
+ .disable = &omap2_apll_disable,
+ .is_enabled = &omap2_apll_is_enabled,
+ .recalc_rate = &omap2_apll_recalc,
+};
+
+static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val)
+{
+ struct dpll_data *ad = clk->dpll_data;
+ u32 v;
+
+ v = ti_clk_ll_ops->clk_readl(ad->autoidle_reg);
+ v &= ~ad->autoidle_mask;
+ v |= val << __ffs(ad->autoidle_mask);
+ ti_clk_ll_ops->clk_writel(v, ad->control_reg);
+}
+
+#define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
+#define OMAP2_APLL_AUTOIDLE_DISABLE 0x0
+
+static void omap2_apll_allow_idle(struct clk_hw_omap *clk)
+{
+ omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP);
+}
+
+static void omap2_apll_deny_idle(struct clk_hw_omap *clk)
+{
+ omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE);
+}
+
+static struct clk_hw_omap_ops omap2_apll_hwops = {
+ .allow_idle = &omap2_apll_allow_idle,
+ .deny_idle = &omap2_apll_deny_idle,
+};
+
+static void __init of_omap2_apll_setup(struct device_node *node)
+{
+ struct dpll_data *ad = NULL;
+ struct clk_hw_omap *clk_hw = NULL;
+ struct clk_init_data *init = NULL;
+ struct clk *clk;
+ const char *parent_name;
+ u32 val;
+
+ ad = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ init = kzalloc(sizeof(*init), GFP_KERNEL);
+
+ if (!ad || !clk_hw || !init)
+ goto cleanup;
+
+ clk_hw->dpll_data = ad;
+ clk_hw->hw.init = init;
+ init->ops = &omap2_apll_ops;
+ init->name = node->name;
+ clk_hw->ops = &omap2_apll_hwops;
+
+ init->num_parents = of_clk_get_parent_count(node);
+ if (init->num_parents != 1) {
+ pr_err("%s must have one parent\n", node->name);
+ goto cleanup;
+ }
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ init->parent_names = &parent_name;
+
+ if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
+ pr_err("%s missing clock-frequency\n", node->name);
+ goto cleanup;
+ }
+ clk_hw->fixed_rate = val;
+
+ if (of_property_read_u32(node, "ti,bit-shift", &val)) {
+ pr_err("%s missing bit-shift\n", node->name);
+ goto cleanup;
+ }
+
+ clk_hw->enable_bit = val;
+ ad->enable_mask = 0x3 << val;
+ ad->autoidle_mask = 0x3 << val;
+
+ if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
+ pr_err("%s missing idlest-shift\n", node->name);
+ goto cleanup;
+ }
+
+ ad->idlest_mask = 1 << val;
+
+ ad->control_reg = ti_clk_get_reg_addr(node, 0);
+ ad->autoidle_reg = ti_clk_get_reg_addr(node, 1);
+ ad->idlest_reg = ti_clk_get_reg_addr(node, 2);
+
+ if (!ad->control_reg || !ad->autoidle_reg || !ad->idlest_reg)
+ goto cleanup;
+
+ clk = clk_register(NULL, &clk_hw->hw);
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ kfree(init);
+ return;
+ }
+cleanup:
+ kfree(clk_hw);
+ kfree(init);
+}
+CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",
+ of_omap2_apll_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 2310adc..ddac0d0 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -94,7 +94,26 @@ struct dpll_data {
u8 flags;
};
-struct clk_hw_omap_ops;
+struct clk_hw_omap;
+
+/**
+ * struct clk_hw_omap_ops - OMAP clk ops
+ * @find_idlest: find idlest register information for a clock
+ * @find_companion: find companion clock register information for a clock,
+ * basically converts CM_ICLKEN* <-> CM_FCLKEN*
+ * @allow_idle: enables autoidle hardware functionality for a clock
+ * @deny_idle: prevent autoidle hardware functionality for a clock
+ */
+struct clk_hw_omap_ops {
+ void (*find_idlest)(struct clk_hw_omap *oclk,
+ void __iomem **idlest_reg,
+ u8 *idlest_bit, u8 *idlest_val);
+ void (*find_companion)(struct clk_hw_omap *oclk,
+ void __iomem **other_reg,
+ u8 *other_bit);
+ void (*allow_idle)(struct clk_hw_omap *oclk);
+ void (*deny_idle)(struct clk_hw_omap *oclk);
+};
/**
* struct clk_hw_omap - OMAP struct clk
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 05/12] CLK: TI: APLL: add support for omap2 aplls
2014-02-28 9:22 ` [PATCH 05/12] CLK: TI: APLL: add support for omap2 aplls Tero Kristo
@ 2014-02-28 19:14 ` Nishanth Menon
0 siblings, 0 replies; 22+ messages in thread
From: Nishanth Menon @ 2014-02-28 19:14 UTC (permalink / raw)
To: Tero Kristo, linux-omap, paul, tony, mturquette
Cc: devicetree, linux-arm-kernel
On 02/28/2014 03:22 AM, Tero Kristo wrote:
[...]
> +static void __init of_omap2_apll_setup(struct device_node *node)
> +{
> + struct dpll_data *ad = NULL;
> + struct clk_hw_omap *clk_hw = NULL;
> + struct clk_init_data *init = NULL;
> + struct clk *clk;
> + const char *parent_name;
> + u32 val;
> +
> + ad = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
> + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
> + init = kzalloc(sizeof(*init), GFP_KERNEL);
> +
> + if (!ad || !clk_hw || !init)
> + goto cleanup;
> +
> + clk_hw->dpll_data = ad;
> + clk_hw->hw.init = init;
> + init->ops = &omap2_apll_ops;
> + init->name = node->name;
> + clk_hw->ops = &omap2_apll_hwops;
> +
> + init->num_parents = of_clk_get_parent_count(node);
> + if (init->num_parents != 1) {
> + pr_err("%s must have one parent\n", node->name);
> + goto cleanup;
> + }
> +
> + parent_name = of_clk_get_parent_name(node, 0);
> + init->parent_names = &parent_name;
> +
> + if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
> + pr_err("%s missing clock-frequency\n", node->name);
> + goto cleanup;
> + }
> + clk_hw->fixed_rate = val;
> +
> + if (of_property_read_u32(node, "ti,bit-shift", &val)) {
> + pr_err("%s missing bit-shift\n", node->name);
> + goto cleanup;
> + }
> +
> + clk_hw->enable_bit = val;
> + ad->enable_mask = 0x3 << val;
> + ad->autoidle_mask = 0x3 << val;
> +
> + if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
> + pr_err("%s missing idlest-shift\n", node->name);
> + goto cleanup;
> + }
> +
> + ad->idlest_mask = 1 << val;
> +
> + ad->control_reg = ti_clk_get_reg_addr(node, 0);
> + ad->autoidle_reg = ti_clk_get_reg_addr(node, 1);
> + ad->idlest_reg = ti_clk_get_reg_addr(node, 2);
> +
> + if (!ad->control_reg || !ad->autoidle_reg || !ad->idlest_reg)
> + goto cleanup;
> +
> + clk = clk_register(NULL, &clk_hw->hw);
> + if (!IS_ERR(clk)) {
> + of_clk_add_provider(node, of_clk_src_simple_get, clk);
> + kfree(init);
> + return;
> + }
> +cleanup:
> + kfree(clk_hw);
> + kfree(init);
kfree(ad)?
smatch reported (as part of the kernel_patch_verify_report:
+drivers/clk/ti/apll.c:400 of_omap2_apll_setup() warn: possible memory
leak of 'ad'
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 03/12] CLK: TI: DPLL: simplify autoidle register detection logic
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
2014-02-28 9:22 ` [PATCH 01/12] ARM: OMAP2: convert sys_ck and osc_ck to standard clock types Tero Kristo
[not found] ` <1393579384-23440-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
@ 2014-02-28 9:22 ` Tero Kristo
2014-02-28 9:22 ` [PATCH 04/12] CLK: TI: DPLL: add support for omap2 core dpll Tero Kristo
` (8 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:22 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, mturquette; +Cc: linux-arm-kernel, devicetree
AMxxxx dpll_data previously had autoidle_mask set, even if these SoC:s
don't have autoidle register. Remove the bit-field value as it is unused,
also drop the unnecessary DPLL_HAS_AUTOIDLE flag passing during init,
as we can just simply check against the contents of the autoidle_mask.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/dpll.c | 39 +++++++++++++++------------------------
1 file changed, 15 insertions(+), 24 deletions(-)
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 7e498a4..dda262d 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -25,8 +25,6 @@
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
-#define DPLL_HAS_AUTOIDLE 0x1
-
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX)
static const struct clk_ops dpll_m4xen_ck_ops = {
@@ -193,14 +191,12 @@ static void ti_clk_register_dpll_x2(struct device_node *node,
* @node: device node containing the DPLL info
* @ops: ops for the DPLL
* @ddt: DPLL data template to use
- * @init_flags: flags for controlling init types
*
* Initializes a DPLL clock from device tree data.
*/
static void __init of_ti_dpll_setup(struct device_node *node,
const struct clk_ops *ops,
- const struct dpll_data *ddt,
- u8 init_flags)
+ const struct dpll_data *ddt)
{
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
@@ -247,7 +243,7 @@ static void __init of_ti_dpll_setup(struct device_node *node,
if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg)
goto cleanup;
- if (init_flags & DPLL_HAS_AUTOIDLE) {
+ if (dd->autoidle_mask) {
dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
if (!dd->autoidle_reg)
goto cleanup;
@@ -310,7 +306,7 @@ static void __init of_ti_omap3_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+ of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
of_ti_omap3_dpll_setup);
@@ -329,7 +325,7 @@ static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
.freqsel_mask = 0xf0,
};
- of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+ of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
of_ti_omap3_core_dpll_setup);
@@ -349,7 +345,7 @@ static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+ of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
of_ti_omap3_per_dpll_setup);
@@ -371,7 +367,7 @@ static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+ of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
of_ti_omap3_per_jtype_dpll_setup);
@@ -391,7 +387,7 @@ static void __init of_ti_omap4_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+ of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
of_ti_omap4_dpll_setup);
@@ -410,7 +406,7 @@ static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+ of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
of_ti_omap4_core_dpll_setup);
@@ -433,7 +429,7 @@ static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+ of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
of_ti_omap4_m4xen_dpll_setup);
@@ -454,7 +450,7 @@ static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+ of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
of_ti_omap4_jtype_dpll_setup);
@@ -465,7 +461,6 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
- .autoidle_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
@@ -474,7 +469,7 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
+ of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
of_ti_am3_no_gate_dpll_setup);
@@ -484,7 +479,6 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
- .autoidle_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 4095,
@@ -494,7 +488,7 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
+ of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
of_ti_am3_jtype_dpll_setup);
@@ -504,7 +498,6 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
- .autoidle_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
@@ -514,7 +507,7 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
+ of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
"ti,am3-dpll-no-gate-j-type-clock",
@@ -525,7 +518,6 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
- .autoidle_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
@@ -534,7 +526,7 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
+ of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
@@ -543,7 +535,6 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
- .autoidle_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
@@ -552,7 +543,7 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
- of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, 0);
+ of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
of_ti_am3_core_dpll_setup);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 04/12] CLK: TI: DPLL: add support for omap2 core dpll
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
` (2 preceding siblings ...)
2014-02-28 9:22 ` [PATCH 03/12] CLK: TI: DPLL: simplify autoidle register detection logic Tero Kristo
@ 2014-02-28 9:22 ` Tero Kristo
2014-02-28 9:22 ` [PATCH 06/12] CLK: TI: gate: fixed DT binding documentation bugs Tero Kristo
` (7 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:22 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, mturquette; +Cc: linux-arm-kernel, devicetree
OMAP2 has slightly different DPLL compared to later OMAP generations.
This patch adds support for the ti,omap2-dpll-core-clock and also adds
the bindings documentation.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/dpll.txt | 9 ++++
arch/arm/mach-omap2/clock.h | 1 -
arch/arm/mach-omap2/clock2xxx.h | 4 --
drivers/clk/ti/dpll.c | 45 ++++++++++++++++++--
include/linux/clk/ti.h | 6 +++
5 files changed, 57 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
index 30bfdb7..50a1a42 100644
--- a/Documentation/devicetree/bindings/clock/ti/dpll.txt
+++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
@@ -30,6 +30,7 @@ Required properties:
"ti,am3-dpll-clock",
"ti,am3-dpll-core-clock",
"ti,am3-dpll-x2-clock",
+ "ti,omap2-dpll-core-clock",
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks, first entry lists reference clock
@@ -41,6 +42,7 @@ Required properties:
"mult-div1" - contains the multiplier / divider register base address
"autoidle" - contains the autoidle register base address (optional)
ti,am3-* dpll types do not have autoidle register
+ ti,omap2-* dpll type does not support idlest / autoidle registers
Optional properties:
- DPLL mode setting - defining any one or more of the following overrides
@@ -73,3 +75,10 @@ Examples:
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x90>, <0x5c>, <0x68>;
};
+
+ dpll_ck: dpll_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap2-dpll-core-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x0500>, <0x0540>;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 3843c9f..7057f37 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -276,7 +276,6 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
extern const struct clk_hw_omap_ops clkhwops_apll54;
extern const struct clk_hw_omap_ops clkhwops_apll96;
-extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
/* clksel_rate blocks shared between OMAP44xx and AM33xx */
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index 8d52a0c..a090225 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -21,10 +21,6 @@ unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
unsigned long parent_rate);
unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
unsigned long parent_rate);
-unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
- unsigned long parent_rate);
-int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
- unsigned long parent_rate);
void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
unsigned long parent_rate);
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index dda262d..bb2c0c4 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -42,6 +42,15 @@ static const struct clk_ops dpll_core_ck_ops = {
.get_parent = &omap2_init_dpll_parent,
};
+#ifdef CONFIG_ARCH_OMAP2
+static const struct clk_ops omap2_dpll_core_ck_ops = {
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap2_dpllcore_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap2_reprogram_dpllcore,
+};
+#endif
+
#ifdef CONFIG_ARCH_OMAP3
static const struct clk_ops omap3_dpll_core_ck_ops = {
.get_parent = &omap2_init_dpll_parent,
@@ -237,10 +246,25 @@ static void __init of_ti_dpll_setup(struct device_node *node,
init->parent_names = parent_names;
dd->control_reg = ti_clk_get_reg_addr(node, 0);
- dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
- dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
- if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg)
+ /*
+ * Special case for OMAP2 DPLL, register order is different due to
+ * missing idlest_reg, also clkhwops is different. Detected from
+ * missing idlest_mask.
+ */
+ if (!dd->idlest_mask) {
+ dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
+ clk_hw->ops = &clkhwops_omap2xxx_dpll;
+ omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
+ } else {
+ dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
+ if (!dd->idlest_reg)
+ goto cleanup;
+
+ dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
+ }
+
+ if (!dd->control_reg || !dd->mult_div1_reg)
goto cleanup;
if (dd->autoidle_mask) {
@@ -547,3 +571,18 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
}
CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
of_ti_am3_core_dpll_setup);
+
+static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .enable_mask = 0x3,
+ .mult_mask = 0x3ff << 12,
+ .div1_mask = 0xf << 8,
+ .max_divider = 16,
+ .min_divider = 1,
+ };
+
+ of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
+}
+CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
+ of_ti_omap2_core_dpll_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 092b641..2310adc 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -255,6 +255,11 @@ int omap2_dflt_clk_enable(struct clk_hw *hw);
void omap2_dflt_clk_disable(struct clk_hw *hw);
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void omap3_clk_lock_dpll5(void);
+unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
+ unsigned long parent_rate);
+int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
+ unsigned long parent_rate);
+void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
@@ -283,6 +288,7 @@ static inline void of_ti_clk_allow_autoidle_all(void) { }
static inline void of_ti_clk_deny_autoidle_all(void) { }
#endif
+extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_wait;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 06/12] CLK: TI: gate: fixed DT binding documentation bugs
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
` (3 preceding siblings ...)
2014-02-28 9:22 ` [PATCH 04/12] CLK: TI: DPLL: add support for omap2 core dpll Tero Kristo
@ 2014-02-28 9:22 ` Tero Kristo
2014-02-28 9:22 ` [PATCH 07/12] CLK: TI: interface: add support for omap2430 specific interface clock Tero Kristo
` (6 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:22 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, mturquette; +Cc: linux-arm-kernel, devicetree
ti,composite-gate-clock documentation was missing, also the register
offset examples were wrong.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/gate.txt | 29 +++++++++++++++++---
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
index 125281a..03f8fde 100644
--- a/Documentation/devicetree/bindings/clock/ti/gate.txt
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
@@ -25,6 +25,11 @@ Required properties:
to map clockdomains properly
"ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
required for a hardware errata
+ "ti,composite-gate-clock" - composite gate clock, to be part of composite
+ clock
+ "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
+ for clock to be active before returning
+ from clk_enable()
- #clock-cells : from common clock binding; shall be set to 0
- clocks : link to phandle of parent clock
- reg : offset for register controlling adjustable gate, not needed for
@@ -41,7 +46,7 @@ Examples:
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&core_96m_fck>;
- reg = <0x48004a00 0x4>;
+ reg = <0x0a00>;
ti,bit-shift = <25>;
};
@@ -57,7 +62,7 @@ Examples:
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&dpll4_m4x2_ck>;
- reg = <0x48004e00 0x4>;
+ reg = <0x0e00>;
ti,bit-shift = <0>;
};
@@ -65,7 +70,7 @@ Examples:
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
- reg = <0x4800259c 0x4>;
+ reg = <0x059c>;
ti,bit-shift = <1>;
};
@@ -80,6 +85,22 @@ Examples:
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m2x2_mul_ck>;
ti,bit-shift = <0x1b>;
- reg = <0x48004d00 0x4>;
+ reg = <0x0d00>;
ti,set-bit-to-disable;
};
+
+ vlynq_gate_fck: vlynq_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x0200>;
+ };
+
+ sys_clkout2_src_gate: sys_clkout2_src_gate {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <15>;
+ reg = <0x0070>;
+ };
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 07/12] CLK: TI: interface: add support for omap2430 specific interface clock
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
` (4 preceding siblings ...)
2014-02-28 9:22 ` [PATCH 06/12] CLK: TI: gate: fixed DT binding documentation bugs Tero Kristo
@ 2014-02-28 9:22 ` Tero Kristo
2014-02-28 9:23 ` [PATCH 08/12] CLK: TI: OMAP2: add clock init support Tero Kristo
` (5 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:22 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, mturquette; +Cc: linux-arm-kernel, devicetree
OMAP2430 I2CHS modules require specific hardware ops to be used, so added
a new compatible string for this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/interface.txt | 2 ++
arch/arm/mach-omap2/clock.h | 1 -
drivers/clk/ti/interface.c | 7 +++++++
include/linux/clk/ti.h | 1 +
4 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt
index 064e8ca..3111a40 100644
--- a/Documentation/devicetree/bindings/clock/ti/interface.txt
+++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
@@ -21,6 +21,8 @@ Required properties:
"ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
"ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
"ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
+ "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
+ handling
- #clock-cells : from common clock binding; shall be set to 0
- clocks : link to phandle of parent clock
- reg : base address for the control register
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7b7a03c..bb67238 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -265,7 +265,6 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
extern const struct clk_hw_omap_ops clkhwops_apll54;
extern const struct clk_hw_omap_ops clkhwops_apll96;
-extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
/* clksel_rate blocks shared between OMAP44xx and AM33xx */
extern const struct clksel_rate div_1_0_rates[];
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index 320a2b1..4b1c336 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -123,3 +123,10 @@ static void __init of_ti_am35xx_interface_clk_setup(struct device_node *node)
}
CLK_OF_DECLARE(ti_am35xx_interface_clk, "ti,am35xx-interface-clock",
of_ti_am35xx_interface_clk_setup);
+
+static void __init of_ti_omap2430_interface_clk_setup(struct device_node *node)
+{
+ _of_ti_interface_clk_setup(node, &clkhwops_omap2430_i2chs_wait);
+}
+CLK_OF_DECLARE(ti_omap2430_interface_clk, "ti,omap2430-interface-clock",
+ of_ti_omap2430_interface_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index ddac0d0..4a05d97 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -308,6 +308,7 @@ static inline void of_ti_clk_deny_autoidle_all(void) { }
#endif
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
+extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_wait;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 08/12] CLK: TI: OMAP2: add clock init support
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
` (5 preceding siblings ...)
2014-02-28 9:22 ` [PATCH 07/12] CLK: TI: interface: add support for omap2430 specific interface clock Tero Kristo
@ 2014-02-28 9:23 ` Tero Kristo
2014-02-28 9:23 ` [PATCH 09/12] ARM: dts: omap2 clock data Tero Kristo
` (4 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:23 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, mturquette; +Cc: linux-arm-kernel, devicetree
Adds support for registering the alias clocks, boot time clock-enable list
and disabling autoidle of clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-2xxx.c | 254 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 2 +
3 files changed, 257 insertions(+)
create mode 100644 drivers/clk/ti/clk-2xxx.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 4319d40..4a67706 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,6 +3,7 @@ obj-y += clk.o autoidle.o clockdomain.o
clk-common = dpll.o composite.o divider.o gate.o \
fixed-factor.o mux.o apll.o
obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
+obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) clk-2xxx.o
obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o clk-3xxx.o
obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o
diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c
new file mode 100644
index 0000000..f6400fb
--- /dev/null
+++ b/drivers/clk/ti/clk-2xxx.c
@@ -0,0 +1,254 @@
+/*
+ * OMAP2 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+static struct ti_dt_clk omap2xxx_clks[] = {
+ DT_CLK(NULL, "func_32k_ck", "func_32k_ck"),
+ DT_CLK(NULL, "secure_32k_ck", "secure_32k_ck"),
+ DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
+ DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_26m_ck", "virt_26m_ck"),
+ DT_CLK(NULL, "aplls_clkin_ck", "aplls_clkin_ck"),
+ DT_CLK(NULL, "aplls_clkin_x2_ck", "aplls_clkin_x2_ck"),
+ DT_CLK(NULL, "osc_ck", "osc_ck"),
+ DT_CLK(NULL, "sys_ck", "sys_ck"),
+ DT_CLK(NULL, "alt_ck", "alt_ck"),
+ DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
+ DT_CLK(NULL, "dpll_ck", "dpll_ck"),
+ DT_CLK(NULL, "apll96_ck", "apll96_ck"),
+ DT_CLK(NULL, "apll54_ck", "apll54_ck"),
+ DT_CLK(NULL, "func_54m_ck", "func_54m_ck"),
+ DT_CLK(NULL, "core_ck", "core_ck"),
+ DT_CLK(NULL, "func_96m_ck", "func_96m_ck"),
+ DT_CLK(NULL, "func_48m_ck", "func_48m_ck"),
+ DT_CLK(NULL, "func_12m_ck", "func_12m_ck"),
+ DT_CLK(NULL, "sys_clkout_src", "sys_clkout_src"),
+ DT_CLK(NULL, "sys_clkout", "sys_clkout"),
+ DT_CLK(NULL, "emul_ck", "emul_ck"),
+ DT_CLK(NULL, "mpu_ck", "mpu_ck"),
+ DT_CLK(NULL, "dsp_fck", "dsp_fck"),
+ DT_CLK(NULL, "gfx_3d_fck", "gfx_3d_fck"),
+ DT_CLK(NULL, "gfx_2d_fck", "gfx_2d_fck"),
+ DT_CLK(NULL, "gfx_ick", "gfx_ick"),
+ DT_CLK("omapdss_dss", "ick", "dss_ick"),
+ DT_CLK(NULL, "dss_ick", "dss_ick"),
+ DT_CLK(NULL, "dss1_fck", "dss1_fck"),
+ DT_CLK(NULL, "dss2_fck", "dss2_fck"),
+ DT_CLK(NULL, "dss_54m_fck", "dss_54m_fck"),
+ DT_CLK(NULL, "core_l3_ck", "core_l3_ck"),
+ DT_CLK(NULL, "ssi_fck", "ssi_ssr_sst_fck"),
+ DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
+ DT_CLK(NULL, "l4_ck", "l4_ck"),
+ DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
+ DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
+ DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
+ DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
+ DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
+ DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
+ DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
+ DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
+ DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
+ DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
+ DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
+ DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
+ DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
+ DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
+ DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
+ DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
+ DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
+ DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
+ DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
+ DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
+ DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
+ DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
+ DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
+ DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
+ DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
+ DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
+ DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
+ DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
+ DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
+ DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
+ DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
+ DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
+ DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
+ DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
+ DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
+ DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
+ DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
+ DT_CLK(NULL, "uart1_ick", "uart1_ick"),
+ DT_CLK(NULL, "uart1_fck", "uart1_fck"),
+ DT_CLK(NULL, "uart2_ick", "uart2_ick"),
+ DT_CLK(NULL, "uart2_fck", "uart2_fck"),
+ DT_CLK(NULL, "uart3_ick", "uart3_ick"),
+ DT_CLK(NULL, "uart3_fck", "uart3_fck"),
+ DT_CLK(NULL, "gpios_ick", "gpios_ick"),
+ DT_CLK(NULL, "gpios_fck", "gpios_fck"),
+ DT_CLK("omap_wdt", "ick", "mpu_wdt_ick"),
+ DT_CLK(NULL, "mpu_wdt_ick", "mpu_wdt_ick"),
+ DT_CLK(NULL, "mpu_wdt_fck", "mpu_wdt_fck"),
+ DT_CLK(NULL, "sync_32k_ick", "sync_32k_ick"),
+ DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
+ DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
+ DT_CLK("omap24xxcam", "fck", "cam_fck"),
+ DT_CLK(NULL, "cam_fck", "cam_fck"),
+ DT_CLK("omap24xxcam", "ick", "cam_ick"),
+ DT_CLK(NULL, "cam_ick", "cam_ick"),
+ DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
+ DT_CLK(NULL, "wdt4_ick", "wdt4_ick"),
+ DT_CLK(NULL, "wdt4_fck", "wdt4_fck"),
+ DT_CLK(NULL, "mspro_ick", "mspro_ick"),
+ DT_CLK(NULL, "mspro_fck", "mspro_fck"),
+ DT_CLK(NULL, "fac_ick", "fac_ick"),
+ DT_CLK(NULL, "fac_fck", "fac_fck"),
+ DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
+ DT_CLK(NULL, "hdq_ick", "hdq_ick"),
+ DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
+ DT_CLK(NULL, "hdq_fck", "hdq_fck"),
+ DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
+ DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
+ DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
+ DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
+ DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
+ DT_CLK(NULL, "sdma_fck", "sdma_fck"),
+ DT_CLK(NULL, "sdma_ick", "sdma_ick"),
+ DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
+ DT_CLK(NULL, "des_ick", "des_ick"),
+ DT_CLK("omap-sham", "ick", "sha_ick"),
+ DT_CLK(NULL, "sha_ick", "sha_ick"),
+ DT_CLK("omap_rng", "ick", "rng_ick"),
+ DT_CLK(NULL, "rng_ick", "rng_ick"),
+ DT_CLK("omap-aes", "ick", "aes_ick"),
+ DT_CLK(NULL, "aes_ick", "aes_ick"),
+ DT_CLK(NULL, "pka_ick", "pka_ick"),
+ DT_CLK(NULL, "usb_fck", "usb_fck"),
+ DT_CLK(NULL, "timer_32k_ck", "func_32k_ck"),
+ DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
+ DT_CLK(NULL, "timer_ext_ck", "alt_ck"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap2420_clks[] = {
+ DT_CLK(NULL, "sys_clkout2_src", "sys_clkout2_src"),
+ DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
+ DT_CLK(NULL, "dsp_ick", "dsp_ick"),
+ DT_CLK(NULL, "iva1_ifck", "iva1_ifck"),
+ DT_CLK(NULL, "iva1_mpu_int_ifck", "iva1_mpu_int_ifck"),
+ DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
+ DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
+ DT_CLK("mmci-omap.0", "ick", "mmc_ick"),
+ DT_CLK(NULL, "mmc_ick", "mmc_ick"),
+ DT_CLK("mmci-omap.0", "fck", "mmc_fck"),
+ DT_CLK(NULL, "mmc_fck", "mmc_fck"),
+ DT_CLK(NULL, "eac_ick", "eac_ick"),
+ DT_CLK(NULL, "eac_fck", "eac_fck"),
+ DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
+ DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
+ DT_CLK(NULL, "vlynq_ick", "vlynq_ick"),
+ DT_CLK(NULL, "vlynq_fck", "vlynq_fck"),
+ DT_CLK("musb-hdrc", "fck", "osc_ck"),
+ { .node_name = NULL },
+};
+
+static struct ti_dt_clk omap2430_clks[] = {
+ DT_CLK("twl", "fck", "osc_ck"),
+ DT_CLK(NULL, "iva2_1_ick", "iva2_1_ick"),
+ DT_CLK(NULL, "mdm_ick", "mdm_ick"),
+ DT_CLK(NULL, "mdm_osc_ck", "mdm_osc_ck"),
+ DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
+ DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
+ DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
+ DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
+ DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
+ DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
+ DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
+ DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
+ DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
+ DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
+ DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
+ DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
+ DT_CLK(NULL, "icr_ick", "icr_ick"),
+ DT_CLK(NULL, "i2chs1_fck", "i2chs1_fck"),
+ DT_CLK(NULL, "i2chs2_fck", "i2chs2_fck"),
+ DT_CLK("musb-omap2430", "ick", "usbhs_ick"),
+ DT_CLK(NULL, "usbhs_ick", "usbhs_ick"),
+ DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
+ DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
+ DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
+ DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
+ DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
+ DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
+ DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
+ DT_CLK(NULL, "gpio5_fck", "gpio5_fck"),
+ DT_CLK(NULL, "mdm_intc_ick", "mdm_intc_ick"),
+ DT_CLK("omap_hsmmc.0", "mmchsdb_fck", "mmchsdb1_fck"),
+ DT_CLK(NULL, "mmchsdb1_fck", "mmchsdb1_fck"),
+ DT_CLK("omap_hsmmc.1", "mmchsdb_fck", "mmchsdb2_fck"),
+ DT_CLK(NULL, "mmchsdb2_fck", "mmchsdb2_fck"),
+ { .node_name = NULL },
+};
+
+static const char *enable_init_clks[] = {
+ "apll96_ck",
+ "apll54_ck",
+ "sync_32k_ick",
+ "omapctrl_ick",
+ "gpmc_fck",
+ "sdrc_ick",
+};
+
+enum {
+ OMAP2_SOC_OMAP2420,
+ OMAP2_SOC_OMAP2430,
+};
+
+static int __init omap2xxx_dt_clk_init(int soc_type)
+{
+ ti_dt_clocks_register(omap2xxx_clks);
+
+ if (soc_type == OMAP2_SOC_OMAP2420)
+ ti_dt_clocks_register(omap2420_clks);
+ else
+ ti_dt_clocks_register(omap2430_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000),
+ (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10,
+ (clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000),
+ (clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000));
+
+ return 0;
+}
+
+int __init omap2420_dt_clk_init(void)
+{
+ return omap2xxx_dt_clk_init(OMAP2_SOC_OMAP2420);
+}
+
+int __init omap2430_dt_clk_init(void)
+{
+ return omap2xxx_dt_clk_init(OMAP2_SOC_OMAP2430);
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 4a05d97..a5aec68 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -298,6 +298,8 @@ int omap5xxx_dt_clk_init(void);
int dra7xx_dt_clk_init(void);
int am33xx_dt_clk_init(void);
int am43xx_dt_clk_init(void);
+int omap2420_dt_clk_init(void);
+int omap2430_dt_clk_init(void);
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 09/12] ARM: dts: omap2 clock data
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
` (6 preceding siblings ...)
2014-02-28 9:23 ` [PATCH 08/12] CLK: TI: OMAP2: add clock init support Tero Kristo
@ 2014-02-28 9:23 ` Tero Kristo
2014-02-28 9:23 ` [PATCH 10/12] ARM: OMAP2: clock: add DT boot support for cpufreq_ck Tero Kristo
` (3 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:23 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, mturquette; +Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each clock in the OMAP2 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap2420-clocks.dtsi | 270 +++++++
arch/arm/boot/dts/omap2420.dtsi | 29 +
arch/arm/boot/dts/omap2430-clocks.dtsi | 344 +++++++++
arch/arm/boot/dts/omap2430.dtsi | 29 +
arch/arm/boot/dts/omap24xx-clocks.dtsi | 1238 ++++++++++++++++++++++++++++++++
5 files changed, 1910 insertions(+)
create mode 100644 arch/arm/boot/dts/omap2420-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap2430-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap24xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap2420-clocks.dtsi b/arch/arm/boot/dts/omap2420-clocks.dtsi
new file mode 100644
index 0000000..c9ea68f
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420-clocks.dtsi
@@ -0,0 +1,270 @@
+/*
+ * Device Tree Source for OMAP2420 clock data
+ *
+ * Copyright (C) 2014 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&prcm_clocks {
+ sys_clkout2_src_gate: sys_clkout2_src_gate {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <15>;
+ reg = <0x0070>;
+ };
+
+ sys_clkout2_src_mux: sys_clkout2_src_mux {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0070>;
+ };
+
+ sys_clkout2_src: sys_clkout2_src {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
+ };
+
+ sys_clkout2: sys_clkout2 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkout2_src>;
+ ti,bit-shift = <11>;
+ ti,max-div = <64>;
+ reg = <0x0070>;
+ ti,index-power-of-two;
+ };
+
+ dsp_gate_ick: dsp_gate_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-interface-clock";
+ clocks = <&dsp_fck>;
+ ti,bit-shift = <1>;
+ reg = <0x0810>;
+ };
+
+ dsp_div_ick: dsp_div_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&dsp_fck>;
+ ti,bit-shift = <5>;
+ ti,max-div = <3>;
+ reg = <0x0840>;
+ ti,index-starts-at-one;
+ };
+
+ dsp_ick: dsp_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
+ };
+
+ iva1_gate_ifck: iva1_gate_ifck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x0800>;
+ };
+
+ iva1_div_ifck: iva1_div_ifck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0840>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
+ };
+
+ iva1_ifck: iva1_ifck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
+ };
+
+ iva1_ifck_div: iva1_ifck_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&iva1_ifck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ iva1_mpu_int_ifck: iva1_mpu_int_ifck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&iva1_ifck_div>;
+ ti,bit-shift = <8>;
+ reg = <0x0800>;
+ };
+
+ wdt3_ick: wdt3_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <28>;
+ reg = <0x0210>;
+ };
+
+ wdt3_fck: wdt3_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <28>;
+ reg = <0x0200>;
+ };
+
+ mmc_ick: mmc_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <26>;
+ reg = <0x0210>;
+ };
+
+ mmc_fck: mmc_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_96m_ck>;
+ ti,bit-shift = <26>;
+ reg = <0x0200>;
+ };
+
+ eac_ick: eac_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x0210>;
+ };
+
+ eac_fck: eac_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_96m_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x0200>;
+ };
+
+ i2c1_fck: i2c1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_12m_ck>;
+ ti,bit-shift = <19>;
+ reg = <0x0200>;
+ };
+
+ i2c2_fck: i2c2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_12m_ck>;
+ ti,bit-shift = <20>;
+ reg = <0x0200>;
+ };
+
+ vlynq_ick: vlynq_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l3_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x0210>;
+ };
+
+ vlynq_gate_fck: vlynq_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x0200>;
+ };
+
+ core_d18_ck: core_d18_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <18>;
+ };
+
+ vlynq_mux_fck: vlynq_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>, <&core_d18_ck>;
+ ti,bit-shift = <15>;
+ reg = <0x0240>;
+ };
+
+ vlynq_fck: vlynq_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
+ };
+};
+
+&prcm_clockdomains {
+ gfx_clkdm: gfx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gfx_ick>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
+ <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
+ <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
+ };
+
+ iva1_clkdm: iva1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&iva1_mpu_int_ifck>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_ick>, <&dss_54m_fck>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
+ <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
+ <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
+ <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
+ <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
+ <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
+ <&uart3_ick>, <&uart3_fck>, <&cam_ick>,
+ <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
+ <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
+ <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
+ <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
+ <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
+ <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
+ <&pka_ick>;
+ };
+};
+
+&func_96m_ck {
+ compatible = "fixed-factor-clock";
+ clocks = <&apll96_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+&dsp_div_fck {
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
+};
+
+&ssi_ssr_sst_div_fck {
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 60c605d..795c9bd 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,6 +14,32 @@
compatible = "ti,omap2420", "ti,omap2";
ocp {
+ prcm: prcm@48008000 {
+ compatible = "ti,omap2-prcm";
+ reg = <0x48008000 0x1000>;
+
+ prcm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prcm_clockdomains: clockdomains {
+ };
+ };
+
+ scrm: scrm@48000000 {
+ compatible = "ti,omap2-scrm";
+ reg = <0x48000000 0x1000>;
+
+ scrm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ scrm_clockdomains: clockdomains {
+ };
+ };
+
counter32k: counter@48004000 {
compatible = "ti,omap-counter32k";
reg = <0x48004000 0x20>;
@@ -146,3 +172,6 @@
&i2c2 {
compatible = "ti,omap2420-i2c";
};
+
+/include/ "omap24xx-clocks.dtsi"
+/include/ "omap2420-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi
new file mode 100644
index 0000000..805f75d
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430-clocks.dtsi
@@ -0,0 +1,344 @@
+/*
+ * Device Tree Source for OMAP2430 clock data
+ *
+ * Copyright (C) 2014 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&scrm_clocks {
+ mcbsp3_mux_fck: mcbsp3_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_96m_ck>, <&mcbsp_clks>;
+ reg = <0x02e8>;
+ };
+
+ mcbsp3_fck: mcbsp3_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
+ };
+
+ mcbsp4_mux_fck: mcbsp4_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_96m_ck>, <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ reg = <0x02e8>;
+ };
+
+ mcbsp4_fck: mcbsp4_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
+ };
+
+ mcbsp5_mux_fck: mcbsp5_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_96m_ck>, <&mcbsp_clks>;
+ ti,bit-shift = <4>;
+ reg = <0x02e8>;
+ };
+
+ mcbsp5_fck: mcbsp5_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
+ };
+};
+
+&prcm_clocks {
+ iva2_1_gate_ick: iva2_1_gate_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&dsp_fck>;
+ ti,bit-shift = <0>;
+ reg = <0x0800>;
+ };
+
+ iva2_1_div_ick: iva2_1_div_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&dsp_fck>;
+ ti,bit-shift = <5>;
+ ti,max-div = <3>;
+ reg = <0x0840>;
+ ti,index-starts-at-one;
+ };
+
+ iva2_1_ick: iva2_1_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
+ };
+
+ mdm_gate_ick: mdm_gate_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-interface-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0c10>;
+ };
+
+ mdm_div_ick: mdm_div_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&core_ck>;
+ reg = <0x0c40>;
+ ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
+ };
+
+ mdm_ick: mdm_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
+ };
+
+ mdm_osc_ck: mdm_osc_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&osc_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0c00>;
+ };
+
+ mcbsp3_ick: mcbsp3_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x0214>;
+ };
+
+ mcbsp3_gate_fck: mcbsp3_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <3>;
+ reg = <0x0204>;
+ };
+
+ mcbsp4_ick: mcbsp4_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x0214>;
+ };
+
+ mcbsp4_gate_fck: mcbsp4_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <4>;
+ reg = <0x0204>;
+ };
+
+ mcbsp5_ick: mcbsp5_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <5>;
+ reg = <0x0214>;
+ };
+
+ mcbsp5_gate_fck: mcbsp5_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <5>;
+ reg = <0x0204>;
+ };
+
+ mcspi3_ick: mcspi3_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <9>;
+ reg = <0x0214>;
+ };
+
+ mcspi3_fck: mcspi3_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_48m_ck>;
+ ti,bit-shift = <9>;
+ reg = <0x0204>;
+ };
+
+ icr_ick: icr_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x0410>;
+ };
+
+ i2chs1_fck: i2chs1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,omap2430-interface-clock";
+ clocks = <&func_96m_ck>;
+ ti,bit-shift = <19>;
+ reg = <0x0204>;
+ };
+
+ i2chs2_fck: i2chs2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,omap2430-interface-clock";
+ clocks = <&func_96m_ck>;
+ ti,bit-shift = <20>;
+ reg = <0x0204>;
+ };
+
+ usbhs_ick: usbhs_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l3_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x0214>;
+ };
+
+ mmchs1_ick: mmchs1_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x0214>;
+ };
+
+ mmchs1_fck: mmchs1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_96m_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x0204>;
+ };
+
+ mmchs2_ick: mmchs2_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0214>;
+ };
+
+ mmchs2_fck: mmchs2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_96m_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0204>;
+ };
+
+ gpio5_ick: gpio5_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x0214>;
+ };
+
+ gpio5_fck: gpio5_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x0204>;
+ };
+
+ mdm_intc_ick: mdm_intc_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x0214>;
+ };
+
+ mmchsdb1_fck: mmchsdb1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x0204>;
+ };
+
+ mmchsdb2_fck: mmchsdb2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <17>;
+ reg = <0x0204>;
+ };
+};
+
+&prcm_clockdomains {
+ gfx_clkdm: gfx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gfx_ick>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
+ <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
+ <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
+ <&icr_ick>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_ick>, <&dss_54m_fck>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
+ <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
+ <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
+ <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+ <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
+ <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
+ <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
+ <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
+ <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
+ <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
+ <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
+ <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
+ <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
+ <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
+ <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
+ <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
+ <&mmchsdb2_fck>;
+ };
+
+ mdm_clkdm: mdm_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mdm_osc_ck>;
+ };
+};
+
+&func_96m_ck {
+ compatible = "ti,mux-clock";
+ clocks = <&apll96_ck>, <&alt_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x0540>;
+};
+
+&dsp_div_fck {
+ ti,max-div = <4>;
+ ti,index-starts-at-one;
+};
+
+&ssi_ssr_sst_div_fck {
+ ti,max-div = <5>;
+ ti,index-starts-at-one;
+};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d624345..bbdd0a9 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,6 +14,32 @@
compatible = "ti,omap2430", "ti,omap2";
ocp {
+ prcm: prcm@49006000 {
+ compatible = "ti,omap2-prcm";
+ reg = <0x49006000 0x1000>;
+
+ prcm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prcm_clockdomains: clockdomains {
+ };
+ };
+
+ scrm: scrm@49002000 {
+ compatible = "ti,omap2-scrm";
+ reg = <0x49002000 0x1000>;
+
+ scrm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ scrm_clockdomains: clockdomains {
+ };
+ };
+
counter32k: counter@49020000 {
compatible = "ti,omap-counter32k";
reg = <0x49020000 0x20>;
@@ -233,3 +259,6 @@
&i2c2 {
compatible = "ti,omap2430-i2c";
};
+
+/include/ "omap24xx-clocks.dtsi"
+/include/ "omap2430-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi
new file mode 100644
index 0000000..7629270
--- /dev/null
+++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi
@@ -0,0 +1,1238 @@
+/*
+ * Device Tree Source for OMAP24xx clock data
+ *
+ * Copyright (C) 2014 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+ mcbsp1_mux_fck: mcbsp1_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_96m_ck>, <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ reg = <0x0274>;
+ };
+
+ mcbsp1_fck: mcbsp1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
+ };
+
+ mcbsp2_mux_fck: mcbsp2_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_96m_ck>, <&mcbsp_clks>;
+ ti,bit-shift = <6>;
+ reg = <0x0274>;
+ };
+
+ mcbsp2_fck: mcbsp2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
+ };
+};
+
+&prcm_clocks {
+ func_32k_ck: func_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ secure_32k_ck: secure_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ virt_12m_ck: virt_12m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ virt_13m_ck: virt_13m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+
+ virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ };
+
+ virt_26m_ck: virt_26m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+
+ aplls_clkin_ck: aplls_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x0540>;
+ };
+
+ aplls_clkin_x2_ck: aplls_clkin_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&aplls_clkin_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ osc_ck: osc_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x0060>;
+ ti,index-starts-at-one;
+ };
+
+ sys_ck: sys_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&osc_ck>;
+ ti,bit-shift = <6>;
+ ti,max-div = <3>;
+ reg = <0x0060>;
+ ti,index-starts-at-one;
+ };
+
+ alt_ck: alt_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <54000000>;
+ };
+
+ mcbsp_clks: mcbsp_clks {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+ };
+
+ dpll_ck: dpll_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap2-dpll-core-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x0500>, <0x0540>;
+ };
+
+ apll96_ck: apll96_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap2-apll-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <2>;
+ ti,idlest-shift = <8>;
+ ti,clock-frequency = <96000000>;
+ reg = <0x0500>, <0x0530>, <0x0520>;
+ };
+
+ apll54_ck: apll54_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap2-apll-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <6>;
+ ti,idlest-shift = <9>;
+ ti,clock-frequency = <54000000>;
+ reg = <0x0500>, <0x0530>, <0x0520>;
+ };
+
+ func_54m_ck: func_54m_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&apll54_ck>, <&alt_ck>;
+ ti,bit-shift = <5>;
+ reg = <0x0540>;
+ };
+
+ core_ck: core_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ func_96m_ck: func_96m_ck {
+ #clock-cells = <0>;
+ };
+
+ apll96_d2_ck: apll96_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll96_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ func_48m_ck: func_48m_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&apll96_d2_ck>, <&alt_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x0540>;
+ };
+
+ func_12m_ck: func_12m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&func_48m_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ sys_clkout_src_gate: sys_clkout_src_gate {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x0070>;
+ };
+
+ sys_clkout_src_mux: sys_clkout_src_mux {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
+ reg = <0x0070>;
+ };
+
+ sys_clkout_src: sys_clkout_src {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
+ };
+
+ sys_clkout: sys_clkout {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkout_src>;
+ ti,bit-shift = <3>;
+ ti,max-div = <64>;
+ reg = <0x0070>;
+ ti,index-power-of-two;
+ };
+
+ emul_ck: emul_ck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_54m_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0078>;
+ };
+
+ mpu_ck: mpu_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,max-div = <31>;
+ reg = <0x0140>;
+ ti,index-starts-at-one;
+ };
+
+ dsp_gate_fck: dsp_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0800>;
+ };
+
+ dsp_div_fck: dsp_div_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&core_ck>;
+ reg = <0x0840>;
+ };
+
+ dsp_fck: dsp_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
+ };
+
+ core_l3_ck: core_l3_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,max-div = <31>;
+ reg = <0x0240>;
+ ti,index-starts-at-one;
+ };
+
+ gfx_3d_gate_fck: gfx_3d_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&core_l3_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0300>;
+ };
+
+ gfx_3d_div_fck: gfx_3d_div_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&core_l3_ck>;
+ ti,max-div = <4>;
+ reg = <0x0340>;
+ ti,index-starts-at-one;
+ };
+
+ gfx_3d_fck: gfx_3d_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
+ };
+
+ gfx_2d_gate_fck: gfx_2d_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&core_l3_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0300>;
+ };
+
+ gfx_2d_div_fck: gfx_2d_div_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&core_l3_ck>;
+ ti,max-div = <4>;
+ reg = <0x0340>;
+ ti,index-starts-at-one;
+ };
+
+ gfx_2d_fck: gfx_2d_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
+ };
+
+ gfx_ick: gfx_ick {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_l3_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0310>;
+ };
+
+ l4_ck: l4_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_l3_ck>;
+ ti,bit-shift = <5>;
+ ti,max-div = <3>;
+ reg = <0x0240>;
+ ti,index-starts-at-one;
+ };
+
+ dss_ick: dss_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0210>;
+ };
+
+ dss1_gate_fck: dss1_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0200>;
+ };
+
+ core_d2_ck: core_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ core_d3_ck: core_d3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ core_d4_ck: core_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ core_d5_ck: core_d5_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <5>;
+ };
+
+ core_d6_ck: core_d6_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <6>;
+ };
+
+ core_d8_ck: core_d8_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ core_d9_ck: core_d9_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <9>;
+ };
+
+ core_d12_ck: core_d12_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <12>;
+ };
+
+ core_d16_ck: core_d16_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ dss1_mux_fck: dss1_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0240>;
+ };
+
+ dss1_fck: dss1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
+ };
+
+ dss2_gate_fck: dss2_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&func_48m_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0200>;
+ };
+
+ dss2_mux_fck: dss2_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_ck>, <&func_48m_ck>;
+ ti,bit-shift = <13>;
+ reg = <0x0240>;
+ };
+
+ dss2_fck: dss2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
+ };
+
+ dss_54m_fck: dss_54m_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_54m_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0200>;
+ };
+
+ ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0204>;
+ };
+
+ ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <20>;
+ reg = <0x0240>;
+ };
+
+ ssi_ssr_sst_fck: ssi_ssr_sst_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
+ };
+
+ usb_l4_gate_ick: usb_l4_gate_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-interface-clock";
+ clocks = <&core_l3_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0214>;
+ };
+
+ usb_l4_div_ick: usb_l4_div_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&core_l3_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x0240>;
+ ti,dividers = <0>, <1>, <2>, <0>, <4>;
+ };
+
+ usb_l4_ick: usb_l4_ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
+ };
+
+ ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0214>;
+ };
+
+ gpt1_ick: gpt1_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0410>;
+ };
+
+ gpt1_gate_fck: gpt1_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0400>;
+ };
+
+ gpt1_mux_fck: gpt1_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ reg = <0x0440>;
+ };
+
+ gpt1_fck: gpt1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
+ };
+
+ gpt2_ick: gpt2_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x0210>;
+ };
+
+ gpt2_gate_fck: gpt2_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x0200>;
+ };
+
+ gpt2_mux_fck: gpt2_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0244>;
+ };
+
+ gpt2_fck: gpt2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
+ };
+
+ gpt3_ick: gpt3_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <5>;
+ reg = <0x0210>;
+ };
+
+ gpt3_gate_fck: gpt3_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <5>;
+ reg = <0x0200>;
+ };
+
+ gpt3_mux_fck: gpt3_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x0244>;
+ };
+
+ gpt3_fck: gpt3_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
+ };
+
+ gpt4_ick: gpt4_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x0210>;
+ };
+
+ gpt4_gate_fck: gpt4_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x0200>;
+ };
+
+ gpt4_mux_fck: gpt4_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x0244>;
+ };
+
+ gpt4_fck: gpt4_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
+ };
+
+ gpt5_ick: gpt5_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x0210>;
+ };
+
+ gpt5_gate_fck: gpt5_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x0200>;
+ };
+
+ gpt5_mux_fck: gpt5_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0244>;
+ };
+
+ gpt5_fck: gpt5_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
+ };
+
+ gpt6_ick: gpt6_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0210>;
+ };
+
+ gpt6_gate_fck: gpt6_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0200>;
+ };
+
+ gpt6_mux_fck: gpt6_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x0244>;
+ };
+
+ gpt6_fck: gpt6_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
+ };
+
+ gpt7_ick: gpt7_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <9>;
+ reg = <0x0210>;
+ };
+
+ gpt7_gate_fck: gpt7_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <9>;
+ reg = <0x0200>;
+ };
+
+ gpt7_mux_fck: gpt7_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <12>;
+ reg = <0x0244>;
+ };
+
+ gpt7_fck: gpt7_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
+ };
+
+ gpt8_ick: gpt8_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x0210>;
+ };
+
+ gpt8_gate_fck: gpt8_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x0200>;
+ };
+
+ gpt8_mux_fck: gpt8_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <14>;
+ reg = <0x0244>;
+ };
+
+ gpt8_fck: gpt8_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
+ };
+
+ gpt9_ick: gpt9_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x0210>;
+ };
+
+ gpt9_gate_fck: gpt9_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x0200>;
+ };
+
+ gpt9_mux_fck: gpt9_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x0244>;
+ };
+
+ gpt9_fck: gpt9_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
+ };
+
+ gpt10_ick: gpt10_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <12>;
+ reg = <0x0210>;
+ };
+
+ gpt10_gate_fck: gpt10_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <12>;
+ reg = <0x0200>;
+ };
+
+ gpt10_mux_fck: gpt10_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <18>;
+ reg = <0x0244>;
+ };
+
+ gpt10_fck: gpt10_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
+ };
+
+ gpt11_ick: gpt11_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <13>;
+ reg = <0x0210>;
+ };
+
+ gpt11_gate_fck: gpt11_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <13>;
+ reg = <0x0200>;
+ };
+
+ gpt11_mux_fck: gpt11_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <20>;
+ reg = <0x0244>;
+ };
+
+ gpt11_fck: gpt11_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
+ };
+
+ gpt12_ick: gpt12_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <14>;
+ reg = <0x0210>;
+ };
+
+ gpt12_gate_fck: gpt12_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <14>;
+ reg = <0x0200>;
+ };
+
+ gpt12_mux_fck: gpt12_mux_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x0244>;
+ };
+
+ gpt12_fck: gpt12_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
+ };
+
+ mcbsp1_ick: mcbsp1_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <15>;
+ reg = <0x0210>;
+ };
+
+ mcbsp1_gate_fck: mcbsp1_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <15>;
+ reg = <0x0200>;
+ };
+
+ mcbsp2_ick: mcbsp2_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x0210>;
+ };
+
+ mcbsp2_gate_fck: mcbsp2_gate_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <16>;
+ reg = <0x0200>;
+ };
+
+ mcspi1_ick: mcspi1_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <17>;
+ reg = <0x0210>;
+ };
+
+ mcspi1_fck: mcspi1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_48m_ck>;
+ ti,bit-shift = <17>;
+ reg = <0x0200>;
+ };
+
+ mcspi2_ick: mcspi2_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <18>;
+ reg = <0x0210>;
+ };
+
+ mcspi2_fck: mcspi2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_48m_ck>;
+ ti,bit-shift = <18>;
+ reg = <0x0200>;
+ };
+
+ uart1_ick: uart1_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <21>;
+ reg = <0x0210>;
+ };
+
+ uart1_fck: uart1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_48m_ck>;
+ ti,bit-shift = <21>;
+ reg = <0x0200>;
+ };
+
+ uart2_ick: uart2_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x0210>;
+ };
+
+ uart2_fck: uart2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_48m_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x0200>;
+ };
+
+ uart3_ick: uart3_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0214>;
+ };
+
+ uart3_fck: uart3_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_48m_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0204>;
+ };
+
+ gpios_ick: gpios_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0410>;
+ };
+
+ gpios_fck: gpios_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0400>;
+ };
+
+ mpu_wdt_ick: mpu_wdt_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x0410>;
+ };
+
+ mpu_wdt_fck: mpu_wdt_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x0400>;
+ };
+
+ sync_32k_ick: sync_32k_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0410>;
+ };
+
+ wdt1_ick: wdt1_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x0410>;
+ };
+
+ omapctrl_ick: omapctrl_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <5>;
+ reg = <0x0410>;
+ };
+
+ cam_fck: cam_fck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_96m_ck>;
+ ti,bit-shift = <31>;
+ reg = <0x0200>;
+ };
+
+ cam_ick: cam_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <31>;
+ reg = <0x0210>;
+ };
+
+ mailboxes_ick: mailboxes_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <30>;
+ reg = <0x0210>;
+ };
+
+ wdt4_ick: wdt4_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <29>;
+ reg = <0x0210>;
+ };
+
+ wdt4_fck: wdt4_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_32k_ck>;
+ ti,bit-shift = <29>;
+ reg = <0x0200>;
+ };
+
+ mspro_ick: mspro_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <27>;
+ reg = <0x0210>;
+ };
+
+ mspro_fck: mspro_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_96m_ck>;
+ ti,bit-shift = <27>;
+ reg = <0x0200>;
+ };
+
+ fac_ick: fac_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x0210>;
+ };
+
+ fac_fck: fac_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_12m_ck>;
+ ti,bit-shift = <25>;
+ reg = <0x0200>;
+ };
+
+ hdq_ick: hdq_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x0210>;
+ };
+
+ hdq_fck: hdq_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_12m_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x0200>;
+ };
+
+ i2c1_ick: i2c1_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <19>;
+ reg = <0x0210>;
+ };
+
+ i2c2_ick: i2c2_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <20>;
+ reg = <0x0210>;
+ };
+
+ gpmc_fck: gpmc_fck {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&core_l3_ck>;
+ ti,clock-div = <1>;
+ ti,autoidle-shift = <1>;
+ reg = <0x0238>;
+ ti,clock-mult = <1>;
+ };
+
+ sdma_fck: sdma_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_l3_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ sdma_ick: sdma_ick {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&core_l3_ck>;
+ ti,clock-div = <1>;
+ ti,autoidle-shift = <0>;
+ reg = <0x0238>;
+ ti,clock-mult = <1>;
+ };
+
+ sdrc_ick: sdrc_ick {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&core_l3_ck>;
+ ti,clock-div = <1>;
+ ti,autoidle-shift = <2>;
+ reg = <0x0238>;
+ ti,clock-mult = <1>;
+ };
+
+ des_ick: des_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x021c>;
+ };
+
+ sha_ick: sha_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x021c>;
+ };
+
+ rng_ick: rng_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x021c>;
+ };
+
+ aes_ick: aes_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x021c>;
+ };
+
+ pka_ick: pka_ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l4_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x021c>;
+ };
+
+ usb_fck: usb_fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&func_48m_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0204>;
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 10/12] ARM: OMAP2: clock: add DT boot support for cpufreq_ck
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
` (7 preceding siblings ...)
2014-02-28 9:23 ` [PATCH 09/12] ARM: dts: omap2 clock data Tero Kristo
@ 2014-02-28 9:23 ` Tero Kristo
2014-02-28 9:23 ` [PATCH 11/12] ARM: OMAP2: PRM: add support for OMAP2 specific clock providers Tero Kristo
` (2 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:23 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, mturquette; +Cc: linux-arm-kernel, devicetree
The clock and clkdev for this are added manually.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 46 ++++++++++++++++++++++++++
drivers/clk/ti/clk-2xxx.c | 2 ++
include/linux/clk/ti.h | 1 +
3 files changed, 49 insertions(+)
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index b935ed2..09af46c 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -208,3 +208,56 @@ void omap2xxx_clkt_vps_late_init(void)
clk_put(c);
}
}
+
+#ifdef CONFIG_OF
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
+static const struct clk_ops virt_prcm_set_ops = {
+ .recalc_rate = &omap2_table_mpu_recalc,
+ .set_rate = &omap2_select_table_rate,
+ .round_rate = &omap2_round_to_table_rate,
+};
+
+/**
+ * omap2xxx_clkt_vps_init - initialize virt_prcm_set clock
+ *
+ * Does a manual init for the virtual prcm DVFS clock for OMAP2. This
+ * function is called only from omap2 DT clock init, as the virtual
+ * node is not modelled in the DT clock data.
+ */
+void omap2xxx_clkt_vps_init(void)
+{
+ struct clk_init_data init = { NULL };
+ struct clk_hw_omap *hw = NULL;
+ struct clk *clk;
+ const char *parent_name = "mpu_ck";
+ struct clk_lookup *lookup = NULL;
+
+ omap2xxx_clkt_vps_late_init();
+ omap2xxx_clkt_vps_check_bootloader_rates();
+
+ hw = kzalloc(sizeof(*hw), GFP_KERNEL);
+ lookup = kzalloc(sizeof(*lookup), GFP_KERNEL);
+ if (!hw || !lookup)
+ goto cleanup;
+ init.name = "virt_prcm_set";
+ init.ops = &virt_prcm_set_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ hw->hw.init = &init;
+
+ clk = clk_register(NULL, &hw->hw);
+
+ lookup->dev_id = NULL;
+ lookup->con_id = "cpufreq_ck";
+ lookup->clk = clk;
+
+ clkdev_add(lookup);
+ return;
+cleanup:
+ kfree(hw);
+ kfree(lookup);
+}
+#endif
diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c
index f6400fb..c808ab3 100644
--- a/drivers/clk/ti/clk-2xxx.c
+++ b/drivers/clk/ti/clk-2xxx.c
@@ -229,6 +229,8 @@ static int __init omap2xxx_dt_clk_init(int soc_type)
else
ti_dt_clocks_register(omap2430_clks);
+ omap2xxx_clkt_vps_init();
+
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index a5aec68..03decc2 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -279,6 +279,7 @@ unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
+void omap2xxx_clkt_vps_init(void);
void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 11/12] ARM: OMAP2: PRM: add support for OMAP2 specific clock providers
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
` (8 preceding siblings ...)
2014-02-28 9:23 ` [PATCH 10/12] ARM: OMAP2: clock: add DT boot support for cpufreq_ck Tero Kristo
@ 2014-02-28 9:23 ` Tero Kristo
2014-02-28 19:17 ` Nishanth Menon
2014-02-28 9:23 ` [PATCH 12/12] ARM: OMAP2: clock: use DT clock boot if available Tero Kristo
2014-02-28 15:59 ` [PATCH 00/12] ARM: OMAP2 DT clock conversion Nishanth Menon
11 siblings, 1 reply; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:23 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, mturquette; +Cc: linux-arm-kernel, devicetree
This patch adds support for initializing also omap2-prcm and omap2-scrm
through DT.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/prm_common.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index b4c4ab9..878ae9f 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -475,6 +475,8 @@ static struct of_device_id omap_prcm_dt_match_table[] = {
{ .compatible = "ti,am3-scrm" },
{ .compatible = "ti,am4-prcm" },
{ .compatible = "ti,am4-scrm" },
+ { .compatible = "ti,omap2-prcm" },
+ { .compatible = "ti,omap2-scrm" },
{ .compatible = "ti,omap3-prm" },
{ .compatible = "ti,omap3-cm" },
{ .compatible = "ti,omap3-scrm" },
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 11/12] ARM: OMAP2: PRM: add support for OMAP2 specific clock providers
2014-02-28 9:23 ` [PATCH 11/12] ARM: OMAP2: PRM: add support for OMAP2 specific clock providers Tero Kristo
@ 2014-02-28 19:17 ` Nishanth Menon
0 siblings, 0 replies; 22+ messages in thread
From: Nishanth Menon @ 2014-02-28 19:17 UTC (permalink / raw)
To: Tero Kristo, linux-omap, paul, tony, mturquette
Cc: linux-arm-kernel, devicetree
On 02/28/2014 03:23 AM, Tero Kristo wrote:
> This patch adds support for initializing also omap2-prcm and omap2-scrm
> through DT.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
> arch/arm/mach-omap2/prm_common.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
> index b4c4ab9..878ae9f 100644
> --- a/arch/arm/mach-omap2/prm_common.c
> +++ b/arch/arm/mach-omap2/prm_common.c
> @@ -475,6 +475,8 @@ static struct of_device_id omap_prcm_dt_match_table[] = {
> { .compatible = "ti,am3-scrm" },
> { .compatible = "ti,am4-prcm" },
> { .compatible = "ti,am4-scrm" },
> + { .compatible = "ti,omap2-prcm" },
> + { .compatible = "ti,omap2-scrm" },
> { .compatible = "ti,omap3-prm" },
> { .compatible = "ti,omap3-cm" },
> { .compatible = "ti,omap3-scrm" },
>
probably needs Bindings documentation as well.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 12/12] ARM: OMAP2: clock: use DT clock boot if available
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
` (9 preceding siblings ...)
2014-02-28 9:23 ` [PATCH 11/12] ARM: OMAP2: PRM: add support for OMAP2 specific clock providers Tero Kristo
@ 2014-02-28 9:23 ` Tero Kristo
2014-02-28 15:59 ` [PATCH 00/12] ARM: OMAP2 DT clock conversion Nishanth Menon
11 siblings, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 9:23 UTC (permalink / raw)
To: linux-omap, paul, tony, nm, mturquette; +Cc: linux-arm-kernel, devicetree
Otherwise legacy boot clock data is used.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/io.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index af432b1..e57088d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -53,6 +53,7 @@
#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm44xx.h"
+#include "opp2xxx.h"
/*
* omap_clk_soc_init: points to a function that does the SoC-specific
@@ -410,7 +411,12 @@ void __init omap2420_init_early(void)
omap242x_clockdomains_init();
omap2420_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_soc_init = omap2420_clk_init;
+ if (of_have_populated_dt()) {
+ omap_clk_soc_init = omap2420_dt_clk_init;
+ rate_table = omap2420_rate_table;
+ } else {
+ omap_clk_soc_init = omap2420_clk_init;
+ }
}
void __init omap2420_init_late(void)
@@ -439,7 +445,12 @@ void __init omap2430_init_early(void)
omap243x_clockdomains_init();
omap2430_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_soc_init = omap2430_clk_init;
+ if (of_have_populated_dt()) {
+ omap_clk_soc_init = omap2430_dt_clk_init;
+ rate_table = omap2430_rate_table;
+ } else {
+ omap_clk_soc_init = omap2430_clk_init;
+ }
}
void __init omap2430_init_late(void)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 00/12] ARM: OMAP2 DT clock conversion
2014-02-28 9:22 [PATCH 00/12] ARM: OMAP2 DT clock conversion Tero Kristo
` (10 preceding siblings ...)
2014-02-28 9:23 ` [PATCH 12/12] ARM: OMAP2: clock: use DT clock boot if available Tero Kristo
@ 2014-02-28 15:59 ` Nishanth Menon
2014-02-28 18:01 ` Tony Lindgren
11 siblings, 1 reply; 22+ messages in thread
From: Nishanth Menon @ 2014-02-28 15:59 UTC (permalink / raw)
To: Tero Kristo, linux-omap, paul, tony, mturquette
Cc: linux-arm-kernel, devicetree
On 02/28/2014 03:22 AM, Tero Kristo wrote:
> Hi,
>
> This set concludes the omap2+ clock DT conversion work by creating the
> DT clock data for omap2 SoC also.
>
> I am also currently doing related work to cleanup CM/PRM codebase in
> preparation to move it into drivers/, this set is basically going to
> be a pre-requisite for that. I'll hopefully post something related
> to that early next week.
>
> This set has been boot tested on OMAP2430 only (thanks Nishanth, I don't
> have access to OMAP2 hardware myself), so any testing feedback on
> 2420 board(s) would be appreciated.
>
> Working tree:
>
> Tree: https://github.com/t-kristo/linux-pm.git
> Branch: 3.14-rc4-omap2-dt-clks
I do see checkpatch warnings in the series:
http://slexy.org/view/s20mzhlJ93
Series boot tested with:
3.14-rc4-omap2-dt-clks fc73a96 ARM: OMAP2: clock: use DT clock boot
if available
from the tree mentioned above.
Things look good other than the checkpatch violation noticed in
report, so other than that,
Tested-by: Nishanth Menon <nm@ti.com>
omap2plus_defconfig
1: am335x-evm: Boot PASS: http://slexy.org/raw/s2jdV3XMCC
2: am335x-sk: Boot PASS: http://slexy.org/raw/s210nZI8Hx
3: am3517-evm: Boot PASS: http://slexy.org/raw/s21MG8kg6u
4: am37x-evm: Boot PASS: http://slexy.org/raw/s20coVhzLt
5: am43xx-epos: Boot PASS: http://slexy.org/raw/s21XKjjwyk
6: BeagleBoard-XM: Boot PASS: http://slexy.org/raw/s27PCmlDq7
7: BeagleBone-Black: Boot PASS: http://slexy.org/raw/s2HX1Q3iPb
8: crane: No Image built - Missing platform support?:
9: dra7: Boot PASS: http://slexy.org/raw/s21ofDfpD2
10: ldp: Boot FAIL: http://slexy.org/raw/s2SbrpyX2p
^^ legacy behavior
11: PandaBoard-ES: Boot PASS: http://slexy.org/raw/s21n4iMUKd
12: sdp2430: Boot PASS: http://slexy.org/raw/s2CJ5hYl72
13: sdp3430: Boot PASS: http://slexy.org/raw/s20axZ1nyb
14: sdp4430: Boot PASS: http://slexy.org/raw/s21wt3C5F3
15: OMAP5432uEVM: Boot PASS: http://slexy.org/raw/s208PhmCpm
TOTAL = 15 boards, Booted Boards = 13, No Boot boards = 2
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 00/12] ARM: OMAP2 DT clock conversion
2014-02-28 15:59 ` [PATCH 00/12] ARM: OMAP2 DT clock conversion Nishanth Menon
@ 2014-02-28 18:01 ` Tony Lindgren
2014-02-28 18:18 ` Tero Kristo
0 siblings, 1 reply; 22+ messages in thread
From: Tony Lindgren @ 2014-02-28 18:01 UTC (permalink / raw)
To: Nishanth Menon
Cc: Tero Kristo, linux-omap, paul, mturquette, linux-arm-kernel,
devicetree
* Nishanth Menon <nm@ti.com> [140228 08:02]:
> On 02/28/2014 03:22 AM, Tero Kristo wrote:
> > Hi,
> >
> > This set concludes the omap2+ clock DT conversion work by creating the
> > DT clock data for omap2 SoC also.
> >
> > I am also currently doing related work to cleanup CM/PRM codebase in
> > preparation to move it into drivers/, this set is basically going to
> > be a pre-requisite for that. I'll hopefully post something related
> > to that early next week.
> >
> > This set has been boot tested on OMAP2430 only (thanks Nishanth, I don't
> > have access to OMAP2 hardware myself), so any testing feedback on
> > 2420 board(s) would be appreciated.
> >
> > Working tree:
> >
> > Tree: https://github.com/t-kristo/linux-pm.git
> > Branch: 3.14-rc4-omap2-dt-clks
>
> I do see checkpatch warnings in the series:
> http://slexy.org/view/s20mzhlJ93
>
> Series boot tested with:
> 3.14-rc4-omap2-dt-clks fc73a96 ARM: OMAP2: clock: use DT clock boot
> if available
> from the tree mentioned above.
>
> Things look good other than the checkpatch violation noticed in
> report, so other than that,
>
> Tested-by: Nishanth Menon <nm@ti.com>
>
> omap2plus_defconfig
> 1: am335x-evm: Boot PASS: http://slexy.org/raw/s2jdV3XMCC
> 2: am335x-sk: Boot PASS: http://slexy.org/raw/s210nZI8Hx
> 3: am3517-evm: Boot PASS: http://slexy.org/raw/s21MG8kg6u
> 4: am37x-evm: Boot PASS: http://slexy.org/raw/s20coVhzLt
> 5: am43xx-epos: Boot PASS: http://slexy.org/raw/s21XKjjwyk
> 6: BeagleBoard-XM: Boot PASS: http://slexy.org/raw/s27PCmlDq7
> 7: BeagleBone-Black: Boot PASS: http://slexy.org/raw/s2HX1Q3iPb
> 8: crane: No Image built - Missing platform support?:
> 9: dra7: Boot PASS: http://slexy.org/raw/s21ofDfpD2
> 10: ldp: Boot FAIL: http://slexy.org/raw/s2SbrpyX2p
> ^^ legacy behavior
> 11: PandaBoard-ES: Boot PASS: http://slexy.org/raw/s21n4iMUKd
> 12: sdp2430: Boot PASS: http://slexy.org/raw/s2CJ5hYl72
> 13: sdp3430: Boot PASS: http://slexy.org/raw/s20axZ1nyb
> 14: sdp4430: Boot PASS: http://slexy.org/raw/s21wt3C5F3
> 15: OMAP5432uEVM: Boot PASS: http://slexy.org/raw/s208PhmCpm
> TOTAL = 15 boards, Booted Boards = 13, No Boot boards = 2
I'm getting this with omap2 only build:
drivers/clk/ti/dpll.c:235: undefined reference to `clkhwops_omap3_dpll'
drivers/built-in.o:(.rodata+0x1dd50): undefined reference to `omap3_noncore_dpll_enable'
drivers/built-in.o:(.rodata+0x1dd54): undefined reference to `omap3_noncore_dpll_disable'
drivers/built-in.o:(.rodata+0x1dd60): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0x1dd74): undefined reference to `omap3_noncore_dpll_set_rate'
drivers/built-in.o:(.rodata+0x1ddb8): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0x1ddfc): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0x1de10): undefined reference to `omap3_noncore_dpll_set_rate'
And this if 2430 is not selected:
drivers/clk/ti/interface.c:129: undefined reference to `clkhwops_omap2430_i2chs_wait'
Then I get this early on when trying to boot on n800:
[ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[ 0.000000] pgd = c0004000
[ 0.000000] [00000000] *pgd=00000000
[ 0.000000] Internal error: Oops: 5 [#1] ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 3.14.0-rc1-00012-ga93a376 #225
[ 0.000000] task: c073ee80 ti: c0734000 task.ti: c0734000
[ 0.000000] PC is at strcmp+0xc/0x34
[ 0.000000] LR is at __clk_init+0x244/0x4d0
[ 0.000000] pc : [<c0273ed8>] lr : [<c0401858>] psr: 200001d3
[ 0.000000] sp : c0735e68 ip : c781cf80 fp : c05440b8
[ 0.000000] r10: 00000000 r9 : c781ba80 r8 : c781ba80
[ 0.000000] r7 : 0000000b r6 : c781ba80 r5 : 0000000b r4 : c0cf27f4
[ 0.000000] r3 : c781cfc0 r2 : 00000000 r1 : 00000000 r0 : 00000076
[ 0.000000] Flags: nzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 0.000000] Control: 00c5387d Table: 80004000 DAC: 00000017
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc0734240)
[ 0.000000] Stack: (0xc0735e68 to 0xc0736000)
[ 0.000000] 5e60: c7df5868 c781ba00 0000000b c781cfc0 c781ba80 c781ba00
[ 0.000000] 5e80: 00000000 c781ce80 c0544074 c0401bcc c781ba80 00000000 c781ba00 c7df5a68
[ 0.000000] 5ea0: c781cec0 c0401d08 c05442b8 c781ba00 0000000b c0403070 c0686038 00000000
[ 0.000000] 5ec0: c0686038 c7df5a68 c781ba08 c781cec0 c0735f0b 00000020 c0d09ce8 00000000
[ 0.000000] 5ee0: c781cf40 c781cf40 00000000 c781cf4c 4107b362 c7df59a8 00000000 c0719f30
[ 0.000000] 5f00: c781ce80 c05442b8 00000000 c0544074 c781cc80 c05440b8 00000000 c781cf44
[ 0.000000] 5f20: 4107b362 c7df59a8 c781cf40 00000002 00000002 c781cf48 c0735f48 c071a040
[ 0.000000] 5f40: c0735f48 c007533c c7df5874 00000000 a00001d3 a00001d3 c0797b6c 80004008
[ 0.000000] 5f60: c0797b6c c04e07c4 a00001d3 c07320d0 c7df59a8 c7df59a8 c7de8d10 c07a7454
[ 0.000000] 5f80: c07408dc 80004008 807244d0 c0403184 c7de8c70 00000000 c07a7454 c07408dc
[ 0.000000] 5fa0: 80004008 c06f6884 c07a69bc 00000001 c073c041 c06f0918 ffffffff c06f317c
[ 0.000000] 5fc0: 4107b362 c06ec8c0 00000000 c06e8a8c ffffffff ffffffff c06e8724 00000000
[ 0.000000] 5fe0: 00000000 c07256d0 00c5387d c073c094 c0725ad4 80008070 00000000 00000000
[ 0.000000] [<c0273ed8>] (strcmp) from [<c0401858>] (__clk_init+0x244/0x4d0)
[ 0.000000] [<c0401858>] (__clk_init) from [<c0401bcc>] (_clk_register+0xe8/0x180)
[ 0.000000] [<c0401bcc>] (_clk_register) from [<c0401d08>] (clk_register+0x38/0x78)
[ 0.000000] [<c0401d08>] (clk_register) from [<c0403070>] (clk_register_composite+0x180/0x244)
[ 0.000000] [<c0403070>] (clk_register_composite) from [<c0719f30>] (ti_clk_register_composite+0x1f8/0x268)
[ 0.000000] [<c0719f30>] (ti_clk_register_composite) from [<c071a040>] (of_ti_composite_clk_setup+0xa0/0xbc)
[ 0.000000] [<c071a040>] (of_ti_composite_clk_setup) from [<c0403184>] (ti_dt_clk_init_provider+0x50/0x10c)
[ 0.000000] [<c0403184>] (ti_dt_clk_init_provider) from [<c06f6884>] (of_prcm_init+0x4c/0x84)
[ 0.000000] [<c06f6884>] (of_prcm_init) from [<c06f0918>] (omap_clk_init+0x18/0x30)
[ 0.000000] [<c06f0918>] (omap_clk_init) from [<c06f317c>] (omap2_sync32k_timer_init+0xc/0x64)
[ 0.000000] [<c06f317c>] (omap2_sync32k_timer_init) from [<c06ec8c0>] (time_init+0x20/0x38)
[ 0.000000] [<c06ec8c0>] (time_init) from [<c06e8a8c>] (start_kernel+0x134/0x2f4)
[ 0.000000] [<c06e8a8c>] (start_kernel) from [<80008070>] (0x80008070)
[ 0.000000] Code: e12fff1e e1a0c000 e3a02000 e7dc0002 (e7d13002)
[ 0.000000] ---[ end trace 3406ff24bd97382e ]---
Regards,
Tony
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 00/12] ARM: OMAP2 DT clock conversion
2014-02-28 18:01 ` Tony Lindgren
@ 2014-02-28 18:18 ` Tero Kristo
2014-02-28 18:33 ` Tony Lindgren
0 siblings, 1 reply; 22+ messages in thread
From: Tero Kristo @ 2014-02-28 18:18 UTC (permalink / raw)
To: Tony Lindgren, Nishanth Menon
Cc: linux-omap, paul, mturquette, linux-arm-kernel, devicetree
On 02/28/2014 08:01 PM, Tony Lindgren wrote:
> * Nishanth Menon <nm@ti.com> [140228 08:02]:
>> On 02/28/2014 03:22 AM, Tero Kristo wrote:
>>> Hi,
>>>
>>> This set concludes the omap2+ clock DT conversion work by creating the
>>> DT clock data for omap2 SoC also.
>>>
>>> I am also currently doing related work to cleanup CM/PRM codebase in
>>> preparation to move it into drivers/, this set is basically going to
>>> be a pre-requisite for that. I'll hopefully post something related
>>> to that early next week.
>>>
>>> This set has been boot tested on OMAP2430 only (thanks Nishanth, I don't
>>> have access to OMAP2 hardware myself), so any testing feedback on
>>> 2420 board(s) would be appreciated.
>>>
>>> Working tree:
>>>
>>> Tree: https://github.com/t-kristo/linux-pm.git
>>> Branch: 3.14-rc4-omap2-dt-clks
>>
>> I do see checkpatch warnings in the series:
>> http://slexy.org/view/s20mzhlJ93
>>
>> Series boot tested with:
>> 3.14-rc4-omap2-dt-clks fc73a96 ARM: OMAP2: clock: use DT clock boot
>> if available
>> from the tree mentioned above.
>>
>> Things look good other than the checkpatch violation noticed in
>> report, so other than that,
I noticed the checkpatch warnings also, most of them are impossible to
fix, and/or are false warnings (see the fixed-factor / fixed-clock
complaints for example.)
>>
>> Tested-by: Nishanth Menon <nm@ti.com>
>>
>> omap2plus_defconfig
>> 1: am335x-evm: Boot PASS: http://slexy.org/raw/s2jdV3XMCC
>> 2: am335x-sk: Boot PASS: http://slexy.org/raw/s210nZI8Hx
>> 3: am3517-evm: Boot PASS: http://slexy.org/raw/s21MG8kg6u
>> 4: am37x-evm: Boot PASS: http://slexy.org/raw/s20coVhzLt
>> 5: am43xx-epos: Boot PASS: http://slexy.org/raw/s21XKjjwyk
>> 6: BeagleBoard-XM: Boot PASS: http://slexy.org/raw/s27PCmlDq7
>> 7: BeagleBone-Black: Boot PASS: http://slexy.org/raw/s2HX1Q3iPb
>> 8: crane: No Image built - Missing platform support?:
>> 9: dra7: Boot PASS: http://slexy.org/raw/s21ofDfpD2
>> 10: ldp: Boot FAIL: http://slexy.org/raw/s2SbrpyX2p
>> ^^ legacy behavior
>> 11: PandaBoard-ES: Boot PASS: http://slexy.org/raw/s21n4iMUKd
>> 12: sdp2430: Boot PASS: http://slexy.org/raw/s2CJ5hYl72
>> 13: sdp3430: Boot PASS: http://slexy.org/raw/s20axZ1nyb
>> 14: sdp4430: Boot PASS: http://slexy.org/raw/s21wt3C5F3
>> 15: OMAP5432uEVM: Boot PASS: http://slexy.org/raw/s208PhmCpm
>> TOTAL = 15 boards, Booted Boards = 13, No Boot boards = 2
>
> I'm getting this with omap2 only build:
>
> drivers/clk/ti/dpll.c:235: undefined reference to `clkhwops_omap3_dpll'
> drivers/built-in.o:(.rodata+0x1dd50): undefined reference to `omap3_noncore_dpll_enable'
> drivers/built-in.o:(.rodata+0x1dd54): undefined reference to `omap3_noncore_dpll_disable'
> drivers/built-in.o:(.rodata+0x1dd60): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0x1dd74): undefined reference to `omap3_noncore_dpll_set_rate'
> drivers/built-in.o:(.rodata+0x1ddb8): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0x1ddfc): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0x1de10): undefined reference to `omap3_noncore_dpll_set_rate'
>
> And this if 2430 is not selected:
>
> drivers/clk/ti/interface.c:129: undefined reference to `clkhwops_omap2430_i2chs_wait'
Hmm okay, these should be easy to fix... I'll need to see if I have
introduced some other build breakages also...
>
> Then I get this early on when trying to boot on n800:
>
> [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000
> [ 0.000000] pgd = c0004000
> [ 0.000000] [00000000] *pgd=00000000
> [ 0.000000] Internal error: Oops: 5 [#1] ARM
> [ 0.000000] Modules linked in:
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 3.14.0-rc1-00012-ga93a376 #225
> [ 0.000000] task: c073ee80 ti: c0734000 task.ti: c0734000
> [ 0.000000] PC is at strcmp+0xc/0x34
> [ 0.000000] LR is at __clk_init+0x244/0x4d0
> [ 0.000000] pc : [<c0273ed8>] lr : [<c0401858>] psr: 200001d3
> [ 0.000000] sp : c0735e68 ip : c781cf80 fp : c05440b8
> [ 0.000000] r10: 00000000 r9 : c781ba80 r8 : c781ba80
> [ 0.000000] r7 : 0000000b r6 : c781ba80 r5 : 0000000b r4 : c0cf27f4
> [ 0.000000] r3 : c781cfc0 r2 : 00000000 r1 : 00000000 r0 : 00000076
> [ 0.000000] Flags: nzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
> [ 0.000000] Control: 00c5387d Table: 80004000 DAC: 00000017
> [ 0.000000] Process swapper (pid: 0, stack limit = 0xc0734240)
> [ 0.000000] Stack: (0xc0735e68 to 0xc0736000)
> [ 0.000000] 5e60: c7df5868 c781ba00 0000000b c781cfc0 c781ba80 c781ba00
> [ 0.000000] 5e80: 00000000 c781ce80 c0544074 c0401bcc c781ba80 00000000 c781ba00 c7df5a68
> [ 0.000000] 5ea0: c781cec0 c0401d08 c05442b8 c781ba00 0000000b c0403070 c0686038 00000000
> [ 0.000000] 5ec0: c0686038 c7df5a68 c781ba08 c781cec0 c0735f0b 00000020 c0d09ce8 00000000
> [ 0.000000] 5ee0: c781cf40 c781cf40 00000000 c781cf4c 4107b362 c7df59a8 00000000 c0719f30
> [ 0.000000] 5f00: c781ce80 c05442b8 00000000 c0544074 c781cc80 c05440b8 00000000 c781cf44
> [ 0.000000] 5f20: 4107b362 c7df59a8 c781cf40 00000002 00000002 c781cf48 c0735f48 c071a040
> [ 0.000000] 5f40: c0735f48 c007533c c7df5874 00000000 a00001d3 a00001d3 c0797b6c 80004008
> [ 0.000000] 5f60: c0797b6c c04e07c4 a00001d3 c07320d0 c7df59a8 c7df59a8 c7de8d10 c07a7454
> [ 0.000000] 5f80: c07408dc 80004008 807244d0 c0403184 c7de8c70 00000000 c07a7454 c07408dc
> [ 0.000000] 5fa0: 80004008 c06f6884 c07a69bc 00000001 c073c041 c06f0918 ffffffff c06f317c
> [ 0.000000] 5fc0: 4107b362 c06ec8c0 00000000 c06e8a8c ffffffff ffffffff c06e8724 00000000
> [ 0.000000] 5fe0: 00000000 c07256d0 00c5387d c073c094 c0725ad4 80008070 00000000 00000000
> [ 0.000000] [<c0273ed8>] (strcmp) from [<c0401858>] (__clk_init+0x244/0x4d0)
> [ 0.000000] [<c0401858>] (__clk_init) from [<c0401bcc>] (_clk_register+0xe8/0x180)
> [ 0.000000] [<c0401bcc>] (_clk_register) from [<c0401d08>] (clk_register+0x38/0x78)
> [ 0.000000] [<c0401d08>] (clk_register) from [<c0403070>] (clk_register_composite+0x180/0x244)
> [ 0.000000] [<c0403070>] (clk_register_composite) from [<c0719f30>] (ti_clk_register_composite+0x1f8/0x268)
> [ 0.000000] [<c0719f30>] (ti_clk_register_composite) from [<c071a040>] (of_ti_composite_clk_setup+0xa0/0xbc)
> [ 0.000000] [<c071a040>] (of_ti_composite_clk_setup) from [<c0403184>] (ti_dt_clk_init_provider+0x50/0x10c)
> [ 0.000000] [<c0403184>] (ti_dt_clk_init_provider) from [<c06f6884>] (of_prcm_init+0x4c/0x84)
> [ 0.000000] [<c06f6884>] (of_prcm_init) from [<c06f0918>] (omap_clk_init+0x18/0x30)
> [ 0.000000] [<c06f0918>] (omap_clk_init) from [<c06f317c>] (omap2_sync32k_timer_init+0xc/0x64)
> [ 0.000000] [<c06f317c>] (omap2_sync32k_timer_init) from [<c06ec8c0>] (time_init+0x20/0x38)
> [ 0.000000] [<c06ec8c0>] (time_init) from [<c06e8a8c>] (start_kernel+0x134/0x2f4)
> [ 0.000000] [<c06e8a8c>] (start_kernel) from [<80008070>] (0x80008070)
> [ 0.000000] Code: e12fff1e e1a0c000 e3a02000 e7dc0002 (e7d13002)
> [ 0.000000] ---[ end trace 3406ff24bd97382e ]---
Hmm, some clock node is broken, might be missing a name or parent name
for some reason. Can you try to boot with DEBUG enabled so you get
pr_debug:s out and see which clock is being initialized during the crash?
-Tero
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 00/12] ARM: OMAP2 DT clock conversion
2014-02-28 18:18 ` Tero Kristo
@ 2014-02-28 18:33 ` Tony Lindgren
2014-03-03 8:16 ` Tero Kristo
0 siblings, 1 reply; 22+ messages in thread
From: Tony Lindgren @ 2014-02-28 18:33 UTC (permalink / raw)
To: Tero Kristo
Cc: Nishanth Menon, linux-omap, paul, mturquette, linux-arm-kernel,
devicetree
* Tero Kristo <t-kristo@ti.com> [140228 10:21]:
>
> Hmm, some clock node is broken, might be missing a name or parent
> name for some reason. Can you try to boot with DEBUG enabled so you
> get pr_debug:s out and see which clock is being initialized during
> the crash?
...
[ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: core_d18_ck
[ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_mux_fck
[ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_fck
[ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000
...
We really should be registering the clocks lazily as needed BTW. That
leaves out the dependency to DEBUG_LL for seeing any kind of decent
error messages during the booting.
Regards,
Tony
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 00/12] ARM: OMAP2 DT clock conversion
2014-02-28 18:33 ` Tony Lindgren
@ 2014-03-03 8:16 ` Tero Kristo
2014-03-03 18:46 ` Tony Lindgren
0 siblings, 1 reply; 22+ messages in thread
From: Tero Kristo @ 2014-03-03 8:16 UTC (permalink / raw)
To: Tony Lindgren
Cc: Nishanth Menon, linux-omap, paul, mturquette, linux-arm-kernel,
devicetree
On 02/28/2014 08:33 PM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [140228 10:21]:
>>
>> Hmm, some clock node is broken, might be missing a name or parent
>> name for some reason. Can you try to boot with DEBUG enabled so you
>> get pr_debug:s out and see which clock is being initialized during
>> the crash?
>
> ...
> [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: core_d18_ck
> [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_mux_fck
> [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_fck
> [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000
> ...
>
> We really should be registering the clocks lazily as needed BTW. That
> leaves out the dependency to DEBUG_LL for seeing any kind of decent
> error messages during the booting.
>
> Regards,
>
> Tony
>
Hey Tony,
Can you retry with the branch? I just pushed one patch there, seems the
parents for the vlynq_mux_fck were somewhat broken (there are holes in
the valid mux values list, which hasn't happened with any other
mux-clock so far.)
If this works, I will rework the series a bit and send v2 out.
Alternatively I need to add extra debug info.
-Tero
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 00/12] ARM: OMAP2 DT clock conversion
2014-03-03 8:16 ` Tero Kristo
@ 2014-03-03 18:46 ` Tony Lindgren
2014-03-03 18:51 ` Tero Kristo
0 siblings, 1 reply; 22+ messages in thread
From: Tony Lindgren @ 2014-03-03 18:46 UTC (permalink / raw)
To: Tero Kristo
Cc: Nishanth Menon, linux-omap, paul, mturquette, linux-arm-kernel,
devicetree
* Tero Kristo <t-kristo@ti.com> [140303 00:20]:
> On 02/28/2014 08:33 PM, Tony Lindgren wrote:
> >* Tero Kristo <t-kristo@ti.com> [140228 10:21]:
> >>
> >>Hmm, some clock node is broken, might be missing a name or parent
> >>name for some reason. Can you try to boot with DEBUG enabled so you
> >>get pr_debug:s out and see which clock is being initialized during
> >>the crash?
> >
> >...
> >[ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: core_d18_ck
> >[ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_mux_fck
> >[ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_fck
> >[ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000
> >...
> >
> >We really should be registering the clocks lazily as needed BTW. That
> >leaves out the dependency to DEBUG_LL for seeing any kind of decent
> >error messages during the booting.
> >
> >Regards,
> >
> >Tony
> >
>
> Hey Tony,
>
> Can you retry with the branch? I just pushed one patch there, seems
> the parents for the vlynq_mux_fck were somewhat broken (there are
> holes in the valid mux values list, which hasn't happened with any
> other mux-clock so far.)
>
> If this works, I will rework the series a bit and send v2 out.
> Alternatively I need to add extra debug info.
Still getting this without omap3:
drivers/built-in.o: In function `of_ti_dpll_setup':
/home/tmlind/src/linux-2.6/drivers/clk/ti/dpll.c:235: undefined reference to `clkhwops_omap3_dpll'
drivers/built-in.o:(.rodata+0x1d7a0): undefined reference to `omap3_noncore_dpll_enable'
drivers/built-in.o:(.rodata+0x1d7a4): undefined reference to `omap3_noncore_dpll_disable'
drivers/built-in.o:(.rodata+0x1d7b0): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0x1d7c4): undefined reference to `omap3_noncore_dpll_set_rate'
drivers/built-in.o:(.rodata+0x1d808): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0x1d84c): undefined reference to `omap3_dpll_recalc'
drivers/built-in.o:(.rodata+0x1d860): undefined reference to `omap3_noncore_dpll_set_rate'
and after enabling omap3 getting this without 2430:
drivers/built-in.o: In function `of_ti_omap2430_interface_clk_setup':
/home/tmlind/src/linux-2.6/drivers/clk/ti/interface.c:129: undefined reference to `clkhwops_omap2430_i2chs_wait'
But after enabling those, it now boots on n8x0. The dmesg is below.
Care to post a patch to try dropping the legacy clock data as it should
now work with the DT clocks only for omap2?
Regards,
Tony
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.14.0-rc5-00014-g2297f72-dirty (tmlind@muffinssi) (gcc version 4.3.5 (Debian 4.3.5-4) ) #388 Mon Mar 3 10:38:58 PST 2014
[ 0.000000] CPU: ARMv6-compatible processor [4107b362] revision 2 (ARMv6TEJ), cr=00c5387d
[ 0.000000] CPU: VIPT aliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine model: Nokia N800
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] debug: ignoring loglevel setting.
[ 0.000000] Memory policy: Data cache writeback
[ 0.000000] On node 0 totalpages: 32512
[ 0.000000] free_area_init_node: node 0, pgdat c07969a8, node_mem_map c7df9000
[ 0.000000] Normal zone: 256 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 32512 pages, LIFO batch:7
[ 0.000000] CPU: All CPU(s) started in SVC mode.
[ 0.000000] OMAP2420
[ 0.000000]
[ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32256
[ 0.000000] Kernel command line: root=/dev/mmcblk0p2 rootwait console=ttyO2,115200 earlyprintk ignore_loglevel
[ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Memory: 115492K/130048K available (5098K kernel code, 457K rwdata, 1884K rodata, 304K init, 5485K bss, 14556K reserved, 0K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc06d9e10 (6984 kB)
[ 0.000000] .init : 0xc06da000 - 0xc072601c ( 305 kB)
[ 0.000000] .data : 0xc0728000 - 0xc079a690 ( 458 kB)
[ 0.000000] .bss : 0xc079a690 - 0xc0cf5b10 (5486 kB)
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] IRQ: Found an INTC at 0xfa0fe000 (revision 2.0) with 96 interrupts
[ 0.000000] Total of 96 interrupts on 1 active controller
[ 0.000000] Clocking rate (Crystal/DPLL/MPU): 19.2/658/329 MHz
[ 0.000000] OMAP clockevent source: timer1 at 32768 Hz
[ 0.000030] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65536000000000ns
[ 0.008758] OMAP clocksource: 32k_counter at 32768 Hz
[ 0.014465] hw-breakpoint: CPUID feature registers not supported. Assuming v6 debug is present.
[ 0.026245] Console: colour dummy device 80x30
[ 0.031005] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.039215] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.043609] ... MAX_LOCK_DEPTH: 48
[ 0.048034] ... MAX_LOCKDEP_KEYS: 8191
[ 0.052673] ... CLASSHASH_SIZE: 4096
[ 0.057250] ... MAX_LOCKDEP_ENTRIES: 16384
[ 0.061981] ... MAX_LOCKDEP_CHAINS: 32768
[ 0.066680] ... CHAINHASH_SIZE: 16384
[ 0.071411] memory used by lock dependency info: 3695 kB
[ 0.077056] per task-struct memory footprint: 1152 bytes
[ 0.082916] Calibrating delay loop... 324.40 BogoMIPS (lpj=1622016)
[ 0.143737] pid_max: default: 32768 minimum: 301
[ 0.149230] Security Framework initialized
[ 0.153930] Mount-cache hash table entries: 512
[ 0.247467] CPU: Testing write buffer coherency: ok
[ 0.256866] Setting up static identity map for 0x804db430 - 0x804db4a0
[ 0.286865] VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 2
[ 0.404479] pinctrl core: initialized pinctrl subsystem
[ 0.424957] regulator-dummy: no parameters
[ 0.437042] NET: Registered protocol family 16
[ 0.443664] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.615081] omap_gpio 48018000.gpio: Could not get gpio dbck
[ 0.626770] gpiochip_add: registered GPIOs 0 to 31 on device: gpio
[ 0.636871] OMAP GPIO hardware version 1.8
[ 0.647003] omap_gpio 4801a000.gpio: Could not get gpio dbck
[ 0.655456] gpiochip_add: registered GPIOs 32 to 63 on device: gpio
[ 0.668640] omap_gpio 4801c000.gpio: Could not get gpio dbck
[ 0.677062] gpiochip_add: registered GPIOs 64 to 95 on device: gpio
[ 0.690704] omap_gpio 4801e000.gpio: Could not get gpio dbck
[ 0.698974] gpiochip_add: registered GPIOs 96 to 127 on device: gpio
[ 0.712554] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
[ 0.730529] platform mmci-omap.0: alias fck already exists
[ 0.743072] No ATAGs?
[ 0.745300] hw-breakpoint: found 6 breakpoint and 1 watchpoint registers.
[ 0.752807] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.771942] OMAP DMA hardware revision 2.0
[ 1.001983] bio: create slab <bio-0> at 0
[ 1.308654] omap-dma-engine 48056000.dma-controller: OMAP DMA engine driver
[ 1.336578] SCSI subsystem initialized
[ 1.351013] usbcore: registered new interface driver usbfs
[ 1.358825] usbcore: registered new interface driver hub
[ 1.366912] usbcore: registered new device driver usb
[ 1.391571] omap_i2c 48070000.i2c: bus 0 rev3.3 at 400 kHz
[ 1.401855] omap_i2c 48072000.i2c: bus 1 rev3.3 at 400 kHz
[ 1.433074] Switched to clocksource 32k_counter
[ 1.892578] NET: Registered protocol family 2
[ 1.902313] TCP established hash table entries: 1024 (order: 0, 4096 bytes)
[ 1.910247] TCP bind hash table entries: 1024 (order: 3, 36864 bytes)
[ 1.918212] TCP: Hash tables configured (established 1024 bind 1024)
[ 1.925659] TCP: reno registered
[ 1.929168] UDP hash table entries: 256 (order: 2, 20480 bytes)
[ 1.936157] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
[ 1.946411] NET: Registered protocol family 1
[ 1.955749] RPC: Registered named UNIX socket transport module.
[ 1.962005] RPC: Registered udp transport module.
[ 1.967132] RPC: Registered tcp transport module.
[ 1.972106] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 1.983520] hw perfevents: enabled with v6 PMU driver, 3 counters available
[ 2.018554] futex hash table entries: 256 (order: 1, 10240 bytes)
[ 2.587036] VFS: Disk quotas dquot_6.5.2
[ 2.591400] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[ 2.603668] NFS: Registering the id_resolver key type
[ 2.610473] Key type id_resolver registered
[ 2.615142] Key type id_legacy registered
[ 2.619812] jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc.
[ 2.629089] msgmni has been set to 225
[ 2.645568] io scheduler noop registered
[ 2.649749] io scheduler deadline registered
[ 2.654632] io scheduler cfq registered (default)
[ 2.671997] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 2.702178] omap_uart 4806a000.serial: no wakeirq for uart0
[ 2.708282] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial@4806a000[0]'
[ 2.720428] 4806a000.serial: ttyO0 at MMIO 0x4806a000 (irq = 88, base_baud = 3000000) is a OMAP UART0
[ 2.736633] omap_uart 4806c000.serial: no wakeirq for uart0
[ 2.742553] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial@4806c000[0]'
[ 2.753723] 4806c000.serial: ttyO1 at MMIO 0x4806c000 (irq = 89, base_baud = 3000000) is a OMAP UART1
[ 2.768005] omap_uart 4806e000.serial: no wakeirq for uart0
[ 2.774078] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial@4806e000[0]'
[ 2.784912] 4806e000.serial: ttyO2 at MMIO 0x4806e000 (irq = 90, base_baud = 3000000) is a OMAP UART2
[ 2.795776] console [ttyO2] enabled
[ 2.795776] console [ttyO2] enabled
[ 2.803344] bootconsole [earlycon0] disabled
[ 2.803344] bootconsole [earlycon0] disabled
[ 2.825744] omap_rng 480a0000.rng: OMAP Random Number Generator ver. 40
[ 2.935699] brd: module loaded
[ 2.997741] loop: module loaded
[ 3.006866] Menelaus rev 2.2
[ 3.047821] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 3.059997] omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base c88c0000, freq 54 MHz
[ 3.071533] OneNAND Manufacturer: Samsung (0xec)
[ 3.076538] Muxed OneNAND(DDP) 256MB 1.8V 16-bit (0x48)
[ 3.082092] OneNAND version = 0x0011
[ 3.085968] Chip support all block unlock
[ 3.090332] onenand_wait: controller error = 0x0400
[ 3.097259] Scanning device for bad blocks
[ 3.254333] 6 ofpart partitions found on MTD device omap2-onenand
[ 3.260803] Creating 6 MTD partitions on "omap2-onenand":
[ 3.266662] 0x000000000000-0x000000020000 : "bootloader"
[ 3.292877] 0x000000020000-0x000000080000 : "config"
[ 3.312042] 0x000000080000-0x000000280000 : "kernel"
[ 3.331085] 0x000000280000-0x000000680000 : "initfs"
[ 3.350555] 0x000000680000-0x000010000000 : "rootfs"
[ 3.393737] 0x000000000000-0x000010000000 : "omap2-onenand"
[ 3.474853] usbcore: registered new interface driver asix
[ 3.482421] usbcore: registered new interface driver ax88179_178a
[ 3.490844] usbcore: registered new interface driver cdc_ether
[ 3.498992] usbcore: registered new interface driver r815x
[ 3.506896] usbcore: registered new interface driver smsc95xx
[ 3.514953] usbcore: registered new interface driver net1080
[ 3.522705] usbcore: registered new interface driver cdc_subset
[ 3.530944] usbcore: registered new interface driver zaurus
[ 3.539093] usbcore: registered new interface driver cdc_ncm
[ 3.551727] usbcore: registered new interface driver cdc_wdm
[ 3.559906] usbcore: registered new interface driver usb-storage
[ 3.568420] usbcore: registered new interface driver usbtest
[ 3.583953] mousedev: PS/2 mouse device common for all mice
[ 3.606262] i2c /dev entries driver
[ 3.620574] of_get_named_gpiod_flags exited with status 0
[ 3.626647] of_get_named_gpiod_flags exited with status 0
[ 3.632476] of_get_named_gpiod_flags exited with status 0
[ 3.656005] retu-mfd 2-0001: Retu & Vilma v1.5 found
[ 3.677124] input: retu-pwrbutton as /devices/ocp.3/i2c.4/i2c-2/2-0001/retu-pwrbutton/input/input0
[ 3.695190] Driver for 1-wire Dallas network protocol.
[ 3.724243] mmci-omap mmci-omap.0: no slots
[ 3.728820] platform mmci-omap.0: Driver mmci-omap requests probe deferral
[ 3.745727] usbcore: registered new interface driver usbhid
[ 3.751678] usbhid: USB HID core driver
[ 3.760375] oprofile: using arm/armv6
[ 3.766571] TCP: cubic registered
[ 3.770111] Initializing XFRM netlink socket
[ 3.775299] NET: Registered protocol family 17
[ 3.780242] NET: Registered protocol family 15
[ 3.786315] Key type dns_resolver registered
[ 3.804290] omap_mux_get_by_name: Could not find signal sys_ndmareq0
[ 3.811065] omap_mux_get_by_name: Could not find signal sys_ndmareq1
[ 3.817932] omap_mux_get_by_name: Could not find signal sys_ndmareq2
[ 3.824768] omap_mux_get_by_name: Could not find signal sys_ndmareq3
[ 3.831512] omap_mux_get_by_name: Could not find signal sys_ndmareq4
[ 3.838317] omap_mux_get_by_name: Could not find signal sys_ndmareq5
[ 3.854064] usb_phy_gen_xceiv supply vcc not found, using dummy regulator
[ 3.883972] tusb: prcm2.0 int2.0 gpio3.0 dma3.0 dieid2 rev3.1
[ 3.890167] musb-hdrc: ConfigData=0x06 (UTMI-8, dyn FIFOs, SoftConn)
[ 3.897064] musb-hdrc: MHDRC RTL version 1.400
[ 3.901885] musb-hdrc: setup fifo_mode 4
[ 3.906188] musb-hdrc: 28/31 max ep, 16384/16384 memory
[ 3.912506] musb-hdrc musb-hdrc.0.auto: MUSB HDRC host driver
[ 3.928985] musb-hdrc musb-hdrc.0.auto: new USB bus registered, assigned bus number 1
[ 3.942871] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[ 3.950256] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.958068] usb usb1: Product: MUSB HDRC host driver
[ 3.963439] usb usb1: Manufacturer: Linux 3.14.0-rc5-00014-g2297f72-dirty musb-hcd
[ 3.971466] usb usb1: SerialNumber: musb-hdrc.0.auto
[ 3.992279] hub 1-0:1.0: USB hub found
[ 3.997680] hub 1-0:1.0: 1 port detected
[ 4.022338] TUSB 6010
[ 4.157165] mmci-omap mmci-omap.0: command timeout (CMD52)
[ 4.165161] mmci-omap mmci-omap.0: command timeout (CMD52)
[ 4.196777] mmci-omap mmci-omap.0: command timeout (CMD5)
[ 4.203491] mmci-omap mmci-omap.0: command timeout (CMD5)
[ 4.210144] mmci-omap mmci-omap.0: command timeout (CMD5)
[ 4.219604] mmci-omap mmci-omap.0: command timeout (CMD5)
[ 4.241088] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 4.353851] Waiting for root device /dev/mmcblk0p2...
[ 4.385711] mmc0: host does not support reading read-only switch. assuming write-enable.
[ 4.395019] mmc0: new SDHC card at address ea4d
[ 4.407897] mmcblk0: mmc0:ea4d SU04G 3.79 GiB
[ 4.428863] mmcblk0: p1 p2
[ 4.447296] mmci-omap mmci-omap.0: command timeout (CMD52)
[ 4.454101] mmci-omap mmci-omap.0: command timeout (CMD52)
[ 4.464874] mmci-omap mmci-omap.0: command timeout (CMD8)
[ 4.477966] mmci-omap mmci-omap.0: command timeout (CMD5)
[ 4.488250] mmci-omap mmci-omap.0: command timeout (CMD5)
[ 4.498260] mmci-omap mmci-omap.0: command timeout (CMD5)
[ 4.506286] EXT3-fs (mmcblk0p2): recovery required on readonly filesystem
[ 4.513671] EXT3-fs (mmcblk0p2): write access will be enabled during recovery
[ 4.523468] mmci-omap mmci-omap.0: command timeout (CMD5)
[ 4.540527] mmci-omap mmci-omap.0: command timeout (CMD8)
[ 4.547363] kjournald starting. Commit interval 5 seconds
[ 4.562103] EXT3-fs (mmcblk0p2): recovery complete
[ 4.567413] EXT3-fs (mmcblk0p2): mounted filesystem with ordered data mode
[ 4.577270] VFS: Mounted root (ext3 filesystem) readonly on device 179:2.
[ 4.587280] Freeing unused kernel memory: 304K (c06da000 - c0726000)
[ 4.662048] mmc1: host does not support reading read-only switch. assuming write-enable.
[ 4.671020] mmc1: new SD card at address e624
[ 4.683898] mmcblk1: mmc1:e624 SD128 120 MiB
[ 4.706298] mmcblk1: p1
INIT: version 2.86 booting
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 00/12] ARM: OMAP2 DT clock conversion
2014-03-03 18:46 ` Tony Lindgren
@ 2014-03-03 18:51 ` Tero Kristo
0 siblings, 0 replies; 22+ messages in thread
From: Tero Kristo @ 2014-03-03 18:51 UTC (permalink / raw)
To: Tony Lindgren
Cc: Nishanth Menon, linux-omap, paul, mturquette, linux-arm-kernel,
devicetree
On 03/03/2014 08:46 PM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [140303 00:20]:
>> On 02/28/2014 08:33 PM, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [140228 10:21]:
>>>>
>>>> Hmm, some clock node is broken, might be missing a name or parent
>>>> name for some reason. Can you try to boot with DEBUG enabled so you
>>>> get pr_debug:s out and see which clock is being initialized during
>>>> the crash?
>>>
>>> ...
>>> [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: core_d18_ck
>>> [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_mux_fck
>>> [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_fck
>>> [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000
>>> ...
>>>
>>> We really should be registering the clocks lazily as needed BTW. That
>>> leaves out the dependency to DEBUG_LL for seeing any kind of decent
>>> error messages during the booting.
>>>
>>> Regards,
>>>
>>> Tony
>>>
>>
>> Hey Tony,
>>
>> Can you retry with the branch? I just pushed one patch there, seems
>> the parents for the vlynq_mux_fck were somewhat broken (there are
>> holes in the valid mux values list, which hasn't happened with any
>> other mux-clock so far.)
>>
>> If this works, I will rework the series a bit and send v2 out.
>> Alternatively I need to add extra debug info.
>
> Still getting this without omap3:
>
> drivers/built-in.o: In function `of_ti_dpll_setup':
> /home/tmlind/src/linux-2.6/drivers/clk/ti/dpll.c:235: undefined reference to `clkhwops_omap3_dpll'
> drivers/built-in.o:(.rodata+0x1d7a0): undefined reference to `omap3_noncore_dpll_enable'
> drivers/built-in.o:(.rodata+0x1d7a4): undefined reference to `omap3_noncore_dpll_disable'
> drivers/built-in.o:(.rodata+0x1d7b0): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0x1d7c4): undefined reference to `omap3_noncore_dpll_set_rate'
> drivers/built-in.o:(.rodata+0x1d808): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0x1d84c): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0x1d860): undefined reference to `omap3_noncore_dpll_set_rate'
>
> and after enabling omap3 getting this without 2430:
>
> drivers/built-in.o: In function `of_ti_omap2430_interface_clk_setup':
> /home/tmlind/src/linux-2.6/drivers/clk/ti/interface.c:129: undefined reference to `clkhwops_omap2430_i2chs_wait'
Yea, I didn't fix these with the patch I pushed, just the boot problem.
I will fix these with the next version of the set, in addition to the
issues reported by Nishanth.
>
> But after enabling those, it now boots on n8x0. The dmesg is below.
This is good, so the culprit was only the vlynq fck.
> Care to post a patch to try dropping the legacy clock data as it should
> now work with the DT clocks only for omap2?
Yes, I can post patches for this for omap2/omap3 also tomorrow.
-Tero
>
> Regards,
>
> Tony
>
>
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 3.14.0-rc5-00014-g2297f72-dirty (tmlind@muffinssi) (gcc version 4.3.5 (Debian 4.3.5-4) ) #388 Mon Mar 3 10:38:58 PST 2014
> [ 0.000000] CPU: ARMv6-compatible processor [4107b362] revision 2 (ARMv6TEJ), cr=00c5387d
> [ 0.000000] CPU: VIPT aliasing data cache, VIPT aliasing instruction cache
> [ 0.000000] Machine model: Nokia N800
> [ 0.000000] bootconsole [earlycon0] enabled
> [ 0.000000] debug: ignoring loglevel setting.
> [ 0.000000] Memory policy: Data cache writeback
> [ 0.000000] On node 0 totalpages: 32512
> [ 0.000000] free_area_init_node: node 0, pgdat c07969a8, node_mem_map c7df9000
> [ 0.000000] Normal zone: 256 pages used for memmap
> [ 0.000000] Normal zone: 0 pages reserved
> [ 0.000000] Normal zone: 32512 pages, LIFO batch:7
> [ 0.000000] CPU: All CPU(s) started in SVC mode.
> [ 0.000000] OMAP2420
> [ 0.000000]
> [ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
> [ 0.000000] pcpu-alloc: [0] 0
> [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32256
> [ 0.000000] Kernel command line: root=/dev/mmcblk0p2 rootwait console=ttyO2,115200 earlyprintk ignore_loglevel
> [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
> [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
> [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
> [ 0.000000] Memory: 115492K/130048K available (5098K kernel code, 457K rwdata, 1884K rodata, 304K init, 5485K bss, 14556K reserved, 0K highmem)
> [ 0.000000] Virtual kernel memory layout:
> [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
> [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
> [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB)
> [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
> [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
> [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
> [ 0.000000] .text : 0xc0008000 - 0xc06d9e10 (6984 kB)
> [ 0.000000] .init : 0xc06da000 - 0xc072601c ( 305 kB)
> [ 0.000000] .data : 0xc0728000 - 0xc079a690 ( 458 kB)
> [ 0.000000] .bss : 0xc079a690 - 0xc0cf5b10 (5486 kB)
> [ 0.000000] NR_IRQS:16 nr_irqs:16 16
> [ 0.000000] IRQ: Found an INTC at 0xfa0fe000 (revision 2.0) with 96 interrupts
> [ 0.000000] Total of 96 interrupts on 1 active controller
> [ 0.000000] Clocking rate (Crystal/DPLL/MPU): 19.2/658/329 MHz
> [ 0.000000] OMAP clockevent source: timer1 at 32768 Hz
> [ 0.000030] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65536000000000ns
> [ 0.008758] OMAP clocksource: 32k_counter at 32768 Hz
> [ 0.014465] hw-breakpoint: CPUID feature registers not supported. Assuming v6 debug is present.
> [ 0.026245] Console: colour dummy device 80x30
> [ 0.031005] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
> [ 0.039215] ... MAX_LOCKDEP_SUBCLASSES: 8
> [ 0.043609] ... MAX_LOCK_DEPTH: 48
> [ 0.048034] ... MAX_LOCKDEP_KEYS: 8191
> [ 0.052673] ... CLASSHASH_SIZE: 4096
> [ 0.057250] ... MAX_LOCKDEP_ENTRIES: 16384
> [ 0.061981] ... MAX_LOCKDEP_CHAINS: 32768
> [ 0.066680] ... CHAINHASH_SIZE: 16384
> [ 0.071411] memory used by lock dependency info: 3695 kB
> [ 0.077056] per task-struct memory footprint: 1152 bytes
> [ 0.082916] Calibrating delay loop... 324.40 BogoMIPS (lpj=1622016)
> [ 0.143737] pid_max: default: 32768 minimum: 301
> [ 0.149230] Security Framework initialized
> [ 0.153930] Mount-cache hash table entries: 512
> [ 0.247467] CPU: Testing write buffer coherency: ok
> [ 0.256866] Setting up static identity map for 0x804db430 - 0x804db4a0
> [ 0.286865] VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 2
> [ 0.404479] pinctrl core: initialized pinctrl subsystem
> [ 0.424957] regulator-dummy: no parameters
> [ 0.437042] NET: Registered protocol family 16
> [ 0.443664] DMA: preallocated 256 KiB pool for atomic coherent allocations
> [ 0.615081] omap_gpio 48018000.gpio: Could not get gpio dbck
> [ 0.626770] gpiochip_add: registered GPIOs 0 to 31 on device: gpio
> [ 0.636871] OMAP GPIO hardware version 1.8
> [ 0.647003] omap_gpio 4801a000.gpio: Could not get gpio dbck
> [ 0.655456] gpiochip_add: registered GPIOs 32 to 63 on device: gpio
> [ 0.668640] omap_gpio 4801c000.gpio: Could not get gpio dbck
> [ 0.677062] gpiochip_add: registered GPIOs 64 to 95 on device: gpio
> [ 0.690704] omap_gpio 4801e000.gpio: Could not get gpio dbck
> [ 0.698974] gpiochip_add: registered GPIOs 96 to 127 on device: gpio
> [ 0.712554] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> [ 0.730529] platform mmci-omap.0: alias fck already exists
> [ 0.743072] No ATAGs?
> [ 0.745300] hw-breakpoint: found 6 breakpoint and 1 watchpoint registers.
> [ 0.752807] hw-breakpoint: maximum watchpoint size is 4 bytes.
> [ 0.771942] OMAP DMA hardware revision 2.0
> [ 1.001983] bio: create slab <bio-0> at 0
> [ 1.308654] omap-dma-engine 48056000.dma-controller: OMAP DMA engine driver
> [ 1.336578] SCSI subsystem initialized
> [ 1.351013] usbcore: registered new interface driver usbfs
> [ 1.358825] usbcore: registered new interface driver hub
> [ 1.366912] usbcore: registered new device driver usb
> [ 1.391571] omap_i2c 48070000.i2c: bus 0 rev3.3 at 400 kHz
> [ 1.401855] omap_i2c 48072000.i2c: bus 1 rev3.3 at 400 kHz
> [ 1.433074] Switched to clocksource 32k_counter
> [ 1.892578] NET: Registered protocol family 2
> [ 1.902313] TCP established hash table entries: 1024 (order: 0, 4096 bytes)
> [ 1.910247] TCP bind hash table entries: 1024 (order: 3, 36864 bytes)
> [ 1.918212] TCP: Hash tables configured (established 1024 bind 1024)
> [ 1.925659] TCP: reno registered
> [ 1.929168] UDP hash table entries: 256 (order: 2, 20480 bytes)
> [ 1.936157] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
> [ 1.946411] NET: Registered protocol family 1
> [ 1.955749] RPC: Registered named UNIX socket transport module.
> [ 1.962005] RPC: Registered udp transport module.
> [ 1.967132] RPC: Registered tcp transport module.
> [ 1.972106] RPC: Registered tcp NFSv4.1 backchannel transport module.
> [ 1.983520] hw perfevents: enabled with v6 PMU driver, 3 counters available
> [ 2.018554] futex hash table entries: 256 (order: 1, 10240 bytes)
> [ 2.587036] VFS: Disk quotas dquot_6.5.2
> [ 2.591400] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
> [ 2.603668] NFS: Registering the id_resolver key type
> [ 2.610473] Key type id_resolver registered
> [ 2.615142] Key type id_legacy registered
> [ 2.619812] jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc.
> [ 2.629089] msgmni has been set to 225
> [ 2.645568] io scheduler noop registered
> [ 2.649749] io scheduler deadline registered
> [ 2.654632] io scheduler cfq registered (default)
> [ 2.671997] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
> [ 2.702178] omap_uart 4806a000.serial: no wakeirq for uart0
> [ 2.708282] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial@4806a000[0]'
> [ 2.720428] 4806a000.serial: ttyO0 at MMIO 0x4806a000 (irq = 88, base_baud = 3000000) is a OMAP UART0
> [ 2.736633] omap_uart 4806c000.serial: no wakeirq for uart0
> [ 2.742553] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial@4806c000[0]'
> [ 2.753723] 4806c000.serial: ttyO1 at MMIO 0x4806c000 (irq = 89, base_baud = 3000000) is a OMAP UART1
> [ 2.768005] omap_uart 4806e000.serial: no wakeirq for uart0
> [ 2.774078] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial@4806e000[0]'
> [ 2.784912] 4806e000.serial: ttyO2 at MMIO 0x4806e000 (irq = 90, base_baud = 3000000) is a OMAP UART2
> [ 2.795776] console [ttyO2] enabled
> [ 2.795776] console [ttyO2] enabled
> [ 2.803344] bootconsole [earlycon0] disabled
> [ 2.803344] bootconsole [earlycon0] disabled
> [ 2.825744] omap_rng 480a0000.rng: OMAP Random Number Generator ver. 40
> [ 2.935699] brd: module loaded
> [ 2.997741] loop: module loaded
> [ 3.006866] Menelaus rev 2.2
> [ 3.047821] mtdoops: mtd device (mtddev=name/number) must be supplied
> [ 3.059997] omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base c88c0000, freq 54 MHz
> [ 3.071533] OneNAND Manufacturer: Samsung (0xec)
> [ 3.076538] Muxed OneNAND(DDP) 256MB 1.8V 16-bit (0x48)
> [ 3.082092] OneNAND version = 0x0011
> [ 3.085968] Chip support all block unlock
> [ 3.090332] onenand_wait: controller error = 0x0400
> [ 3.097259] Scanning device for bad blocks
> [ 3.254333] 6 ofpart partitions found on MTD device omap2-onenand
> [ 3.260803] Creating 6 MTD partitions on "omap2-onenand":
> [ 3.266662] 0x000000000000-0x000000020000 : "bootloader"
> [ 3.292877] 0x000000020000-0x000000080000 : "config"
> [ 3.312042] 0x000000080000-0x000000280000 : "kernel"
> [ 3.331085] 0x000000280000-0x000000680000 : "initfs"
> [ 3.350555] 0x000000680000-0x000010000000 : "rootfs"
> [ 3.393737] 0x000000000000-0x000010000000 : "omap2-onenand"
> [ 3.474853] usbcore: registered new interface driver asix
> [ 3.482421] usbcore: registered new interface driver ax88179_178a
> [ 3.490844] usbcore: registered new interface driver cdc_ether
> [ 3.498992] usbcore: registered new interface driver r815x
> [ 3.506896] usbcore: registered new interface driver smsc95xx
> [ 3.514953] usbcore: registered new interface driver net1080
> [ 3.522705] usbcore: registered new interface driver cdc_subset
> [ 3.530944] usbcore: registered new interface driver zaurus
> [ 3.539093] usbcore: registered new interface driver cdc_ncm
> [ 3.551727] usbcore: registered new interface driver cdc_wdm
> [ 3.559906] usbcore: registered new interface driver usb-storage
> [ 3.568420] usbcore: registered new interface driver usbtest
> [ 3.583953] mousedev: PS/2 mouse device common for all mice
> [ 3.606262] i2c /dev entries driver
> [ 3.620574] of_get_named_gpiod_flags exited with status 0
> [ 3.626647] of_get_named_gpiod_flags exited with status 0
> [ 3.632476] of_get_named_gpiod_flags exited with status 0
> [ 3.656005] retu-mfd 2-0001: Retu & Vilma v1.5 found
> [ 3.677124] input: retu-pwrbutton as /devices/ocp.3/i2c.4/i2c-2/2-0001/retu-pwrbutton/input/input0
> [ 3.695190] Driver for 1-wire Dallas network protocol.
> [ 3.724243] mmci-omap mmci-omap.0: no slots
> [ 3.728820] platform mmci-omap.0: Driver mmci-omap requests probe deferral
> [ 3.745727] usbcore: registered new interface driver usbhid
> [ 3.751678] usbhid: USB HID core driver
> [ 3.760375] oprofile: using arm/armv6
> [ 3.766571] TCP: cubic registered
> [ 3.770111] Initializing XFRM netlink socket
> [ 3.775299] NET: Registered protocol family 17
> [ 3.780242] NET: Registered protocol family 15
> [ 3.786315] Key type dns_resolver registered
> [ 3.804290] omap_mux_get_by_name: Could not find signal sys_ndmareq0
> [ 3.811065] omap_mux_get_by_name: Could not find signal sys_ndmareq1
> [ 3.817932] omap_mux_get_by_name: Could not find signal sys_ndmareq2
> [ 3.824768] omap_mux_get_by_name: Could not find signal sys_ndmareq3
> [ 3.831512] omap_mux_get_by_name: Could not find signal sys_ndmareq4
> [ 3.838317] omap_mux_get_by_name: Could not find signal sys_ndmareq5
> [ 3.854064] usb_phy_gen_xceiv supply vcc not found, using dummy regulator
> [ 3.883972] tusb: prcm2.0 int2.0 gpio3.0 dma3.0 dieid2 rev3.1
> [ 3.890167] musb-hdrc: ConfigData=0x06 (UTMI-8, dyn FIFOs, SoftConn)
> [ 3.897064] musb-hdrc: MHDRC RTL version 1.400
> [ 3.901885] musb-hdrc: setup fifo_mode 4
> [ 3.906188] musb-hdrc: 28/31 max ep, 16384/16384 memory
> [ 3.912506] musb-hdrc musb-hdrc.0.auto: MUSB HDRC host driver
> [ 3.928985] musb-hdrc musb-hdrc.0.auto: new USB bus registered, assigned bus number 1
> [ 3.942871] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
> [ 3.950256] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
> [ 3.958068] usb usb1: Product: MUSB HDRC host driver
> [ 3.963439] usb usb1: Manufacturer: Linux 3.14.0-rc5-00014-g2297f72-dirty musb-hcd
> [ 3.971466] usb usb1: SerialNumber: musb-hdrc.0.auto
> [ 3.992279] hub 1-0:1.0: USB hub found
> [ 3.997680] hub 1-0:1.0: 1 port detected
> [ 4.022338] TUSB 6010
> [ 4.157165] mmci-omap mmci-omap.0: command timeout (CMD52)
> [ 4.165161] mmci-omap mmci-omap.0: command timeout (CMD52)
> [ 4.196777] mmci-omap mmci-omap.0: command timeout (CMD5)
> [ 4.203491] mmci-omap mmci-omap.0: command timeout (CMD5)
> [ 4.210144] mmci-omap mmci-omap.0: command timeout (CMD5)
> [ 4.219604] mmci-omap mmci-omap.0: command timeout (CMD5)
> [ 4.241088] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
> [ 4.353851] Waiting for root device /dev/mmcblk0p2...
> [ 4.385711] mmc0: host does not support reading read-only switch. assuming write-enable.
> [ 4.395019] mmc0: new SDHC card at address ea4d
> [ 4.407897] mmcblk0: mmc0:ea4d SU04G 3.79 GiB
> [ 4.428863] mmcblk0: p1 p2
> [ 4.447296] mmci-omap mmci-omap.0: command timeout (CMD52)
> [ 4.454101] mmci-omap mmci-omap.0: command timeout (CMD52)
> [ 4.464874] mmci-omap mmci-omap.0: command timeout (CMD8)
> [ 4.477966] mmci-omap mmci-omap.0: command timeout (CMD5)
> [ 4.488250] mmci-omap mmci-omap.0: command timeout (CMD5)
> [ 4.498260] mmci-omap mmci-omap.0: command timeout (CMD5)
> [ 4.506286] EXT3-fs (mmcblk0p2): recovery required on readonly filesystem
> [ 4.513671] EXT3-fs (mmcblk0p2): write access will be enabled during recovery
> [ 4.523468] mmci-omap mmci-omap.0: command timeout (CMD5)
> [ 4.540527] mmci-omap mmci-omap.0: command timeout (CMD8)
> [ 4.547363] kjournald starting. Commit interval 5 seconds
> [ 4.562103] EXT3-fs (mmcblk0p2): recovery complete
> [ 4.567413] EXT3-fs (mmcblk0p2): mounted filesystem with ordered data mode
> [ 4.577270] VFS: Mounted root (ext3 filesystem) readonly on device 179:2.
> [ 4.587280] Freeing unused kernel memory: 304K (c06da000 - c0726000)
> [ 4.662048] mmc1: host does not support reading read-only switch. assuming write-enable.
> [ 4.671020] mmc1: new SD card at address e624
> [ 4.683898] mmcblk1: mmc1:e624 SD128 120 MiB
> [ 4.706298] mmcblk1: p1
> INIT: version 2.86 booting
>
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