[PATCH 0/8] USB support for DRA7-evm

[PATCH 0/8] USB support for DRA7-evm

[Roger Quadros]

Hi,

This series enables the 2 USB ports on the DRA7-evm.

Patches are based on on 3.14-rc4 with balbi/next, linux-phy/next,
omap-for-v3.15/dt merged and [1] applied.

[1] - http://article.gmane.org/gmane.linux.drivers.devicetree/65223.

cheers,
-roger

---
Roger Quadros (8):
  CLK: ti: dra7: Initialize USB_DPLL
  ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate
  ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
  phy: omap-usb2: Use generic clock names "wkupclk" and "refclk"
  phy: omap-usb2: Add clock names to Documentation binding
  ARM: dts: omap4+: Add clocks to USB2 PHY node
  ARM: dts: dra7: Add USB related nodes
  dts: dra7-evm: add USB support

 Documentation/devicetree/bindings/phy/ti-phy.txt |   7 ++
 arch/arm/boot/dts/dra7-evm.dts                   |  24 +++++
 arch/arm/boot/dts/dra7.dtsi                      | 110 +++++++++++++++++++++++
 arch/arm/boot/dts/dra7xx-clocks.dtsi             |  12 ++-
 arch/arm/boot/dts/omap4.dtsi                     |   2 +
 arch/arm/boot/dts/omap5.dtsi                     |   2 +
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c        |  22 ++---
 drivers/clk/ti/clk-7xx.c                         |  11 +++
 drivers/phy/phy-omap-usb2.c                      |   8 +-
 9 files changed, 182 insertions(+), 16 deletions(-)

-- 
1.8.3.2

[PATCH 1/8] CLK: ti: dra7: Initialize USB_DPLL

[Roger Quadros]

USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Also program USB_DLL_M2 output to half rate.

CC: Mike Turquette <mturquette@linaro.org>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 drivers/clk/ti/clk-7xx.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 9977653..f89f3c2 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -18,6 +18,7 @@
 
 #define DRA7_DPLL_ABE_DEFFREQ				361267200
 #define DRA7_DPLL_GMAC_DEFFREQ				1000000000
+#define DRA7_DPLL_USB_DEFFREQ				960000000
 
 
 static struct ti_dt_clk dra7xx_clks[] = {
@@ -328,5 +329,15 @@ int __init dra7xx_dt_clk_init(void)
 	if (rc)
 		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
 
+	dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
+	rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+	dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
+	rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
+	if (rc)
+		pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
+
 	return rc;
 }
-- 
1.8.3.2

[PATCH 2/8] ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate

[Roger Quadros]

This clock gate description was missing in older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.

Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
usb_otg_ss2_refclk960m.

CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e96da9a..b8d3a9d 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1386,6 +1386,14 @@
 		ti,dividers = <1>, <8>;
 	};
 
+	l3init_960m_gfclk: l3init_960m_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_clkdcoldo>;
+		ti,bit-shift = <8>;
+		reg = <0x06c0>;
+	};
+
 	dss_32khz_clk: dss_32khz_clk {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
@@ -1533,7 +1541,7 @@
 	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_usb_clkdcoldo>;
+		clocks = <&l3init_960m_gfclk>;
 		ti,bit-shift = <8>;
 		reg = <0x13f0>;
 	};
@@ -1541,7 +1549,7 @@
 	usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_usb_clkdcoldo>;
+		clocks = <&l3init_960m_gfclk>;
 		ti,bit-shift = <8>;
 		reg = <0x1340>;
 	};
-- 
1.8.3.2

[PATCH 3/8] ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss

[Roger Quadros]

Add the sysconfig class bits for the Super Speed USB
controllers

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 3c9a430..cca24ad 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1752,8 +1752,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
  *
  */
 
+static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+			   SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
 	.name	= "usb_otg_ss",
+	.sysc	= &dra7xx_usb_otg_ss_sysc,
 };
 
 /* usb_otg_ss1 */
-- 
1.8.3.2

[PATCH 4/8] phy: omap-usb2: Use generic clock names "wkupclk" and "refclk"

[Roger Quadros]

As clocks might be named differently on multiple platforms, use a generic
name in the driver and allow device tree node to specify the platform
specific clock name.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 drivers/phy/phy-omap-usb2.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index a2205a8..fb5e515 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -275,16 +275,16 @@ static int omap_usb2_probe(struct platform_device *pdev)
 	if (IS_ERR(phy_provider))
 		return PTR_ERR(phy_provider);
 
-	phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
+	phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
 	if (IS_ERR(phy->wkupclk)) {
-		dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
+		dev_err(&pdev->dev, "unable to get wkupclk\n");
 		return PTR_ERR(phy->wkupclk);
 	}
 	clk_prepare(phy->wkupclk);
 
-	phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
+	phy->optclk = devm_clk_get(phy->dev, "refclk");
 	if (IS_ERR(phy->optclk))
-		dev_vdbg(&pdev->dev, "unable to get refclk960m\n");
+		dev_dbg(&pdev->dev, "unable to get refclk\n");
 	else
 		clk_prepare(phy->optclk);
 
-- 
1.8.3.2

[PATCH 5/8] phy: omap-usb2: Add clock names to Documentation binding

[Roger Quadros]

Add "wkupclk" and "refclk" information to DT binding information.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 Documentation/devicetree/bindings/phy/ti-phy.txt | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 4ab9cb1..49c381c 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -36,6 +36,11 @@ Required properties:
  - reg : Address and length of the register set for the device.
  - #phy-cells: determine the number of cells that should be given in the
    phandle while referencing this phy.
+ - clocks: a list of phandles and clock-specifier pairs, one for each entry in
+   clock-names.
+ - clock-names: should include:
+   * "wkupclk" - wakeup clock.
+   * "refclk" - reference clock (optional).
 
 Optional properties:
  - ctrl-module : phandle of the control module used by PHY driver to power on
@@ -48,6 +53,8 @@ usb2phy@4a0ad080 {
 	reg = <0x4a0ad080 0x58>;
 	ctrl-module = <&omap_control_usb>;
 	#phy-cells = <0>;
+	clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
+	clock-names = "wkupclk", "refclk";
 };
 
 TI PIPE3 PHY
-- 
1.8.3.2

[PATCH 6/8] ARM: dts: omap4+: Add clocks to USB2 PHY node

[Roger Quadros]

The USB2 PHY driver expects named clocks for wakeup clock
and reference clock. Provide this information for USB2 PHY
nodes in OMAP4 and OMAP5 SoC DTS.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi | 2 ++
 arch/arm/boot/dts/omap5.dtsi | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4e15be5..2f6cfa6 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -608,6 +608,8 @@
 				compatible = "ti,omap-usb2";
 				reg = <0x4a0ad080 0x58>;
 				ctrl-module = <&omap_control_usb2phy>;
+				clocks = <&usb_phy_cm_clk32k>;
+				clock-names = "wkupclk";
 				#phy-cells = <0>;
 			};
 		};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 521caab..bf629bb 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -769,6 +769,8 @@
 				compatible = "ti,omap-usb2";
 				reg = <0x4a084000 0x7c>;
 				ctrl-module = <&omap_control_usb2phy>;
+				clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
+				clock-names = "wkupclk", "refclk";
 				#phy-cells = <0>;
 			};
 
-- 
1.8.3.2

[PATCH 7/8] ARM: dts: dra7: Add USB related nodes

[Roger Quadros]

Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.

Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi               | 110 ++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  10 ---
 2 files changed, 110 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 597979b..1e73900 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -811,6 +811,116 @@
 			clocks = <&sata_ref_clk>;
 			ti,hwmods = "sata";
 		};
+
+		omap_control_usb2phy1: control-phy@4a002300 {
+			compatible = "ti,control-phy-usb2";
+			reg = <0x4a002300 0x4>;
+			reg-names = "power";
+		};
+
+		omap_control_usb3phy1: control-phy@4a002370 {
+			compatible = "ti,control-phy-pipe3";
+			reg = <0x4a002370 0x4>;
+			reg-names = "power";
+		};
+
+		omap_control_usb2phy2: control-phy@0x4a002e74 {
+			compatible = "ti,control-phy-usb2-dra7";
+			reg = <0x4a002e74 0x4>;
+			reg-names = "power";
+		};
+
+		/* OCP2SCP1 */
+		ocp2scp@4a080000 {
+			compatible = "ti,omap-ocp2scp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = <0x4a080000 0x20>;
+			ti,hwmods = "ocp2scp1";
+
+			usb2_phy1: phy@4a084000 {
+				compatible = "ti,omap-usb2";
+				reg = <0x4a084000 0x400>;
+				ctrl-module = <&omap_control_usb2phy1>;
+				clocks = <&usb_phy1_always_on_clk32k>,
+					 <&usb_otg_ss1_refclk960m>;
+				clock-names =	"wkupclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+
+			usb2_phy2: phy@4a085000 {
+				compatible = "ti,omap-usb2";
+				reg = <0x4a085000 0x400>;
+				ctrl-module = <&omap_control_usb2phy2>;
+				clocks = <&usb_phy2_always_on_clk32k>,
+					 <&usb_otg_ss2_refclk960m>;
+				clock-names =	"wkupclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+
+			usb3_phy1: phy@4a084400 {
+				compatible = "ti,omap-usb3";
+				reg = <0x4a084400 0x80>,
+				      <0x4a084800 0x64>,
+				      <0x4a084c00 0x40>;
+				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+				ctrl-module = <&omap_control_usb3phy1>;
+				clocks = <&usb_phy3_always_on_clk32k>,
+					 <&sys_clkin1>,
+					 <&usb_otg_ss1_refclk960m>,
+					 <&dpll_core_h13x2_ck>;
+				clock-names =	"wkupclk",
+						"sysclk",
+						"refclk",
+						"optclk";
+				#phy-cells = <0>;
+			};
+		};
+
+		omap_dwc3_1@48880000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss1";
+			reg = <0x48880000 0x10000>;
+			interrupts = <0 77 4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			usb1: usb@48890000 {
+				compatible = "snps,dwc3";
+				reg = <0x48890000 0x17000>;
+				interrupts = <0 76 4>;
+				phys = <&usb2_phy1>, <&usb3_phy1>;
+				phy-names = "usb2-phy", "usb3-phy";
+				tx-fifo-resize;
+				maximum-speed = "super-speed";
+				dr_mode = "otg";
+			};
+		};
+
+		omap_dwc3_2@488c0000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss2";
+			reg = <0x488c0000 0x10000>;
+			interrupts = <0 92 4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			usb2: usb@488d0000 {
+				compatible = "snps,dwc3";
+				reg = <0x488d0000 0x17000>;
+				interrupts = <0 78 4>;
+				phys = <&usb2_phy2>;
+				phy-names = "usb2-phy";
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
 	};
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index cca24ad..403ba02 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -2351,21 +2351,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
-	{
-		.pa_start	= 0x4a080000,
-		.pa_end		= 0x4a08001f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_cfg -> ocp2scp1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
 	.master		= &dra7xx_l4_cfg_hwmod,
 	.slave		= &dra7xx_ocp2scp1_hwmod,
 	.clk		= "l4_root_clk_div",
-	.addr		= dra7xx_ocp2scp1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-- 
1.8.3.2

[PATCH 8/8] dts: dra7-evm: add USB support

[Roger Quadros]

Add USB pinmux information and USB modes
for the first 2 USB controllers.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..41c600b 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,18 @@
 			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
+
+	usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+			0x280	0xc0000	/* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
+                >;
+        };
+
+	usb2_pins: pinmux_usb2_pins {
+                pinctrl-single,pins = <
+			0x284	0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
+                >;
+        };
 };
 
 &i2c1 {
@@ -273,3 +285,15 @@
 &cpu0 {
 	cpu0-supply = <&smps123_reg>;
 };
+
+&usb1 {
+	dr_mode = "otg";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2 {
+	dr_mode = "otg";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb2_pins>;
+};
-- 
1.8.3.2

Re: [PATCH 1/8] CLK: ti: dra7: Initialize USB_DPLL

[Tero Kristo]

On 03/07/2014 03:09 PM, Roger Quadros wrote:
> USB_DPLL must be initialized and locked at boot so that
> USB modules can work.
>
> Also program USB_DLL_M2 output to half rate.
>
> CC: Mike Turquette <mturquette@linaro.org>
> CC: Tero Kristo <t-kristo@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>   drivers/clk/ti/clk-7xx.c | 11 +++++++++++
>   1 file changed, 11 insertions(+)
>
> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
> index 9977653..f89f3c2 100644
> --- a/drivers/clk/ti/clk-7xx.c
> +++ b/drivers/clk/ti/clk-7xx.c
> @@ -18,6 +18,7 @@
>
>   #define DRA7_DPLL_ABE_DEFFREQ				361267200
>   #define DRA7_DPLL_GMAC_DEFFREQ				1000000000
> +#define DRA7_DPLL_USB_DEFFREQ				960000000
>
>
>   static struct ti_dt_clk dra7xx_clks[] = {
> @@ -328,5 +329,15 @@ int __init dra7xx_dt_clk_init(void)
>   	if (rc)
>   		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
>
> +	dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
> +	rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
> +	if (rc)
> +		pr_err("%s: failed to configure USB DPLL!\n", __func__);
> +
> +	dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
> +	rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
> +	if (rc)
> +		pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
> +

I would rather see this done using the default-rate mechanism provided here:

https://www.mail-archive.com/linux-omap@vger.kernel.org/msg101300.html

However, this remains to be commented by Mike whether the patch is okay 
or not.

-Tero

>   	return rc;
>   }
>

Re: [PATCH 2/8] ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate

[Tero Kristo]

On 03/07/2014 03:09 PM, Roger Quadros wrote:
> This clock gate description was missing in older Reference manuals.
> It is present on the SoC to provide 960MHz reference clock to the
> internal USB PHYs.

Can you provide a document reference here?

-Tero

>
> Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
> usb_otg_ss2_refclk960m.
>
> CC: Tero Kristo <t-kristo@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>   arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++++++++++--
>   1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> index e96da9a..b8d3a9d 100644
> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> @@ -1386,6 +1386,14 @@
>   		ti,dividers = <1>, <8>;
>   	};
>
> +	l3init_960m_gfclk: l3init_960m_gfclk {
> +		#clock-cells = <0>;
> +		compatible = "ti,gate-clock";
> +		clocks = <&dpll_usb_clkdcoldo>;
> +		ti,bit-shift = <8>;
> +		reg = <0x06c0>;
> +	};
> +
>   	dss_32khz_clk: dss_32khz_clk {
>   		#clock-cells = <0>;
>   		compatible = "ti,gate-clock";
> @@ -1533,7 +1541,7 @@
>   	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
>   		#clock-cells = <0>;
>   		compatible = "ti,gate-clock";
> -		clocks = <&dpll_usb_clkdcoldo>;
> +		clocks = <&l3init_960m_gfclk>;
>   		ti,bit-shift = <8>;
>   		reg = <0x13f0>;
>   	};
> @@ -1541,7 +1549,7 @@
>   	usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
>   		#clock-cells = <0>;
>   		compatible = "ti,gate-clock";
> -		clocks = <&dpll_usb_clkdcoldo>;
> +		clocks = <&l3init_960m_gfclk>;
>   		ti,bit-shift = <8>;
>   		reg = <0x1340>;
>   	};
>

Re: [PATCH 5/8] phy: omap-usb2: Add clock names to Documentation binding

[Felipe Balbi]

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On Fri, Mar 07, 2014 at 03:09:08PM +0200, Roger Quadros wrote:
> Add "wkupclk" and "refclk" information to DT binding information.
> 
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---

so, should I take this one ?

-- 
balbi

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Re: [PATCH 5/8] phy: omap-usb2: Add clock names to Documentation binding

[Kishon Vijay Abraham I]

Felipe,

On Friday 07 March 2014 09:34 PM, Felipe Balbi wrote:
> On Fri, Mar 07, 2014 at 03:09:08PM +0200, Roger Quadros wrote:
>> Add "wkupclk" and "refclk" information to DT binding information.
>>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>
> so, should I take this one ?

yes.. the ti-phy.txt is only in your tree.

Thanks
Kishon
>

Re: [PATCH 5/8] phy: omap-usb2: Add clock names to Documentation binding

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 555 bytes --]

On Fri, Mar 07, 2014 at 09:53:03PM +0530, Kishon Vijay Abraham I wrote:
> Felipe,
> 
> On Friday 07 March 2014 09:34 PM, Felipe Balbi wrote:
> >On Fri, Mar 07, 2014 at 03:09:08PM +0200, Roger Quadros wrote:
> >>Add "wkupclk" and "refclk" information to DT binding information.
> >>
> >>Signed-off-by: Roger Quadros <rogerq@ti.com>
> >>---
> >
> >so, should I take this one ?
> 
> yes.. the ti-phy.txt is only in your tree.

yeah, I know that, but I need to know if this is safe to be applied as
in "it won't change anymore".

-- 
balbi

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Re: [PATCH 1/8] CLK: ti: dra7: Initialize USB_DPLL

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [140307 05:46]:
> On 03/07/2014 03:09 PM, Roger Quadros wrote:
> >USB_DPLL must be initialized and locked at boot so that
> >USB modules can work.
> >
> >Also program USB_DLL_M2 output to half rate.
> >
> >CC: Mike Turquette <mturquette@linaro.org>
> >CC: Tero Kristo <t-kristo@ti.com>
> >Signed-off-by: Roger Quadros <rogerq@ti.com>
> >---
> >  drivers/clk/ti/clk-7xx.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> >diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
> >index 9977653..f89f3c2 100644
> >--- a/drivers/clk/ti/clk-7xx.c
> >+++ b/drivers/clk/ti/clk-7xx.c
> >@@ -18,6 +18,7 @@
> >
> >  #define DRA7_DPLL_ABE_DEFFREQ				361267200
> >  #define DRA7_DPLL_GMAC_DEFFREQ				1000000000
> >+#define DRA7_DPLL_USB_DEFFREQ				960000000
> >
> >
> >  static struct ti_dt_clk dra7xx_clks[] = {
> >@@ -328,5 +329,15 @@ int __init dra7xx_dt_clk_init(void)
> >  	if (rc)
> >  		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
> >
> >+	dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
> >+	rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
> >+	if (rc)
> >+		pr_err("%s: failed to configure USB DPLL!\n", __func__);
> >+
> >+	dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
> >+	rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
> >+	if (rc)
> >+		pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
> >+
> 
> I would rather see this done using the default-rate mechanism provided here:
> 
> https://www.mail-archive.com/linux-omap@vger.kernel.org/msg101300.html
> 
> However, this remains to be commented by Mike whether the patch is
> okay or not.

Yes let's wait for that and not add hacks for new features.

Regards,

Tony

Re: [PATCH 2/8] ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate

[Roger Quadros]

On 03/07/2014 03:59 PM, Tero Kristo wrote:
> On 03/07/2014 03:09 PM, Roger Quadros wrote:
>> This clock gate description was missing in older Reference manuals.
>> It is present on the SoC to provide 960MHz reference clock to the
>> internal USB PHYs.
> 
> Can you provide a document reference here?
> 

Unfortunately it hasn't yet been included in the TRM.
I have the internal defect ID but I don't think it makes any sense here.

DRA7xx-TRMINC00203

cheers,
-roger

> 
>>
>> Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
>> usb_otg_ss2_refclk960m.
>>
>> CC: Tero Kristo <t-kristo@ti.com>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>>   arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++++++++++--
>>   1 file changed, 10 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> index e96da9a..b8d3a9d 100644
>> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> @@ -1386,6 +1386,14 @@
>>           ti,dividers = <1>, <8>;
>>       };
>>
>> +    l3init_960m_gfclk: l3init_960m_gfclk {
>> +        #clock-cells = <0>;
>> +        compatible = "ti,gate-clock";
>> +        clocks = <&dpll_usb_clkdcoldo>;
>> +        ti,bit-shift = <8>;
>> +        reg = <0x06c0>;
>> +    };
>> +
>>       dss_32khz_clk: dss_32khz_clk {
>>           #clock-cells = <0>;
>>           compatible = "ti,gate-clock";
>> @@ -1533,7 +1541,7 @@
>>       usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
>>           #clock-cells = <0>;
>>           compatible = "ti,gate-clock";
>> -        clocks = <&dpll_usb_clkdcoldo>;
>> +        clocks = <&l3init_960m_gfclk>;
>>           ti,bit-shift = <8>;
>>           reg = <0x13f0>;
>>       };
>> @@ -1541,7 +1549,7 @@
>>       usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
>>           #clock-cells = <0>;
>>           compatible = "ti,gate-clock";
>> -        clocks = <&dpll_usb_clkdcoldo>;
>> +        clocks = <&l3init_960m_gfclk>;
>>           ti,bit-shift = <8>;
>>           reg = <0x1340>;
>>       };
>>
> 

[PATCH v2 1/8] ARM: dts: dra7: Initialize USB_DPLL

[Roger Quadros]

USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Program USB_DLL_M2 output to half rate as well.

Patch depends on
https://www.mail-archive.com/linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg101300.html

CC: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
CC: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Signed-off-by: Roger Quadros <rogerq-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/dra7.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 597979b..f376923 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -815,3 +815,11 @@
 };
 
 /include/ "dra7xx-clocks.dtsi"
+
+&dpll_usb_ck {
+        default-rate = <960000000>;
+};
+
+&dpll_usb_m2_ck {
+	default-rate = <480000000>;
+};
-- 
1.8.3.2

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Re: [PATCH v2 1/8] ARM: dts: dra7: Initialize USB_DPLL

[Tero Kristo]

On 03/10/2014 02:49 PM, Roger Quadros wrote:
> USB_DPLL must be initialized and locked at boot so that
> USB modules can work.
>
> Program USB_DLL_M2 output to half rate as well.
>
> Patch depends on
> https://www.mail-archive.com/linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg101300.html
>
> CC: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> CC: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Roger Quadros <rogerq-l0cyMroinI0@public.gmane.org>
> ---
>   arch/arm/boot/dts/dra7.dtsi | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 597979b..f376923 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -815,3 +815,11 @@
>   };
>
>   /include/ "dra7xx-clocks.dtsi"
> +
> +&dpll_usb_ck {
> +        default-rate = <960000000>;
> +};
> +
> +&dpll_usb_m2_ck {
> +	default-rate = <480000000>;
> +};
>

You can add these directly under the dra7xx-clocks.dtsi file as well, as 
I don't think anybody needs to modify these. And the properties can be 
added directly under the nodes themselves.

However, this patch can't be acked yet as we have no feedback from Mike 
for the default-rate proposal.

-Tero

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Re: [PATCH v2 1/8] ARM: dts: dra7: Initialize USB_DPLL

[Roger Quadros]

On 03/10/2014 03:28 PM, Tero Kristo wrote:
> On 03/10/2014 02:49 PM, Roger Quadros wrote:
>> USB_DPLL must be initialized and locked at boot so that
>> USB modules can work.
>>
>> Program USB_DLL_M2 output to half rate as well.
>>
>> Patch depends on
>> https://www.mail-archive.com/linux-omap@vger.kernel.org/msg101300.html
>>
>> CC: Mike Turquette <mturquette@linaro.org>
>> CC: Tero Kristo <t-kristo@ti.com>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>>   arch/arm/boot/dts/dra7.dtsi | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 597979b..f376923 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -815,3 +815,11 @@
>>   };
>>
>>   /include/ "dra7xx-clocks.dtsi"
>> +
>> +&dpll_usb_ck {
>> +        default-rate = <960000000>;
>> +};
>> +
>> +&dpll_usb_m2_ck {
>> +    default-rate = <480000000>;
>> +};
>>
> 
> You can add these directly under the dra7xx-clocks.dtsi file as well, as I don't think anybody needs to modify these. And the properties can be added directly under the nodes themselves.
> 
> However, this patch can't be acked yet as we have no feedback from Mike for the default-rate proposal.

OK. I'll wait for the "default-rate" patch to be approved first and then revise this patch based on your
suggestion. Thanks for the review.

cheers,
-roger

Re: [PATCH 7/8] ARM: dts: dra7: Add USB related nodes

[Kishon Vijay Abraham I]

Hi Roger,

On Friday 07 March 2014 06:39 PM, Roger Quadros wrote:
> Add nodes for the Super Speed USB controllers, omap-control-usb,
> USB2 PHY and USB3 PHY devices.
>
> Remove ocp2scp1 address space from hwmod data as it is
> now provided via device tree.
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>   arch/arm/boot/dts/dra7.dtsi               | 110 ++++++++++++++++++++++++++++++
>   arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  10 ---
>   2 files changed, 110 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 597979b..1e73900 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -811,6 +811,116 @@
>   			clocks = <&sata_ref_clk>;
>   			ti,hwmods = "sata";
>   		};
> +
> +		omap_control_usb2phy1: control-phy@4a002300 {
> +			compatible = "ti,control-phy-usb2";
> +			reg = <0x4a002300 0x4>;
> +			reg-names = "power";
> +		};
> +
> +		omap_control_usb3phy1: control-phy@4a002370 {
> +			compatible = "ti,control-phy-pipe3";
> +			reg = <0x4a002370 0x4>;
> +			reg-names = "power";
> +		};
> +
> +		omap_control_usb2phy2: control-phy@0x4a002e74 {
> +			compatible = "ti,control-phy-usb2-dra7";
> +			reg = <0x4a002e74 0x4>;
> +			reg-names = "power";
> +		};
> +
> +		/* OCP2SCP1 */
> +		ocp2scp@4a080000 {
> +			compatible = "ti,omap-ocp2scp";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			reg = <0x4a080000 0x20>;
> +			ti,hwmods = "ocp2scp1";
> +
> +			usb2_phy1: phy@4a084000 {
> +				compatible = "ti,omap-usb2";
> +				reg = <0x4a084000 0x400>;
> +				ctrl-module = <&omap_control_usb2phy1>;
> +				clocks = <&usb_phy1_always_on_clk32k>,
> +					 <&usb_otg_ss1_refclk960m>;
> +				clock-names =	"wkupclk",
> +						"refclk";
> +				#phy-cells = <0>;
> +			};
> +
> +			usb2_phy2: phy@4a085000 {
> +				compatible = "ti,omap-usb2";
> +				reg = <0x4a085000 0x400>;
> +				ctrl-module = <&omap_control_usb2phy2>;
> +				clocks = <&usb_phy2_always_on_clk32k>,
> +					 <&usb_otg_ss2_refclk960m>;
> +				clock-names =	"wkupclk",
> +						"refclk";
> +				#phy-cells = <0>;
> +			};
> +
> +			usb3_phy1: phy@4a084400 {
> +				compatible = "ti,omap-usb3";
> +				reg = <0x4a084400 0x80>,
> +				      <0x4a084800 0x64>,
> +				      <0x4a084c00 0x40>;
> +				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> +				ctrl-module = <&omap_control_usb3phy1>;
> +				clocks = <&usb_phy3_always_on_clk32k>,
> +					 <&sys_clkin1>,
> +					 <&usb_otg_ss1_refclk960m>,
> +					 <&dpll_core_h13x2_ck>;
> +				clock-names =	"wkupclk",
> +						"sysclk",
> +						"refclk",
> +						"optclk";

Do we use this 'optclk' in driver?

-Kishon

Re: [PATCH 7/8] ARM: dts: dra7: Add USB related nodes

[Roger Quadros]

On 03/14/2014 12:38 PM, Kishon Vijay Abraham I wrote:
> Hi Roger,
> 
> On Friday 07 March 2014 06:39 PM, Roger Quadros wrote:
>> Add nodes for the Super Speed USB controllers, omap-control-usb,
>> USB2 PHY and USB3 PHY devices.
>>
>> Remove ocp2scp1 address space from hwmod data as it is
>> now provided via device tree.
>>
>> Signed-off-by: Roger Quadros <rogerq-l0cyMroinI0@public.gmane.org>
>> ---
>>   arch/arm/boot/dts/dra7.dtsi               | 110 ++++++++++++++++++++++++++++++
>>   arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  10 ---
>>   2 files changed, 110 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 597979b..1e73900 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -811,6 +811,116 @@
>>               clocks = <&sata_ref_clk>;
>>               ti,hwmods = "sata";
>>           };
>> +
>> +        omap_control_usb2phy1: control-phy@4a002300 {
>> +            compatible = "ti,control-phy-usb2";
>> +            reg = <0x4a002300 0x4>;
>> +            reg-names = "power";
>> +        };
>> +
>> +        omap_control_usb3phy1: control-phy@4a002370 {
>> +            compatible = "ti,control-phy-pipe3";
>> +            reg = <0x4a002370 0x4>;
>> +            reg-names = "power";
>> +        };
>> +
>> +        omap_control_usb2phy2: control-phy@0x4a002e74 {
>> +            compatible = "ti,control-phy-usb2-dra7";
>> +            reg = <0x4a002e74 0x4>;
>> +            reg-names = "power";
>> +        };
>> +
>> +        /* OCP2SCP1 */
>> +        ocp2scp@4a080000 {
>> +            compatible = "ti,omap-ocp2scp";
>> +            #address-cells = <1>;
>> +            #size-cells = <1>;
>> +            ranges;
>> +            reg = <0x4a080000 0x20>;
>> +            ti,hwmods = "ocp2scp1";
>> +
>> +            usb2_phy1: phy@4a084000 {
>> +                compatible = "ti,omap-usb2";
>> +                reg = <0x4a084000 0x400>;
>> +                ctrl-module = <&omap_control_usb2phy1>;
>> +                clocks = <&usb_phy1_always_on_clk32k>,
>> +                     <&usb_otg_ss1_refclk960m>;
>> +                clock-names =    "wkupclk",
>> +                        "refclk";
>> +                #phy-cells = <0>;
>> +            };
>> +
>> +            usb2_phy2: phy@4a085000 {
>> +                compatible = "ti,omap-usb2";
>> +                reg = <0x4a085000 0x400>;
>> +                ctrl-module = <&omap_control_usb2phy2>;
>> +                clocks = <&usb_phy2_always_on_clk32k>,
>> +                     <&usb_otg_ss2_refclk960m>;
>> +                clock-names =    "wkupclk",
>> +                        "refclk";
>> +                #phy-cells = <0>;
>> +            };
>> +
>> +            usb3_phy1: phy@4a084400 {
>> +                compatible = "ti,omap-usb3";
>> +                reg = <0x4a084400 0x80>,
>> +                      <0x4a084800 0x64>,
>> +                      <0x4a084c00 0x40>;
>> +                reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>> +                ctrl-module = <&omap_control_usb3phy1>;
>> +                clocks = <&usb_phy3_always_on_clk32k>,
>> +                     <&sys_clkin1>,
>> +                     <&usb_otg_ss1_refclk960m>,
>> +                     <&dpll_core_h13x2_ck>;
>> +                clock-names =    "wkupclk",
>> +                        "sysclk",
>> +                        "refclk",
>> +                        "optclk";
> 
> Do we use this 'optclk' in driver?

No we don't. Still the device seems to work without it.
This is supposed to be USB_LFPS_TX_GFCLK or USB3PHY_REF_CLK.

Any idea why it works without that on OMAP5 as well?

cheers,
-roger

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Re: [PATCH 7/8] ARM: dts: dra7: Add USB related nodes

[Kishon Vijay Abraham I]

On Friday 14 March 2014 05:41 PM, Roger Quadros wrote:
> On 03/14/2014 12:38 PM, Kishon Vijay Abraham I wrote:
>> Hi Roger,
>>
>> On Friday 07 March 2014 06:39 PM, Roger Quadros wrote:
>>> Add nodes for the Super Speed USB controllers, omap-control-usb,
>>> USB2 PHY and USB3 PHY devices.
>>>
>>> Remove ocp2scp1 address space from hwmod data as it is
>>> now provided via device tree.
>>>
>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>>> ---
>>>    arch/arm/boot/dts/dra7.dtsi               | 110 ++++++++++++++++++++++++++++++
>>>    arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  10 ---
>>>    2 files changed, 110 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>>> index 597979b..1e73900 100644
>>> --- a/arch/arm/boot/dts/dra7.dtsi
>>> +++ b/arch/arm/boot/dts/dra7.dtsi
>>> @@ -811,6 +811,116 @@
>>>                clocks = <&sata_ref_clk>;
>>>                ti,hwmods = "sata";
>>>            };
>>> +
>>> +        omap_control_usb2phy1: control-phy@4a002300 {
>>> +            compatible = "ti,control-phy-usb2";
>>> +            reg = <0x4a002300 0x4>;
>>> +            reg-names = "power";
>>> +        };
>>> +
>>> +        omap_control_usb3phy1: control-phy@4a002370 {
>>> +            compatible = "ti,control-phy-pipe3";
>>> +            reg = <0x4a002370 0x4>;
>>> +            reg-names = "power";
>>> +        };
>>> +
>>> +        omap_control_usb2phy2: control-phy@0x4a002e74 {
>>> +            compatible = "ti,control-phy-usb2-dra7";
>>> +            reg = <0x4a002e74 0x4>;
>>> +            reg-names = "power";
>>> +        };
>>> +
>>> +        /* OCP2SCP1 */
>>> +        ocp2scp@4a080000 {
>>> +            compatible = "ti,omap-ocp2scp";
>>> +            #address-cells = <1>;
>>> +            #size-cells = <1>;
>>> +            ranges;
>>> +            reg = <0x4a080000 0x20>;
>>> +            ti,hwmods = "ocp2scp1";
>>> +
>>> +            usb2_phy1: phy@4a084000 {
>>> +                compatible = "ti,omap-usb2";
>>> +                reg = <0x4a084000 0x400>;
>>> +                ctrl-module = <&omap_control_usb2phy1>;
>>> +                clocks = <&usb_phy1_always_on_clk32k>,
>>> +                     <&usb_otg_ss1_refclk960m>;
>>> +                clock-names =    "wkupclk",
>>> +                        "refclk";
>>> +                #phy-cells = <0>;
>>> +            };
>>> +
>>> +            usb2_phy2: phy@4a085000 {
>>> +                compatible = "ti,omap-usb2";
>>> +                reg = <0x4a085000 0x400>;
>>> +                ctrl-module = <&omap_control_usb2phy2>;
>>> +                clocks = <&usb_phy2_always_on_clk32k>,
>>> +                     <&usb_otg_ss2_refclk960m>;
>>> +                clock-names =    "wkupclk",
>>> +                        "refclk";
>>> +                #phy-cells = <0>;
>>> +            };
>>> +
>>> +            usb3_phy1: phy@4a084400 {
>>> +                compatible = "ti,omap-usb3";
>>> +                reg = <0x4a084400 0x80>,
>>> +                      <0x4a084800 0x64>,
>>> +                      <0x4a084c00 0x40>;
>>> +                reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>>> +                ctrl-module = <&omap_control_usb3phy1>;
>>> +                clocks = <&usb_phy3_always_on_clk32k>,
>>> +                     <&sys_clkin1>,
>>> +                     <&usb_otg_ss1_refclk960m>,
>>> +                     <&dpll_core_h13x2_ck>;
>>> +                clock-names =    "wkupclk",
>>> +                        "sysclk",
>>> +                        "refclk",
>>> +                        "optclk";
>>
>> Do we use this 'optclk' in driver?
>
> No we don't. Still the device seems to work without it.
> This is supposed to be USB_LFPS_TX_GFCLK or USB3PHY_REF_CLK.

I think it should be enabled. Did you check the status of this clock in 
CM_L3INIT_CLKSTCTRL? Moreover USB_LFPS_TX_GFCLK is an interface clock, 
so IIUC setting the module mode will enable it.

Btw how did you tell dpll_core_h13x2_ck enables USB_LFPS_TX_GFCLK?

Cheers
Kishon

Re: [PATCH 7/8] ARM: dts: dra7: Add USB related nodes

[Roger Quadros]

On 03/14/2014 04:54 PM, Kishon Vijay Abraham I wrote:
> 
> 
> On Friday 14 March 2014 05:41 PM, Roger Quadros wrote:
>> On 03/14/2014 12:38 PM, Kishon Vijay Abraham I wrote:
>>> Hi Roger,
>>>
>>> On Friday 07 March 2014 06:39 PM, Roger Quadros wrote:
>>>> Add nodes for the Super Speed USB controllers, omap-control-usb,
>>>> USB2 PHY and USB3 PHY devices.
>>>>
>>>> Remove ocp2scp1 address space from hwmod data as it is
>>>> now provided via device tree.
>>>>
>>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>>>> ---
>>>>    arch/arm/boot/dts/dra7.dtsi               | 110 ++++++++++++++++++++++++++++++
>>>>    arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  10 ---
>>>>    2 files changed, 110 insertions(+), 10 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>>>> index 597979b..1e73900 100644
>>>> --- a/arch/arm/boot/dts/dra7.dtsi
>>>> +++ b/arch/arm/boot/dts/dra7.dtsi
>>>> @@ -811,6 +811,116 @@
>>>>                clocks = <&sata_ref_clk>;
>>>>                ti,hwmods = "sata";
>>>>            };
>>>> +
>>>> +        omap_control_usb2phy1: control-phy@4a002300 {
>>>> +            compatible = "ti,control-phy-usb2";
>>>> +            reg = <0x4a002300 0x4>;
>>>> +            reg-names = "power";
>>>> +        };
>>>> +
>>>> +        omap_control_usb3phy1: control-phy@4a002370 {
>>>> +            compatible = "ti,control-phy-pipe3";
>>>> +            reg = <0x4a002370 0x4>;
>>>> +            reg-names = "power";
>>>> +        };
>>>> +
>>>> +        omap_control_usb2phy2: control-phy@0x4a002e74 {
>>>> +            compatible = "ti,control-phy-usb2-dra7";
>>>> +            reg = <0x4a002e74 0x4>;
>>>> +            reg-names = "power";
>>>> +        };
>>>> +
>>>> +        /* OCP2SCP1 */
>>>> +        ocp2scp@4a080000 {
>>>> +            compatible = "ti,omap-ocp2scp";
>>>> +            #address-cells = <1>;
>>>> +            #size-cells = <1>;
>>>> +            ranges;
>>>> +            reg = <0x4a080000 0x20>;
>>>> +            ti,hwmods = "ocp2scp1";
>>>> +
>>>> +            usb2_phy1: phy@4a084000 {
>>>> +                compatible = "ti,omap-usb2";
>>>> +                reg = <0x4a084000 0x400>;
>>>> +                ctrl-module = <&omap_control_usb2phy1>;
>>>> +                clocks = <&usb_phy1_always_on_clk32k>,
>>>> +                     <&usb_otg_ss1_refclk960m>;
>>>> +                clock-names =    "wkupclk",
>>>> +                        "refclk";
>>>> +                #phy-cells = <0>;
>>>> +            };
>>>> +
>>>> +            usb2_phy2: phy@4a085000 {
>>>> +                compatible = "ti,omap-usb2";
>>>> +                reg = <0x4a085000 0x400>;
>>>> +                ctrl-module = <&omap_control_usb2phy2>;
>>>> +                clocks = <&usb_phy2_always_on_clk32k>,
>>>> +                     <&usb_otg_ss2_refclk960m>;
>>>> +                clock-names =    "wkupclk",
>>>> +                        "refclk";
>>>> +                #phy-cells = <0>;
>>>> +            };
>>>> +
>>>> +            usb3_phy1: phy@4a084400 {
>>>> +                compatible = "ti,omap-usb3";
>>>> +                reg = <0x4a084400 0x80>,
>>>> +                      <0x4a084800 0x64>,
>>>> +                      <0x4a084c00 0x40>;
>>>> +                reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>>>> +                ctrl-module = <&omap_control_usb3phy1>;
>>>> +                clocks = <&usb_phy3_always_on_clk32k>,
>>>> +                     <&sys_clkin1>,
>>>> +                     <&usb_otg_ss1_refclk960m>,
>>>> +                     <&dpll_core_h13x2_ck>;
>>>> +                clock-names =    "wkupclk",
>>>> +                        "sysclk",
>>>> +                        "refclk",
>>>> +                        "optclk";
>>>
>>> Do we use this 'optclk' in driver?
>>
>> No we don't. Still the device seems to work without it.
>> This is supposed to be USB_LFPS_TX_GFCLK or USB3PHY_REF_CLK.
> 
> I think it should be enabled. Did you check the status of this clock in CM_L3INIT_CLKSTCTRL? Moreover USB_LFPS_TX_GFCLK is an interface clock, so IIUC setting the module mode will enable it.
> 
> Btw how did you tell dpll_core_h13x2_ck enables USB_LFPS_TX_GFCLK?
> 

>From the clock tree tool. It looks like the clock is gated automatically with the module mode
as you suggested. I'll get rid of this clock reference then.

cheers,
-roger

Re: [PATCH 7/8] ARM: dts: dra7: Add USB related nodes

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 4883 bytes --]

On Fri, Mar 14, 2014 at 05:34:29PM +0200, Roger Quadros wrote:
> On 03/14/2014 04:54 PM, Kishon Vijay Abraham I wrote:
> > 
> > 
> > On Friday 14 March 2014 05:41 PM, Roger Quadros wrote:
> >> On 03/14/2014 12:38 PM, Kishon Vijay Abraham I wrote:
> >>> Hi Roger,
> >>>
> >>> On Friday 07 March 2014 06:39 PM, Roger Quadros wrote:
> >>>> Add nodes for the Super Speed USB controllers, omap-control-usb,
> >>>> USB2 PHY and USB3 PHY devices.
> >>>>
> >>>> Remove ocp2scp1 address space from hwmod data as it is
> >>>> now provided via device tree.
> >>>>
> >>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
> >>>> ---
> >>>>    arch/arm/boot/dts/dra7.dtsi               | 110 ++++++++++++++++++++++++++++++
> >>>>    arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  10 ---
> >>>>    2 files changed, 110 insertions(+), 10 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> >>>> index 597979b..1e73900 100644
> >>>> --- a/arch/arm/boot/dts/dra7.dtsi
> >>>> +++ b/arch/arm/boot/dts/dra7.dtsi
> >>>> @@ -811,6 +811,116 @@
> >>>>                clocks = <&sata_ref_clk>;
> >>>>                ti,hwmods = "sata";
> >>>>            };
> >>>> +
> >>>> +        omap_control_usb2phy1: control-phy@4a002300 {
> >>>> +            compatible = "ti,control-phy-usb2";
> >>>> +            reg = <0x4a002300 0x4>;
> >>>> +            reg-names = "power";
> >>>> +        };
> >>>> +
> >>>> +        omap_control_usb3phy1: control-phy@4a002370 {
> >>>> +            compatible = "ti,control-phy-pipe3";
> >>>> +            reg = <0x4a002370 0x4>;
> >>>> +            reg-names = "power";
> >>>> +        };
> >>>> +
> >>>> +        omap_control_usb2phy2: control-phy@0x4a002e74 {
> >>>> +            compatible = "ti,control-phy-usb2-dra7";
> >>>> +            reg = <0x4a002e74 0x4>;
> >>>> +            reg-names = "power";
> >>>> +        };
> >>>> +
> >>>> +        /* OCP2SCP1 */
> >>>> +        ocp2scp@4a080000 {
> >>>> +            compatible = "ti,omap-ocp2scp";
> >>>> +            #address-cells = <1>;
> >>>> +            #size-cells = <1>;
> >>>> +            ranges;
> >>>> +            reg = <0x4a080000 0x20>;
> >>>> +            ti,hwmods = "ocp2scp1";
> >>>> +
> >>>> +            usb2_phy1: phy@4a084000 {
> >>>> +                compatible = "ti,omap-usb2";
> >>>> +                reg = <0x4a084000 0x400>;
> >>>> +                ctrl-module = <&omap_control_usb2phy1>;
> >>>> +                clocks = <&usb_phy1_always_on_clk32k>,
> >>>> +                     <&usb_otg_ss1_refclk960m>;
> >>>> +                clock-names =    "wkupclk",
> >>>> +                        "refclk";
> >>>> +                #phy-cells = <0>;
> >>>> +            };
> >>>> +
> >>>> +            usb2_phy2: phy@4a085000 {
> >>>> +                compatible = "ti,omap-usb2";
> >>>> +                reg = <0x4a085000 0x400>;
> >>>> +                ctrl-module = <&omap_control_usb2phy2>;
> >>>> +                clocks = <&usb_phy2_always_on_clk32k>,
> >>>> +                     <&usb_otg_ss2_refclk960m>;
> >>>> +                clock-names =    "wkupclk",
> >>>> +                        "refclk";
> >>>> +                #phy-cells = <0>;
> >>>> +            };
> >>>> +
> >>>> +            usb3_phy1: phy@4a084400 {
> >>>> +                compatible = "ti,omap-usb3";
> >>>> +                reg = <0x4a084400 0x80>,
> >>>> +                      <0x4a084800 0x64>,
> >>>> +                      <0x4a084c00 0x40>;
> >>>> +                reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> >>>> +                ctrl-module = <&omap_control_usb3phy1>;
> >>>> +                clocks = <&usb_phy3_always_on_clk32k>,
> >>>> +                     <&sys_clkin1>,
> >>>> +                     <&usb_otg_ss1_refclk960m>,
> >>>> +                     <&dpll_core_h13x2_ck>;
> >>>> +                clock-names =    "wkupclk",
> >>>> +                        "sysclk",
> >>>> +                        "refclk",
> >>>> +                        "optclk";
> >>>
> >>> Do we use this 'optclk' in driver?
> >>
> >> No we don't. Still the device seems to work without it.
> >> This is supposed to be USB_LFPS_TX_GFCLK or USB3PHY_REF_CLK.
> > 
> > I think it should be enabled. Did you check the status of this clock
> > in CM_L3INIT_CLKSTCTRL? Moreover USB_LFPS_TX_GFCLK is an interface
> > clock, so IIUC setting the module mode will enable it.
> > 
> > Btw how did you tell dpll_core_h13x2_ck enables USB_LFPS_TX_GFCLK?
> > 
> 
> From the clock tree tool. It looks like the clock is gated
> automatically with the module mode as you suggested. I'll get rid of
> this clock reference then.

note that we can change the input clock of some parts of dwc3, maybe
that's why it works without, we're probably using another clock as
input.

-- 
balbi

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Re: [PATCH 1/8] CLK: ti: dra7: Initialize USB_DPLL

[Tero Kristo]

On 03/07/2014 03:09 PM, Roger Quadros wrote:
> USB_DPLL must be initialized and locked at boot so that
> USB modules can work.
>
> Also program USB_DLL_M2 output to half rate.
>
> CC: Mike Turquette <mturquette@linaro.org>
> CC: Tero Kristo <t-kristo@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>   drivers/clk/ti/clk-7xx.c | 11 +++++++++++
>   1 file changed, 11 insertions(+)

Hi,

Resurrecting this patch, as it seems the clock-parenting stuff via DT 
hasn't really moved that much forward.

Thus, this patch has been now queued for 3.17, thanks.

-Tero

>
> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
> index 9977653..f89f3c2 100644
> --- a/drivers/clk/ti/clk-7xx.c
> +++ b/drivers/clk/ti/clk-7xx.c
> @@ -18,6 +18,7 @@
>
>   #define DRA7_DPLL_ABE_DEFFREQ				361267200
>   #define DRA7_DPLL_GMAC_DEFFREQ				1000000000
> +#define DRA7_DPLL_USB_DEFFREQ				960000000
>
>
>   static struct ti_dt_clk dra7xx_clks[] = {
> @@ -328,5 +329,15 @@ int __init dra7xx_dt_clk_init(void)
>   	if (rc)
>   		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
>
> +	dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
> +	rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
> +	if (rc)
> +		pr_err("%s: failed to configure USB DPLL!\n", __func__);
> +
> +	dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
> +	rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
> +	if (rc)
> +		pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
> +
>   	return rc;
>   }
>