From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomasz Figa Subject: Re: [PATCH v4 3/5] clk/samsung: add support for pll2650xx Date: Mon, 10 Mar 2014 01:29:36 +0100 Message-ID: <531D0770.1050201@gmail.com> References: <1393931558-23502-1-git-send-email-rahul.sharma@samsung.com> <1393931558-23502-4-git-send-email-rahul.sharma@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1393931558-23502-4-git-send-email-rahul.sharma@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org To: Rahul Sharma , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, joshi@samsung.com, r.sh.open@gmail.com List-Id: devicetree@vger.kernel.org On 04.03.2014 12:12, Rahul Sharma wrote: > Add support for pll2650xx in samsung pll file. This pll variant > is close to pll36xx but uses CON2 registers instead of CON1. > > Aud_pll in Exynos5260 is pll2650xx and uses this code. > > Signed-off-by: Rahul Sharma > --- > drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++ > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 102 insertions(+) Acked-by: Tomasz Figa Best regards, Tomasz