[PATCH v2 0/7] exynos5420: clock file cleanup

[PATCH v2 0/7] exynos5420: clock file cleanup

[Shaik Ameer Basha]

Many changes/fixes have been identified for clock file for exynos5420.
These include correct parents, bit fields, new clocks etc. Existing
files needs some correction in terms of names of the clock and
indentation. These issues are addressed in this patch series. It also
replaces the usage of enums with macro as clock ids.

This patch series is rebased on,
git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git:samsung-next

This patch is also dependent on the following patches.
ARM: dts: Add I2S nodes to exynos5420
ARM: dts: add dt node for sss module for exynos5250/5420
ARM: dts: update watchdog device nodes for exynos5250 and exynos5420
ARM: dts: use macros in clock bindings for exynos5420

Changes since v1:
-----------------
1] Addressed review comments from Tomasz Figa.
    http://www.spinics.net/lists/devicetree/msg16759.html
    http://www.spinics.net/lists/devicetree/msg16760.html

Rahul Sharma (7):
  clk: exynos5420: Add more clock register offsets
  clk: exynos5420: Add more clock IDs
  clk: exynos5420: Rename clock IDs
  clk: exynos5420: Rename clock names
  clk: exynos5420: Add missing clocks
  clk: exynos5420: Add more registers to restore list
  ARM: dts: update macros in clock bindings for exynos5420

 arch/arm/boot/dts/exynos5420.dtsi      |   90 +--
 drivers/clk/samsung/clk-exynos5420.c   | 1029 +++++++++++++++++++++-----------
 include/dt-bindings/clock/exynos5420.h |  214 ++++---
 3 files changed, 871 insertions(+), 462 deletions(-)

-- 
1.7.9.5

[PATCH v2 1/7] clk: exynos5420: Add more clock register offsets

[Shaik Ameer Basha]

From: Rahul Sharma <rahul.sharma@samsung.com>

This patch adds the missing clock register offsets for Exynos5420.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c |   29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 13f624d..3d0fb77 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -27,6 +27,9 @@
 #define DIV_CPU1		0x504
 #define GATE_BUS_CPU		0x700
 #define GATE_SCLK_CPU		0x800
+#define CLKOUT_CMU_CPU		0xa00
+#define DIV_G2D			0x8500
+#define GATE_BUS_G2D		0x8700
 #define GATE_IP_G2D		0x8800
 #define CPLL_LOCK		0x10020
 #define DPLL_LOCK		0x10030
@@ -39,7 +42,11 @@
 #define CPLL_CON0		0x10120
 #define DPLL_CON0		0x10128
 #define EPLL_CON0		0x10130
+#define EPLL_CON1		0x10134
+#define EPLL_CON2		0x10138
 #define RPLL_CON0		0x10140
+#define RPLL_CON1		0x10144
+#define RPLL_CON2		0x10148
 #define IPLL_CON0		0x10150
 #define SPLL_CON0		0x10160
 #define VPLL_CON0		0x10170
@@ -57,10 +64,13 @@
 #define SRC_FSYS		0x10244
 #define SRC_PERIC0		0x10250
 #define SRC_PERIC1		0x10254
+#define SRC_ISP			0x10270
 #define SRC_TOP10		0x10280
 #define SRC_TOP11		0x10284
 #define SRC_TOP12		0x10288
-#define	SRC_MASK_DISP10		0x1032c
+#define SRC_MASK_TOP2		0x10308
+#define SRC_MASK_DISP10		0x1032c
+#define SRC_MASK_MAU		0x10334
 #define SRC_MASK_FSYS		0x10340
 #define SRC_MASK_PERIC0		0x10350
 #define SRC_MASK_PERIC1		0x10354
@@ -77,24 +87,41 @@
 #define DIV_PERIC2		0x10560
 #define DIV_PERIC3		0x10564
 #define DIV_PERIC4		0x10568
+#define SCLK_DIV_ISP0		0x10580
+#define SCLK_DIV_ISP1		0x10584
+#define DIV2_RATIO0		0x10590
+#define DIV4_RATIO		0x105a0
 #define GATE_BUS_TOP		0x10700
+#define GATE_BUS_GSCL0		0x10710
+#define GATE_BUS_GSCL1		0x10720
+#define GATE_BUS_DISP1		0x10728
+#define GATE_BUS_MFC		0x10734
+#define GATE_BUS_GEN		0x1073c
 #define GATE_BUS_FSYS0		0x10740
+#define GATE_BUS_FSYS2		0x10748
+#define GATE_BUS_MSCL		0x1074C
 #define GATE_BUS_PERIC		0x10750
 #define GATE_BUS_PERIC1		0x10754
 #define GATE_BUS_PERIS0		0x10760
 #define GATE_BUS_PERIS1		0x10764
+#define GATE_BUS_NOC		0x10770
+#define GATE_TOP_SCLK_ISP	0x10870
 #define GATE_IP_GSCL0		0x10910
 #define GATE_IP_GSCL1		0x10920
 #define GATE_IP_MFC		0x1092c
 #define GATE_IP_DISP1		0x10928
 #define GATE_IP_G3D		0x10930
 #define GATE_IP_GEN		0x10934
+#define GATE_IP_FSYS		0x10944
+#define GATE_IP_PERIC		0x10950
+#define GATE_IP_PERIS		0x10960
 #define GATE_IP_MSCL		0x10970
 #define GATE_TOP_SCLK_GSCL	0x10820
 #define GATE_TOP_SCLK_DISP1	0x10828
 #define GATE_TOP_SCLK_MAU	0x1083c
 #define GATE_TOP_SCLK_FSYS	0x10840
 #define GATE_TOP_SCLK_PERIC	0x10850
+#define TOP_SPARE2		0x10b08
 #define BPLL_LOCK		0x20010
 #define BPLL_CON0		0x20110
 #define SRC_CDREX		0x20200
-- 
1.7.9.5

Re: [PATCH v2 1/7] clk: exynos5420: Add more clock register offsets

[Tomasz Figa]

Hi Shaik,

On 27.03.2014 12:07, Shaik Ameer Basha wrote:
> From: Rahul Sharma <rahul.sharma@samsung.com>
>
> This patch adds the missing clock register offsets for Exynos5420.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
> ---
>   drivers/clk/samsung/clk-exynos5420.c |   29 ++++++++++++++++++++++++++++-
>   1 file changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 13f624d..3d0fb77 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -27,6 +27,9 @@
>   #define DIV_CPU1		0x504
>   #define GATE_BUS_CPU		0x700
>   #define GATE_SCLK_CPU		0x800
> +#define CLKOUT_CMU_CPU		0xa00
> +#define DIV_G2D			0x8500
> +#define GATE_BUS_G2D		0x8700
>   #define GATE_IP_G2D		0x8800
>   #define CPLL_LOCK		0x10020
>   #define DPLL_LOCK		0x10030
> @@ -39,7 +42,11 @@
>   #define CPLL_CON0		0x10120
>   #define DPLL_CON0		0x10128
>   #define EPLL_CON0		0x10130
> +#define EPLL_CON1		0x10134
> +#define EPLL_CON2		0x10138
>   #define RPLL_CON0		0x10140
> +#define RPLL_CON1		0x10144
> +#define RPLL_CON2		0x10148
>   #define IPLL_CON0		0x10150
>   #define SPLL_CON0		0x10160
>   #define VPLL_CON0		0x10170
> @@ -57,10 +64,13 @@
>   #define SRC_FSYS		0x10244
>   #define SRC_PERIC0		0x10250
>   #define SRC_PERIC1		0x10254
> +#define SRC_ISP			0x10270
>   #define SRC_TOP10		0x10280
>   #define SRC_TOP11		0x10284
>   #define SRC_TOP12		0x10288
> -#define	SRC_MASK_DISP10		0x1032c
> +#define SRC_MASK_TOP2		0x10308
> +#define SRC_MASK_DISP10		0x1032c
> +#define SRC_MASK_MAU		0x10334
>   #define SRC_MASK_FSYS		0x10340
>   #define SRC_MASK_PERIC0		0x10350
>   #define SRC_MASK_PERIC1		0x10354
> @@ -77,24 +87,41 @@
>   #define DIV_PERIC2		0x10560
>   #define DIV_PERIC3		0x10564
>   #define DIV_PERIC4		0x10568
> +#define SCLK_DIV_ISP0		0x10580
> +#define SCLK_DIV_ISP1		0x10584
> +#define DIV2_RATIO0		0x10590
> +#define DIV4_RATIO		0x105a0
>   #define GATE_BUS_TOP		0x10700
> +#define GATE_BUS_GSCL0		0x10710
> +#define GATE_BUS_GSCL1		0x10720
> +#define GATE_BUS_DISP1		0x10728
> +#define GATE_BUS_MFC		0x10734
> +#define GATE_BUS_GEN		0x1073c
>   #define GATE_BUS_FSYS0		0x10740
> +#define GATE_BUS_FSYS2		0x10748
> +#define GATE_BUS_MSCL		0x1074C
>   #define GATE_BUS_PERIC		0x10750
>   #define GATE_BUS_PERIC1		0x10754
>   #define GATE_BUS_PERIS0		0x10760
>   #define GATE_BUS_PERIS1		0x10764
> +#define GATE_BUS_NOC		0x10770
> +#define GATE_TOP_SCLK_ISP	0x10870
>   #define GATE_IP_GSCL0		0x10910
>   #define GATE_IP_GSCL1		0x10920
>   #define GATE_IP_MFC		0x1092c
>   #define GATE_IP_DISP1		0x10928
>   #define GATE_IP_G3D		0x10930
>   #define GATE_IP_GEN		0x10934
> +#define GATE_IP_FSYS		0x10944
> +#define GATE_IP_PERIC		0x10950
> +#define GATE_IP_PERIS		0x10960
>   #define GATE_IP_MSCL		0x10970
>   #define GATE_TOP_SCLK_GSCL	0x10820
>   #define GATE_TOP_SCLK_DISP1	0x10828
>   #define GATE_TOP_SCLK_MAU	0x1083c
>   #define GATE_TOP_SCLK_FSYS	0x10840
>   #define GATE_TOP_SCLK_PERIC	0x10850
> +#define TOP_SPARE2		0x10b08
>   #define BPLL_LOCK		0x20010
>   #define BPLL_CON0		0x20110
>   #define SRC_CDREX		0x20200
>

 From this patch, it's hard to tell what is the use for those registers. 
I think they should be added along with definitions that need them.

Best regards,
Tomasz

Re: [PATCH v2 1/7] clk: exynos5420: Add more clock register offsets

[Shaik Ameer Basha]

Hi Tomasz,

Thanks for the review comments.

On Tue, Apr 15, 2014 at 10:15 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Shaik,
>
>
> On 27.03.2014 12:07, Shaik Ameer Basha wrote:
>>
>> From: Rahul Sharma <rahul.sharma@samsung.com>
>>
>> This patch adds the missing clock register offsets for Exynos5420.
>>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos5420.c |   29
>> ++++++++++++++++++++++++++++-
>>   1 file changed, 28 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c
>> b/drivers/clk/samsung/clk-exynos5420.c
>> index 13f624d..3d0fb77 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -27,6 +27,9 @@
>>   #define DIV_CPU1              0x504
>>   #define GATE_BUS_CPU          0x700
>>   #define GATE_SCLK_CPU         0x800
>> +#define CLKOUT_CMU_CPU         0xa00
>> +#define DIV_G2D                        0x8500
>> +#define GATE_BUS_G2D           0x8700
>>   #define GATE_IP_G2D           0x8800
>>   #define CPLL_LOCK             0x10020
>>   #define DPLL_LOCK             0x10030
>> @@ -39,7 +42,11 @@
>>   #define CPLL_CON0             0x10120
>>   #define DPLL_CON0             0x10128
>>   #define EPLL_CON0             0x10130
>> +#define EPLL_CON1              0x10134
>> +#define EPLL_CON2              0x10138
>>   #define RPLL_CON0             0x10140
>> +#define RPLL_CON1              0x10144
>> +#define RPLL_CON2              0x10148
>>   #define IPLL_CON0             0x10150
>>   #define SPLL_CON0             0x10160
>>   #define VPLL_CON0             0x10170
>> @@ -57,10 +64,13 @@
>>   #define SRC_FSYS              0x10244
>>   #define SRC_PERIC0            0x10250
>>   #define SRC_PERIC1            0x10254
>> +#define SRC_ISP                        0x10270
>>   #define SRC_TOP10             0x10280
>>   #define SRC_TOP11             0x10284
>>   #define SRC_TOP12             0x10288
>> -#define        SRC_MASK_DISP10         0x1032c
>> +#define SRC_MASK_TOP2          0x10308
>> +#define SRC_MASK_DISP10                0x1032c
>> +#define SRC_MASK_MAU           0x10334
>>   #define SRC_MASK_FSYS         0x10340
>>   #define SRC_MASK_PERIC0               0x10350
>>   #define SRC_MASK_PERIC1               0x10354
>> @@ -77,24 +87,41 @@
>>   #define DIV_PERIC2            0x10560
>>   #define DIV_PERIC3            0x10564
>>   #define DIV_PERIC4            0x10568
>> +#define SCLK_DIV_ISP0          0x10580
>> +#define SCLK_DIV_ISP1          0x10584
>> +#define DIV2_RATIO0            0x10590
>> +#define DIV4_RATIO             0x105a0
>>   #define GATE_BUS_TOP          0x10700
>> +#define GATE_BUS_GSCL0         0x10710
>> +#define GATE_BUS_GSCL1         0x10720
>> +#define GATE_BUS_DISP1         0x10728
>> +#define GATE_BUS_MFC           0x10734
>> +#define GATE_BUS_GEN           0x1073c
>>   #define GATE_BUS_FSYS0                0x10740
>> +#define GATE_BUS_FSYS2         0x10748
>> +#define GATE_BUS_MSCL          0x1074C
>>   #define GATE_BUS_PERIC                0x10750
>>   #define GATE_BUS_PERIC1               0x10754
>>   #define GATE_BUS_PERIS0               0x10760
>>   #define GATE_BUS_PERIS1               0x10764
>> +#define GATE_BUS_NOC           0x10770
>> +#define GATE_TOP_SCLK_ISP      0x10870
>>   #define GATE_IP_GSCL0         0x10910
>>   #define GATE_IP_GSCL1         0x10920
>>   #define GATE_IP_MFC           0x1092c
>>   #define GATE_IP_DISP1         0x10928
>>   #define GATE_IP_G3D           0x10930
>>   #define GATE_IP_GEN           0x10934
>> +#define GATE_IP_FSYS           0x10944
>> +#define GATE_IP_PERIC          0x10950
>> +#define GATE_IP_PERIS          0x10960
>>   #define GATE_IP_MSCL          0x10970
>>   #define GATE_TOP_SCLK_GSCL    0x10820
>>   #define GATE_TOP_SCLK_DISP1   0x10828
>>   #define GATE_TOP_SCLK_MAU     0x1083c
>>   #define GATE_TOP_SCLK_FSYS    0x10840
>>   #define GATE_TOP_SCLK_PERIC   0x10850
>> +#define TOP_SPARE2             0x10b08
>>   #define BPLL_LOCK             0x20010
>>   #define BPLL_CON0             0x20110
>>   #define SRC_CDREX             0x20200
>>
>
> From this patch, it's hard to tell what is the use for those registers. I
> think they should be added along with definitions that need them.
>

Ok. will add this macros along with the corresponding clock definitions.

Regards,
Shaik Ameer Basha


> Best regards,
> Tomasz

[PATCH v2 2/7] clk: exynos5420: Add more clock IDs

[Shaik Ameer Basha]

From: Rahul Sharma <rahul.sharma@samsung.com>

Add more clock IDs to be used in DT bindings for Exynos5420.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
---
 include/dt-bindings/clock/exynos5420.h |   62 ++++++++++++++++++++++++++++++--
 1 file changed, 60 insertions(+), 2 deletions(-)

diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 5eefd88..e921913 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -58,6 +58,16 @@
 #define CLK_SCLK_GSCL_WA	156
 #define CLK_SCLK_GSCL_WB	157
 #define CLK_SCLK_HDMIPHY	158
+#define CLK_SCLK_MPHY_REFCLK	159
+#define CLK_SCLK_SPI0_ISP	160
+#define CLK_SCLK_SPI1_ISP	161
+#define CLK_SCLK_UART_ISP	162
+#define CLK_SCLK_ISP_SENSOR0	163
+#define CLK_SCLK_ISP_SENSOR1	164
+#define CLK_SCLK_ISP_SENSOR2	165
+#define CLK_SCLK_PWM_ISP	166
+#define CLK_SCLK_HSIC_12M	167
+#define CLK_SCLK_MPHY_IXTAL24	168
 
 /* gate clocks */
 #define CLK_ACLK66_PERIC	256
@@ -123,6 +133,7 @@
 #define CLK_USBH20		365
 #define CLK_USBD300		366
 #define CLK_USBD301		367
+#define CLK_PCLK200_FSYS	370
 #define CLK_ACLK400_MSCL	380
 #define CLK_MSCL0		381
 #define CLK_MSCL1		382
@@ -141,6 +152,8 @@
 #define CLK_ACLK300_DISP1	420
 #define CLK_FIMD1		421
 #define CLK_SMMU_FIMD1		422
+#define CLK_SMMU_FIMD1M1	423
+#define CLK_ACLK400_DISP1	424
 #define CLK_ACLK166		430
 #define CLK_MIXER		431
 #define CLK_ACLK266		440
@@ -172,12 +185,57 @@
 #define CLK_SMMU_FIMCL1		493
 #define CLK_SMMU_FIMCL3		494
 #define CLK_FIMC_LITE3		495
-#define CLK_ACLK_G3D		500
-#define CLK_G3D			501
+#define CLK_G3D			500
 #define CLK_SMMU_MIXER		502
+#define CLK_PCLK_TZPC10		503
+#define CLK_PCLK_TZPC11		504
+#define CLK_PCLK_MC		505
+#define CLK_PCLK_TOP_RTC	506
+#define CLK_SMMU_JPEG2		507
+#define CLK_PCLK_ROTATOR	508
+#define CLK_SMMU_RTIC		509
+#define CLK_PCLK_G2D		510
+#define CLK_ACLK_SMMU_G2D	511
+#define CLK_SMMU_G2D		512
+#define CLK_ACLK_SMMU_MDMA0	513
+#define CLK_SMMU_MDMA0		514
+#define CLK_ACLK_SMMU_SSS	515
+#define CLK_SMMU_SSS		516
+#define CLK_SMMU_SLIM_SSS	517
+#define CLK_ACLK_SMMU_SLIM_SSS	518
+#define CLK_ACLK266_ISP		519
+#define CLK_ACLK400_ISP		520
+#define CLK_ACLK333_432_ISP0	521
+#define CLK_ACLK333_432_ISP	522
+#define CLK_ACLK_SMMU_MIXER	523
+#define CLK_PCLK_HDMIPHY	524
+#define CLK_PCLK_GSCL0		525
+#define CLK_PCLK_GSCL1		526
+#define CLK_PCLK_FIMC_3AA	527
+#define CLK_ACLK_FIMC_LITE0	528
+#define CLK_ACLK_FIMC_LITE1	529
+#define CLK_PCLK_FIMC_LITE0	530
+#define CLK_PCLK_FIMC_LITE1	531
+#define CLK_PCLK_FIMC_LITE3	532
+#define CLK_PCLK_MSCL0		533
+#define CLK_PCLK_MSCL1		534
+#define CLK_PCLK_MSCL2		535
+#define CLK_PCLK_MFC		536
 
 /* mux clocks */
 #define CLK_MOUT_HDMI		640
+#define CLK_MOUT_FIMD1			641
+#define CLK_MOUT_MAUDIO0		642
+#define CLK_MOUT_SPI0			643
+#define CLK_MOUT_SPI1			644
+#define CLK_MOUT_SPI2			645
+#define CLK_MOUT_SW_ACLK333		646
+#define CLK_MOUT_USER_ACLK333		647
+#define CLK_MOUT_SW_ACLK300_GSCL	648
+#define CLK_MOUT_USER_ACLK300_GSCL	649
+#define CLK_MOUT_SW_ACLK333_432_GSCL	650
+#define CLK_MOUT_USER_ACLK333_432_GSCL	651
+#define CLK_MOUT_G3D			652
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL		768
-- 
1.7.9.5

Re: [PATCH v2 2/7] clk: exynos5420: Add more clock IDs

[Tomasz Figa]

Hi Shaik,

On 27.03.2014 12:07, Shaik Ameer Basha wrote:
> From: Rahul Sharma <rahul.sharma@samsung.com>
>
> Add more clock IDs to be used in DT bindings for Exynos5420.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
> ---
>   include/dt-bindings/clock/exynos5420.h |   62 ++++++++++++++++++++++++++++++--
>   1 file changed, 60 insertions(+), 2 deletions(-)
>
> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
> index 5eefd88..e921913 100644
> --- a/include/dt-bindings/clock/exynos5420.h
> +++ b/include/dt-bindings/clock/exynos5420.h
> @@ -58,6 +58,16 @@
>   #define CLK_SCLK_GSCL_WA	156
>   #define CLK_SCLK_GSCL_WB	157
>   #define CLK_SCLK_HDMIPHY	158
> +#define CLK_SCLK_MPHY_REFCLK	159
> +#define CLK_SCLK_SPI0_ISP	160
> +#define CLK_SCLK_SPI1_ISP	161
> +#define CLK_SCLK_UART_ISP	162
> +#define CLK_SCLK_ISP_SENSOR0	163
> +#define CLK_SCLK_ISP_SENSOR1	164
> +#define CLK_SCLK_ISP_SENSOR2	165
> +#define CLK_SCLK_PWM_ISP	166
> +#define CLK_SCLK_HSIC_12M	167
> +#define CLK_SCLK_MPHY_IXTAL24	168
>
>   /* gate clocks */
>   #define CLK_ACLK66_PERIC	256
> @@ -123,6 +133,7 @@
>   #define CLK_USBH20		365
>   #define CLK_USBD300		366
>   #define CLK_USBD301		367
> +#define CLK_PCLK200_FSYS	370
>   #define CLK_ACLK400_MSCL	380
>   #define CLK_MSCL0		381
>   #define CLK_MSCL1		382
> @@ -141,6 +152,8 @@
>   #define CLK_ACLK300_DISP1	420
>   #define CLK_FIMD1		421
>   #define CLK_SMMU_FIMD1		422
> +#define CLK_SMMU_FIMD1M1	423
> +#define CLK_ACLK400_DISP1	424
>   #define CLK_ACLK166		430
>   #define CLK_MIXER		431
>   #define CLK_ACLK266		440
> @@ -172,12 +185,57 @@
>   #define CLK_SMMU_FIMCL1		493
>   #define CLK_SMMU_FIMCL3		494
>   #define CLK_FIMC_LITE3		495
> -#define CLK_ACLK_G3D		500
> -#define CLK_G3D			501
> +#define CLK_G3D			500

What is the reason for this ID change? Even if CLK_ACLK_G3D is removed, 
as it wasn't even referenced by the driver, original clock IDs should 
remain fixed.

>   #define CLK_SMMU_MIXER		502
> +#define CLK_PCLK_TZPC10		503
> +#define CLK_PCLK_TZPC11		504
> +#define CLK_PCLK_MC		505
> +#define CLK_PCLK_TOP_RTC	506
> +#define CLK_SMMU_JPEG2		507
> +#define CLK_PCLK_ROTATOR	508
> +#define CLK_SMMU_RTIC		509
> +#define CLK_PCLK_G2D		510
> +#define CLK_ACLK_SMMU_G2D	511
> +#define CLK_SMMU_G2D		512
> +#define CLK_ACLK_SMMU_MDMA0	513
> +#define CLK_SMMU_MDMA0		514
> +#define CLK_ACLK_SMMU_SSS	515
> +#define CLK_SMMU_SSS		516
> +#define CLK_SMMU_SLIM_SSS	517
> +#define CLK_ACLK_SMMU_SLIM_SSS	518
> +#define CLK_ACLK266_ISP		519
> +#define CLK_ACLK400_ISP		520
> +#define CLK_ACLK333_432_ISP0	521
> +#define CLK_ACLK333_432_ISP	522
> +#define CLK_ACLK_SMMU_MIXER	523
> +#define CLK_PCLK_HDMIPHY	524
> +#define CLK_PCLK_GSCL0		525
> +#define CLK_PCLK_GSCL1		526
> +#define CLK_PCLK_FIMC_3AA	527
> +#define CLK_ACLK_FIMC_LITE0	528
> +#define CLK_ACLK_FIMC_LITE1	529
> +#define CLK_PCLK_FIMC_LITE0	530
> +#define CLK_PCLK_FIMC_LITE1	531
> +#define CLK_PCLK_FIMC_LITE3	532
> +#define CLK_PCLK_MSCL0		533
> +#define CLK_PCLK_MSCL1		534
> +#define CLK_PCLK_MSCL2		535
> +#define CLK_PCLK_MFC		536
>
>   /* mux clocks */
>   #define CLK_MOUT_HDMI		640
> +#define CLK_MOUT_FIMD1			641
> +#define CLK_MOUT_MAUDIO0		642
> +#define CLK_MOUT_SPI0			643
> +#define CLK_MOUT_SPI1			644
> +#define CLK_MOUT_SPI2			645
> +#define CLK_MOUT_SW_ACLK333		646
> +#define CLK_MOUT_USER_ACLK333		647
> +#define CLK_MOUT_SW_ACLK300_GSCL	648
> +#define CLK_MOUT_USER_ACLK300_GSCL	649
> +#define CLK_MOUT_SW_ACLK333_432_GSCL	650
> +#define CLK_MOUT_USER_ACLK333_432_GSCL	651
> +#define CLK_MOUT_G3D			652
>
>   /* divider clocks */
>   #define CLK_DOUT_PIXEL		768
>

Also similar comment as for patch 1/7, it's hard to tell why this change 
is needed at all.

Best regards,
Tomasz

Re: [PATCH v2 2/7] clk: exynos5420: Add more clock IDs

[Shaik Ameer Basha]

Hi Tomasz,


On Tue, Apr 15, 2014 at 10:20 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Shaik,
>
>
> On 27.03.2014 12:07, Shaik Ameer Basha wrote:
>>
>> From: Rahul Sharma <rahul.sharma@samsung.com>
>>
>> Add more clock IDs to be used in DT bindings for Exynos5420.
>>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
>> ---
>>   include/dt-bindings/clock/exynos5420.h |   62
>> ++++++++++++++++++++++++++++++--
>>   1 file changed, 60 insertions(+), 2 deletions(-)
>>
>> diff --git a/include/dt-bindings/clock/exynos5420.h
>> b/include/dt-bindings/clock/exynos5420.h
>> index 5eefd88..e921913 100644
>> --- a/include/dt-bindings/clock/exynos5420.h
>> +++ b/include/dt-bindings/clock/exynos5420.h
>> @@ -58,6 +58,16 @@
>>   #define CLK_SCLK_GSCL_WA      156
>>   #define CLK_SCLK_GSCL_WB      157
>>   #define CLK_SCLK_HDMIPHY      158
>> +#define CLK_SCLK_MPHY_REFCLK   159
>> +#define CLK_SCLK_SPI0_ISP      160
>> +#define CLK_SCLK_SPI1_ISP      161
>> +#define CLK_SCLK_UART_ISP      162
>> +#define CLK_SCLK_ISP_SENSOR0   163
>> +#define CLK_SCLK_ISP_SENSOR1   164
>> +#define CLK_SCLK_ISP_SENSOR2   165
>> +#define CLK_SCLK_PWM_ISP       166
>> +#define CLK_SCLK_HSIC_12M      167
>> +#define CLK_SCLK_MPHY_IXTAL24  168
>>
>>   /* gate clocks */
>>   #define CLK_ACLK66_PERIC      256
>> @@ -123,6 +133,7 @@
>>   #define CLK_USBH20            365
>>   #define CLK_USBD300           366
>>   #define CLK_USBD301           367
>> +#define CLK_PCLK200_FSYS       370
>>   #define CLK_ACLK400_MSCL      380
>>   #define CLK_MSCL0             381
>>   #define CLK_MSCL1             382
>> @@ -141,6 +152,8 @@
>>   #define CLK_ACLK300_DISP1     420
>>   #define CLK_FIMD1             421
>>   #define CLK_SMMU_FIMD1                422
>> +#define CLK_SMMU_FIMD1M1       423
>> +#define CLK_ACLK400_DISP1      424
>>   #define CLK_ACLK166           430
>>   #define CLK_MIXER             431
>>   #define CLK_ACLK266           440
>> @@ -172,12 +185,57 @@
>>   #define CLK_SMMU_FIMCL1               493
>>   #define CLK_SMMU_FIMCL3               494
>>   #define CLK_FIMC_LITE3                495
>> -#define CLK_ACLK_G3D           500
>> -#define CLK_G3D                        501
>> +#define CLK_G3D                        500
>
>
> What is the reason for this ID change? Even if CLK_ACLK_G3D is removed, as
> it wasn't even referenced by the driver, original clock IDs should remain
> fixed.

My Bad.
Anyways, I am planning to post one more patch at the end of the series
to remove the gaps b/w the numbers.
I hope there is no significance of the numbers once we move completely
to macros.

>
>
>>   #define CLK_SMMU_MIXER                502
>> +#define CLK_PCLK_TZPC10                503
>> +#define CLK_PCLK_TZPC11                504
>> +#define CLK_PCLK_MC            505
>> +#define CLK_PCLK_TOP_RTC       506
>> +#define CLK_SMMU_JPEG2         507
>> +#define CLK_PCLK_ROTATOR       508
>> +#define CLK_SMMU_RTIC          509
>> +#define CLK_PCLK_G2D           510
>> +#define CLK_ACLK_SMMU_G2D      511
>> +#define CLK_SMMU_G2D           512
>> +#define CLK_ACLK_SMMU_MDMA0    513
>> +#define CLK_SMMU_MDMA0         514
>> +#define CLK_ACLK_SMMU_SSS      515
>> +#define CLK_SMMU_SSS           516
>> +#define CLK_SMMU_SLIM_SSS      517
>> +#define CLK_ACLK_SMMU_SLIM_SSS 518
>> +#define CLK_ACLK266_ISP                519
>> +#define CLK_ACLK400_ISP                520
>> +#define CLK_ACLK333_432_ISP0   521
>> +#define CLK_ACLK333_432_ISP    522
>> +#define CLK_ACLK_SMMU_MIXER    523
>> +#define CLK_PCLK_HDMIPHY       524
>> +#define CLK_PCLK_GSCL0         525
>> +#define CLK_PCLK_GSCL1         526
>> +#define CLK_PCLK_FIMC_3AA      527
>> +#define CLK_ACLK_FIMC_LITE0    528
>> +#define CLK_ACLK_FIMC_LITE1    529
>> +#define CLK_PCLK_FIMC_LITE0    530
>> +#define CLK_PCLK_FIMC_LITE1    531
>> +#define CLK_PCLK_FIMC_LITE3    532
>> +#define CLK_PCLK_MSCL0         533
>> +#define CLK_PCLK_MSCL1         534
>> +#define CLK_PCLK_MSCL2         535
>> +#define CLK_PCLK_MFC           536
>>
>>   /* mux clocks */
>>   #define CLK_MOUT_HDMI         640
>> +#define CLK_MOUT_FIMD1                 641
>> +#define CLK_MOUT_MAUDIO0               642
>> +#define CLK_MOUT_SPI0                  643
>> +#define CLK_MOUT_SPI1                  644
>> +#define CLK_MOUT_SPI2                  645
>> +#define CLK_MOUT_SW_ACLK333            646
>> +#define CLK_MOUT_USER_ACLK333          647
>> +#define CLK_MOUT_SW_ACLK300_GSCL       648
>> +#define CLK_MOUT_USER_ACLK300_GSCL     649
>> +#define CLK_MOUT_SW_ACLK333_432_GSCL   650
>> +#define CLK_MOUT_USER_ACLK333_432_GSCL 651
>> +#define CLK_MOUT_G3D                   652
>>
>>   /* divider clocks */
>>   #define CLK_DOUT_PIXEL                768
>>
>
> Also similar comment as for patch 1/7, it's hard to tell why this change is
> needed at all.

Ok. Will take care for the next series.

Regards,
Shaik Ameer Basha

>
> Best regards,
> Tomasz

[PATCH v2 3/7] clk: exynos5420: Rename clock IDs

[Shaik Ameer Basha]

From: Rahul Sharma <rahul.sharma@samsung.com>

This patch renames the clock IDs used for the DT bindings as
per Exynos5420 datasheet.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c   |  162 +++++++++++++++++---------------
 include/dt-bindings/clock/exynos5420.h |  138 +++++++++++++--------------
 2 files changed, 154 insertions(+), 146 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 3d0fb77..1402554 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -544,8 +544,8 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 
 static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 	/* TODO: Re-verify the CG bits for all the gate clocks */
-	GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0,
-		"mct"),
+	GATE_A(CLK_PCLK_MCT, "pclk_st", "aclk66_psgen",
+			GATE_BUS_PERIS1, 2, 0, 0, "mct"),
 
 	GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
 			GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
@@ -643,83 +643,90 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 		GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
 	/* FSYS */
 	GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
-	GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
-	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
+	GATE(CLK_ACLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
+	GATE(CLK_ACLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
 	GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
-	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
-	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
-	GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
-	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
-	GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
+	GATE(CLK_ACLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
+	GATE(CLK_ACLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
+	GATE(CLK_ACLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
+	GATE(CLK_ACLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
+	GATE(CLK_HCLK_SROMC, "sromc", "aclk200_fsys2",
 			GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
-	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
-	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
-	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
+	GATE(CLK_HCLK_USBH20, "usbh20", "aclk200_fsys",
+			GATE_BUS_FSYS0, 20, 0, 0),
+	GATE(CLK_HCLK_USBD300, "usbd300", "aclk200_fsys",
+			GATE_BUS_FSYS0, 21, 0, 0),
+	GATE(CLK_HCLK_USBD301, "usbd301", "aclk200_fsys",
+			GATE_BUS_FSYS0, 28, 0, 0),
 
 	/* UART */
-	GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
-	GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
-	GATE_A(CLK_UART2, "uart2", "aclk66_peric",
+	GATE(CLK_PCLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
+	GATE(CLK_PCLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
+	GATE_A(CLK_PCLK_UART2, "uart2", "aclk66_peric",
 		GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
-	GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
+	GATE(CLK_PCLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
 	/* I2C */
-	GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
-	GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
-	GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
-	GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
-	GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
-	GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
-	GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
-	GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
-	GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
-		0),
-	GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
+	GATE(CLK_PCLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
+	GATE(CLK_PCLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
+	GATE(CLK_PCLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
+	GATE(CLK_PCLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
+	GATE(CLK_PCLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric",
+			GATE_BUS_PERIC, 17, 0, 0),
+	GATE(CLK_PCLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
 	/* SPI */
-	GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
-	GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
-	GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
+	GATE(CLK_PCLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
+	GATE(CLK_PCLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
+	GATE(CLK_PCLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
 	GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
 	/* I2S */
-	GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
-	GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
+	GATE(CLK_PCLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
+	GATE(CLK_PCLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
 	/* PCM */
-	GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
-	GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
+	GATE(CLK_PCLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
+	GATE(CLK_PCLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
 	/* PWM */
-	GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
+	GATE(CLK_PCLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
 	/* SPDIF */
-	GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
-
-	GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
-	GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
-	GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
+	GATE(CLK_PCLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
 
-	GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
+	GATE(CLK_PCLK_CHIPID, "chipid", "aclk66_psgen",
 			GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
-	GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
+	GATE(CLK_PCLK_SYSREG, "sysreg", "aclk66_psgen",
 			GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
-	GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
-	GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
-	GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
-	GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
-	GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
-	GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
-	GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
-	GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
-	GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
-	GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
+	GATE(CLK_PCLK_TZPC0, "tzpc0", "aclk66_psgen",
+			GATE_BUS_PERIS0, 18, 0, 0),
+	GATE(CLK_PCLK_TZPC1, "tzpc1", "aclk66_psgen",
+			GATE_BUS_PERIS0, 19, 0, 0),
+	GATE(CLK_PCLK_TZPC2, "tzpc2", "aclk66_psgen",
+			GATE_BUS_PERIS0, 20, 0, 0),
+	GATE(CLK_PCLK_TZPC3, "tzpc3", "aclk66_psgen",
+			GATE_BUS_PERIS0, 21, 0, 0),
+	GATE(CLK_PCLK_TZPC4, "tzpc4", "aclk66_psgen",
+			GATE_BUS_PERIS0, 22, 0, 0),
+	GATE(CLK_PCLK_TZPC5, "tzpc5", "aclk66_psgen",
+			GATE_BUS_PERIS0, 23, 0, 0),
+	GATE(CLK_PCLK_TZPC6, "tzpc6", "aclk66_psgen",
+			GATE_BUS_PERIS0, 24, 0, 0),
+	GATE(CLK_PCLK_TZPC7, "tzpc7", "aclk66_psgen",
+			GATE_BUS_PERIS0, 25, 0, 0),
+	GATE(CLK_PCLK_TZPC8, "tzpc8", "aclk66_psgen",
+			GATE_BUS_PERIS0, 26, 0, 0),
+	GATE(CLK_PCLK_TZPC9, "tzpc9", "aclk66_psgen",
+			GATE_BUS_PERIS0, 27, 0, 0),
 
 	GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0,
 		0),
 	GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
-	GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
-	GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
-	GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
-	GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
+	GATE(CLK_PCLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
+	GATE(CLK_PCLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
+	GATE(CLK_PCLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
+	GATE(CLK_PCLK_TMU_GPU, "tmu_gpu", "aclk66_psgen",
+			GATE_BUS_PERIS1, 6, 0, 0),
 
-	GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
-	GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
-	GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
+	GATE(CLK_ACLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
+	GATE(CLK_ACLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
+	GATE(CLK_ACLK_FIMC_3AA, "clk_3aa", "aclk300_gscl",
+			GATE_IP_GSCL0, 4, 0, 0),
 
 	GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0,
 		0),
@@ -731,38 +738,39 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 		0),
 	GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0,
 		0),
-	GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
+	GATE(CLK_PCLK_GSCL_WA, "gscl_wa", "aclk300_gscl",
+			GATE_IP_GSCL1, 12, 0, 0),
 	GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
 	GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl",
 			GATE_IP_GSCL1, 16, 0, 0),
-	GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
+	GATE(CLK_ACLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
 			GATE_IP_GSCL1, 17, 0, 0),
 
-	GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
-	GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
-	GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
-	GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
-	GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
-	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0,
-		0),
+	GATE(CLK_ACLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
+	GATE(CLK_PCLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
+	GATE(CLK_PCLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
+	GATE(CLK_ACLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
+	GATE(CLK_PCLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
+	GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1", "aclk300_disp1",
+			GATE_IP_DISP1, 8, 0, 0),
 
-	GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
+	GATE(CLK_ACLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
 	GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
 	GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
 
 	GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
 
-	GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
-	GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
-	GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
-	GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
+	GATE(CLK_ACLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
+	GATE(CLK_ACLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
+	GATE(CLK_ACLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
+	GATE(CLK_ACLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
 	GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
 	GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
 	GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
 
-	GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
-	GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
-	GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
+	GATE(CLK_ACLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
+	GATE(CLK_ACLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
+	GATE(CLK_ACLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
 	GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
 		0),
 	GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
@@ -773,7 +781,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 		0),
 
 	/* SSS */
-	GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
+	GATE(CLK_ACLK_SSS, "aclk_sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
 };
 
 static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index e921913..598eb48 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -71,120 +71,120 @@
 
 /* gate clocks */
 #define CLK_ACLK66_PERIC	256
-#define CLK_UART0		257
-#define CLK_UART1		258
-#define CLK_UART2		259
-#define CLK_UART3		260
-#define CLK_I2C0		261
-#define CLK_I2C1		262
-#define CLK_I2C2		263
-#define CLK_I2C3		264
+#define CLK_PCLK_UART0		257
+#define CLK_PCLK_UART1		258
+#define CLK_PCLK_UART2		259
+#define CLK_PCLK_UART3		260
+#define CLK_PCLK_I2C0		261
+#define CLK_PCLK_I2C1		262
+#define CLK_PCLK_I2C2		263
+#define CLK_PCLK_I2C3		264
 #define CLK_I2C4		265
 #define CLK_I2C5		266
 #define CLK_I2C6		267
 #define CLK_I2C7		268
-#define CLK_I2C_HDMI		269
-#define CLK_TSADC		270
-#define CLK_SPI0		271
-#define CLK_SPI1		272
-#define CLK_SPI2		273
+#define CLK_PCLK_I2C_HDMI	269
+#define CLK_PCLK_TSADC		270
+#define CLK_PCLK_SPI0		271
+#define CLK_PCLK_SPI1		272
+#define CLK_PCLK_SPI2		273
 #define CLK_KEYIF		274
-#define CLK_I2S1		275
-#define CLK_I2S2		276
-#define CLK_PCM1		277
-#define CLK_PCM2		278
-#define CLK_PWM			279
-#define CLK_SPDIF		280
+#define CLK_PCLK_I2S1		275
+#define CLK_PCLK_I2S2		276
+#define CLK_PCLK_PCM1		277
+#define CLK_PCLK_PCM2		278
+#define CLK_PCLK_PWM		279
+#define CLK_PCLK_SPDIF		280
 #define CLK_I2C8		281
 #define CLK_I2C9		282
 #define CLK_I2C10		283
 #define CLK_ACLK66_PSGEN	300
-#define CLK_CHIPID		301
-#define CLK_SYSREG		302
-#define CLK_TZPC0		303
-#define CLK_TZPC1		304
-#define CLK_TZPC2		305
-#define CLK_TZPC3		306
-#define CLK_TZPC4		307
-#define CLK_TZPC5		308
-#define CLK_TZPC6		309
-#define CLK_TZPC7		310
-#define CLK_TZPC8		311
-#define CLK_TZPC9		312
+#define CLK_PCLK_CHIPID		301
+#define CLK_PCLK_SYSREG		302
+#define CLK_PCLK_TZPC0		303
+#define CLK_PCLK_TZPC1		304
+#define CLK_PCLK_TZPC2		305
+#define CLK_PCLK_TZPC3		306
+#define CLK_PCLK_TZPC4		307
+#define CLK_PCLK_TZPC5		308
+#define CLK_PCLK_TZPC6		309
+#define CLK_PCLK_TZPC7		310
+#define CLK_PCLK_TZPC8		311
+#define CLK_PCLK_TZPC9		312
 #define CLK_HDMI_CEC		313
 #define CLK_SECKEY		314
-#define CLK_MCT			315
-#define CLK_WDT			316
-#define CLK_RTC			317
-#define CLK_TMU			318
-#define CLK_TMU_GPU		319
+#define CLK_PCLK_MCT		315
+#define CLK_PCLK_WDT		316
+#define CLK_PCLK_RTC		317
+#define CLK_PCLK_TMU		318
+#define CLK_PCLK_TMU_GPU	319
 #define CLK_PCLK66_GPIO		330
 #define CLK_ACLK200_FSYS2	350
-#define CLK_MMC0		351
-#define CLK_MMC1		352
-#define CLK_MMC2		353
-#define CLK_SROMC		354
+#define CLK_ACLK_MMC0		351
+#define CLK_ACLK_MMC1		352
+#define CLK_ACLK_MMC2		353
+#define CLK_HCLK_SROMC		354
 #define CLK_UFS			355
 #define CLK_ACLK200_FSYS	360
 #define CLK_TSI			361
-#define CLK_PDMA0		362
-#define CLK_PDMA1		363
-#define CLK_RTIC		364
-#define CLK_USBH20		365
-#define CLK_USBD300		366
-#define CLK_USBD301		367
+#define CLK_ACLK_PDMA0		362
+#define CLK_ACLK_PDMA1		363
+#define CLK_ACLK_RTIC		364
+#define CLK_HCLK_USBH20		365
+#define CLK_HCLK_USBD300	366
+#define CLK_HCLK_USBD301	367
 #define CLK_PCLK200_FSYS	370
 #define CLK_ACLK400_MSCL	380
-#define CLK_MSCL0		381
-#define CLK_MSCL1		382
-#define CLK_MSCL2		383
+#define CLK_ACLK_MSCL0		381
+#define CLK_ACLK_MSCL1		382
+#define CLK_ACLK_MSCL2		383
 #define CLK_SMMU_MSCL0		384
 #define CLK_SMMU_MSCL1		385
 #define CLK_SMMU_MSCL2		386
 #define CLK_ACLK333		400
-#define CLK_MFC			401
+#define CLK_ACLK_MFC		401
 #define CLK_SMMU_MFCL		402
 #define CLK_SMMU_MFCR		403
 #define CLK_ACLK200_DISP1	410
-#define CLK_DSIM1		411
-#define CLK_DP1			412
-#define CLK_HDMI		413
+#define CLK_PCLK_DSIM1		411
+#define CLK_PCLK_DP1		412
+#define CLK_PCLK_HDMI		413
 #define CLK_ACLK300_DISP1	420
-#define CLK_FIMD1		421
-#define CLK_SMMU_FIMD1		422
+#define CLK_ACLK_FIMD1		421
+#define CLK_SMMU_FIMD1M0	422
 #define CLK_SMMU_FIMD1M1	423
 #define CLK_ACLK400_DISP1	424
 #define CLK_ACLK166		430
-#define CLK_MIXER		431
+#define CLK_ACLK_MIXER		431
 #define CLK_ACLK266		440
-#define CLK_ROTATOR		441
-#define CLK_MDMA1		442
+#define CLK_ACLK_ROTATOR	441
+#define CLK_ACLK_MDMA1		442
 #define CLK_SMMU_ROTATOR	443
 #define CLK_SMMU_MDMA1		444
 #define CLK_ACLK300_JPEG	450
-#define CLK_JPEG		451
-#define CLK_JPEG2		452
+#define CLK_ACLK_JPEG		451
+#define CLK_ACLK_JPEG2		452
 #define CLK_SMMU_JPEG		453
 #define CLK_ACLK300_GSCL	460
 #define CLK_SMMU_GSCL0		461
 #define CLK_SMMU_GSCL1		462
-#define CLK_GSCL_WA		463
+#define CLK_PCLK_GSCL_WA	463
 #define CLK_GSCL_WB		464
-#define CLK_GSCL0		465
-#define CLK_GSCL1		466
-#define CLK_CLK_3AA		467
+#define CLK_ACLK_GSCL0		465
+#define CLK_ACLK_GSCL1		466
+#define CLK_ACLK_FIMC_3AA	467
 #define CLK_ACLK266_G2D		470
-#define CLK_SSS			471
-#define CLK_SLIM_SSS		472
-#define CLK_MDMA0		473
+#define CLK_ACLK_SSS		471
+#define CLK_ACLK_SLIM_SSS	472
+#define CLK_ACLK_MDMA0		473
 #define CLK_ACLK333_G2D		480
-#define CLK_G2D			481
+#define CLK_ACLK_G2D		481
 #define CLK_ACLK333_432_GSCL	490
 #define CLK_SMMU_3AA		491
 #define CLK_SMMU_FIMCL0		492
 #define CLK_SMMU_FIMCL1		493
 #define CLK_SMMU_FIMCL3		494
-#define CLK_FIMC_LITE3		495
+#define CLK_ACLK_FIMC_LITE3	495
 #define CLK_G3D			500
 #define CLK_SMMU_MIXER		502
 #define CLK_PCLK_TZPC10		503
-- 
1.7.9.5

Re: [PATCH v2 3/7] clk: exynos5420: Rename clock IDs

[Gerhard Sittig]

On Thu, 2014-03-27 at 16:37 +0530, Shaik Ameer Basha wrote:
> 
> From: Rahul Sharma <rahul.sharma@samsung.com>
> 
> This patch renames the clock IDs used for the DT bindings as
> per Exynos5420 datasheet.
> 
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c   |  162 +++++++++++++++++---------------
>  include/dt-bindings/clock/exynos5420.h |  138 +++++++++++++--------------
>  2 files changed, 154 insertions(+), 146 deletions(-)

does this break bisection when you rename symbolic identifiers in
their declaration yet don't update references at the users?


virtually yours
Gerhard Sittig
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office@denx.de

Re: [PATCH v2 3/7] clk: exynos5420: Rename clock IDs

[Shaik Ameer Basha]

On Fri, Mar 28, 2014 at 1:19 AM, Gerhard Sittig <gsi@denx.de> wrote:
> On Thu, 2014-03-27 at 16:37 +0530, Shaik Ameer Basha wrote:
>>
>> From: Rahul Sharma <rahul.sharma@samsung.com>
>>
>> This patch renames the clock IDs used for the DT bindings as
>> per Exynos5420 datasheet.
>>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos5420.c   |  162 +++++++++++++++++---------------
>>  include/dt-bindings/clock/exynos5420.h |  138 +++++++++++++--------------
>>  2 files changed, 154 insertions(+), 146 deletions(-)
>
> does this break bisection when you rename symbolic identifiers in
> their declaration yet don't update references at the users?

Hi Gerhard,

Thanks for the review.
You are right. Actually I check for bisect build when I rebased to
linux-next and samsung-clk (of tomasz figa) branches.

I didn't check for bisect build after rebased to following patch.
ARM: dts: use macros in clock bindings for exynos5420

>
>
> virtually yours
> Gerhard Sittig
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office@denx.de

Re: [PATCH v2 3/7] clk: exynos5420: Rename clock IDs

[Shaik Ameer Basha]

On Tue, Apr 1, 2014 at 10:12 AM, Shaik Ameer Basha
<shaik.samsung@gmail.com> wrote:
> On Fri, Mar 28, 2014 at 1:19 AM, Gerhard Sittig <gsi@denx.de> wrote:
>> On Thu, 2014-03-27 at 16:37 +0530, Shaik Ameer Basha wrote:
>>>
>>> From: Rahul Sharma <rahul.sharma@samsung.com>
>>>
>>> This patch renames the clock IDs used for the DT bindings as
>>> per Exynos5420 datasheet.
>>>
>>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>>> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
>>> ---
>>>  drivers/clk/samsung/clk-exynos5420.c   |  162 +++++++++++++++++---------------
>>>  include/dt-bindings/clock/exynos5420.h |  138 +++++++++++++--------------
>>>  2 files changed, 154 insertions(+), 146 deletions(-)
>>
>> does this break bisection when you rename symbolic identifiers in
>> their declaration yet don't update references at the users?
>
> Hi Gerhard,
>
> Thanks for the review.
> You are right. Actually I check for bisect build when I rebased to
> linux-next and samsung-clk (of tomasz figa) branches.
>
> I didn't check for bisect build after rebased to following patch.
> ARM: dts: use macros in clock bindings for exynos5420
>

Will fix this in the next version of patch series.

Regards,
Shaik Ameer Basha

>>
>>
>> virtually yours
>> Gerhard Sittig
>> --
>> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
>> HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
>> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office@denx.de

Re: [PATCH v2 3/7] clk: exynos5420: Rename clock IDs

[Tomasz Figa]

Hi Shaik,

On 27.03.2014 12:07, Shaik Ameer Basha wrote:
> From: Rahul Sharma <rahul.sharma@samsung.com>
>
> This patch renames the clock IDs used for the DT bindings as
> per Exynos5420 datasheet.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
> ---
>   drivers/clk/samsung/clk-exynos5420.c   |  162 +++++++++++++++++---------------
>   include/dt-bindings/clock/exynos5420.h |  138 +++++++++++++--------------
>   2 files changed, 154 insertions(+), 146 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 3d0fb77..1402554 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -544,8 +544,8 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
>
>   static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>   	/* TODO: Re-verify the CG bits for all the gate clocks */
> -	GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0,
> -		"mct"),
> +	GATE_A(CLK_PCLK_MCT, "pclk_st", "aclk66_psgen",
> +			GATE_BUS_PERIS1, 2, 0, 0, "mct"),

Clock IDs should generally match clock names, while this one obviously 
does not. Either you should update both, or... (see below)

>
>   	GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
>   			GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
> @@ -643,83 +643,90 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>   		GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
>   	/* FSYS */
>   	GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
> -	GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> -	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> +	GATE(CLK_ACLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> +	GATE(CLK_ACLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
>   	GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
> -	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
> -	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
> -	GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
> -	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
> -	GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
> +	GATE(CLK_ACLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
> +	GATE(CLK_ACLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
> +	GATE(CLK_ACLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
> +	GATE(CLK_ACLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
> +	GATE(CLK_HCLK_SROMC, "sromc", "aclk200_fsys2",
>   			GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
> -	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
> -	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
> -	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
> +	GATE(CLK_HCLK_USBH20, "usbh20", "aclk200_fsys",
> +			GATE_BUS_FSYS0, 20, 0, 0),
> +	GATE(CLK_HCLK_USBD300, "usbd300", "aclk200_fsys",
> +			GATE_BUS_FSYS0, 21, 0, 0),
> +	GATE(CLK_HCLK_USBD301, "usbd301", "aclk200_fsys",
> +			GATE_BUS_FSYS0, 28, 0, 0),
>
>   	/* UART */
> -	GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
> -	GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
> -	GATE_A(CLK_UART2, "uart2", "aclk66_peric",
> +	GATE(CLK_PCLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
> +	GATE(CLK_PCLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
> +	GATE_A(CLK_PCLK_UART2, "uart2", "aclk66_peric",
>   		GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
> -	GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
> +	GATE(CLK_PCLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
>   	/* I2C */
> -	GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
> -	GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
> -	GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
> -	GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
> -	GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
> -	GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
> -	GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
> -	GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
> -	GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
> -		0),
> -	GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
> +	GATE(CLK_PCLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
> +	GATE(CLK_PCLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
> +	GATE(CLK_PCLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
> +	GATE(CLK_PCLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
> +	GATE(CLK_PCLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric",
> +			GATE_BUS_PERIC, 17, 0, 0),
> +	GATE(CLK_PCLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
>   	/* SPI */
> -	GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
> -	GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
> -	GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
> +	GATE(CLK_PCLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
> +	GATE(CLK_PCLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
> +	GATE(CLK_PCLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
>   	GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
>   	/* I2S */
> -	GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
> -	GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
> +	GATE(CLK_PCLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
> +	GATE(CLK_PCLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
>   	/* PCM */
> -	GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
> -	GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
> +	GATE(CLK_PCLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
> +	GATE(CLK_PCLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
>   	/* PWM */
> -	GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
> +	GATE(CLK_PCLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
>   	/* SPDIF */
> -	GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
> -
> -	GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
> -	GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
> -	GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
> +	GATE(CLK_PCLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
>
> -	GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
> +	GATE(CLK_PCLK_CHIPID, "chipid", "aclk66_psgen",
>   			GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
> -	GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
> +	GATE(CLK_PCLK_SYSREG, "sysreg", "aclk66_psgen",
>   			GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
> -	GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
> -	GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
> -	GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
> -	GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
> -	GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
> -	GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
> -	GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
> -	GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
> -	GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
> -	GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
> +	GATE(CLK_PCLK_TZPC0, "tzpc0", "aclk66_psgen",
> +			GATE_BUS_PERIS0, 18, 0, 0),
> +	GATE(CLK_PCLK_TZPC1, "tzpc1", "aclk66_psgen",
> +			GATE_BUS_PERIS0, 19, 0, 0),
> +	GATE(CLK_PCLK_TZPC2, "tzpc2", "aclk66_psgen",
> +			GATE_BUS_PERIS0, 20, 0, 0),
> +	GATE(CLK_PCLK_TZPC3, "tzpc3", "aclk66_psgen",
> +			GATE_BUS_PERIS0, 21, 0, 0),
> +	GATE(CLK_PCLK_TZPC4, "tzpc4", "aclk66_psgen",
> +			GATE_BUS_PERIS0, 22, 0, 0),
> +	GATE(CLK_PCLK_TZPC5, "tzpc5", "aclk66_psgen",
> +			GATE_BUS_PERIS0, 23, 0, 0),
> +	GATE(CLK_PCLK_TZPC6, "tzpc6", "aclk66_psgen",
> +			GATE_BUS_PERIS0, 24, 0, 0),
> +	GATE(CLK_PCLK_TZPC7, "tzpc7", "aclk66_psgen",
> +			GATE_BUS_PERIS0, 25, 0, 0),
> +	GATE(CLK_PCLK_TZPC8, "tzpc8", "aclk66_psgen",
> +			GATE_BUS_PERIS0, 26, 0, 0),
> +	GATE(CLK_PCLK_TZPC9, "tzpc9", "aclk66_psgen",
> +			GATE_BUS_PERIS0, 27, 0, 0),
>
>   	GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0,
>   		0),
>   	GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
> -	GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
> -	GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
> -	GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
> -	GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
> +	GATE(CLK_PCLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
> +	GATE(CLK_PCLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
> +	GATE(CLK_PCLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
> +	GATE(CLK_PCLK_TMU_GPU, "tmu_gpu", "aclk66_psgen",
> +			GATE_BUS_PERIS1, 6, 0, 0),
>

I'm starting to suspect that there is something wrong with this driver. 
Why does it use GATE_BUS_* registers? I believe they provide too fine 
grained control over clocks to suit expectations of our drivers, which 
usually need one "bus clock" gate and optionally one "special clock" gate.

The problem with GATE_BUS_* bits is that they provide control over every 
single clock of over single IP and each IP can have multiple bus clocks 
(e.g. ACLK, PCLK, HCLK, etc.). Gating or ungating one is not enough to 
either properly save power or make the device operable. That's why all 
previous SoCs (Exynos4, Exynos5250) simply used GATE_IP_* registers that 
provide per IP control which matches what our drivers use.

I need to verify this further in datasheet (as soon as I get access to 
one...), but I suspect this is plain wrong.

Now, one side effect of using GATE_IP_* registers will be no need to add 
*CLK_ prefix to clock IDs as they would be simply gating the IPs, not 
their particular clocks.

> -	GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
> -	GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
> -	GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
> +	GATE(CLK_ACLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
> +	GATE(CLK_ACLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
> +	GATE(CLK_ACLK_FIMC_3AA, "clk_3aa", "aclk300_gscl",
> +			GATE_IP_GSCL0, 4, 0, 0),
>
>   	GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0,
>   		0),
> @@ -731,38 +738,39 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>   		0),
>   	GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0,
>   		0),
> -	GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
> +	GATE(CLK_PCLK_GSCL_WA, "gscl_wa", "aclk300_gscl",
> +			GATE_IP_GSCL1, 12, 0, 0),
>   	GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
>   	GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl",
>   			GATE_IP_GSCL1, 16, 0, 0),
> -	GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
> +	GATE(CLK_ACLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
>   			GATE_IP_GSCL1, 17, 0, 0),
>
> -	GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
> -	GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
> -	GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
> -	GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
> -	GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
> -	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0,
> -		0),
> +	GATE(CLK_ACLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
> +	GATE(CLK_PCLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
> +	GATE(CLK_PCLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
> +	GATE(CLK_ACLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
> +	GATE(CLK_PCLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
> +	GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1", "aclk300_disp1",
> +			GATE_IP_DISP1, 8, 0, 0),
>
> -	GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
> +	GATE(CLK_ACLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
>   	GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
>   	GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
>
>   	GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
>
> -	GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
> -	GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
> -	GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
> -	GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
> +	GATE(CLK_ACLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
> +	GATE(CLK_ACLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
> +	GATE(CLK_ACLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
> +	GATE(CLK_ACLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
>   	GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
>   	GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
>   	GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
>
> -	GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
> -	GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
> -	GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
> +	GATE(CLK_ACLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
> +	GATE(CLK_ACLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
> +	GATE(CLK_ACLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
>   	GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
>   		0),
>   	GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
> @@ -773,7 +781,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>   		0),
>
>   	/* SSS */
> -	GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
> +	GATE(CLK_ACLK_SSS, "aclk_sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
>   };
>
>   static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
> index e921913..598eb48 100644
> --- a/include/dt-bindings/clock/exynos5420.h
> +++ b/include/dt-bindings/clock/exynos5420.h
> @@ -71,120 +71,120 @@
>
>   /* gate clocks */
>   #define CLK_ACLK66_PERIC	256
> -#define CLK_UART0		257
> -#define CLK_UART1		258
> -#define CLK_UART2		259
> -#define CLK_UART3		260
> -#define CLK_I2C0		261
> -#define CLK_I2C1		262
> -#define CLK_I2C2		263
> -#define CLK_I2C3		264
> +#define CLK_PCLK_UART0		257
> +#define CLK_PCLK_UART1		258
> +#define CLK_PCLK_UART2		259
> +#define CLK_PCLK_UART3		260
> +#define CLK_PCLK_I2C0		261
> +#define CLK_PCLK_I2C1		262
> +#define CLK_PCLK_I2C2		263
> +#define CLK_PCLK_I2C3		264
>   #define CLK_I2C4		265
>   #define CLK_I2C5		266
>   #define CLK_I2C6		267
>   #define CLK_I2C7		268
> -#define CLK_I2C_HDMI		269
> -#define CLK_TSADC		270
> -#define CLK_SPI0		271
> -#define CLK_SPI1		272
> -#define CLK_SPI2		273
> +#define CLK_PCLK_I2C_HDMI	269
> +#define CLK_PCLK_TSADC		270
> +#define CLK_PCLK_SPI0		271
> +#define CLK_PCLK_SPI1		272
> +#define CLK_PCLK_SPI2		273
>   #define CLK_KEYIF		274
> -#define CLK_I2S1		275
> -#define CLK_I2S2		276
> -#define CLK_PCM1		277
> -#define CLK_PCM2		278
> -#define CLK_PWM			279
> -#define CLK_SPDIF		280
> +#define CLK_PCLK_I2S1		275
> +#define CLK_PCLK_I2S2		276
> +#define CLK_PCLK_PCM1		277
> +#define CLK_PCLK_PCM2		278
> +#define CLK_PCLK_PWM		279
> +#define CLK_PCLK_SPDIF		280
>   #define CLK_I2C8		281
>   #define CLK_I2C9		282
>   #define CLK_I2C10		283
>   #define CLK_ACLK66_PSGEN	300
> -#define CLK_CHIPID		301
> -#define CLK_SYSREG		302
> -#define CLK_TZPC0		303
> -#define CLK_TZPC1		304
> -#define CLK_TZPC2		305
> -#define CLK_TZPC3		306
> -#define CLK_TZPC4		307
> -#define CLK_TZPC5		308
> -#define CLK_TZPC6		309
> -#define CLK_TZPC7		310
> -#define CLK_TZPC8		311
> -#define CLK_TZPC9		312
> +#define CLK_PCLK_CHIPID		301
> +#define CLK_PCLK_SYSREG		302
> +#define CLK_PCLK_TZPC0		303
> +#define CLK_PCLK_TZPC1		304
> +#define CLK_PCLK_TZPC2		305
> +#define CLK_PCLK_TZPC3		306
> +#define CLK_PCLK_TZPC4		307
> +#define CLK_PCLK_TZPC5		308
> +#define CLK_PCLK_TZPC6		309
> +#define CLK_PCLK_TZPC7		310
> +#define CLK_PCLK_TZPC8		311
> +#define CLK_PCLK_TZPC9		312
>   #define CLK_HDMI_CEC		313
>   #define CLK_SECKEY		314
> -#define CLK_MCT			315
> -#define CLK_WDT			316
> -#define CLK_RTC			317
> -#define CLK_TMU			318
> -#define CLK_TMU_GPU		319
> +#define CLK_PCLK_MCT		315
> +#define CLK_PCLK_WDT		316
> +#define CLK_PCLK_RTC		317
> +#define CLK_PCLK_TMU		318
> +#define CLK_PCLK_TMU_GPU	319
>   #define CLK_PCLK66_GPIO		330
>   #define CLK_ACLK200_FSYS2	350
> -#define CLK_MMC0		351
> -#define CLK_MMC1		352
> -#define CLK_MMC2		353
> -#define CLK_SROMC		354
> +#define CLK_ACLK_MMC0		351
> +#define CLK_ACLK_MMC1		352
> +#define CLK_ACLK_MMC2		353
> +#define CLK_HCLK_SROMC		354
>   #define CLK_UFS			355
>   #define CLK_ACLK200_FSYS	360
>   #define CLK_TSI			361
> -#define CLK_PDMA0		362
> -#define CLK_PDMA1		363
> -#define CLK_RTIC		364
> -#define CLK_USBH20		365
> -#define CLK_USBD300		366
> -#define CLK_USBD301		367
> +#define CLK_ACLK_PDMA0		362
> +#define CLK_ACLK_PDMA1		363
> +#define CLK_ACLK_RTIC		364
> +#define CLK_HCLK_USBH20		365
> +#define CLK_HCLK_USBD300	366
> +#define CLK_HCLK_USBD301	367
>   #define CLK_PCLK200_FSYS	370
>   #define CLK_ACLK400_MSCL	380
> -#define CLK_MSCL0		381
> -#define CLK_MSCL1		382
> -#define CLK_MSCL2		383
> +#define CLK_ACLK_MSCL0		381
> +#define CLK_ACLK_MSCL1		382
> +#define CLK_ACLK_MSCL2		383
>   #define CLK_SMMU_MSCL0		384
>   #define CLK_SMMU_MSCL1		385
>   #define CLK_SMMU_MSCL2		386
>   #define CLK_ACLK333		400
> -#define CLK_MFC			401
> +#define CLK_ACLK_MFC		401
>   #define CLK_SMMU_MFCL		402
>   #define CLK_SMMU_MFCR		403
>   #define CLK_ACLK200_DISP1	410
> -#define CLK_DSIM1		411
> -#define CLK_DP1			412
> -#define CLK_HDMI		413
> +#define CLK_PCLK_DSIM1		411
> +#define CLK_PCLK_DP1		412
> +#define CLK_PCLK_HDMI		413
>   #define CLK_ACLK300_DISP1	420
> -#define CLK_FIMD1		421
> -#define CLK_SMMU_FIMD1		422
> +#define CLK_ACLK_FIMD1		421
> +#define CLK_SMMU_FIMD1M0	422
>   #define CLK_SMMU_FIMD1M1	423
>   #define CLK_ACLK400_DISP1	424
>   #define CLK_ACLK166		430
> -#define CLK_MIXER		431
> +#define CLK_ACLK_MIXER		431
>   #define CLK_ACLK266		440
> -#define CLK_ROTATOR		441
> -#define CLK_MDMA1		442
> +#define CLK_ACLK_ROTATOR	441
> +#define CLK_ACLK_MDMA1		442
>   #define CLK_SMMU_ROTATOR	443
>   #define CLK_SMMU_MDMA1		444
>   #define CLK_ACLK300_JPEG	450
> -#define CLK_JPEG		451
> -#define CLK_JPEG2		452
> +#define CLK_ACLK_JPEG		451
> +#define CLK_ACLK_JPEG2		452
>   #define CLK_SMMU_JPEG		453
>   #define CLK_ACLK300_GSCL	460
>   #define CLK_SMMU_GSCL0		461
>   #define CLK_SMMU_GSCL1		462
> -#define CLK_GSCL_WA		463
> +#define CLK_PCLK_GSCL_WA	463
>   #define CLK_GSCL_WB		464
> -#define CLK_GSCL0		465
> -#define CLK_GSCL1		466
> -#define CLK_CLK_3AA		467
> +#define CLK_ACLK_GSCL0		465
> +#define CLK_ACLK_GSCL1		466
> +#define CLK_ACLK_FIMC_3AA	467
>   #define CLK_ACLK266_G2D		470
> -#define CLK_SSS			471
> -#define CLK_SLIM_SSS		472
> -#define CLK_MDMA0		473
> +#define CLK_ACLK_SSS		471
> +#define CLK_ACLK_SLIM_SSS	472
> +#define CLK_ACLK_MDMA0		473
>   #define CLK_ACLK333_G2D		480
> -#define CLK_G2D			481
> +#define CLK_ACLK_G2D		481
>   #define CLK_ACLK333_432_GSCL	490
>   #define CLK_SMMU_3AA		491
>   #define CLK_SMMU_FIMCL0		492
>   #define CLK_SMMU_FIMCL1		493
>   #define CLK_SMMU_FIMCL3		494
> -#define CLK_FIMC_LITE3		495
> +#define CLK_ACLK_FIMC_LITE3	495
>   #define CLK_G3D			500
>   #define CLK_SMMU_MIXER		502
>   #define CLK_PCLK_TZPC10		503
>

As Gerhard already mentioned, this will break bisection of existing 
users of old macros, so this is a bad idea to change them this way.

Anyway, most of those renames are mostly adding *CLK_ prefixes, so I 
really wonder if this is necessary, especially considering the 
GATE_BUS_* issue I mentioned above and that clock names (and parent 
names in all their children) would have to be updated as well. What do 
you think?

Best regards,
Tomasz

Re: [PATCH v2 3/7] clk: exynos5420: Rename clock IDs

[Shaik Ameer Basha]

Hi Tomasz,

Thanks for the review comments.

On Tue, Apr 15, 2014 at 10:33 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Shaik,
>
>
> On 27.03.2014 12:07, Shaik Ameer Basha wrote:
>>
>> From: Rahul Sharma <rahul.sharma@samsung.com>
>>
>> This patch renames the clock IDs used for the DT bindings as
>> per Exynos5420 datasheet.
>>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos5420.c   |  162
>> +++++++++++++++++---------------
>>   include/dt-bindings/clock/exynos5420.h |  138
>> +++++++++++++--------------
>>   2 files changed, 154 insertions(+), 146 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c
>> b/drivers/clk/samsung/clk-exynos5420.c
>> index 3d0fb77..1402554 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -544,8 +544,8 @@ static struct samsung_div_clock exynos5420_div_clks[]
>> __initdata = {
>>
>>   static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>>         /* TODO: Re-verify the CG bits for all the gate clocks */
>> -       GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0,
>> 0,
>> -               "mct"),
>> +       GATE_A(CLK_PCLK_MCT, "pclk_st", "aclk66_psgen",
>> +                       GATE_BUS_PERIS1, 2, 0, 0, "mct"),

True. I think somehow i missed it. I will fix that.

>
>
> Clock IDs should generally match clock names, while this one obviously does
> not. Either you should update both, or... (see below)
>
>
>>
>>         GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
>>                         GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
>> @@ -643,83 +643,90 @@ static struct samsung_gate_clock
>> exynos5420_gate_clks[] __initdata = {
>>                 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
>>         /* FSYS */
>>         GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
>> -       GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
>> -       GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
>> +       GATE(CLK_ACLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1,
>> 0, 0),
>> +       GATE(CLK_ACLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2,
>> 0, 0),
>>         GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
>> -       GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
>> -       GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
>> -       GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
>> -       GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
>> -       GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
>> +       GATE(CLK_ACLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0,
>> 0),
>> +       GATE(CLK_ACLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12,
>> 0, 0),
>> +       GATE(CLK_ACLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13,
>> 0, 0),
>> +       GATE(CLK_ACLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14,
>> 0, 0),
>> +       GATE(CLK_HCLK_SROMC, "sromc", "aclk200_fsys2",
>>                         GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
>> -       GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0,
>> 0),
>> -       GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21,
>> 0, 0),
>> -       GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28,
>> 0, 0),
>> +       GATE(CLK_HCLK_USBH20, "usbh20", "aclk200_fsys",
>> +                       GATE_BUS_FSYS0, 20, 0, 0),
>> +       GATE(CLK_HCLK_USBD300, "usbd300", "aclk200_fsys",
>> +                       GATE_BUS_FSYS0, 21, 0, 0),
>> +       GATE(CLK_HCLK_USBD301, "usbd301", "aclk200_fsys",
>> +                       GATE_BUS_FSYS0, 28, 0, 0),
>>
>>         /* UART */
>> -       GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
>> -       GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
>> -       GATE_A(CLK_UART2, "uart2", "aclk66_peric",
>> +       GATE(CLK_PCLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4,
>> 0, 0),
>> +       GATE(CLK_PCLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5,
>> 0, 0),
>> +       GATE_A(CLK_PCLK_UART2, "uart2", "aclk66_peric",
>>                 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
>> -       GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
>> +       GATE(CLK_PCLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7,
>> 0, 0),
>>         /* I2C */
>> -       GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
>> -       GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
>> -       GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
>> -       GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
>> -       GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
>> -       GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
>> -       GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
>> -       GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
>> -       GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17,
>> 0,
>> -               0),
>> -       GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0,
>> 0),
>> +       GATE(CLK_PCLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0,
>> 0),
>> +       GATE(CLK_PCLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0,
>> 0),
>> +       GATE(CLK_PCLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0,
>> 0),
>> +       GATE(CLK_PCLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0,
>> 0),
>> +       GATE(CLK_PCLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric",
>> +                       GATE_BUS_PERIC, 17, 0, 0),
>> +       GATE(CLK_PCLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18,
>> 0, 0),
>>         /* SPI */
>> -       GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
>> -       GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
>> -       GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
>> +       GATE(CLK_PCLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0,
>> 0),
>> +       GATE(CLK_PCLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0,
>> 0),
>> +       GATE(CLK_PCLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0,
>> 0),
>>         GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0,
>> 0),
>>         /* I2S */
>> -       GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
>> -       GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
>> +       GATE(CLK_PCLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0,
>> 0),
>> +       GATE(CLK_PCLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0,
>> 0),
>>         /* PCM */
>> -       GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
>> -       GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
>> +       GATE(CLK_PCLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0,
>> 0),
>> +       GATE(CLK_PCLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0,
>> 0),
>>         /* PWM */
>> -       GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
>> +       GATE(CLK_PCLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0,
>> 0),
>>         /* SPDIF */
>> -       GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0,
>> 0),
>> -
>> -       GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
>> -       GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
>> -       GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0,
>> 0),
>> +       GATE(CLK_PCLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29,
>> 0, 0),
>>
>> -       GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
>> +       GATE(CLK_PCLK_CHIPID, "chipid", "aclk66_psgen",
>>                         GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
>> -       GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
>> +       GATE(CLK_PCLK_SYSREG, "sysreg", "aclk66_psgen",
>>                         GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
>> -       GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0,
>> 0),
>> -       GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0,
>> 0),
>> -       GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0,
>> 0),
>> -       GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0,
>> 0),
>> -       GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0,
>> 0),
>> -       GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0,
>> 0),
>> -       GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0,
>> 0),
>> -       GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0,
>> 0),
>> -       GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0,
>> 0),
>> -       GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0,
>> 0),
>> +       GATE(CLK_PCLK_TZPC0, "tzpc0", "aclk66_psgen",
>> +                       GATE_BUS_PERIS0, 18, 0, 0),
>> +       GATE(CLK_PCLK_TZPC1, "tzpc1", "aclk66_psgen",
>> +                       GATE_BUS_PERIS0, 19, 0, 0),
>> +       GATE(CLK_PCLK_TZPC2, "tzpc2", "aclk66_psgen",
>> +                       GATE_BUS_PERIS0, 20, 0, 0),
>> +       GATE(CLK_PCLK_TZPC3, "tzpc3", "aclk66_psgen",
>> +                       GATE_BUS_PERIS0, 21, 0, 0),
>> +       GATE(CLK_PCLK_TZPC4, "tzpc4", "aclk66_psgen",
>> +                       GATE_BUS_PERIS0, 22, 0, 0),
>> +       GATE(CLK_PCLK_TZPC5, "tzpc5", "aclk66_psgen",
>> +                       GATE_BUS_PERIS0, 23, 0, 0),
>> +       GATE(CLK_PCLK_TZPC6, "tzpc6", "aclk66_psgen",
>> +                       GATE_BUS_PERIS0, 24, 0, 0),
>> +       GATE(CLK_PCLK_TZPC7, "tzpc7", "aclk66_psgen",
>> +                       GATE_BUS_PERIS0, 25, 0, 0),
>> +       GATE(CLK_PCLK_TZPC8, "tzpc8", "aclk66_psgen",
>> +                       GATE_BUS_PERIS0, 26, 0, 0),
>> +       GATE(CLK_PCLK_TZPC9, "tzpc9", "aclk66_psgen",
>> +                       GATE_BUS_PERIS0, 27, 0, 0),
>>
>>         GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0,
>> 0,
>>                 0),
>>         GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0,
>> 0),
>> -       GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
>> -       GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
>> -       GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
>> -       GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6,
>> 0, 0),
>> +       GATE(CLK_PCLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0,
>> 0),
>> +       GATE(CLK_PCLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0,
>> 0),
>> +       GATE(CLK_PCLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0,
>> 0),
>> +       GATE(CLK_PCLK_TMU_GPU, "tmu_gpu", "aclk66_psgen",
>> +                       GATE_BUS_PERIS1, 6, 0, 0),
>>
>
> I'm starting to suspect that there is something wrong with this driver. Why
> does it use GATE_BUS_* registers? I believe they provide too fine grained
> control over clocks to suit expectations of our drivers, which usually need
> one "bus clock" gate and optionally one "special clock" gate.
>
> The problem with GATE_BUS_* bits is that they provide control over every
> single clock of over single IP and each IP can have multiple bus clocks
> (e.g. ACLK, PCLK, HCLK, etc.). Gating or ungating one is not enough to
> either properly save power or make the device operable. That's why all
> previous SoCs (Exynos4, Exynos5250) simply used GATE_IP_* registers that
> provide per IP control which matches what our drivers use.

True.
According to the datasheet for Exynos5420, Clock gating of any IP is
described like this

------>
Four types of clock gating control registers to disable/enable clock operation:
        [1] Clock gating control register for function block (CLK_GATE_BLOCK_*)
        [2] Clock gating control register for IP (CLK_GATE_IP_*)
        [3] Clock gating control register for special clocks
(CLK_GATE_SCLK_*, CLK_GATE_TOP_SCLK_*)
        [4] Clock gating control register for BUS (CLK_GATE_BUS_*)

Any combination of above four register are ANDed together to generate
a final clock gating enable signal.
As a result, if one of the combined register field is truned off, the
resulting clock stops.
For instance, in order to stop clocks that are provided to MIXER
module, one may set
        CLK_MIXER field in CLK_GATE_BUS_IP_DISP1 register to 0 or
        CLK_DISP1 field in CLK_GATE_BLOCK register to 0 or
        ACLK_MIXER field in CLK_GATE_BUS_DISP1 register to 0
<---------

But if we see the Exynos5250 datasheet, points [3], [4] are not mentioned.
Currently we are using point [4] to gate any IP wherever possible.

And even CLK_GATE_IP_* register also distinguishes between APB and AXI
clock gating.
For example, there are two different bits to gate APB and AXI clocks
separately in CLK_GATE_IP_GSCL0.

Register: CLK_GATE_IP_GSCL0
CLK_GSCALER1 - [15] -  Gating APB clock for GSCALER1,  0 = Masks and 1 = Passes
CLK_GSCALER0 - [14]  - Gating APB clock for GSCALER0,  0 = Masks and 1 = Passes

CLK_GSCL1 - [1]   - Gating AXI clock for SYSMMU_GSCALER1
                                 Gating AXI clock for QE_GSCALER1
                                 Gating AXI clock for GSCALER1
                                 0 = Masks and 1 = Passes

CLK_GSCL0 - [0]  - Gating AXI clock for SYSMMU_GSCALER0
                                Gating AXI clock for QE_GSCALER0
                                Gating AXI clock for GSCALER0
                                0 = Masks and 1 = Passes

Rahul may have other requirements for selecting this method [4] for
chrome project.
I hope he will clarify the same here.

For me, If I see no difference b/w using CLK_GATE_BUS_* and
CLK_GATE_IP_* registers,
then I will definitely interested to use the CLK_GATE_IP_* in the next series.

Incase if I see any difficulty in implementation with above method, I
will share with you and
provide a suitable workaround.

Regards,
Shaik Ameer Basha

>
> I need to verify this further in datasheet (as soon as I get access to
> one...), but I suspect this is plain wrong.
>
> Now, one side effect of using GATE_IP_* registers will be no need to add
> *CLK_ prefix to clock IDs as they would be simply gating the IPs, not their
> particular clocks.
>
>
>> -       GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
>> -       GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
>> -       GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0,
>> 0),
>> +       GATE(CLK_ACLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0,
>> 0),
>> +       GATE(CLK_ACLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0,
>> 0),
>> +       GATE(CLK_ACLK_FIMC_3AA, "clk_3aa", "aclk300_gscl",
>> +                       GATE_IP_GSCL0, 4, 0, 0),
>>
>>         GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1,
>> 2, 0,
>>                 0),
>> @@ -731,38 +738,39 @@ static struct samsung_gate_clock
>> exynos5420_gate_clks[] __initdata = {
>>                 0),
>>         GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1,
>> 7, 0,
>>                 0),
>> -       GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0,
>> 0),
>> +       GATE(CLK_PCLK_GSCL_WA, "gscl_wa", "aclk300_gscl",
>> +                       GATE_IP_GSCL1, 12, 0, 0),
>>         GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0,
>> 0),
>>         GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl",
>>                         GATE_IP_GSCL1, 16, 0, 0),
>> -       GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
>> +       GATE(CLK_ACLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
>>                         GATE_IP_GSCL1, 17, 0, 0),
>>
>> -       GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
>> -       GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
>> -       GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
>> -       GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
>> -       GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
>> -       GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1,
>> 8, 0,
>> -               0),
>> +       GATE(CLK_ACLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0,
>> 0, 0),
>> +       GATE(CLK_PCLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3,
>> 0, 0),
>> +       GATE(CLK_PCLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0,
>> 0),
>> +       GATE(CLK_ACLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
>> +       GATE(CLK_PCLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0,
>> 0),
>> +       GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1", "aclk300_disp1",
>> +                       GATE_IP_DISP1, 8, 0, 0),
>>
>> -       GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
>> +       GATE(CLK_ACLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
>>         GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
>>         GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
>>
>>         GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
>>
>> -       GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
>> -       GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
>> -       GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
>> -       GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
>> +       GATE(CLK_ACLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0,
>> 0),
>> +       GATE(CLK_ACLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
>> +       GATE(CLK_ACLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0,
>> 0),
>> +       GATE(CLK_ACLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
>>         GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6,
>> 0, 0),
>>         GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7,
>> 0, 0),
>>         GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0,
>> 0),
>>
>> -       GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
>> -       GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
>> -       GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
>> +       GATE(CLK_ACLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0,
>> 0),
>> +       GATE(CLK_ACLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0,
>> 0),
>> +       GATE(CLK_ACLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0,
>> 0),
>>         GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL,
>> 8, 0,
>>                 0),
>>         GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL,
>> 9, 0,
>> @@ -773,7 +781,7 @@ static struct samsung_gate_clock
>> exynos5420_gate_clks[] __initdata = {
>>                 0),
>>
>>         /* SSS */
>> -       GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
>> +       GATE(CLK_ACLK_SSS, "aclk_sss", "aclk266_g2d", GATE_IP_G2D, 2, 0,
>> 0),
>>   };
>>
>>   static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
>> diff --git a/include/dt-bindings/clock/exynos5420.h
>> b/include/dt-bindings/clock/exynos5420.h
>> index e921913..598eb48 100644
>> --- a/include/dt-bindings/clock/exynos5420.h
>> +++ b/include/dt-bindings/clock/exynos5420.h
>> @@ -71,120 +71,120 @@
>>
>>   /* gate clocks */
>>   #define CLK_ACLK66_PERIC      256
>> -#define CLK_UART0              257
>> -#define CLK_UART1              258
>> -#define CLK_UART2              259
>> -#define CLK_UART3              260
>> -#define CLK_I2C0               261
>> -#define CLK_I2C1               262
>> -#define CLK_I2C2               263
>> -#define CLK_I2C3               264
>> +#define CLK_PCLK_UART0         257
>> +#define CLK_PCLK_UART1         258
>> +#define CLK_PCLK_UART2         259
>> +#define CLK_PCLK_UART3         260
>> +#define CLK_PCLK_I2C0          261
>> +#define CLK_PCLK_I2C1          262
>> +#define CLK_PCLK_I2C2          263
>> +#define CLK_PCLK_I2C3          264
>>   #define CLK_I2C4              265
>>   #define CLK_I2C5              266
>>   #define CLK_I2C6              267
>>   #define CLK_I2C7              268
>> -#define CLK_I2C_HDMI           269
>> -#define CLK_TSADC              270
>> -#define CLK_SPI0               271
>> -#define CLK_SPI1               272
>> -#define CLK_SPI2               273
>> +#define CLK_PCLK_I2C_HDMI      269
>> +#define CLK_PCLK_TSADC         270
>> +#define CLK_PCLK_SPI0          271
>> +#define CLK_PCLK_SPI1          272
>> +#define CLK_PCLK_SPI2          273
>>   #define CLK_KEYIF             274
>> -#define CLK_I2S1               275
>> -#define CLK_I2S2               276
>> -#define CLK_PCM1               277
>> -#define CLK_PCM2               278
>> -#define CLK_PWM                        279
>> -#define CLK_SPDIF              280
>> +#define CLK_PCLK_I2S1          275
>> +#define CLK_PCLK_I2S2          276
>> +#define CLK_PCLK_PCM1          277
>> +#define CLK_PCLK_PCM2          278
>> +#define CLK_PCLK_PWM           279
>> +#define CLK_PCLK_SPDIF         280
>>   #define CLK_I2C8              281
>>   #define CLK_I2C9              282
>>   #define CLK_I2C10             283
>>   #define CLK_ACLK66_PSGEN      300
>> -#define CLK_CHIPID             301
>> -#define CLK_SYSREG             302
>> -#define CLK_TZPC0              303
>> -#define CLK_TZPC1              304
>> -#define CLK_TZPC2              305
>> -#define CLK_TZPC3              306
>> -#define CLK_TZPC4              307
>> -#define CLK_TZPC5              308
>> -#define CLK_TZPC6              309
>> -#define CLK_TZPC7              310
>> -#define CLK_TZPC8              311
>> -#define CLK_TZPC9              312
>> +#define CLK_PCLK_CHIPID                301
>> +#define CLK_PCLK_SYSREG                302
>> +#define CLK_PCLK_TZPC0         303
>> +#define CLK_PCLK_TZPC1         304
>> +#define CLK_PCLK_TZPC2         305
>> +#define CLK_PCLK_TZPC3         306
>> +#define CLK_PCLK_TZPC4         307
>> +#define CLK_PCLK_TZPC5         308
>> +#define CLK_PCLK_TZPC6         309
>> +#define CLK_PCLK_TZPC7         310
>> +#define CLK_PCLK_TZPC8         311
>> +#define CLK_PCLK_TZPC9         312
>>   #define CLK_HDMI_CEC          313
>>   #define CLK_SECKEY            314
>> -#define CLK_MCT                        315
>> -#define CLK_WDT                        316
>> -#define CLK_RTC                        317
>> -#define CLK_TMU                        318
>> -#define CLK_TMU_GPU            319
>> +#define CLK_PCLK_MCT           315
>> +#define CLK_PCLK_WDT           316
>> +#define CLK_PCLK_RTC           317
>> +#define CLK_PCLK_TMU           318
>> +#define CLK_PCLK_TMU_GPU       319
>>   #define CLK_PCLK66_GPIO               330
>>   #define CLK_ACLK200_FSYS2     350
>> -#define CLK_MMC0               351
>> -#define CLK_MMC1               352
>> -#define CLK_MMC2               353
>> -#define CLK_SROMC              354
>> +#define CLK_ACLK_MMC0          351
>> +#define CLK_ACLK_MMC1          352
>> +#define CLK_ACLK_MMC2          353
>> +#define CLK_HCLK_SROMC         354
>>   #define CLK_UFS                       355
>>   #define CLK_ACLK200_FSYS      360
>>   #define CLK_TSI                       361
>> -#define CLK_PDMA0              362
>> -#define CLK_PDMA1              363
>> -#define CLK_RTIC               364
>> -#define CLK_USBH20             365
>> -#define CLK_USBD300            366
>> -#define CLK_USBD301            367
>> +#define CLK_ACLK_PDMA0         362
>> +#define CLK_ACLK_PDMA1         363
>> +#define CLK_ACLK_RTIC          364
>> +#define CLK_HCLK_USBH20                365
>> +#define CLK_HCLK_USBD300       366
>> +#define CLK_HCLK_USBD301       367
>>   #define CLK_PCLK200_FSYS      370
>>   #define CLK_ACLK400_MSCL      380
>> -#define CLK_MSCL0              381
>> -#define CLK_MSCL1              382
>> -#define CLK_MSCL2              383
>> +#define CLK_ACLK_MSCL0         381
>> +#define CLK_ACLK_MSCL1         382
>> +#define CLK_ACLK_MSCL2         383
>>   #define CLK_SMMU_MSCL0                384
>>   #define CLK_SMMU_MSCL1                385
>>   #define CLK_SMMU_MSCL2                386
>>   #define CLK_ACLK333           400
>> -#define CLK_MFC                        401
>> +#define CLK_ACLK_MFC           401
>>   #define CLK_SMMU_MFCL         402
>>   #define CLK_SMMU_MFCR         403
>>   #define CLK_ACLK200_DISP1     410
>> -#define CLK_DSIM1              411
>> -#define CLK_DP1                        412
>> -#define CLK_HDMI               413
>> +#define CLK_PCLK_DSIM1         411
>> +#define CLK_PCLK_DP1           412
>> +#define CLK_PCLK_HDMI          413
>>   #define CLK_ACLK300_DISP1     420
>> -#define CLK_FIMD1              421
>> -#define CLK_SMMU_FIMD1         422
>> +#define CLK_ACLK_FIMD1         421
>> +#define CLK_SMMU_FIMD1M0       422
>>   #define CLK_SMMU_FIMD1M1      423
>>   #define CLK_ACLK400_DISP1     424
>>   #define CLK_ACLK166           430
>> -#define CLK_MIXER              431
>> +#define CLK_ACLK_MIXER         431
>>   #define CLK_ACLK266           440
>> -#define CLK_ROTATOR            441
>> -#define CLK_MDMA1              442
>> +#define CLK_ACLK_ROTATOR       441
>> +#define CLK_ACLK_MDMA1         442
>>   #define CLK_SMMU_ROTATOR      443
>>   #define CLK_SMMU_MDMA1                444
>>   #define CLK_ACLK300_JPEG      450
>> -#define CLK_JPEG               451
>> -#define CLK_JPEG2              452
>> +#define CLK_ACLK_JPEG          451
>> +#define CLK_ACLK_JPEG2         452
>>   #define CLK_SMMU_JPEG         453
>>   #define CLK_ACLK300_GSCL      460
>>   #define CLK_SMMU_GSCL0                461
>>   #define CLK_SMMU_GSCL1                462
>> -#define CLK_GSCL_WA            463
>> +#define CLK_PCLK_GSCL_WA       463
>>   #define CLK_GSCL_WB           464
>> -#define CLK_GSCL0              465
>> -#define CLK_GSCL1              466
>> -#define CLK_CLK_3AA            467
>> +#define CLK_ACLK_GSCL0         465
>> +#define CLK_ACLK_GSCL1         466
>> +#define CLK_ACLK_FIMC_3AA      467
>>   #define CLK_ACLK266_G2D               470
>> -#define CLK_SSS                        471
>> -#define CLK_SLIM_SSS           472
>> -#define CLK_MDMA0              473
>> +#define CLK_ACLK_SSS           471
>> +#define CLK_ACLK_SLIM_SSS      472
>> +#define CLK_ACLK_MDMA0         473
>>   #define CLK_ACLK333_G2D               480
>> -#define CLK_G2D                        481
>> +#define CLK_ACLK_G2D           481
>>   #define CLK_ACLK333_432_GSCL  490
>>   #define CLK_SMMU_3AA          491
>>   #define CLK_SMMU_FIMCL0               492
>>   #define CLK_SMMU_FIMCL1               493
>>   #define CLK_SMMU_FIMCL3               494
>> -#define CLK_FIMC_LITE3         495
>> +#define CLK_ACLK_FIMC_LITE3    495
>>   #define CLK_G3D                       500
>>   #define CLK_SMMU_MIXER                502
>>   #define CLK_PCLK_TZPC10               503
>>
>
> As Gerhard already mentioned, this will break bisection of existing users of
> old macros, so this is a bad idea to change them this way.
>
> Anyway, most of those renames are mostly adding *CLK_ prefixes, so I really
> wonder if this is necessary, especially considering the GATE_BUS_* issue I
> mentioned above and that clock names (and parent names in all their
> children) would have to be updated as well. What do you think?
>
> Best regards,
> Tomasz

[PATCH v2 4/7] clk: exynos5420: Rename clock names

[Shaik Ameer Basha]

From: Rahul Sharma <rahul.sharma@samsung.com>

Maintain the mout_, dout_, sclk_ prefix to the clock names
wherever applicable.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c   |  750 ++++++++++++++++++--------------
 include/dt-bindings/clock/exynos5420.h |   14 +-
 2 files changed, 419 insertions(+), 345 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 1402554..793fb3d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -244,85 +244,92 @@ static void exynos5420_clk_sleep_init(void) {}
 #endif
 
 /* list of all parent clocks */
-PNAME(mspll_cpu_p)	= { "sclk_cpll", "sclk_dpll",
-				"sclk_mpll", "sclk_spll" };
-PNAME(cpu_p)		= { "mout_apll" , "mout_mspll_cpu" };
-PNAME(kfc_p)		= { "mout_kpll" , "mout_mspll_kfc" };
-PNAME(apll_p)		= { "fin_pll", "fout_apll", };
-PNAME(bpll_p)		= { "fin_pll", "fout_bpll", };
-PNAME(cpll_p)		= { "fin_pll", "fout_cpll", };
-PNAME(dpll_p)		= { "fin_pll", "fout_dpll", };
-PNAME(epll_p)		= { "fin_pll", "fout_epll", };
-PNAME(ipll_p)		= { "fin_pll", "fout_ipll", };
-PNAME(kpll_p)		= { "fin_pll", "fout_kpll", };
-PNAME(mpll_p)		= { "fin_pll", "fout_mpll", };
-PNAME(rpll_p)		= { "fin_pll", "fout_rpll", };
-PNAME(spll_p)		= { "fin_pll", "fout_spll", };
-PNAME(vpll_p)		= { "fin_pll", "fout_vpll", };
-
-PNAME(group1_p)		= { "sclk_cpll", "sclk_dpll", "sclk_mpll" };
-PNAME(group2_p)		= { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
-			  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(group3_p)		= { "sclk_rpll", "sclk_spll" };
-PNAME(group4_p)		= { "sclk_ipll", "sclk_dpll", "sclk_mpll" };
-PNAME(group5_p)		= { "sclk_vpll", "sclk_dpll" };
-
-PNAME(sw_aclk66_p)	= { "dout_aclk66", "sclk_spll" };
-PNAME(aclk66_peric_p)	= { "fin_pll", "mout_sw_aclk66" };
-
-PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"};
-PNAME(user_aclk200_fsys_p)	= { "fin_pll", "mout_sw_aclk200_fsys" };
-
-PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"};
-PNAME(user_aclk200_fsys2_p)	= { "fin_pll", "mout_sw_aclk200_fsys2" };
-
-PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"};
-PNAME(aclk200_disp1_p)	= { "fin_pll", "mout_sw_aclk200" };
-
-PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"};
-PNAME(user_aclk400_mscl_p)	= { "fin_pll", "mout_sw_aclk400_mscl" };
-
-PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"};
-PNAME(user_aclk333_p)	= { "fin_pll", "mout_sw_aclk333" };
-
-PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"};
-PNAME(user_aclk166_p)	= { "fin_pll", "mout_sw_aclk166" };
-
-PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"};
-PNAME(user_aclk266_p)	= { "fin_pll", "mout_sw_aclk266" };
-
-PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"};
-PNAME(user_aclk333_432_gscl_p)	= { "fin_pll", "mout_sw_aclk333_432_gscl" };
-
-PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"};
-PNAME(user_aclk300_gscl_p)	= { "fin_pll", "mout_sw_aclk300_gscl" };
-
-PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"};
-PNAME(user_aclk300_disp1_p)	= { "fin_pll", "mout_sw_aclk300_disp1" };
-
-PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"};
-PNAME(user_aclk300_jpeg_p)	= { "fin_pll", "mout_sw_aclk300_jpeg" };
-
-PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"};
-PNAME(user_aclk_g3d_p)	= { "fin_pll", "mout_sw_aclk_g3d" };
-
-PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"};
-PNAME(user_aclk266_g2d_p)	= { "fin_pll", "mout_sw_aclk266_g2d" };
-
-PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"};
-PNAME(user_aclk333_g2d_p)	= { "fin_pll", "mout_sw_aclk333_g2d" };
-
-PNAME(audio0_p)	= { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll",
-		  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(audio1_p)	= { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll",
-		  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(audio2_p)	= { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
-		  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(spdif_p)	= { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
-		  "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(hdmi_p)	= { "dout_hdmi_pixel", "sclk_hdmiphy" };
-PNAME(maudio0_p)	= { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
-			  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
+PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
+				"mout_sclk_mpll", "mout_sclk_spll"};
+PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
+PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
+PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
+PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
+PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
+PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
+PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
+PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
+PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
+PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
+PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
+PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
+PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
+
+PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
+					"mout_sclk_mpll"};
+PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
+			"mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
+			"mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
+PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
+PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
+
+PNAME(mout_sw_aclk66_p)	= {"dout_aclk66", "mout_sclk_spll"};
+PNAME(mout_user_aclk66_peric_p) = {"fin_pll", "mout_sw_aclk66"};
+
+PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
+PNAME(mout_user_aclk200_fsys_p)	= {"fin_pll", "mout_sw_aclk200_fsys"};
+
+PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
+PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
+
+PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
+PNAME(mout_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
+
+PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
+PNAME(mout_user_aclk400_mscl_p)	= {"fin_pll", "mout_sw_aclk400_mscl"};
+
+PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
+
+PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
+PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
+
+PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
+PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
+
+PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
+
+PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
+PNAME(mout_user_aclk300_gscl_p)	= {"fin_pll", "mout_sw_aclk300_gscl"};
+
+PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
+PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
+
+PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
+PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
+
+PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
+PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
+
+PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
+PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
+
+PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
+
+PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
+			"mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+			"mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
+			"mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+			"mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
+			"mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+			"mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
+			"dout_audio2", "spdif_extclk", "mout_sclk_ipll",
+			"mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
+PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
+			 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+			 "mout_sclk_epll", "mout_sclk_rpll"};
 
 /* fixed rate clocks generated outside the soc */
 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
@@ -339,134 +346,145 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata =
 };
 
 static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
-	FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
+	FFACTOR(0, "ffactor_hsic_12m", "fin_pll", 1, 2, 0),
 };
 
 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
-	MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
-	MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
-	MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
-	MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
-	MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
-	MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
+	MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
+	MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
+	MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+	MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
+	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
 
-	MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
+	MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
 
-	MUX_A(0, "mout_aclk400_mscl", group1_p,
+	MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
 			SRC_TOP0, 4, 2, "aclk400_mscl"),
-	MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
-	MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
-	MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
-
-	MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
-	MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
-	MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
-	MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
-	MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
-
-	MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
-	MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
-	MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
-	MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
-	MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
-	MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
-
-	MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
+	MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
+	MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
+	MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
+
+	MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
+	MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
+	MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
+	MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
+	MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
+
+	MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
+	MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
+	MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
+	MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
+	MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
+	MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
+
+	MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
 			SRC_TOP3, 4, 1),
-	MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p,
-			SRC_TOP3, 8, 1, "aclk200_disp1"),
-	MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
+	MUX(0, "mout_aclk200_disp1", mout_aclk200_disp1_p, SRC_TOP3, 8, 1),
+	MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
 			SRC_TOP3, 12, 1),
-	MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
+	MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
 			SRC_TOP3, 28, 1),
 
-	MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
-			SRC_TOP4, 0, 1),
-	MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
-	MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
-	MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
-	MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
-
-	MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
-	MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
-	MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
-	MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p,
-			SRC_TOP5, 16, 1, "aclkg3d"),
-	MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
+	MUX(CLK_MOUT_USER_ACLK333_432_GSCL, "mout_user_aclk333_432_gscl",
+			mout_user_aclk333_432_gscl_p, SRC_TOP4, 0, 1),
+	MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
+			SRC_TOP4, 8, 1),
+	MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
+	MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
+	MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
+			SRC_TOP4, 28, 1),
+
+	MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, SRC_TOP5,
+			4, 1),
+	MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, SRC_TOP5,
+			8, 1),
+	MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, SRC_TOP5,
+			12, 1),
+	MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
+			SRC_TOP5, 16, 1),
+	MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
 			SRC_TOP5, 20, 1),
-	MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
+	MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
 			SRC_TOP5, 24, 1),
-	MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
-			SRC_TOP5, 28, 1),
-
-	MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
-	MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
-	MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
-	MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
-	MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
-	MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
-	MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
-	MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
-
-	MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
-	MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
-	MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
+	MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
+			mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
+
+	MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
+	MUX(0, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
+	MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
+	MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
+	MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
+	MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
+	MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
+	MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
+
+	MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
+			SRC_TOP10, 4, 1),
+	MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
+	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
 			SRC_TOP10, 12, 1),
-	MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
-
-	MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
-			SRC_TOP11, 0, 1),
-	MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
-	MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
-	MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
-	MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
-
-	MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
-	MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
-	MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
-	MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
-	MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
+	MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
+			SRC_TOP10, 28, 1),
+	MUX(CLK_MOUT_SW_ACLK333_432_GSCL, "mout_sw_aclk333_432_gscl",
+			mout_sw_aclk333_432_gscl_p, SRC_TOP11, 0, 1),
+	MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
+	MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
+	MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
+	MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
+			SRC_TOP11, 28, 1),
+
+	MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
+			SRC_TOP12, 8, 1),
+	MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
+			SRC_TOP12, 12, 1),
+	MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
+	MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
+			SRC_TOP12, 20, 1),
+	MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
 			SRC_TOP12, 24, 1),
-	MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
+	MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
+			mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
 
 	/* DISP1 Block */
-	MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
-	MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
-	MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
-	MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
-	MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
+	MUX(CLK_MOUT_FIMD1, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
+	MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
+	MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
+	MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
+	MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
 
 	/* MAU Block */
-	MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
+	MUX_F(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3,
+						CLK_SET_RATE_PARENT, 0),
 
 	/* FSYS Block */
-	MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
-	MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
-	MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
-	MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
-	MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
-	MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
+	MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
+	MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
+	MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
+	MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
+	MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
+	MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
 
 	/* PERIC Block */
-	MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
-	MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
-	MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
-	MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
-	MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
-	MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
-	MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
-	MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
-	MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
-	MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
-	MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
-	MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
+	MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
+	MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
+	MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
+	MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
+	MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
+	MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
+	MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
+	MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
+	MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
+	MUX(CLK_MOUT_SPI0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
+	MUX(CLK_MOUT_SPI1, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
+	MUX(CLK_MOUT_SPI2, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
 };
 
 static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
-	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+	DIV(0, "dout_armclk1", "mout_cpu", DIV_CPU0, 0, 3),
 	DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
-	DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
-	DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
+	DIV(0, "dout_armclk2", "dout_armclk1", DIV_CPU0, 28, 3),
+	DIV(0, "dout_kfc", "mout_kfc", DIV_KFC0, 0, 3),
 	DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
 
 	DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
@@ -486,12 +504,11 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 	DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
 	DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
 	DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
-	DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1",
-			DIV_TOP2, 24, 3, "aclk300_disp1"),
+	DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
 	DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
 
 	/* DISP1 Block */
-	DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
+	DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
 	DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
 	DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
 	DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
@@ -537,41 +554,41 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 	DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
 
 	/* SPI Pre-Ratio */
-	DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
-	DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
-	DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
+	DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
+	DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
+	DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
 };
 
 static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
-	/* TODO: Re-verify the CG bits for all the gate clocks */
-	GATE_A(CLK_PCLK_MCT, "pclk_st", "aclk66_psgen",
-			GATE_BUS_PERIS1, 2, 0, 0, "mct"),
-
-	GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
-			GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
-			GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
-
-	GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
-			GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
-			GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
-			GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
-			GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
-			GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "pclk66_gpio", "mout_sw_aclk66",
-			GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "aclk66_psgen", "mout_aclk66_psgen",
-			GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "aclk66_peric", "mout_aclk66_peric",
-			GATE_BUS_TOP, 11, 0, 0),
-	GATE(0, "aclk166", "mout_user_aclk166",
-			GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "aclk333", "mout_aclk333",
-			GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_MCT, "pclk_mct", "aclk66_psgen",
+		GATE_BUS_PERIS1, 2, 0, 0),
+
+	GATE(CLK_ACLK200_FSYS, "aclk200_fsys", "mout_user_aclk200_fsys",
+		GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK200_FSYS2, "aclk200_fsys2", "mout_user_aclk200_fsys2",
+		GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_ACLK333_G2D, "aclk333_g2d", "mout_user_aclk333_g2d",
+		GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK266_G2D, "aclk266_g2d", "mout_user_aclk266_g2d",
+		GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK300_JPEG, "aclk300_jpeg", "mout_user_aclk300_jpeg",
+		GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK300_GSCL, "aclk300_gscl", "mout_user_aclk300_gscl",
+		GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK333_432_GSCL, "aclk333_432_gscl",
+		"mout_user_aclk333_432_gscl",
+		GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_aclk66_gpio",
+		GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK66_PSGEN, "aclk66_psgen", "mout_user_aclk66_psgen",
+		GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK66_PERIC, "aclk66_peric", "mout_user_aclk66_peric",
+		GATE_BUS_TOP, 11, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK166, "aclk166", "mout_user_aclk166",
+		GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
+		GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
 
 	/* sclk */
 	GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
@@ -582,11 +599,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 		GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
 		GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
-	GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0",
+	GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
 		GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
-	GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1",
+	GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
 		GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
-	GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2",
+	GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
 		GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
 		GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
@@ -612,16 +629,16 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 	GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
 		GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
-		GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+		GATE_TOP_SCLK_FSYS, 9, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
-		GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
+		GATE_TOP_SCLK_FSYS, 10, CLK_IGNORE_UNUSED, 0),
 
-	GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
-		SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
+		GATE_IP_FSYS, 23, CLK_SET_RATE_PARENT, 0),
 
-	GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl",
+	GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
 		GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
-	GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl",
+	GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
 		GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
 
 	/* Display */
@@ -643,142 +660,199 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 		GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
 	/* FSYS */
 	GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
-	GATE(CLK_ACLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
-	GATE(CLK_ACLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
+	GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "aclk200_fsys",
+			GATE_BUS_FSYS0, 1, 0, 0),
+	GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "aclk200_fsys",
+			GATE_BUS_FSYS0, 2, 0, 0),
 	GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
-	GATE(CLK_ACLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
-	GATE(CLK_ACLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
-	GATE(CLK_ACLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
-	GATE(CLK_ACLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
-	GATE(CLK_HCLK_SROMC, "sromc", "aclk200_fsys2",
-			GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
-	GATE(CLK_HCLK_USBH20, "usbh20", "aclk200_fsys",
-			GATE_BUS_FSYS0, 20, 0, 0),
-	GATE(CLK_HCLK_USBD300, "usbd300", "aclk200_fsys",
+	GATE(CLK_ACLK_RTIC, "aclk_rtic", "aclk200_fsys2",
+			GATE_IP_FSYS, 9, 0, 0),
+	GATE(CLK_ACLK_MMC0, "aclk_mmc0", "aclk200_fsys2",
+			GATE_BUS_FSYS0, 12, 0, 0),
+	GATE(CLK_ACLK_MMC1, "aclk_mmc1", "aclk200_fsys2",
+			GATE_BUS_FSYS0, 13, 0, 0),
+	GATE(CLK_ACLK_MMC2, "aclk_mmc2", "aclk200_fsys2",
+			GATE_BUS_FSYS0, 14, 0, 0),
+	GATE(CLK_HCLK_SROMC, "hclk_sromc", "aclk200_fsys2",
+			GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_HCLK_USBH20, "hclk_usbh20", "aclk200_fsys",
+			GATE_IP_FSYS, 18, 0, 0),
+	GATE(CLK_HCLK_USBD300, "hclk_usbd300", "aclk200_fsys",
 			GATE_BUS_FSYS0, 21, 0, 0),
-	GATE(CLK_HCLK_USBD301, "usbd301", "aclk200_fsys",
+	GATE(CLK_HCLK_USBD301, "hclk_usbd301", "aclk200_fsys",
 			GATE_BUS_FSYS0, 28, 0, 0),
 
 	/* UART */
-	GATE(CLK_PCLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
-	GATE(CLK_PCLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
-	GATE_A(CLK_PCLK_UART2, "uart2", "aclk66_peric",
-		GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
-	GATE(CLK_PCLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
+	GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk66_peric",
+			GATE_BUS_PERIC, 4, 0, 0),
+	GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk66_peric",
+			GATE_BUS_PERIC, 5, 0, 0),
+	GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk66_peric",
+			GATE_BUS_PERIC, 6, 0, 0),
+	GATE(CLK_PCLK_UART3, "pclk_uart3", "aclk66_peric",
+			GATE_BUS_PERIC, 7, 0, 0),
 	/* I2C */
-	GATE(CLK_PCLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
-	GATE(CLK_PCLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
-	GATE(CLK_PCLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
-	GATE(CLK_PCLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
-	GATE(CLK_PCLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric",
+	GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk66_peric",
+			GATE_IP_PERIC, 6, 0, 0),
+	GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk66_peric",
+			GATE_IP_PERIC, 7, 0, 0),
+	GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk66_peric",
+			GATE_IP_PERIC, 8, 0, 0),
+	GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk66_peric",
+			GATE_IP_PERIC, 9, 0, 0),
+	GATE(CLK_PCLK_USI0, "pclk_usi0", "aclk66_peric",
+			GATE_IP_PERIC, 10, 0, 0),
+	GATE(CLK_PCLK_USI1, "pclk_usi1", "aclk66_peric",
+			GATE_IP_PERIC, 11, 0, 0),
+	GATE(CLK_PCLK_USI2, "pclk_usi2", "aclk66_peric",
+			GATE_IP_PERIC, 12, 0, 0),
+	GATE(CLK_PCLK_USI3, "pclk_usi3", "aclk66_peric",
+			GATE_IP_PERIC, 13, 0, 0),
+	GATE(CLK_PCLK_USI4, "pclk_usi4", "aclk66_peric",
+			GATE_IP_PERIC, 28, 0, 0),
+	GATE(CLK_PCLK_USI5, "pclk_usi5", "aclk66_peric",
+			GATE_IP_PERIC, 30, 0, 0),
+	GATE(CLK_PCLK_USI6, "pclk_usi6", "aclk66_peric",
+			GATE_IP_PERIC, 31, 0, 0),
+
+	GATE(CLK_PCLK_I2C_HDMI, "pclk_i2c_hdmi", "aclk66_peric",
 			GATE_BUS_PERIC, 17, 0, 0),
-	GATE(CLK_PCLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
+	GATE(CLK_PCLK_TSADC, "pclk_tsadc", "aclk66_peric",
+			GATE_IP_PERIC, 15, 0, 0),
 	/* SPI */
-	GATE(CLK_PCLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
-	GATE(CLK_PCLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
-	GATE(CLK_PCLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
+	GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk66_peric",
+			GATE_BUS_PERIC, 19, 0, 0),
+	GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk66_peric",
+			GATE_BUS_PERIC, 20, 0, 0),
+	GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk66_peric",
+			GATE_BUS_PERIC, 21, 0, 0),
 	GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
 	/* I2S */
-	GATE(CLK_PCLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
-	GATE(CLK_PCLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
+	GATE(CLK_PCLK_I2S1, "pclk_i2s1", "aclk66_peric",
+			GATE_BUS_PERIC, 23, 0, 0),
+	GATE(CLK_PCLK_I2S2, "pclk_i2s2", "aclk66_peric",
+			GATE_BUS_PERIC, 24, 0, 0),
 	/* PCM */
-	GATE(CLK_PCLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
-	GATE(CLK_PCLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
+	GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk66_peric",
+			GATE_BUS_PERIC, 25, 0, 0),
+	GATE(CLK_PCLK_PCM2, "pclk_pcm2", "aclk66_peric",
+			GATE_BUS_PERIC, 26, 0, 0),
 	/* PWM */
 	GATE(CLK_PCLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
 	/* SPDIF */
-	GATE(CLK_PCLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
-
-	GATE(CLK_PCLK_CHIPID, "chipid", "aclk66_psgen",
-			GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
-	GATE(CLK_PCLK_SYSREG, "sysreg", "aclk66_psgen",
-			GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
-	GATE(CLK_PCLK_TZPC0, "tzpc0", "aclk66_psgen",
-			GATE_BUS_PERIS0, 18, 0, 0),
-	GATE(CLK_PCLK_TZPC1, "tzpc1", "aclk66_psgen",
-			GATE_BUS_PERIS0, 19, 0, 0),
-	GATE(CLK_PCLK_TZPC2, "tzpc2", "aclk66_psgen",
-			GATE_BUS_PERIS0, 20, 0, 0),
-	GATE(CLK_PCLK_TZPC3, "tzpc3", "aclk66_psgen",
-			GATE_BUS_PERIS0, 21, 0, 0),
-	GATE(CLK_PCLK_TZPC4, "tzpc4", "aclk66_psgen",
-			GATE_BUS_PERIS0, 22, 0, 0),
-	GATE(CLK_PCLK_TZPC5, "tzpc5", "aclk66_psgen",
-			GATE_BUS_PERIS0, 23, 0, 0),
-	GATE(CLK_PCLK_TZPC6, "tzpc6", "aclk66_psgen",
-			GATE_BUS_PERIS0, 24, 0, 0),
-	GATE(CLK_PCLK_TZPC7, "tzpc7", "aclk66_psgen",
-			GATE_BUS_PERIS0, 25, 0, 0),
-	GATE(CLK_PCLK_TZPC8, "tzpc8", "aclk66_psgen",
-			GATE_BUS_PERIS0, 26, 0, 0),
-	GATE(CLK_PCLK_TZPC9, "tzpc9", "aclk66_psgen",
-			GATE_BUS_PERIS0, 27, 0, 0),
-
-	GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0,
-		0),
+	GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk66_peric",
+			GATE_BUS_PERIC, 29, 0, 0),
+
+	GATE(CLK_PCLK_CHIPID, "pclk_chipid", "aclk66_psgen",
+			GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_SYSREG, "pclk_sysreg", "aclk66_psgen",
+			GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk66_psgen",
+			GATE_IP_PERIS, 6, 0, 0),
+	GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk66_psgen",
+			GATE_IP_PERIS, 7, 0, 0),
+	GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk66_psgen",
+			GATE_IP_PERIS, 8, 0, 0),
+	GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk66_psgen",
+			GATE_IP_PERIS, 9, 0, 0),
+	GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk66_psgen",
+			GATE_IP_PERIS, 10, 0, 0),
+	GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk66_psgen",
+			GATE_IP_PERIS, 11, 0, 0),
+	GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk66_psgen",
+			GATE_IP_PERIS, 12, 0, 0),
+	GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk66_psgen",
+			GATE_IP_PERIS, 13, 0, 0),
+	GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk66_psgen",
+			GATE_IP_PERIS, 14, 0, 0),
+	GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk66_psgen",
+			GATE_IP_PERIS, 15, 0, 0),
+	GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk66_psgen",
+			GATE_BUS_GEN, 30, 0, 0),
+	GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk66_psgen",
+			GATE_BUS_GEN, 31, 0, 0),
+
+	GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen",
+			GATE_BUS_PERIS1, 0, 0, 0),
 	GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
-	GATE(CLK_PCLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
-	GATE(CLK_PCLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
-	GATE(CLK_PCLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
-	GATE(CLK_PCLK_TMU_GPU, "tmu_gpu", "aclk66_psgen",
-			GATE_BUS_PERIS1, 6, 0, 0),
-
-	GATE(CLK_ACLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
-	GATE(CLK_ACLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
-	GATE(CLK_ACLK_FIMC_3AA, "clk_3aa", "aclk300_gscl",
+	GATE(CLK_PCLK_WDT, "pclk_wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
+	GATE(CLK_PCLK_RTC, "pclk_rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
+	GATE(CLK_PCLK_TMU, "pclk_tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
+	GATE(CLK_PCLK_TMU_GPU, "pclk_tmu_gpu", "aclk66_psgen",
+			GATE_IP_PERIS, 22, 0, 0),
+
+	GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_user_aclk300_gscl",
+			GATE_IP_GSCL0, 0, 0, 0),
+	GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_user_aclk300_gscl",
+			GATE_IP_GSCL0, 1, 0, 0),
+	GATE(CLK_ACLK_FIMC_3AA, "aclk_fimc_3aa", "aclk333_432_gscl",
 			GATE_IP_GSCL0, 4, 0, 0),
 
-	GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0,
-		0),
-	GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl",
+	GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
+			GATE_IP_GSCL1, 2, 0, 0),
+	GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
 			GATE_IP_GSCL1, 3, 0, 0),
-	GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl",
+	GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
 			GATE_IP_GSCL1, 4, 0, 0),
-	GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0,
-		0),
-	GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0,
-		0),
-	GATE(CLK_PCLK_GSCL_WA, "gscl_wa", "aclk300_gscl",
-			GATE_IP_GSCL1, 12, 0, 0),
+	GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
+			GATE_IP_GSCL1, 6, 0, 0),
+	GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
+			GATE_IP_GSCL1, 7, 0, 0),
+	GATE(CLK_PCLK_GSCL_WA, "pclk_gscl_wa", "dout_gscl_blk_333",
+			GATE_BUS_GSCL1, 28, 0, 0),
 	GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
-	GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl",
+	GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
 			GATE_IP_GSCL1, 16, 0, 0),
-	GATE(CLK_ACLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
+	GATE(CLK_ACLK_FIMC_LITE3, "aclk_fimc_lite3", "aclk333_432_gscl",
 			GATE_IP_GSCL1, 17, 0, 0),
 
-	GATE(CLK_ACLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
-	GATE(CLK_PCLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
-	GATE(CLK_PCLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
-	GATE(CLK_ACLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
-	GATE(CLK_PCLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
-	GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1", "aclk300_disp1",
-			GATE_IP_DISP1, 8, 0, 0),
-
-	GATE(CLK_ACLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
-	GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
-	GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
-
-	GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
-
-	GATE(CLK_ACLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
-	GATE(CLK_ACLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
-	GATE(CLK_ACLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
-	GATE(CLK_ACLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
-	GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
-	GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
-	GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
-
-	GATE(CLK_ACLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
-	GATE(CLK_ACLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
-	GATE(CLK_ACLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
-	GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
-		0),
-	GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
-		0),
-	GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0,
-		0),
-	GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
-		0),
+	GATE(CLK_ACLK_FIMD1, "aclk_fimd1", "mout_user_aclk300_disp1",
+			GATE_IP_DISP1, 0, 0, 0),
+	GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "dout_disp1_blk",
+			GATE_BUS_DISP1, 17, 0, 0),
+	GATE(CLK_PCLK_DP1, "pclk_dp1", "dout_disp1_blk",
+			GATE_BUS_DISP1, 18, 0, 0),
+	GATE(CLK_ACLK_MIXER, "aclk_mixer", "aclk200_disp1",
+			GATE_IP_DISP1, 5, 0, 0),
+	GATE(CLK_PCLK_HDMI, "pclk_hdmi", "dout_disp1_blk",
+			GATE_BUS_DISP1, 19, 0, 0),
+	GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
+			GATE_IP_DISP1, 7, 0, 0),
+
+	GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_user_aclk333",
+			GATE_BUS_MFC, 0, 0, 0),
+	GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
+	GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
+	GATE(CLK_G3D, "clk_g3d", "mout_user_aclk_g3d",
+			GATE_IP_G3D, 9, 0, 0),
+
+	GATE(CLK_ACLK_ROTATOR, "aclk_rotator", "mout_user_aclk266",
+			GATE_IP_GEN, 1, 0, 0),
+	GATE(CLK_ACLK_JPEG, "aclk_jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
+	GATE(CLK_ACLK_JPEG2, "aclk_jpeg2", "aclk300_jpeg",
+			GATE_IP_GEN, 3, 0, 0),
+	GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_user_aclk266",
+			GATE_IP_GEN, 4, 0, 0),
+	GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
+			GATE_IP_GEN, 6, 0, 0),
+	GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
+	GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
+			GATE_IP_GEN, 9, 0, 0),
+
+	GATE(CLK_ACLK_MSCL0, "aclk_mscl0", "aclk400_mscl",
+			GATE_BUS_MSCL, 0, 0, 0),
+	GATE(CLK_ACLK_MSCL1, "aclk_mscl1", "aclk400_mscl",
+			GATE_BUS_MSCL, 1, 0, 0),
+	GATE(CLK_ACLK_MSCL2, "aclk_mscl2", "aclk400_mscl",
+			GATE_BUS_MSCL, 2, 0, 0),
+	GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
+			GATE_IP_MSCL, 8, 0, 0),
+	GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
+			GATE_IP_MSCL, 9, 0, 0),
+	GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
+			GATE_IP_MSCL, 10, 0, 0),
+	GATE(CLK_SMMU_MIXER, "smmu_mixer", "dout_disp1_blk",
+			GATE_IP_DISP1, 9, 0, 0),
 
 	/* SSS */
 	GATE(CLK_ACLK_SSS, "aclk_sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 598eb48..dde01fc 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -79,10 +79,10 @@
 #define CLK_PCLK_I2C1		262
 #define CLK_PCLK_I2C2		263
 #define CLK_PCLK_I2C3		264
-#define CLK_I2C4		265
-#define CLK_I2C5		266
-#define CLK_I2C6		267
-#define CLK_I2C7		268
+#define CLK_PCLK_USI0		265
+#define CLK_PCLK_USI1		266
+#define CLK_PCLK_USI2		267
+#define CLK_PCLK_USI3		268
 #define CLK_PCLK_I2C_HDMI	269
 #define CLK_PCLK_TSADC		270
 #define CLK_PCLK_SPI0		271
@@ -95,9 +95,9 @@
 #define CLK_PCLK_PCM2		278
 #define CLK_PCLK_PWM		279
 #define CLK_PCLK_SPDIF		280
-#define CLK_I2C8		281
-#define CLK_I2C9		282
-#define CLK_I2C10		283
+#define CLK_PCLK_USI4		281
+#define CLK_PCLK_USI5		282
+#define CLK_PCLK_USI6		283
 #define CLK_ACLK66_PSGEN	300
 #define CLK_PCLK_CHIPID		301
 #define CLK_PCLK_SYSREG		302
-- 
1.7.9.5

Re: [PATCH v2 4/7] clk: exynos5420: Rename clock names

[Tomasz Figa]

Hi Shaik,

On 27.03.2014 12:07, Shaik Ameer Basha wrote:
> From: Rahul Sharma <rahul.sharma@samsung.com>
>
> Maintain the mout_, dout_, sclk_ prefix to the clock names
> wherever applicable.

Looking at the patch, it does seem to do more than that. Considering my 
comments to patch 3/7, I would drop the renames simply adding *CLK_ 
prefix (except SCLK_, which is fine as it specifies clock type, just as 
MOUT_/DOUT_/etc.).

Best regards,
Tomasz

[PATCH v2 5/7] clk: exynos5420: Add missing clocks

[Shaik Ameer Basha]

From: Rahul Sharma <rahul.sharma@samsung.com>

This patch adds the missing clocks related to the modules
like FIMD, DP, GSCL, MSCL, ISP, MFC etc.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c |  221 +++++++++++++++++++++++++++++++++-
 1 file changed, 219 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 793fb3d..26ddf33 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -269,15 +269,36 @@ PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
 
+PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
 PNAME(mout_sw_aclk66_p)	= {"dout_aclk66", "mout_sclk_spll"};
 PNAME(mout_user_aclk66_peric_p) = {"fin_pll", "mout_sw_aclk66"};
+PNAME(mout_user_aclk66_gpio_p) = {"mout_sw_aclk66", "ffactor_sw_aclk66"};
 
 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
+PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
+PNAME(mout_user_pclk200_fsys_p)	= {"fin_pll", "mout_sw_pclk200_fsys"};
 PNAME(mout_user_aclk200_fsys_p)	= {"fin_pll", "mout_sw_aclk200_fsys"};
 
 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
 
+PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
+PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
+
+PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
+PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
+PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
+
+PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
+PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
+
+PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
+					"mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
+
+PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
+
 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
 PNAME(mout_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
 
@@ -292,6 +313,7 @@ PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
 
 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
+PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
 
 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
@@ -300,7 +322,9 @@ PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
 PNAME(mout_user_aclk300_gscl_p)	= {"fin_pll", "mout_sw_aclk300_gscl"};
 
 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
+PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
+PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
 
 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
@@ -330,6 +354,8 @@ PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
 			 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 			 "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
+				"mout_sclk_mpll", "mout_sclk_spll"};
 
 /* fixed rate clocks generated outside the soc */
 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
@@ -347,6 +373,7 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata =
 
 static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
 	FFACTOR(0, "ffactor_hsic_12m", "fin_pll", 1, 2, 0),
+	FFACTOR(0, "ffactor_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
 };
 
 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
@@ -452,6 +479,10 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 	MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
 	MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
 	MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
+	MUX_F(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3,
+						CLK_SET_RATE_PARENT, 0),
+	MUX_F(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1,
+						CLK_SET_RATE_PARENT, 0),
 
 	/* MAU Block */
 	MUX_F(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3,
@@ -464,6 +495,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 	MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
 	MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
 	MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
+	MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
 
 	/* PERIC Block */
 	MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
@@ -478,6 +510,58 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 	MUX(CLK_MOUT_SPI0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
 	MUX(CLK_MOUT_SPI1, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
 	MUX(CLK_MOUT_SPI2, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
+
+	MUX(0, "mout_user_aclk66_gpio", mout_user_aclk66_gpio_p,
+		SRC_TOP7, 4, 1),
+	MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
+		CLK_SET_RATE_PARENT, 0),
+	MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
+	MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
+		SRC_TOP10, 24, 1),
+	MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
+		SRC_TOP3, 24, 1),
+	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
+	MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
+		SRC_TOP10, 20, 1),
+	MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
+		SRC_TOP3, 20, 1),
+	MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
+	MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
+		TOP_SPARE2, 4, 1),
+	MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
+		SRC_TOP10, 16, 1),
+	MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
+		SRC_TOP3, 16, 1),
+	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
+	MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
+		SRC_TOP10, 0, 1),
+	MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
+		SRC_TOP3, 0, 1),
+	MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
+	MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
+		SRC_TOP11, 12, 1),
+	MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
+		SRC_TOP4, 12, 1),
+	MUX(0, "mout_aclk333_432_isp", mout_group4_p,
+		SRC_TOP1, 4, 2),
+	MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
+		SRC_TOP11, 4, 1),
+	MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
+		SRC_TOP4, 4, 1),
+	MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
+		SRC_TOP4, 16, 1),
+	MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
+	MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
+		SRC_TOP12, 4, 1),
+	MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
+		SRC_TOP5, 0, 1),
+
+	/* ISP Block*/
+	MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
+	MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
+	MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
+	MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
+	MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
 };
 
 static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
@@ -512,6 +596,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 	DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
 	DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
 	DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
+	DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
 
 	/* Audio Block */
 	DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
@@ -529,6 +614,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 	DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
 
 	DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
+	DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
 
 	/* UART and PWM */
 	DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
@@ -557,6 +643,39 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 	DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
 	DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
 	DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
+
+	DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1",
+		DIV_TOP2, 4, 3),
+	DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
+	DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
+		DIV_TOP0, 16, 3),
+	DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
+	DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
+		DIV_TOP1, 16, 3),
+	DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
+		DIV_TOP1, 4, 3),
+	/* Mfc Blk */
+	DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
+	/* Gscl Blk */
+	DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
+						DIV2_RATIO0, 4, 2),
+	DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
+	/* Mscl Blk */
+	DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
+	/* Psgen */
+	DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
+	/* Jpeg */
+	DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
+	/* isp */
+	DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
+	DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
+	DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
+	DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
+	DIV(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8),
+	DIV(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8),
+	DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
+	DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
+	DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
 };
 
 static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
@@ -781,12 +900,18 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 	GATE(CLK_PCLK_TMU_GPU, "pclk_tmu_gpu", "aclk66_psgen",
 			GATE_IP_PERIS, 22, 0, 0),
 
+	GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "dout_gscl_blk_300",
+			GATE_IP_GSCL0, 14, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "dout_gscl_blk_300",
+			GATE_IP_GSCL0, 15, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_user_aclk300_gscl",
 			GATE_IP_GSCL0, 0, 0, 0),
 	GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_user_aclk300_gscl",
 			GATE_IP_GSCL0, 1, 0, 0),
 	GATE(CLK_ACLK_FIMC_3AA, "aclk_fimc_3aa", "aclk333_432_gscl",
 			GATE_IP_GSCL0, 4, 0, 0),
+	GATE(CLK_PCLK_FIMC_3AA, "pclk_fimc_3aa", "dout_gscl_blk_333",
+			GATE_IP_GSCL0, 9, 0, 0),
 
 	GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
 			GATE_IP_GSCL1, 2, 0, 0),
@@ -818,9 +943,13 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 			GATE_BUS_DISP1, 19, 0, 0),
 	GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
 			GATE_IP_DISP1, 7, 0, 0),
+	GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
+			GATE_IP_DISP1, 8, 0, 0),
 
 	GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_user_aclk333",
 			GATE_BUS_MFC, 0, 0, 0),
+	GATE(CLK_PCLK_MFC, "pclk_mfc", "dout_mfc_blk",
+			GATE_BUS_MFC, 16, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
 	GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
 	GATE(CLK_G3D, "clk_g3d", "mout_user_aclk_g3d",
@@ -828,14 +957,24 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 
 	GATE(CLK_ACLK_ROTATOR, "aclk_rotator", "mout_user_aclk266",
 			GATE_IP_GEN, 1, 0, 0),
+	GATE(CLK_PCLK_ROTATOR, "pclk_rotator", "dout_gen_blk",
+			GATE_BUS_GEN, 13, 0, 0),
 	GATE(CLK_ACLK_JPEG, "aclk_jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
 	GATE(CLK_ACLK_JPEG2, "aclk_jpeg2", "aclk300_jpeg",
 			GATE_IP_GEN, 3, 0, 0),
+	GATE(CLK_ACLK_MDMA0, "aclk_mdma0", "aclk266_g2d",
+			GATE_BUS_G2D, 1, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_user_aclk266",
 			GATE_IP_GEN, 4, 0, 0),
 	GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
 			GATE_IP_GEN, 6, 0, 0),
+	GATE(CLK_ACLK_SMMU_MDMA0, "aclk_smmu_mdma0", "aclk266_g2d",
+			GATE_BUS_G2D, 5, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d",
+			GATE_BUS_G2D, 20, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
+	GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
+			GATE_BUS_GEN, 28, 0, 0),
 	GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
 			GATE_IP_GEN, 9, 0, 0),
 
@@ -845,14 +984,92 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 			GATE_BUS_MSCL, 1, 0, 0),
 	GATE(CLK_ACLK_MSCL2, "aclk_mscl2", "aclk400_mscl",
 			GATE_BUS_MSCL, 2, 0, 0),
+	GATE(CLK_PCLK_MSCL0, "pclk_mscl0", "dout_mscl_blk",
+			GATE_BUS_MSCL, 8, 0, 0),
+	GATE(CLK_PCLK_MSCL1, "pclk_mscl1", "dout_mscl_blk",
+			GATE_BUS_MSCL, 9, 0, 0),
+	GATE(CLK_PCLK_MSCL2, "pclk_mscl2", "dout_mscl_blk",
+			GATE_BUS_MSCL, 10, 0, 0),
 	GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
 			GATE_IP_MSCL, 8, 0, 0),
 	GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
 			GATE_IP_MSCL, 9, 0, 0),
 	GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
 			GATE_IP_MSCL, 10, 0, 0),
-	GATE(CLK_SMMU_MIXER, "smmu_mixer", "dout_disp1_blk",
-			GATE_IP_DISP1, 9, 0, 0),
+	GATE(CLK_ACLK_SMMU_MIXER, "aclk_smmu_mixer", "aclk200_disp1",
+			GATE_BUS_DISP1, 9, CLK_IGNORE_UNUSED, 0),
+
+	/* aclk333 gates internal MFC busses and should not be gated. */
+	/* aclk266 also gates other IPs in psgen. It should not be gated. */
+	GATE(CLK_ACLK266, "aclk266", "mout_user_aclk266",
+			GATE_BUS_NOC, 22, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK200_DISP1, "aclk200_disp1", "mout_aclk200_disp1",
+			GATE_BUS_TOP, 18, CLK_IGNORE_UNUSED, 0),
+	/* gating of aclk300_gscl causes system hang. It should not be gated. */
+	GATE(CLK_ACLK400_MSCL, "aclk400_mscl", "mout_user_aclk400_mscl",
+			GATE_BUS_TOP, 17, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK300_DISP1, "aclk300_disp1", "mout_user_aclk300_disp1",
+			SRC_MASK_TOP2, 24, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK266_ISP, "aclk266_isp", "mout_user_aclk266_isp",
+			GATE_BUS_TOP, 13, 0, 0),
+	GATE(CLK_ACLK400_ISP, "aclk400_isp", "mout_user_aclk400_isp",
+			GATE_BUS_TOP, 16, 0, 0),
+	GATE(CLK_ACLK333_432_ISP0, "aclk333_432_isp0",
+			"mout_user_aclk333_432_isp0", GATE_BUS_TOP, 5, 0, 0),
+	GATE(CLK_ACLK333_432_ISP, "aclk333_432_isp",
+			"mout_user_aclk333_432_isp", GATE_BUS_TOP, 8, 0, 0),
+	/* misc: mct, adc, chipid, wdt, rtc, sysreg etc */
+	GATE(CLK_PCLK_MC, "pclk_mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
+	GATE(CLK_PCLK_TOP_RTC, "pclk_top_rtc", "aclk66_psgen",
+			GATE_IP_GEN, 5, 0, 0),
+	GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ffactor_hsic_12m",
+			GATE_BUS_TOP, 29, 0, 0),
+	GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
+			GATE_BUS_TOP, 28, 0, 0),
+	/*
+	* HACK: When aclk_fimd1 is gated, aclk300_disp1 also gets gated as
+	* aclk_fimd1 is the only child node. aclk300_disp1 is connected
+	* to hdmi, mixer IPs through internal busses. gating of aclk300_disp1
+	* breaks HDMI S2R.
+	*/
+	GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "dout_disp1_blk",
+			GATE_BUS_DISP1, 15, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_MPHY_REFCLK, "sclk_mphy_refclk", "dout_mphy_refclk",
+			GATE_BUS_TOP, 30, 0, 0),
+	GATE(CLK_ACLK_FIMC_LITE0, "aclk_fimc_lite0", "aclk333_432_gscl",
+			GATE_IP_GSCL0, 5, 0, 0),
+	GATE(CLK_ACLK_FIMC_LITE1, "aclk_fimc_lite1", "aclk333_432_gscl",
+			GATE_IP_GSCL0, 6, 0, 0),
+	GATE(CLK_PCLK_FIMC_LITE0, "pclk_fimc_lite0", "dout_gscl_blk_333",
+			GATE_IP_GSCL0, 10, 0, 0),
+	GATE(CLK_PCLK_FIMC_LITE1, "pclk_fimc_lite1", "dout_gscl_blk_333",
+			GATE_IP_GSCL0, 11, 0, 0),
+	GATE(CLK_PCLK_FIMC_LITE3, "pclk_fimc_lite3", "dout_gscl_blk_333",
+			GATE_BUS_GSCL0, 13, 0, 0),
+	/* g2d */
+	GATE(CLK_ACLK_G2D, "aclk_g2d", "aclk333_g2d",
+			GATE_BUS_G2D, 3, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_G2D, "pclk_g2d", "aclk266_g2d",
+			GATE_BUS_G2D, 19, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "aclk333_g2d",
+			GATE_BUS_G2D, 7, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk266_g2d",
+			GATE_BUS_G2D, 22, CLK_IGNORE_UNUSED, 0),
+	/* ISP */
+	GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
+			GATE_TOP_SCLK_ISP, 3, 0, 0),
+	GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
+			GATE_TOP_SCLK_ISP, 0, 0, 0),
+	GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
+			GATE_TOP_SCLK_ISP, 1, 0, 0),
+	GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
+			GATE_TOP_SCLK_ISP, 2, 0, 0),
+	GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
+			GATE_TOP_SCLK_ISP, 4, 0, 0),
+	GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
+			GATE_TOP_SCLK_ISP, 8, 0, 0),
+	GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
+			GATE_TOP_SCLK_ISP, 12, 0, 0),
 
 	/* SSS */
 	GATE(CLK_ACLK_SSS, "aclk_sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
-- 
1.7.9.5

Re: [PATCH v2 5/7] clk: exynos5420: Add missing clocks

[Tomasz Figa]

Hi Shaik,

On 27.03.2014 12:07, Shaik Ameer Basha wrote:
> From: Rahul Sharma <rahul.sharma@samsung.com>
>
> This patch adds the missing clocks related to the modules
> like FIMD, DP, GSCL, MSCL, ISP, MFC etc.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
> ---
>   drivers/clk/samsung/clk-exynos5420.c |  221 +++++++++++++++++++++++++++++++++-
>   1 file changed, 219 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 793fb3d..26ddf33 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -269,15 +269,36 @@ PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
>   PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
>   PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
>
> +PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
>   PNAME(mout_sw_aclk66_p)	= {"dout_aclk66", "mout_sclk_spll"};
>   PNAME(mout_user_aclk66_peric_p) = {"fin_pll", "mout_sw_aclk66"};
> +PNAME(mout_user_aclk66_gpio_p) = {"mout_sw_aclk66", "ffactor_sw_aclk66"};
>
>   PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
> +PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
> +PNAME(mout_user_pclk200_fsys_p)	= {"fin_pll", "mout_sw_pclk200_fsys"};
>   PNAME(mout_user_aclk200_fsys_p)	= {"fin_pll", "mout_sw_aclk200_fsys"};
>
>   PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
>   PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
>
> +PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
> +PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
> +
> +PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
> +PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
> +PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
> +
> +PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
> +PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
> +
> +PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
> +					"mout_sclk_spll"};
> +PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
> +
> +PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
> +PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
> +
>   PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
>   PNAME(mout_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
>
> @@ -292,6 +313,7 @@ PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
>
>   PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
>   PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
> +PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
>
>   PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
>   PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
> @@ -300,7 +322,9 @@ PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
>   PNAME(mout_user_aclk300_gscl_p)	= {"fin_pll", "mout_sw_aclk300_gscl"};
>
>   PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
> +PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
>   PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
> +PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
>
>   PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
>   PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
> @@ -330,6 +354,8 @@ PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
>   PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
>   			 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
>   			 "mout_sclk_epll", "mout_sclk_rpll"};
> +PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
> +				"mout_sclk_mpll", "mout_sclk_spll"};
>
>   /* fixed rate clocks generated outside the soc */
>   static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
> @@ -347,6 +373,7 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata =
>
>   static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
>   	FFACTOR(0, "ffactor_hsic_12m", "fin_pll", 1, 2, 0),
> +	FFACTOR(0, "ffactor_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
>   };
>
>   static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
> @@ -452,6 +479,10 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
>   	MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
>   	MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
>   	MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
> +	MUX_F(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3,
> +						CLK_SET_RATE_PARENT, 0),
> +	MUX_F(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1,
> +						CLK_SET_RATE_PARENT, 0),
>
>   	/* MAU Block */
>   	MUX_F(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3,
> @@ -464,6 +495,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
>   	MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
>   	MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
>   	MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
> +	MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
>
>   	/* PERIC Block */
>   	MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
> @@ -478,6 +510,58 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
>   	MUX(CLK_MOUT_SPI0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
>   	MUX(CLK_MOUT_SPI1, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
>   	MUX(CLK_MOUT_SPI2, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
> +
> +	MUX(0, "mout_user_aclk66_gpio", mout_user_aclk66_gpio_p,
> +		SRC_TOP7, 4, 1),
> +	MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
> +		CLK_SET_RATE_PARENT, 0),
> +	MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
> +	MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
> +		SRC_TOP10, 24, 1),
> +	MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
> +		SRC_TOP3, 24, 1),
> +	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
> +	MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
> +		SRC_TOP10, 20, 1),
> +	MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
> +		SRC_TOP3, 20, 1),
> +	MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
> +	MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
> +		TOP_SPARE2, 4, 1),
> +	MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
> +		SRC_TOP10, 16, 1),
> +	MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
> +		SRC_TOP3, 16, 1),
> +	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
> +	MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
> +		SRC_TOP10, 0, 1),
> +	MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
> +		SRC_TOP3, 0, 1),
> +	MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
> +	MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
> +		SRC_TOP11, 12, 1),
> +	MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
> +		SRC_TOP4, 12, 1),
> +	MUX(0, "mout_aclk333_432_isp", mout_group4_p,
> +		SRC_TOP1, 4, 2),
> +	MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
> +		SRC_TOP11, 4, 1),
> +	MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
> +		SRC_TOP4, 4, 1),
> +	MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
> +		SRC_TOP4, 16, 1),
> +	MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
> +	MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
> +		SRC_TOP12, 4, 1),
> +	MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
> +		SRC_TOP5, 0, 1),
> +
> +	/* ISP Block*/
> +	MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
> +	MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
> +	MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
> +	MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
> +	MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
>   };
>
>   static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
> @@ -512,6 +596,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
>   	DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
>   	DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
>   	DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
> +	DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
>
>   	/* Audio Block */
>   	DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
> @@ -529,6 +614,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
>   	DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
>
>   	DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
> +	DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
>
>   	/* UART and PWM */
>   	DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
> @@ -557,6 +643,39 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
>   	DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
>   	DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
>   	DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
> +
> +	DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1",
> +		DIV_TOP2, 4, 3),
> +	DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
> +	DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
> +		DIV_TOP0, 16, 3),
> +	DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
> +	DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
> +		DIV_TOP1, 16, 3),
> +	DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
> +		DIV_TOP1, 4, 3),
> +	/* Mfc Blk */
> +	DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
> +	/* Gscl Blk */
> +	DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
> +						DIV2_RATIO0, 4, 2),
> +	DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
> +	/* Mscl Blk */
> +	DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
> +	/* Psgen */
> +	DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
> +	/* Jpeg */
> +	DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
> +	/* isp */
> +	DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
> +	DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
> +	DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
> +	DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
> +	DIV(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8),
> +	DIV(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8),
> +	DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
> +	DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
> +	DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
>   };
>
>   static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
> @@ -781,12 +900,18 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>   	GATE(CLK_PCLK_TMU_GPU, "pclk_tmu_gpu", "aclk66_psgen",
>   			GATE_IP_PERIS, 22, 0, 0),
>
> +	GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "dout_gscl_blk_300",
> +			GATE_IP_GSCL0, 14, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "dout_gscl_blk_300",
> +			GATE_IP_GSCL0, 15, CLK_IGNORE_UNUSED, 0),
>   	GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_user_aclk300_gscl",
>   			GATE_IP_GSCL0, 0, 0, 0),
>   	GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_user_aclk300_gscl",
>   			GATE_IP_GSCL0, 1, 0, 0),
>   	GATE(CLK_ACLK_FIMC_3AA, "aclk_fimc_3aa", "aclk333_432_gscl",
>   			GATE_IP_GSCL0, 4, 0, 0),
> +	GATE(CLK_PCLK_FIMC_3AA, "pclk_fimc_3aa", "dout_gscl_blk_333",
> +			GATE_IP_GSCL0, 9, 0, 0),
>
>   	GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
>   			GATE_IP_GSCL1, 2, 0, 0),
> @@ -818,9 +943,13 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>   			GATE_BUS_DISP1, 19, 0, 0),
>   	GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
>   			GATE_IP_DISP1, 7, 0, 0),
> +	GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
> +			GATE_IP_DISP1, 8, 0, 0),
>
>   	GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_user_aclk333",
>   			GATE_BUS_MFC, 0, 0, 0),
> +	GATE(CLK_PCLK_MFC, "pclk_mfc", "dout_mfc_blk",
> +			GATE_BUS_MFC, 16, CLK_IGNORE_UNUSED, 0),
>   	GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
>   	GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
>   	GATE(CLK_G3D, "clk_g3d", "mout_user_aclk_g3d",
> @@ -828,14 +957,24 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>
>   	GATE(CLK_ACLK_ROTATOR, "aclk_rotator", "mout_user_aclk266",
>   			GATE_IP_GEN, 1, 0, 0),
> +	GATE(CLK_PCLK_ROTATOR, "pclk_rotator", "dout_gen_blk",
> +			GATE_BUS_GEN, 13, 0, 0),
>   	GATE(CLK_ACLK_JPEG, "aclk_jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
>   	GATE(CLK_ACLK_JPEG2, "aclk_jpeg2", "aclk300_jpeg",
>   			GATE_IP_GEN, 3, 0, 0),
> +	GATE(CLK_ACLK_MDMA0, "aclk_mdma0", "aclk266_g2d",
> +			GATE_BUS_G2D, 1, CLK_IGNORE_UNUSED, 0),
>   	GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_user_aclk266",
>   			GATE_IP_GEN, 4, 0, 0),
>   	GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
>   			GATE_IP_GEN, 6, 0, 0),
> +	GATE(CLK_ACLK_SMMU_MDMA0, "aclk_smmu_mdma0", "aclk266_g2d",
> +			GATE_BUS_G2D, 5, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d",
> +			GATE_BUS_G2D, 20, CLK_IGNORE_UNUSED, 0),
>   	GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
> +	GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
> +			GATE_BUS_GEN, 28, 0, 0),
>   	GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
>   			GATE_IP_GEN, 9, 0, 0),
>
> @@ -845,14 +984,92 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>   			GATE_BUS_MSCL, 1, 0, 0),
>   	GATE(CLK_ACLK_MSCL2, "aclk_mscl2", "aclk400_mscl",
>   			GATE_BUS_MSCL, 2, 0, 0),
> +	GATE(CLK_PCLK_MSCL0, "pclk_mscl0", "dout_mscl_blk",
> +			GATE_BUS_MSCL, 8, 0, 0),
> +	GATE(CLK_PCLK_MSCL1, "pclk_mscl1", "dout_mscl_blk",
> +			GATE_BUS_MSCL, 9, 0, 0),
> +	GATE(CLK_PCLK_MSCL2, "pclk_mscl2", "dout_mscl_blk",
> +			GATE_BUS_MSCL, 10, 0, 0),
>   	GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
>   			GATE_IP_MSCL, 8, 0, 0),
>   	GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
>   			GATE_IP_MSCL, 9, 0, 0),
>   	GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
>   			GATE_IP_MSCL, 10, 0, 0),
> -	GATE(CLK_SMMU_MIXER, "smmu_mixer", "dout_disp1_blk",
> -			GATE_IP_DISP1, 9, 0, 0),
> +	GATE(CLK_ACLK_SMMU_MIXER, "aclk_smmu_mixer", "aclk200_disp1",
> +			GATE_BUS_DISP1, 9, CLK_IGNORE_UNUSED, 0),
> +
> +	/* aclk333 gates internal MFC busses and should not be gated. */
> +	/* aclk266 also gates other IPs in psgen. It should not be gated. */
> +	GATE(CLK_ACLK266, "aclk266", "mout_user_aclk266",
> +			GATE_BUS_NOC, 22, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_ACLK200_DISP1, "aclk200_disp1", "mout_aclk200_disp1",
> +			GATE_BUS_TOP, 18, CLK_IGNORE_UNUSED, 0),
> +	/* gating of aclk300_gscl causes system hang. It should not be gated. */
> +	GATE(CLK_ACLK400_MSCL, "aclk400_mscl", "mout_user_aclk400_mscl",
> +			GATE_BUS_TOP, 17, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_ACLK300_DISP1, "aclk300_disp1", "mout_user_aclk300_disp1",
> +			SRC_MASK_TOP2, 24, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_ACLK266_ISP, "aclk266_isp", "mout_user_aclk266_isp",
> +			GATE_BUS_TOP, 13, 0, 0),
> +	GATE(CLK_ACLK400_ISP, "aclk400_isp", "mout_user_aclk400_isp",
> +			GATE_BUS_TOP, 16, 0, 0),
> +	GATE(CLK_ACLK333_432_ISP0, "aclk333_432_isp0",
> +			"mout_user_aclk333_432_isp0", GATE_BUS_TOP, 5, 0, 0),
> +	GATE(CLK_ACLK333_432_ISP, "aclk333_432_isp",
> +			"mout_user_aclk333_432_isp", GATE_BUS_TOP, 8, 0, 0),
> +	/* misc: mct, adc, chipid, wdt, rtc, sysreg etc */
> +	GATE(CLK_PCLK_MC, "pclk_mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
> +	GATE(CLK_PCLK_TOP_RTC, "pclk_top_rtc", "aclk66_psgen",
> +			GATE_IP_GEN, 5, 0, 0),
> +	GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ffactor_hsic_12m",
> +			GATE_BUS_TOP, 29, 0, 0),
> +	GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
> +			GATE_BUS_TOP, 28, 0, 0),
> +	/*
> +	* HACK: When aclk_fimd1 is gated, aclk300_disp1 also gets gated as
> +	* aclk_fimd1 is the only child node. aclk300_disp1 is connected
> +	* to hdmi, mixer IPs through internal busses. gating of aclk300_disp1
> +	* breaks HDMI S2R.
> +	*/
> +	GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "dout_disp1_blk",
> +			GATE_BUS_DISP1, 15, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_SCLK_MPHY_REFCLK, "sclk_mphy_refclk", "dout_mphy_refclk",
> +			GATE_BUS_TOP, 30, 0, 0),
> +	GATE(CLK_ACLK_FIMC_LITE0, "aclk_fimc_lite0", "aclk333_432_gscl",
> +			GATE_IP_GSCL0, 5, 0, 0),
> +	GATE(CLK_ACLK_FIMC_LITE1, "aclk_fimc_lite1", "aclk333_432_gscl",
> +			GATE_IP_GSCL0, 6, 0, 0),
> +	GATE(CLK_PCLK_FIMC_LITE0, "pclk_fimc_lite0", "dout_gscl_blk_333",
> +			GATE_IP_GSCL0, 10, 0, 0),
> +	GATE(CLK_PCLK_FIMC_LITE1, "pclk_fimc_lite1", "dout_gscl_blk_333",
> +			GATE_IP_GSCL0, 11, 0, 0),
> +	GATE(CLK_PCLK_FIMC_LITE3, "pclk_fimc_lite3", "dout_gscl_blk_333",
> +			GATE_BUS_GSCL0, 13, 0, 0),
> +	/* g2d */
> +	GATE(CLK_ACLK_G2D, "aclk_g2d", "aclk333_g2d",
> +			GATE_BUS_G2D, 3, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PCLK_G2D, "pclk_g2d", "aclk266_g2d",
> +			GATE_BUS_G2D, 19, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "aclk333_g2d",
> +			GATE_BUS_G2D, 7, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk266_g2d",
> +			GATE_BUS_G2D, 22, CLK_IGNORE_UNUSED, 0),
> +	/* ISP */
> +	GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
> +			GATE_TOP_SCLK_ISP, 3, 0, 0),
> +	GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
> +			GATE_TOP_SCLK_ISP, 0, 0, 0),
> +	GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
> +			GATE_TOP_SCLK_ISP, 1, 0, 0),
> +	GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
> +			GATE_TOP_SCLK_ISP, 2, 0, 0),
> +	GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
> +			GATE_TOP_SCLK_ISP, 4, 0, 0),
> +	GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
> +			GATE_TOP_SCLK_ISP, 8, 0, 0),
> +	GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
> +			GATE_TOP_SCLK_ISP, 12, 0, 0),
>
>   	/* SSS */
>   	GATE(CLK_ACLK_SSS, "aclk_sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
>

This is really hard to review. May I ask you to split it into separate 
patch adding clocks for each block mentioned in description, please?

Also, as I mentioned in my comments to patches 1/7 and 2/7, respective 
IDs and registers being added should be in respective patches.

Best regards,
Tomasz

[PATCH v2 6/7] clk: exynos5420: Add more registers to restore list

[Shaik Ameer Basha]

From: Rahul Sharma <rahul.sharma@samsung.com>

Some of the clock registers should retain their state during
system suspend/resume operation. This patch adds more clock
registers to this list.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c |   27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 26ddf33..2067797 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -152,6 +152,13 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
 	DIV_CPU1,
 	GATE_BUS_CPU,
 	GATE_SCLK_CPU,
+	CLKOUT_CMU_CPU,
+	EPLL_CON0,
+	EPLL_CON1,
+	EPLL_CON2,
+	RPLL_CON0,
+	RPLL_CON1,
+	RPLL_CON2,
 	SRC_TOP0,
 	SRC_TOP1,
 	SRC_TOP2,
@@ -172,6 +179,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
 	SRC_MASK_FSYS,
 	SRC_MASK_PERIC0,
 	SRC_MASK_PERIC1,
+	SRC_ISP,
 	DIV_TOP0,
 	DIV_TOP1,
 	DIV_TOP2,
@@ -185,27 +193,44 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
 	DIV_PERIC2,
 	DIV_PERIC3,
 	DIV_PERIC4,
+	SCLK_DIV_ISP0,
+	SCLK_DIV_ISP1,
+	DIV2_RATIO0,
+	DIV4_RATIO,
 	GATE_BUS_TOP,
+	GATE_BUS_GSCL0,
+	GATE_BUS_GSCL1,
+	GATE_BUS_DISP1,
+	GATE_BUS_MFC,
+	GATE_BUS_GEN,
 	GATE_BUS_FSYS0,
+	GATE_BUS_FSYS2,
+	GATE_BUS_MSCL,
 	GATE_BUS_PERIC,
 	GATE_BUS_PERIC1,
 	GATE_BUS_PERIS0,
 	GATE_BUS_PERIS1,
+	GATE_BUS_NOC,
+	GATE_TOP_SCLK_ISP,
 	GATE_IP_GSCL0,
 	GATE_IP_GSCL1,
 	GATE_IP_MFC,
 	GATE_IP_DISP1,
 	GATE_IP_G3D,
 	GATE_IP_GEN,
+	GATE_IP_FSYS,
+	GATE_IP_PERIC,
+	GATE_IP_PERIS,
 	GATE_IP_MSCL,
 	GATE_TOP_SCLK_GSCL,
 	GATE_TOP_SCLK_DISP1,
 	GATE_TOP_SCLK_MAU,
 	GATE_TOP_SCLK_FSYS,
 	GATE_TOP_SCLK_PERIC,
-	SRC_CDREX,
+	TOP_SPARE2,
 	SRC_KFC,
 	DIV_KFC0,
+	SRC_MASK_TOP2,
 };
 
 static int exynos5420_clk_suspend(void)
-- 
1.7.9.5

[PATCH v2 7/7] ARM: dts: update macros in clock bindings for exynos5420

[Shaik Ameer Basha]

From: Rahul Sharma <rahul.sharma@samsung.com>

This patch updates the macros as per the latest changes and
replaces magic numbers with macros defined in DT header for
exynos5420.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi |   90 ++++++++++++++++++-------------------
 1 file changed, 45 insertions(+), 45 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 7c53ae9..2e60c80 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -129,7 +129,7 @@
 		compatible = "samsung,mfc-v7";
 		reg = <0x11000000 0x10000>;
 		interrupts = <0 96 0>;
-		clocks = <&clock CLK_MFC>;
+		clocks = <&clock CLK_ACLK_MFC>;
 		clock-names = "mfc";
 	};
 
@@ -139,7 +139,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		reg = <0x12200000 0x2000>;
-		clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
+		clocks = <&clock CLK_ACLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 		clock-names = "biu", "ciu";
 		fifo-depth = <0x40>;
 		status = "disabled";
@@ -151,7 +151,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		reg = <0x12210000 0x2000>;
-		clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
+		clocks = <&clock CLK_ACLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 		clock-names = "biu", "ciu";
 		fifo-depth = <0x40>;
 		status = "disabled";
@@ -163,7 +163,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		reg = <0x12220000 0x1000>;
-		clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
+		clocks = <&clock CLK_ACLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 		clock-names = "biu", "ciu";
 		fifo-depth = <0x40>;
 		status = "disabled";
@@ -177,7 +177,7 @@
 		interrupt-parent = <&mct_map>;
 		interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 				<8>, <9>, <10>, <11>;
-		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_PCLK_MCT>;
 		clock-names = "fin_pll", "mct";
 
 		mct_map: mct-map {
@@ -271,7 +271,7 @@
 	};
 
 	rtc@101E0000 {
-		clocks = <&clock CLK_RTC>;
+		clocks = <&clock CLK_PCLK_RTC>;
 		clock-names = "rtc";
 		status = "okay";
 	};
@@ -287,7 +287,7 @@
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x121A0000 0x1000>;
 			interrupts = <0 34 0>;
-			clocks = <&clock CLK_PDMA0>;
+			clocks = <&clock CLK_ACLK_PDMA0>;
 			clock-names = "apb_pclk";
 			#dma-cells = <1>;
 			#dma-channels = <8>;
@@ -298,7 +298,7 @@
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x121B0000 0x1000>;
 			interrupts = <0 35 0>;
-			clocks = <&clock CLK_PDMA1>;
+			clocks = <&clock CLK_ACLK_PDMA1>;
 			clock-names = "apb_pclk";
 			#dma-cells = <1>;
 			#dma-channels = <8>;
@@ -309,7 +309,7 @@
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x10800000 0x1000>;
 			interrupts = <0 33 0>;
-			clocks = <&clock CLK_MDMA0>;
+			clocks = <&clock CLK_ACLK_MDMA0>;
 			clock-names = "apb_pclk";
 			#dma-cells = <1>;
 			#dma-channels = <8>;
@@ -320,7 +320,7 @@
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x11C10000 0x1000>;
 			interrupts = <0 124 0>;
-			clocks = <&clock CLK_MDMA1>;
+			clocks = <&clock CLK_ACLK_MDMA1>;
 			clock-names = "apb_pclk";
 			#dma-cells = <1>;
 			#dma-channels = <8>;
@@ -351,7 +351,7 @@
 		dmas = <&pdma1 12
 			&pdma1 11>;
 		dma-names = "tx", "rx";
-		clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
+		clocks = <&clock CLK_PCLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 		clock-names = "iis", "i2s_opclk0";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s1_bus>;
@@ -364,7 +364,7 @@
 		dmas = <&pdma0 12
 			&pdma0 11>;
 		dma-names = "tx", "rx";
-		clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
+		clocks = <&clock CLK_PCLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 		clock-names = "iis", "i2s_opclk0";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s2_bus>;
@@ -382,7 +382,7 @@
 		#size-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&spi0_bus>;
-		clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
+		clocks = <&clock CLK_PCLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 		clock-names = "spi", "spi_busclk0";
 		status = "disabled";
 	};
@@ -398,7 +398,7 @@
 		#size-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&spi1_bus>;
-		clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
+		clocks = <&clock CLK_PCLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 		clock-names = "spi", "spi_busclk0";
 		status = "disabled";
 	};
@@ -414,28 +414,28 @@
 		#size-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&spi2_bus>;
-		clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
+		clocks = <&clock CLK_PCLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 		clock-names = "spi", "spi_busclk0";
 		status = "disabled";
 	};
 
 	serial@12C00000 {
-		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+		clocks = <&clock CLK_PCLK_UART0>, <&clock CLK_SCLK_UART0>;
 		clock-names = "uart", "clk_uart_baud0";
 	};
 
 	serial@12C10000 {
-		clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+		clocks = <&clock CLK_PCLK_UART1>, <&clock CLK_SCLK_UART1>;
 		clock-names = "uart", "clk_uart_baud0";
 	};
 
 	serial@12C20000 {
-		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+		clocks = <&clock CLK_PCLK_UART2>, <&clock CLK_SCLK_UART2>;
 		clock-names = "uart", "clk_uart_baud0";
 	};
 
 	serial@12C30000 {
-		clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
+		clocks = <&clock CLK_PCLK_UART3>, <&clock CLK_SCLK_UART3>;
 		clock-names = "uart", "clk_uart_baud0";
 	};
 
@@ -444,7 +444,7 @@
 		reg = <0x12dd0000 0x100>;
 		samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 		#pwm-cells = <3>;
-		clocks = <&clock CLK_PWM>;
+		clocks = <&clock CLK_PCLK_PWM>;
 		clock-names = "timers";
 	};
 
@@ -455,7 +455,7 @@
 	};
 
 	dp-controller@145B0000 {
-		clocks = <&clock CLK_DP1>;
+		clocks = <&clock CLK_PCLK_DP1>;
 		clock-names = "dp";
 		phys = <&dp_phy>;
 		phy-names = "dp";
@@ -463,7 +463,7 @@
 
 	fimd@14400000 {
 		samsung,power-domain = <&disp_pd>;
-		clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
+		clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_ACLK_FIMD1>;
 		clock-names = "sclk_fimd", "fimd";
 	};
 
@@ -471,7 +471,7 @@
 		compatible = "samsung,exynos-adc-v2";
 		reg = <0x12D10000 0x100>, <0x10040720 0x4>;
 		interrupts = <0 106 0>;
-		clocks = <&clock CLK_TSADC>;
+		clocks = <&clock CLK_PCLK_TSADC>;
 		clock-names = "adc";
 		#io-channel-cells = <1>;
 		io-channel-ranges;
@@ -484,7 +484,7 @@
 		interrupts = <0 56 0>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&clock CLK_I2C0>;
+		clocks = <&clock CLK_PCLK_I2C0>;
 		clock-names = "i2c";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c0_bus>;
@@ -497,7 +497,7 @@
 		interrupts = <0 57 0>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&clock CLK_I2C1>;
+		clocks = <&clock CLK_PCLK_I2C1>;
 		clock-names = "i2c";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c1_bus>;
@@ -510,7 +510,7 @@
 		interrupts = <0 58 0>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&clock CLK_I2C2>;
+		clocks = <&clock CLK_PCLK_I2C2>;
 		clock-names = "i2c";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c2_bus>;
@@ -523,7 +523,7 @@
 		interrupts = <0 59 0>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&clock CLK_I2C3>;
+		clocks = <&clock CLK_PCLK_I2C3>;
 		clock-names = "i2c";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c3_bus>;
@@ -538,7 +538,7 @@
 		#size-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c4_hs_bus>;
-		clocks = <&clock CLK_I2C4>;
+		clocks = <&clock CLK_PCLK_USI0>;
 		clock-names = "hsi2c";
 		status = "disabled";
 	};
@@ -551,7 +551,7 @@
 		#size-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c5_hs_bus>;
-		clocks = <&clock CLK_I2C5>;
+		clocks = <&clock CLK_PCLK_USI1>;
 		clock-names = "hsi2c";
 		status = "disabled";
 	};
@@ -564,7 +564,7 @@
 		#size-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c6_hs_bus>;
-		clocks = <&clock CLK_I2C6>;
+		clocks = <&clock CLK_PCLK_USI2>;
 		clock-names = "hsi2c";
 		status = "disabled";
 	};
@@ -577,7 +577,7 @@
 		#size-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c7_hs_bus>;
-		clocks = <&clock CLK_I2C7>;
+		clocks = <&clock CLK_PCLK_USI3>;
 		clock-names = "hsi2c";
 		status = "disabled";
 	};
@@ -590,7 +590,7 @@
 		#size-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c8_hs_bus>;
-		clocks = <&clock CLK_I2C8>;
+		clocks = <&clock CLK_PCLK_USI4>;
 		clock-names = "hsi2c";
 		status = "disabled";
 	};
@@ -603,7 +603,7 @@
 		#size-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c9_hs_bus>;
-		clocks = <&clock CLK_I2C9>;
+		clocks = <&clock CLK_PCLK_USI5>;
 		clock-names = "hsi2c";
 		status = "disabled";
 	};
@@ -616,7 +616,7 @@
 		#size-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c10_hs_bus>;
-		clocks = <&clock CLK_I2C10>;
+		clocks = <&clock CLK_PCLK_USI6>;
 		clock-names = "hsi2c";
 		status = "disabled";
 	};
@@ -625,7 +625,7 @@
 		compatible = "samsung,exynos4212-hdmi";
 		reg = <0x14530000 0x70000>;
 		interrupts = <0 95 0>;
-		clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
+		clocks = <&clock CLK_PCLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 			 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 			 <&clock CLK_MOUT_HDMI>;
 		clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
@@ -637,7 +637,7 @@
 		compatible = "samsung,exynos5420-mixer";
 		reg = <0x14450000 0x10000>;
 		interrupts = <0 94 0>;
-		clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
+		clocks = <&clock CLK_ACLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 		clock-names = "mixer", "sclk_hdmi";
 	};
 
@@ -645,7 +645,7 @@
 		compatible = "samsung,exynos5-gsc";
 		reg = <0x13e00000 0x1000>;
 		interrupts = <0 85 0>;
-		clocks = <&clock CLK_GSCL0>;
+		clocks = <&clock CLK_ACLK_GSCL0>;
 		clock-names = "gscl";
 		samsung,power-domain = <&gsc_pd>;
 	};
@@ -654,7 +654,7 @@
 		compatible = "samsung,exynos5-gsc";
 		reg = <0x13e10000 0x1000>;
 		interrupts = <0 86 0>;
-		clocks = <&clock CLK_GSCL1>;
+		clocks = <&clock CLK_ACLK_GSCL1>;
 		clock-names = "gscl";
 		samsung,power-domain = <&gsc_pd>;
 	};
@@ -668,7 +668,7 @@
 		compatible = "samsung,exynos5420-tmu";
 		reg = <0x10060000 0x100>;
 		interrupts = <0 65 0>;
-		clocks = <&clock CLK_TMU>;
+		clocks = <&clock CLK_PCLK_TMU>;
 		clock-names = "tmu_apbif";
 	};
 
@@ -676,7 +676,7 @@
 		compatible = "samsung,exynos5420-tmu";
 		reg = <0x10064000 0x100>;
 		interrupts = <0 183 0>;
-		clocks = <&clock CLK_TMU>;
+		clocks = <&clock CLK_PCLK_TMU>;
 		clock-names = "tmu_apbif";
 	};
 
@@ -684,7 +684,7 @@
 		compatible = "samsung,exynos5420-tmu-ext-triminfo";
 		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 		interrupts = <0 184 0>;
-		clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
+		clocks = <&clock CLK_PCLK_TMU>, <&clock CLK_PCLK_TMU>;
 		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 	};
 
@@ -692,7 +692,7 @@
 		compatible = "samsung,exynos5420-tmu-ext-triminfo";
 		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 		interrupts = <0 185 0>;
-		clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
+		clocks = <&clock CLK_PCLK_TMU>, <&clock CLK_PCLK_TMU_GPU>;
 		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 	};
 
@@ -700,7 +700,7 @@
 		compatible = "samsung,exynos5420-tmu-ext-triminfo";
 		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 		interrupts = <0 215 0>;
-		clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
+		clocks = <&clock CLK_PCLK_TMU_GPU>, <&clock CLK_PCLK_TMU>;
 		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 	};
 
@@ -708,7 +708,7 @@
 		compatible = "samsung,exynos5420-wdt";
 		reg = <0x101D0000 0x100>;
 		interrupts = <0 42 0>;
-		clocks = <&clock CLK_WDT>;
+		clocks = <&clock CLK_PCLK_WDT>;
 		clock-names = "watchdog";
 		samsung,syscon-phandle = <&pmu_system_controller>;
         };
@@ -717,7 +717,7 @@
 		compatible = "samsung,exynos4210-secss";
 		reg = <0x10830000 0x10000>;
 		interrupts = <0 112 0>;
-		clocks = <&clock 471>;
+		clocks = <&clock CLK_ACLK_SSS>;
 		clock-names = "secss";
 		samsung,power-domain = <&g2d_pd>;
 	};
-- 
1.7.9.5

Re: [PATCH v2 7/7] ARM: dts: update macros in clock bindings for exynos5420

[Tomasz Figa]

Hi Shaik,

On 27.03.2014 12:07, Shaik Ameer Basha wrote:
> From: Rahul Sharma <rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>
> This patch updates the macros as per the latest changes and
> replaces magic numbers with macros defined in DT header for
> exynos5420.
>

Contents of dts files are not "bindings", they are just device tree 
sources/data, defined according to some bindings. Bindings are defined 
sets of nodes and properties and their formats, as you can see in 
Documentation/devicetree/bindings/, where documentation of supported 
bindings is available.

So this patch doesn't update clock bindings, but rather device nodes. 
Following would be more appropriate: "ARM: dts: update clock IDs in 
device tree of Exynos5420".

However, as mentioned in comments to previous patches, most (if not all) 
of the changes below could be probably dropped.

Best regards,
Tomasz
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