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([2a00:1fa0:4e2:ae96:6d06:66d1:d6f1:88dc]) by smtp.gmail.com with ESMTPSA id s8sm1116394lfc.83.2020.05.20.07.38.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 May 2020 07:38:22 -0700 (PDT) Subject: Re: [PATCH v2 1/2] dt-bindings: memory: document Renesas RPC-IF bindings To: Rob Herring Cc: devicetree@vger.kernel.org, Mason Yang , linux-spi@vger.kernel.org, Chris Brandt , linux-mtd@lists.infradead.org References: <812e6e58-d13f-3f44-5f55-22266b690c57@cogentembedded.com> <116683d1-d402-4d7f-3357-1c8cde807076@cogentembedded.com> <20200501212547.GB15294@bogus> From: Sergei Shtylyov Message-ID: <5359d5a2-5d28-058e-ce37-bc91e1aa7988@cogentembedded.com> Date: Wed, 20 May 2020 17:38:12 +0300 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200501212547.GB15294@bogus> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 02.05.2020 0:25, Rob Herring wrote: >> Renesas Reduced Pin Count Interface (RPC-IF) allows a SPI flash or >> HyperFlash connected to the SoC to be accessed via the external address >> space read mode or the manual mode. >> >> Document the device tree bindings for the Renesas RPC-IF found in the R-Car >> gen3 SoCs. >> >> Based on the original patch by Mason Yang . >> >> Signed-off-by: Sergei Shtylyov >> >> --- >> Changes in version 2: >> - rewrote the bindings in YAML. >> >> Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml | 88 ++++++++++ > > Not where we normally put SPI flash controllers... RPC-IF is not exactly SPI flash controller, it's bimodal. MBR, Sergei