From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH v12 11/31] documentation: iommu: add binding document of Exynos System MMU Date: Thu, 01 May 2014 11:41:37 -0600 Message-ID: <53628751.9000609@wwwdotorg.org> References: <1398584283-22846-1-git-send-email-shaik.ameer@samsung.com> <20140429181601.GE3582@e103592.cambridge.arm.com> <7044616.kdaKNu3Qet@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <7044616.kdaKNu3Qet@wuerfel> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Arnd Bergmann , Grant Grundler Cc: "t.figa-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org" , Will Deacon , "tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" , "joshi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org" , Thierry Reding , "s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org" , "Varun.Sethi-KZfg59tc24xl57MIdRCFDg@public.gmane.org" , "linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "prathyush.k-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org" , "sachin.kamat-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org" , Dave Martin , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "kgene.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org" , "a.motakis-lrHrjnjw1UfHK3s98zE1ajGjJy/sRE9J@public.gmane.org" , "pullip.cho-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org" List-Id: devicetree@vger.kernel.org On 04/29/2014 03:00 PM, Arnd Bergmann wrote: ... > Yes. It's very complicated unfortunately, because we have to be > able to deal with arbitrary combinations of a lot of oddball cases > that can show up in random SoCs: ... > - a device may have DMA access to a bus that is invisible to the CPU The issue is slightly more general than that. It's more that the bus structure "seen" by a device is simply /different/ than that seen by the CPU. I don't think it's a requirement that there be CPU-invisible buses for that to be true. For example, I could conceive of a HW setup like: primary CPU bus ----------------------> other devices | \_________________ / | \ | v v ^ device registers ----> some secondary bus | v memory Here, all the buses are visible to the CPU, yet the path that transactions take between the buses is simply different to the CPU. More complex situations than the above, while still maintaining that description, are certainly possible.