[PATCH V5 0/3] arm: dts: dra7: Updates for adding crossbar device

[PATCH V5 0/3] arm: dts: dra7: Updates for adding crossbar device

[Sricharan R]

Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the interrupt
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the controllers appropriately.
In such places a interrupt controllers are preceded by an
IRQ CROSSBAR that provides flexibility in muxing the device interrupt
requests to the controller inputs.

The dts file update to support the crossbar device and convert
peripheral irq numbers to crossbar number are added here.

This is a rebase of V4 series on top of 3.15-rc4

This series depends on crossbar-driver-fixes sent below
http://marc.info/?l=linux-omap&m=139929963420299&w=2

Sricharan R (3):
  arm: dts: dra7: Add crossbar device binding
  arm: dts: dra7: Replace peripheral interrupt numbers with crossbar
    inputs
  arm: dts: dra7: Add routable-irqs property for gic node

 arch/arm/boot/dts/dra7.dtsi |  109 +++++++++++++++++++++++++------------------
 1 file changed, 63 insertions(+), 46 deletions(-)

-- 
1.7.9.5

[PATCH V5 1/3] arm: dts: dra7: Add crossbar device binding

[Sricharan R]

This adds the irq crossbar device node.

There is a IRQ crossbar device in the soc, which
maps the irq requests from the peripherals to the
mpu interrupt controller's inputs. The Peripheral irq
requests are connected to only one crossbar
input and the output of the crossbar is connected to only one
controller's input line. The crossbar device is used to map
a peripheral input to a free mpu's interrupt controller line.

Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
[V5] Rebased on top of 3.15-rc4 and corrected the
     irqs-reserved list

 arch/arm/boot/dts/dra7.dtsi |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 149b550..0274a86 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -790,6 +790,14 @@
 			status = "disabled";
 		};
 	};
+
+	crossbar_mpu: crossbar@4a020000 {
+		compatible = "ti,irq-crossbar";
+		reg = <0x4a002a48 0x130>;
+		ti,max-irqs = <160>;
+		ti,reg-size = <2>;
+		ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
+	};
 };
 
 /include/ "dra7xx-clocks.dtsi"
-- 
1.7.9.5

Re: [PATCH V5 1/3] arm: dts: dra7: Add crossbar device binding

[Felipe Balbi]

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On Tue, May 06, 2014 at 07:26:17PM +0530, Sricharan R wrote:
> This adds the irq crossbar device node.
> 
> There is a IRQ crossbar device in the soc, which
> maps the irq requests from the peripherals to the
> mpu interrupt controller's inputs. The Peripheral irq
> requests are connected to only one crossbar
> input and the output of the crossbar is connected to only one
> controller's input line. The crossbar device is used to map
> a peripheral input to a free mpu's interrupt controller line.
> 
> Cc: Benoit Cousson <bcousson@baylibre.com>
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Sricharan R <r.sricharan@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
> [V5] Rebased on top of 3.15-rc4 and corrected the
>      irqs-reserved list
> 
>  arch/arm/boot/dts/dra7.dtsi |    8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 149b550..0274a86 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -790,6 +790,14 @@
>  			status = "disabled";
>  		};
>  	};
> +
> +	crossbar_mpu: crossbar@4a020000 {

shouldn't this be "status = disabled"; so that boards enable this
on-demand ??

-- 
balbi

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Re: [PATCH V5 1/3] arm: dts: dra7: Add crossbar device binding

[Nishanth Menon]

On 05/06/2014 02:40 PM, Felipe Balbi wrote:
> On Tue, May 06, 2014 at 07:26:17PM +0530, Sricharan R wrote:
>> This adds the irq crossbar device node.
>>
>> There is a IRQ crossbar device in the soc, which
>> maps the irq requests from the peripherals to the
>> mpu interrupt controller's inputs. The Peripheral irq
>> requests are connected to only one crossbar
>> input and the output of the crossbar is connected to only one
>> controller's input line. The crossbar device is used to map
>> a peripheral input to a free mpu's interrupt controller line.
>>
>> Cc: Benoit Cousson <bcousson@baylibre.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Cc: Rajendra Nayak <rnayak@ti.com>
>> Cc: Tony Lindgren <tony@atomide.com>
>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>> Signed-off-by: Nishanth Menon <nm@ti.com>
>> ---
>> [V5] Rebased on top of 3.15-rc4 and corrected the
>>      irqs-reserved list
>>
>>  arch/arm/boot/dts/dra7.dtsi |    8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 149b550..0274a86 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -790,6 +790,14 @@
>>  			status = "disabled";
>>  		};
>>  	};
>> +
>> +	crossbar_mpu: crossbar@4a020000 {
> 
> shouldn't this be "status = disabled"; so that boards enable this
> on-demand ??
> 
It cannot be and does not need to be. crossbar is an SoC feature. by
defining crossbar, the IRQ numbers we provide in DTS now becomes
crossbar numbers which get mapped to GIC interrupt numbers dynamically.

further crossbar is not a board feature. it is as ingrained in DRA7
behavior as GIC is. we are fortunate that we have some default mapping
of crossbar that allows the current peripherals to work, with this
support, we dont have to depend any longer on "we are lucky that is
mapped".

That said, in hindsight, patch #1 and 2 should be squashed IMHO. else
we have a bisectability problem here.

-- 
Regards,
Nishanth Menon

Re: [PATCH V5 1/3] arm: dts: dra7: Add crossbar device binding

[Darren Etheridge]

Nishanth Menon <nm@ti.com> wrote on Tue [2014-May-06 14:46:10 -0500]:
> On 05/06/2014 02:40 PM, Felipe Balbi wrote:
> > On Tue, May 06, 2014 at 07:26:17PM +0530, Sricharan R wrote:
> >> This adds the irq crossbar device node.
> >>
> >> There is a IRQ crossbar device in the soc, which
> >> maps the irq requests from the peripherals to the
> >> mpu interrupt controller's inputs. The Peripheral irq
> >> requests are connected to only one crossbar
> >> input and the output of the crossbar is connected to only one
> >> controller's input line. The crossbar device is used to map
> >> a peripheral input to a free mpu's interrupt controller line.
> >>
> >> Cc: Benoit Cousson <bcousson@baylibre.com>
> >> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> >> Cc: Rajendra Nayak <rnayak@ti.com>
> >> Cc: Tony Lindgren <tony@atomide.com>
> >> Signed-off-by: Sricharan R <r.sricharan@ti.com>
> >> Signed-off-by: Nishanth Menon <nm@ti.com>
> >> ---
> >> [V5] Rebased on top of 3.15-rc4 and corrected the
> >>      irqs-reserved list
> >>
> >>  arch/arm/boot/dts/dra7.dtsi |    8 ++++++++
> >>  1 file changed, 8 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> >> index 149b550..0274a86 100644
> >> --- a/arch/arm/boot/dts/dra7.dtsi
> >> +++ b/arch/arm/boot/dts/dra7.dtsi
> >> @@ -790,6 +790,14 @@
> >>  			status = "disabled";
> >>  		};
> >>  	};
> >> +
> >> +	crossbar_mpu: crossbar@4a020000 {
> > 
> > shouldn't this be "status = disabled"; so that boards enable this
> > on-demand ??
> > 
> It cannot be and does not need to be. crossbar is an SoC feature. by
> defining crossbar, the IRQ numbers we provide in DTS now becomes
> crossbar numbers which get mapped to GIC interrupt numbers dynamically.
> 
> further crossbar is not a board feature. it is as ingrained in DRA7
> behavior as GIC is. we are fortunate that we have some default mapping
> of crossbar that allows the current peripherals to work, with this
> support, we dont have to depend any longer on "we are lucky that is
> mapped".
> 
> That said, in hindsight, patch #1 and 2 should be squashed IMHO. else
> we have a bisectability problem here.
> 
Yes the bisectability problem is completely true - I was just testing
that as your email came in.  In fact I think all three patches need to
be squashed into one, I can't boot the dra7-EVM unless I have all three
patches applied.

With all three patches applied, basic boot is looking good.  I will
reply with my tested-by once I have got VIP, etc up and running.

Darren

Re: [PATCH V5 1/3] arm: dts: dra7: Add crossbar device binding

[Darren Etheridge]

Darren Etheridge <detheridge@ti.com> wrote on Tue [2014-May-06 14:58:04 -0500]:
> Nishanth Menon <nm@ti.com> wrote on Tue [2014-May-06 14:46:10 -0500]:
> > On 05/06/2014 02:40 PM, Felipe Balbi wrote:
> > > On Tue, May 06, 2014 at 07:26:17PM +0530, Sricharan R wrote:
> > >> This adds the irq crossbar device node.
> > >>
> > >> There is a IRQ crossbar device in the soc, which
> > >> maps the irq requests from the peripherals to the
> > >> mpu interrupt controller's inputs. The Peripheral irq
> > >> requests are connected to only one crossbar
> > >> input and the output of the crossbar is connected to only one
> > >> controller's input line. The crossbar device is used to map
> > >> a peripheral input to a free mpu's interrupt controller line.
> > >>
> > >> Cc: Benoit Cousson <bcousson@baylibre.com>
> > >> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > >> Cc: Rajendra Nayak <rnayak@ti.com>
> > >> Cc: Tony Lindgren <tony@atomide.com>
> > >> Signed-off-by: Sricharan R <r.sricharan@ti.com>
> > >> Signed-off-by: Nishanth Menon <nm@ti.com>
> > >> ---
> > >> [V5] Rebased on top of 3.15-rc4 and corrected the
> > >>      irqs-reserved list
> > >>
> > >>  arch/arm/boot/dts/dra7.dtsi |    8 ++++++++
> > >>  1 file changed, 8 insertions(+)
> > >>
> > >> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> > >> index 149b550..0274a86 100644
> > >> --- a/arch/arm/boot/dts/dra7.dtsi
> > >> +++ b/arch/arm/boot/dts/dra7.dtsi
> > >> @@ -790,6 +790,14 @@
> > >>  			status = "disabled";
> > >>  		};
> > >>  	};
> > >> +
> > >> +	crossbar_mpu: crossbar@4a020000 {
> > > 
> > > shouldn't this be "status = disabled"; so that boards enable this
> > > on-demand ??
> > > 
> > It cannot be and does not need to be. crossbar is an SoC feature. by
> > defining crossbar, the IRQ numbers we provide in DTS now becomes
> > crossbar numbers which get mapped to GIC interrupt numbers dynamically.
> > 
> > further crossbar is not a board feature. it is as ingrained in DRA7
> > behavior as GIC is. we are fortunate that we have some default mapping
> > of crossbar that allows the current peripherals to work, with this
> > support, we dont have to depend any longer on "we are lucky that is
> > mapped".
> > 
> > That said, in hindsight, patch #1 and 2 should be squashed IMHO. else
> > we have a bisectability problem here.
> > 
> Yes the bisectability problem is completely true - I was just testing
> that as your email came in.  In fact I think all three patches need to
> be squashed into one, I can't boot the dra7-EVM unless I have all three
> patches applied.
> 

Or I just tried reordering, so patch 3/3 becomes patch 1 and then squash
patch 1/3 and patch 2/3 together to form patch 2.  That seems to at
least let the kernel boot to completion.

Darren

[PATCH V5 2/3] arm: dts: dra7: Replace peripheral interrupt numbers with crossbar inputs

[Sricharan R]

Now with the crossbar IP in picture, the peripherals do not have the
fixed interrupt lines. Instead they rely on the crossbar irqchip to
allocate and map a free interrupt line to its crossbar input. So replacing
all the peripheral interrupt numbers with its fixed crossbar input lines.

Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
[V5] Rebased on 3.15-rc4 and replaced irqs numbers with crossbar
     numbers for new peripherals.

 arch/arm/boot/dts/dra7.dtsi |  100 +++++++++++++++++++++++--------------------
 1 file changed, 54 insertions(+), 46 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 0274a86..52e4bd0 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -106,8 +106,8 @@
 		ti,hwmods = "l3_main_1", "l3_main_2";
 		reg = <0x44000000 0x2000>,
 		      <0x44800000 0x3000>;
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 
 		prm: prm@4ae06000 {
 			compatible = "ti,dra7-prm";
@@ -182,10 +182,10 @@
 		sdma: dma-controller@4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			#dma-channels = <32>;
 			#dma-requests = <127>;
@@ -194,7 +194,7 @@
 		gpio1: gpio@4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio1";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -205,7 +205,7 @@
 		gpio2: gpio@48055000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48055000 0x200>;
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio2";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -216,7 +216,7 @@
 		gpio3: gpio@48057000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48057000 0x200>;
-			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio3";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -227,7 +227,7 @@
 		gpio4: gpio@48059000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48059000 0x200>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio4";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -238,7 +238,7 @@
 		gpio5: gpio@4805b000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805b000 0x200>;
-			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio5";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -249,7 +249,7 @@
 		gpio6: gpio@4805d000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4805d000 0x200>;
-			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio6";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -260,7 +260,7 @@
 		gpio7: gpio@48051000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48051000 0x200>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio7";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -271,7 +271,7 @@
 		gpio8: gpio@48053000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x48053000 0x200>;
-			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "gpio8";
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -282,7 +282,7 @@
 		uart1: serial@4806a000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806a000 0x100>;
-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -291,7 +291,7 @@
 		uart2: serial@4806c000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806c000 0x100>;
-			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -300,7 +300,7 @@
 		uart3: serial@48020000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48020000 0x100>;
-			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -309,7 +309,7 @@
 		uart4: serial@4806e000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806e000 0x100>;
-			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
                         status = "disabled";
@@ -318,7 +318,7 @@
 		uart5: serial@48066000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48066000 0x100>;
-			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -327,7 +327,7 @@
 		uart6: serial@48068000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48068000 0x100>;
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -336,6 +336,7 @@
 		uart7: serial@48420000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48420000 0x100>;
+			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart7";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -344,6 +345,7 @@
 		uart8: serial@48422000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48422000 0x100>;
+			interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart8";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -352,6 +354,7 @@
 		uart9: serial@48424000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48424000 0x100>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart9";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -360,6 +363,7 @@
 		uart10: serial@4ae2b000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4ae2b000 0x100>;
+			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart10";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -368,7 +372,7 @@
 		timer1: timer@4ae18000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4ae18000 0x80>;
-			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
 		};
@@ -376,28 +380,28 @@
 		timer2: timer@48032000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48032000 0x80>;
-			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
 		};
 
 		timer3: timer@48034000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48034000 0x80>;
-			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
 		};
 
 		timer4: timer@48036000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48036000 0x80>;
-			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
 		};
 
 		timer5: timer@48820000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48820000 0x80>;
-			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
 		};
@@ -405,7 +409,7 @@
 		timer6: timer@48822000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48822000 0x80>;
-			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
 			ti,timer-pwm;
@@ -414,7 +418,7 @@
 		timer7: timer@48824000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48824000 0x80>;
-			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
 		};
@@ -422,7 +426,7 @@
 		timer8: timer@48826000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48826000 0x80>;
-			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer8";
 			ti,timer-dsp;
 			ti,timer-pwm;
@@ -431,21 +435,21 @@
 		timer9: timer@4803e000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4803e000 0x80>;
-			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 		};
 
 		timer10: timer@48086000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48086000 0x80>;
-			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 		};
 
 		timer11: timer@48088000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48088000 0x80>;
-			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
 		};
@@ -453,6 +457,7 @@
 		timer13: timer@48828000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48828000 0x80>;
+			interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer13";
 			status = "disabled";
 		};
@@ -460,6 +465,7 @@
 		timer14: timer@4882a000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4882a000 0x80>;
+			interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer14";
 			status = "disabled";
 		};
@@ -467,6 +473,7 @@
 		timer15: timer@4882c000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4882c000 0x80>;
+			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer15";
 			status = "disabled";
 		};
@@ -474,6 +481,7 @@
 		timer16: timer@4882e000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x4882e000 0x80>;
+			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer16";
 			status = "disabled";
 		};
@@ -481,7 +489,7 @@
 		wdt2: wdt@4ae14000 {
 			compatible = "ti,omap4-wdt";
 			reg = <0x4ae14000 0x80>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
 		};
 
@@ -495,14 +503,14 @@
 		dmm@4e000000 {
 			compatible = "ti,omap5-dmm";
 			reg = <0x4e000000 0x800>;
-			interrupts = <0 113 0x4>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "dmm";
 		};
 
 		i2c1: i2c@48070000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48070000 0x100>;
-			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
@@ -512,7 +520,7 @@
 		i2c2: i2c@48072000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48072000 0x100>;
-			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
@@ -522,7 +530,7 @@
 		i2c3: i2c@48060000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x48060000 0x100>;
-			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
@@ -532,7 +540,7 @@
 		i2c4: i2c@4807a000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x4807a000 0x100>;
-			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
@@ -542,7 +550,7 @@
 		i2c5: i2c@4807c000 {
 			compatible = "ti,omap4-i2c";
 			reg = <0x4807c000 0x100>;
-			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c5";
@@ -552,7 +560,7 @@
 		mmc1: mmc@4809c000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x4809c000 0x400>;
-			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc1";
 			ti,dual-volt;
 			ti,needs-special-reset;
@@ -565,7 +573,7 @@
 		mmc2: mmc@480b4000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480b4000 0x400>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc2";
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
@@ -576,7 +584,7 @@
 		mmc3: mmc@480ad000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480ad000 0x400>;
-			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc3";
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
@@ -587,7 +595,7 @@
 		mmc4: mmc@480d1000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480d1000 0x400>;
-			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmc4";
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
@@ -730,7 +738,7 @@
 		mcspi1: spi@48098000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x48098000 0x200>;
-			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi1";
@@ -751,7 +759,7 @@
 		mcspi2: spi@4809a000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x4809a000 0x200>;
-			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi2";
@@ -767,7 +775,7 @@
 		mcspi3: spi@480b8000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480b8000 0x200>;
-			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi3";
@@ -780,7 +788,7 @@
 		mcspi4: spi@480ba000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480ba000 0x200>;
-			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "mcspi4";
-- 
1.7.9.5

Re: [PATCH V5 2/3] arm: dts: dra7: Replace peripheral interrupt numbers with crossbar inputs

[Tony Lindgren]

* Sricharan R <r.sricharan-l0cyMroinI0@public.gmane.org> [140506 06:58]:
> Now with the crossbar IP in picture, the peripherals do not have the
> fixed interrupt lines. Instead they rely on the crossbar irqchip to
> allocate and map a free interrupt line to its crossbar input. So replacing
> all the peripheral interrupt numbers with its fixed crossbar input lines.

Presumably this depends on the crossbar fixes?

Are you guys sure this is OK to apply now? Has it really been tested
for the devices to work with the mainline kernel?

I do not want to see constant patching of things over and over again
with this stuff, so I'd like to see at least two Tested-by's for this
series before applying.

Regards,

Tony
 
> Cc: Benoit Cousson <bcousson-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Cc: Santosh Shilimkar <santosh.shilimkar-l0cyMroinI0@public.gmane.org>
> Cc: Rajendra Nayak <rnayak-l0cyMroinI0@public.gmane.org>
> Cc: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Sricharan R <r.sricharan-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
> ---
> [V5] Rebased on 3.15-rc4 and replaced irqs numbers with crossbar
>      numbers for new peripherals.
> 
>  arch/arm/boot/dts/dra7.dtsi |  100 +++++++++++++++++++++++--------------------
>  1 file changed, 54 insertions(+), 46 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 0274a86..52e4bd0 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -106,8 +106,8 @@
>  		ti,hwmods = "l3_main_1", "l3_main_2";
>  		reg = <0x44000000 0x2000>,
>  		      <0x44800000 0x3000>;
> -		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> -			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>  
>  		prm: prm@4ae06000 {
>  			compatible = "ti,dra7-prm";
> @@ -182,10 +182,10 @@
>  		sdma: dma-controller@4a056000 {
>  			compatible = "ti,omap4430-sdma";
>  			reg = <0x4a056000 0x1000>;
> -			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>  			#dma-cells = <1>;
>  			#dma-channels = <32>;
>  			#dma-requests = <127>;
> @@ -194,7 +194,7 @@
>  		gpio1: gpio@4ae10000 {
>  			compatible = "ti,omap4-gpio";
>  			reg = <0x4ae10000 0x200>;
> -			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "gpio1";
>  			gpio-controller;
>  			#gpio-cells = <2>;
> @@ -205,7 +205,7 @@
>  		gpio2: gpio@48055000 {
>  			compatible = "ti,omap4-gpio";
>  			reg = <0x48055000 0x200>;
> -			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "gpio2";
>  			gpio-controller;
>  			#gpio-cells = <2>;
> @@ -216,7 +216,7 @@
>  		gpio3: gpio@48057000 {
>  			compatible = "ti,omap4-gpio";
>  			reg = <0x48057000 0x200>;
> -			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "gpio3";
>  			gpio-controller;
>  			#gpio-cells = <2>;
> @@ -227,7 +227,7 @@
>  		gpio4: gpio@48059000 {
>  			compatible = "ti,omap4-gpio";
>  			reg = <0x48059000 0x200>;
> -			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "gpio4";
>  			gpio-controller;
>  			#gpio-cells = <2>;
> @@ -238,7 +238,7 @@
>  		gpio5: gpio@4805b000 {
>  			compatible = "ti,omap4-gpio";
>  			reg = <0x4805b000 0x200>;
> -			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "gpio5";
>  			gpio-controller;
>  			#gpio-cells = <2>;
> @@ -249,7 +249,7 @@
>  		gpio6: gpio@4805d000 {
>  			compatible = "ti,omap4-gpio";
>  			reg = <0x4805d000 0x200>;
> -			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "gpio6";
>  			gpio-controller;
>  			#gpio-cells = <2>;
> @@ -260,7 +260,7 @@
>  		gpio7: gpio@48051000 {
>  			compatible = "ti,omap4-gpio";
>  			reg = <0x48051000 0x200>;
> -			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "gpio7";
>  			gpio-controller;
>  			#gpio-cells = <2>;
> @@ -271,7 +271,7 @@
>  		gpio8: gpio@48053000 {
>  			compatible = "ti,omap4-gpio";
>  			reg = <0x48053000 0x200>;
> -			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "gpio8";
>  			gpio-controller;
>  			#gpio-cells = <2>;
> @@ -282,7 +282,7 @@
>  		uart1: serial@4806a000 {
>  			compatible = "ti,omap4-uart";
>  			reg = <0x4806a000 0x100>;
> -			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "uart1";
>  			clock-frequency = <48000000>;
>  			status = "disabled";
> @@ -291,7 +291,7 @@
>  		uart2: serial@4806c000 {
>  			compatible = "ti,omap4-uart";
>  			reg = <0x4806c000 0x100>;
> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "uart2";
>  			clock-frequency = <48000000>;
>  			status = "disabled";
> @@ -300,7 +300,7 @@
>  		uart3: serial@48020000 {
>  			compatible = "ti,omap4-uart";
>  			reg = <0x48020000 0x100>;
> -			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "uart3";
>  			clock-frequency = <48000000>;
>  			status = "disabled";
> @@ -309,7 +309,7 @@
>  		uart4: serial@4806e000 {
>  			compatible = "ti,omap4-uart";
>  			reg = <0x4806e000 0x100>;
> -			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "uart4";
>  			clock-frequency = <48000000>;
>                          status = "disabled";
> @@ -318,7 +318,7 @@
>  		uart5: serial@48066000 {
>  			compatible = "ti,omap4-uart";
>  			reg = <0x48066000 0x100>;
> -			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "uart5";
>  			clock-frequency = <48000000>;
>  			status = "disabled";
> @@ -327,7 +327,7 @@
>  		uart6: serial@48068000 {
>  			compatible = "ti,omap4-uart";
>  			reg = <0x48068000 0x100>;
> -			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "uart6";
>  			clock-frequency = <48000000>;
>  			status = "disabled";
> @@ -336,6 +336,7 @@
>  		uart7: serial@48420000 {
>  			compatible = "ti,omap4-uart";
>  			reg = <0x48420000 0x100>;
> +			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "uart7";
>  			clock-frequency = <48000000>;
>  			status = "disabled";
> @@ -344,6 +345,7 @@
>  		uart8: serial@48422000 {
>  			compatible = "ti,omap4-uart";
>  			reg = <0x48422000 0x100>;
> +			interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "uart8";
>  			clock-frequency = <48000000>;
>  			status = "disabled";
> @@ -352,6 +354,7 @@
>  		uart9: serial@48424000 {
>  			compatible = "ti,omap4-uart";
>  			reg = <0x48424000 0x100>;
> +			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "uart9";
>  			clock-frequency = <48000000>;
>  			status = "disabled";
> @@ -360,6 +363,7 @@
>  		uart10: serial@4ae2b000 {
>  			compatible = "ti,omap4-uart";
>  			reg = <0x4ae2b000 0x100>;
> +			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "uart10";
>  			clock-frequency = <48000000>;
>  			status = "disabled";
> @@ -368,7 +372,7 @@
>  		timer1: timer@4ae18000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x4ae18000 0x80>;
> -			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer1";
>  			ti,timer-alwon;
>  		};
> @@ -376,28 +380,28 @@
>  		timer2: timer@48032000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x48032000 0x80>;
> -			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer2";
>  		};
>  
>  		timer3: timer@48034000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x48034000 0x80>;
> -			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer3";
>  		};
>  
>  		timer4: timer@48036000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x48036000 0x80>;
> -			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer4";
>  		};
>  
>  		timer5: timer@48820000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x48820000 0x80>;
> -			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer5";
>  			ti,timer-dsp;
>  		};
> @@ -405,7 +409,7 @@
>  		timer6: timer@48822000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x48822000 0x80>;
> -			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer6";
>  			ti,timer-dsp;
>  			ti,timer-pwm;
> @@ -414,7 +418,7 @@
>  		timer7: timer@48824000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x48824000 0x80>;
> -			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer7";
>  			ti,timer-dsp;
>  		};
> @@ -422,7 +426,7 @@
>  		timer8: timer@48826000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x48826000 0x80>;
> -			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer8";
>  			ti,timer-dsp;
>  			ti,timer-pwm;
> @@ -431,21 +435,21 @@
>  		timer9: timer@4803e000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x4803e000 0x80>;
> -			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer9";
>  		};
>  
>  		timer10: timer@48086000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x48086000 0x80>;
> -			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer10";
>  		};
>  
>  		timer11: timer@48088000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x48088000 0x80>;
> -			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer11";
>  			ti,timer-pwm;
>  		};
> @@ -453,6 +457,7 @@
>  		timer13: timer@48828000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x48828000 0x80>;
> +			interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer13";
>  			status = "disabled";
>  		};
> @@ -460,6 +465,7 @@
>  		timer14: timer@4882a000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x4882a000 0x80>;
> +			interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer14";
>  			status = "disabled";
>  		};
> @@ -467,6 +473,7 @@
>  		timer15: timer@4882c000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x4882c000 0x80>;
> +			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer15";
>  			status = "disabled";
>  		};
> @@ -474,6 +481,7 @@
>  		timer16: timer@4882e000 {
>  			compatible = "ti,omap5430-timer";
>  			reg = <0x4882e000 0x80>;
> +			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "timer16";
>  			status = "disabled";
>  		};
> @@ -481,7 +489,7 @@
>  		wdt2: wdt@4ae14000 {
>  			compatible = "ti,omap4-wdt";
>  			reg = <0x4ae14000 0x80>;
> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "wd_timer2";
>  		};
>  
> @@ -495,14 +503,14 @@
>  		dmm@4e000000 {
>  			compatible = "ti,omap5-dmm";
>  			reg = <0x4e000000 0x800>;
> -			interrupts = <0 113 0x4>;
> +			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "dmm";
>  		};
>  
>  		i2c1: i2c@48070000 {
>  			compatible = "ti,omap4-i2c";
>  			reg = <0x48070000 0x100>;
> -			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "i2c1";
> @@ -512,7 +520,7 @@
>  		i2c2: i2c@48072000 {
>  			compatible = "ti,omap4-i2c";
>  			reg = <0x48072000 0x100>;
> -			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "i2c2";
> @@ -522,7 +530,7 @@
>  		i2c3: i2c@48060000 {
>  			compatible = "ti,omap4-i2c";
>  			reg = <0x48060000 0x100>;
> -			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "i2c3";
> @@ -532,7 +540,7 @@
>  		i2c4: i2c@4807a000 {
>  			compatible = "ti,omap4-i2c";
>  			reg = <0x4807a000 0x100>;
> -			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "i2c4";
> @@ -542,7 +550,7 @@
>  		i2c5: i2c@4807c000 {
>  			compatible = "ti,omap4-i2c";
>  			reg = <0x4807c000 0x100>;
> -			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "i2c5";
> @@ -552,7 +560,7 @@
>  		mmc1: mmc@4809c000 {
>  			compatible = "ti,omap4-hsmmc";
>  			reg = <0x4809c000 0x400>;
> -			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "mmc1";
>  			ti,dual-volt;
>  			ti,needs-special-reset;
> @@ -565,7 +573,7 @@
>  		mmc2: mmc@480b4000 {
>  			compatible = "ti,omap4-hsmmc";
>  			reg = <0x480b4000 0x400>;
> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "mmc2";
>  			ti,needs-special-reset;
>  			dmas = <&sdma 47>, <&sdma 48>;
> @@ -576,7 +584,7 @@
>  		mmc3: mmc@480ad000 {
>  			compatible = "ti,omap4-hsmmc";
>  			reg = <0x480ad000 0x400>;
> -			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "mmc3";
>  			ti,needs-special-reset;
>  			dmas = <&sdma 77>, <&sdma 78>;
> @@ -587,7 +595,7 @@
>  		mmc4: mmc@480d1000 {
>  			compatible = "ti,omap4-hsmmc";
>  			reg = <0x480d1000 0x400>;
> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
>  			ti,hwmods = "mmc4";
>  			ti,needs-special-reset;
>  			dmas = <&sdma 57>, <&sdma 58>;
> @@ -730,7 +738,7 @@
>  		mcspi1: spi@48098000 {
>  			compatible = "ti,omap4-mcspi";
>  			reg = <0x48098000 0x200>;
> -			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "mcspi1";
> @@ -751,7 +759,7 @@
>  		mcspi2: spi@4809a000 {
>  			compatible = "ti,omap4-mcspi";
>  			reg = <0x4809a000 0x200>;
> -			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "mcspi2";
> @@ -767,7 +775,7 @@
>  		mcspi3: spi@480b8000 {
>  			compatible = "ti,omap4-mcspi";
>  			reg = <0x480b8000 0x200>;
> -			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "mcspi3";
> @@ -780,7 +788,7 @@
>  		mcspi4: spi@480ba000 {
>  			compatible = "ti,omap4-mcspi";
>  			reg = <0x480ba000 0x200>;
> -			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "mcspi4";
> -- 
> 1.7.9.5
> 
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[PATCH V5 3/3] arm: dts: dra7: Add routable-irqs property for gic node

[Sricharan R]

There is a IRQ crossbar device in the soc, which maps the
irq requests from the peripherals to the mpu interrupt
controller's inputs. The gic provides the support for such
IPs in the form of routable-irqs. So adding the property
here to gic node.

Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
[V5] Rebased and corrected routable irqs from 160 to 192

 arch/arm/boot/dts/dra7.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 52e4bd0..cec826f 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -72,6 +72,7 @@
 		compatible = "arm,cortex-a15-gic";
 		interrupt-controller;
 		#interrupt-cells = <3>;
+		arm,routable-irqs = <192>;
 		reg = <0x48211000 0x1000>,
 		      <0x48212000 0x1000>,
 		      <0x48214000 0x2000>,
-- 
1.7.9.5

Re: [PATCH V5 0/3] arm: dts: dra7: Updates for adding crossbar device

[Darren Etheridge]

Sricharan R <r.sricharan@ti.com> wrote on Tue [2014-May-06 19:26:16 +0530]:
> Some socs have a large number of interrupts requests to service
> the needs of its many peripherals and subsystems. All of the interrupt
> requests lines from the subsystems are not needed at the same
> time, so they have to be muxed to the controllers appropriately.
> In such places a interrupt controllers are preceded by an
> IRQ CROSSBAR that provides flexibility in muxing the device interrupt
> requests to the controller inputs.
> 
> The dts file update to support the crossbar device and convert
> peripheral irq numbers to crossbar number are added here.
> 
> This is a rebase of V4 series on top of 3.15-rc4
> 
> This series depends on crossbar-driver-fixes sent below
> http://marc.info/?l=linux-omap&m=139929963420299&w=2
> 
> Sricharan R (3):
>   arm: dts: dra7: Add crossbar device binding
>   arm: dts: dra7: Replace peripheral interrupt numbers with crossbar
>     inputs
>   arm: dts: dra7: Add routable-irqs property for gic node
> 

OK, assuming the bisectability issues discussed earlier on this thread
are addressed.  I have tested the earlier crossbar patch series in
conjunction with this dts series with VIP capture and DSS display
running together on DRA7.  Looks good with this combination of
devices. VIP is one of the modules that must have a crossbar mapping as
there is no default interrupt mapping for it, therefore VIP makes a good
test case.

So please feel free to add:

Tested-by: Darren Etheridge <detheridge@ti.com>


>  arch/arm/boot/dts/dra7.dtsi |  109 +++++++++++++++++++++++++------------------
>  1 file changed, 63 insertions(+), 46 deletions(-)
> 
> -- 
> 1.7.9.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
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Re: [PATCH V5 0/3] arm: dts: dra7: Updates for adding crossbar device

[Sricharan R]

On Wednesday 07 May 2014 03:15 AM, Darren Etheridge wrote:
> Sricharan R <r.sricharan@ti.com> wrote on Tue [2014-May-06 19:26:16 +0530]:
>> Some socs have a large number of interrupts requests to service
>> the needs of its many peripherals and subsystems. All of the interrupt
>> requests lines from the subsystems are not needed at the same
>> time, so they have to be muxed to the controllers appropriately.
>> In such places a interrupt controllers are preceded by an
>> IRQ CROSSBAR that provides flexibility in muxing the device interrupt
>> requests to the controller inputs.
>>
>> The dts file update to support the crossbar device and convert
>> peripheral irq numbers to crossbar number are added here.
>>
>> This is a rebase of V4 series on top of 3.15-rc4
>>
>> This series depends on crossbar-driver-fixes sent below
>> http://marc.info/?l=linux-omap&m=139929963420299&w=2
>>
>> Sricharan R (3):
>>   arm: dts: dra7: Add crossbar device binding
>>   arm: dts: dra7: Replace peripheral interrupt numbers with crossbar
>>     inputs
>>   arm: dts: dra7: Add routable-irqs property for gic node
>>
> 
> OK, assuming the bisectability issues discussed earlier on this thread
> are addressed.  I have tested the earlier crossbar patch series in
> conjunction with this dts series with VIP capture and DSS display
> running together on DRA7.  Looks good with this combination of
> devices. VIP is one of the modules that must have a crossbar mapping as
> there is no default interrupt mapping for it, therefore VIP makes a good
> test case.
> 
> So please feel free to add:
> 
> Tested-by: Darren Etheridge <detheridge@ti.com>

  Thanks for the testing. Will reorder and repost.

Regards,
 Sricharan

Re: [PATCH V5 0/3] arm: dts: dra7: Updates for adding crossbar device

[Archit Taneja]

On Wednesday 07 May 2014 03:15 AM, Darren Etheridge wrote:
> Sricharan R <r.sricharan@ti.com> wrote on Tue [2014-May-06 19:26:16 +0530]:
>> Some socs have a large number of interrupts requests to service
>> the needs of its many peripherals and subsystems. All of the interrupt
>> requests lines from the subsystems are not needed at the same
>> time, so they have to be muxed to the controllers appropriately.
>> In such places a interrupt controllers are preceded by an
>> IRQ CROSSBAR that provides flexibility in muxing the device interrupt
>> requests to the controller inputs.
>>
>> The dts file update to support the crossbar device and convert
>> peripheral irq numbers to crossbar number are added here.
>>
>> This is a rebase of V4 series on top of 3.15-rc4
>>
>> This series depends on crossbar-driver-fixes sent below
>> http://marc.info/?l=linux-omap&m=139929963420299&w=2
>>
>> Sricharan R (3):
>>    arm: dts: dra7: Add crossbar device binding
>>    arm: dts: dra7: Replace peripheral interrupt numbers with crossbar
>>      inputs
>>    arm: dts: dra7: Add routable-irqs property for gic node
>>
>
> OK, assuming the bisectability issues discussed earlier on this thread
> are addressed.  I have tested the earlier crossbar patch series in
> conjunction with this dts series with VIP capture and DSS display
> running together on DRA7.  Looks good with this combination of
> devices. VIP is one of the modules that must have a crossbar mapping as
> there is no default interrupt mapping for it, therefore VIP makes a good
> test case.
>
> So please feel free to add:
>
> Tested-by: Darren Etheridge <detheridge@ti.com>

DMM doesn't get used by default since it's hwmod is missing in DRA7x's 
hwmod data. I added the hwmod and tried using dmm with omapdrm, it works 
fine.

So, for DSS and DMM:

Tested-by: Archit Taneja <archit@ti.com>

>
>
>>   arch/arm/boot/dts/dra7.dtsi |  109 +++++++++++++++++++++++++------------------
>>   1 file changed, 63 insertions(+), 46 deletions(-)
>>
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
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>

Re: [PATCH V5 0/3] arm: dts: dra7: Updates for adding crossbar device

[Roger Quadros]

On 05/06/2014 04:56 PM, Sricharan R wrote:
> Some socs have a large number of interrupts requests to service
> the needs of its many peripherals and subsystems. All of the interrupt
> requests lines from the subsystems are not needed at the same
> time, so they have to be muxed to the controllers appropriately.
> In such places a interrupt controllers are preceded by an
> IRQ CROSSBAR that provides flexibility in muxing the device interrupt
> requests to the controller inputs.
> 
> The dts file update to support the crossbar device and convert
> peripheral irq numbers to crossbar number are added here.
> 
> This is a rebase of V4 series on top of 3.15-rc4
> 
> This series depends on crossbar-driver-fixes sent below
> http://marc.info/?l=linux-omap&m=139929963420299&w=2

For USB and SATA

Tested-by: Roger Quadros <rogerq@ti.com>

NOTE: I've updated the USB and SATA patches on l-o list to work with this series.

cheers,
-roger

> 
> Sricharan R (3):
>   arm: dts: dra7: Add crossbar device binding
>   arm: dts: dra7: Replace peripheral interrupt numbers with crossbar
>     inputs
>   arm: dts: dra7: Add routable-irqs property for gic node
> 
>  arch/arm/boot/dts/dra7.dtsi |  109 +++++++++++++++++++++++++------------------
>  1 file changed, 63 insertions(+), 46 deletions(-)
>