* [PATCH 1/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12
[not found] ` <1399305223-18703-1-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
@ 2014-05-05 15:53 ` Gabriel FERNANDEZ
2014-05-06 7:18 ` Lee Jones
2014-05-05 15:53 ` [PATCH 5/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A9/DDR/GPU Gabriel FERNANDEZ
` (3 subsequent siblings)
4 siblings, 1 reply; 17+ messages in thread
From: Gabriel FERNANDEZ @ 2014-05-05 15:53 UTC (permalink / raw)
To: Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Lee Jones, Gabriel Fernandez,
Pankaj Dev
Patch adds DT entries for clockgen A0/1/10/11/12
Signed-off-by: Pankaj Dev <pankaj.dev-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/boot/dts/stih416-clks.h | 15 ++
arch/arm/boot/dts/stih416-clock.dtsi | 477 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih416.dtsi | 10 +-
3 files changed, 497 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/stih416-clks.h
diff --git a/arch/arm/boot/dts/stih416-clks.h b/arch/arm/boot/dts/stih416-clks.h
new file mode 100644
index 0000000..552c779
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-clks.h
@@ -0,0 +1,15 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH416 SoC.
+ */
+#ifndef _CLK_STIH416
+#define _CLK_STIH416
+
+/* CLOCKGEN A0 */
+#define CLK_ICN_REG 0
+#define CLK_ETH1_PHY 4
+
+/* CLOCKGEN A1 */
+#define CLK_GMAC0_PHY 3
+
+#endif
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index a6942c7..66693e4 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -6,8 +6,15 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+
+#include "stih416-clks.h"
+
/ {
clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
/*
* Fixed 30MHz oscillator inputs to SoC
*/
@@ -51,5 +58,475 @@
clock-frequency = <25000000>;
clock-output-names = "CLK_S_ETH1_PHY";
};
+
+ /*
+ * ClockGenAs on SASG2
+ */
+ clockgenA@fee62000 {
+ reg = <0xfee62000 0xb48>;
+
+ CLK_S_A0_PLL: CLK_S_A0_PLL {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-plls-c65";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_S_A0_PLL0_HS",
+ "CLK_S_A0_PLL0_LS",
+ "CLK_S_A0_PLL1";
+ };
+
+ CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
+ #clock-cells = <0>;
+ compatible = "st,clkgena-prediv-c65",
+ "st,clkgena-prediv";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_S_A0_OSC_PREDIV";
+ };
+
+ CLK_S_A0_HS: CLK_S_A0_HS {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c65-hs",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_S_A0_OSC_PREDIV>,
+ <&CLK_S_A0_PLL 0>, /* PLL0 HS */
+ <&CLK_S_A0_PLL 2>; /* PLL1 */
+
+ clock-output-names = "CLK_S_FDMA_0",
+ "CLK_S_FDMA_1",
+ ""; /* CLK_S_JIT_SENSE */
+ /* Fourth output unused */
+ };
+
+ CLK_S_A0_LS: CLK_S_A0_LS {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c65-ls",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_S_A0_OSC_PREDIV>,
+ <&CLK_S_A0_PLL 1>, /* PLL0 LS */
+ <&CLK_S_A0_PLL 2>; /* PLL1 */
+
+ clock-output-names = "CLK_S_ICN_REG_0",
+ "CLK_S_ICN_IF_0",
+ "CLK_S_ICN_REG_LP_0",
+ "CLK_S_EMISS",
+ "CLK_S_ETH1_PHY",
+ "CLK_S_MII_REF_OUT";
+ /* Remaining outputs unused */
+ };
+ };
+
+ clockgenA@fee81000 {
+ reg = <0xfee81000 0xb48>;
+
+ CLK_S_A1_PLL: CLK_S_A1_PLL {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-plls-c65";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_S_A1_PLL0_HS",
+ "CLK_S_A1_PLL0_LS",
+ "CLK_S_A1_PLL1";
+ };
+
+ CLK_S_A1_OSC_PREDIV: CLK_S_A1_OSC_PREDIV {
+ #clock-cells = <0>;
+ compatible = "st,clkgena-prediv-c65",
+ "st,clkgena-prediv";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_S_A1_OSC_PREDIV";
+ };
+
+ CLK_S_A1_HS: CLK_S_A1_HS {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c65-hs",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_S_A1_OSC_PREDIV>,
+ <&CLK_S_A1_PLL 0>, /* PLL0 HS */
+ <&CLK_S_A1_PLL 2>; /* PLL1 */
+
+ clock-output-names = "", /* Reserved */
+ "", /* Reserved */
+ "CLK_S_STAC_PHY",
+ "CLK_S_VTAC_TX_PHY";
+ };
+
+ CLK_S_A1_LS: CLK_S_A1_LS {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c65-ls",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_S_A1_OSC_PREDIV>,
+ <&CLK_S_A1_PLL 1>, /* PLL0 LS */
+ <&CLK_S_A1_PLL 2>; /* PLL1 */
+
+ clock-output-names = "CLK_S_ICN_IF_2",
+ "CLK_S_CARD_MMC_0",
+ "CLK_S_ICN_IF_1",
+ "CLK_S_GMAC0_PHY",
+ "CLK_S_NAND_CTRL",
+ "", /* Reserved */
+ "CLK_S_MII0_REF_OUT",
+ "CLK_S_STAC_SYS",
+ "CLK_S_CARD_MMC_1";
+ /* Remaining outputs unused */
+ };
+ };
+
+ /*
+ * ClockGenAs on MPE42
+ */
+ clockgenA@fde12000 {
+ reg = <0xfde12000 0xb50>;
+
+ CLK_M_A0_PLL0: CLK_M_A0_PLL0 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A0_PLL0_PHI0",
+ "CLK_M_A0_PLL0_PHI1",
+ "CLK_M_A0_PLL0_PHI2",
+ "CLK_M_A0_PLL0_PHI3";
+ };
+
+ CLK_M_A0_PLL1: CLK_M_A0_PLL1 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A0_PLL1_PHI0",
+ "CLK_M_A0_PLL1_PHI1",
+ "CLK_M_A0_PLL1_PHI2",
+ "CLK_M_A0_PLL1_PHI3";
+ };
+
+ CLK_M_A0_OSC_PREDIV: CLK_M_A0_OSC_PREDIV {
+ #clock-cells = <0>;
+ compatible = "st,clkgena-prediv-c32",
+ "st,clkgena-prediv";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A0_OSC_PREDIV";
+ };
+
+ CLK_M_A0_DIV0: CLK_M_A0_DIV0 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf0",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A0_OSC_PREDIV>,
+ <&CLK_M_A0_PLL0 0>, /* PLL0 PHI0 */
+ <&CLK_M_A0_PLL1 0>; /* PLL1 PHI0 */
+
+ clock-output-names = "", /* Unused */
+ "", /* Unused */
+ "CLK_M_FDMA_12",
+ "", /* Unused */
+ "CLK_M_PP_DMU_0",
+ "CLK_M_PP_DMU_1",
+ "CLK_M_ICM_LMI",
+ "CLK_M_VID_DMU_0";
+ };
+
+ CLK_M_A0_DIV1: CLK_M_A0_DIV1 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf1",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A0_OSC_PREDIV>,
+ <&CLK_M_A0_PLL0 1>, /* PLL0 PHI1 */
+ <&CLK_M_A0_PLL1 1>; /* PLL1 PHI1 */
+
+ clock-output-names = "CLK_M_VID_DMU_1",
+ "", /* Unused */
+ "CLK_M_A9_EXT2F",
+ "CLK_M_ST40RT",
+ "CLK_M_ST231_DMU_0",
+ "CLK_M_ST231_DMU_1",
+ "CLK_M_ST231_AUD",
+ "CLK_M_ST231_GP_0";
+ };
+
+ CLK_M_A0_DIV2: CLK_M_A0_DIV2 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf2",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A0_OSC_PREDIV>,
+ <&CLK_M_A0_PLL0 2>, /* PLL0 PHI2 */
+ <&CLK_M_A0_PLL1 2>; /* PLL1 PHI2 */
+
+ clock-output-names = "CLK_M_ST231_GP_1",
+ "CLK_M_ICN_CPU",
+ "CLK_M_ICN_STAC",
+ "CLK_M_TX_ICN_DMU_0",
+ "CLK_M_TX_ICN_DMU_1",
+ "CLK_M_TX_ICN_TS",
+ "CLK_M_ICN_VDP_0",
+ "CLK_M_ICN_VDP_1";
+ };
+
+ CLK_M_A0_DIV3: CLK_M_A0_DIV3 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf3",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A0_OSC_PREDIV>,
+ <&CLK_M_A0_PLL0 3>, /* PLL0 PHI3 */
+ <&CLK_M_A0_PLL1 3>; /* PLL1 PHI3 */
+
+ clock-output-names = "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "CLK_M_ICN_VP8",
+ "", /* Unused */
+ "CLK_M_ICN_REG_11",
+ "CLK_M_A9_TRACE";
+ };
+ };
+
+ clockgenA@fd6db000 {
+ reg = <0xfd6db000 0xb50>;
+
+ CLK_M_A1_PLL0: CLK_M_A1_PLL0 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A1_PLL0_PHI0",
+ "CLK_M_A1_PLL0_PHI1",
+ "CLK_M_A1_PLL0_PHI2",
+ "CLK_M_A1_PLL0_PHI3";
+ };
+
+ CLK_M_A1_PLL1: CLK_M_A1_PLL1 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A1_PLL1_PHI0",
+ "CLK_M_A1_PLL1_PHI1",
+ "CLK_M_A1_PLL1_PHI2",
+ "CLK_M_A1_PLL1_PHI3";
+ };
+
+ CLK_M_A1_OSC_PREDIV: CLK_M_A1_OSC_PREDIV {
+ #clock-cells = <0>;
+ compatible = "st,clkgena-prediv-c32",
+ "st,clkgena-prediv";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A1_OSC_PREDIV";
+ };
+
+ CLK_M_A1_DIV0: CLK_M_A1_DIV0 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf0",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A1_OSC_PREDIV>,
+ <&CLK_M_A1_PLL0 0>, /* PLL0 PHI0 */
+ <&CLK_M_A1_PLL1 0>; /* PLL1 PHI0 */
+
+ clock-output-names = "", /* Unused */
+ "CLK_M_FDMA_10",
+ "CLK_M_FDMA_11",
+ "CLK_M_HVA_ALT",
+ "CLK_M_PROC_SC",
+ "CLK_M_TP",
+ "CLK_M_RX_ICN_DMU_0",
+ "CLK_M_RX_ICN_DMU_1";
+ };
+
+ CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf1",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A1_OSC_PREDIV>,
+ <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
+ <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
+
+ clock-output-names = "CLK_M_RX_ICN_TS",
+ "CLK_M_RX_ICN_VDP_0",
+ "", /* Unused */
+ "CLK_M_PRV_T1_BUS",
+ "CLK_M_ICN_REG_12",
+ "CLK_M_ICN_REG_10",
+ "", /* Unused */
+ "CLK_M_ICN_ST231";
+ };
+
+ CLK_M_A1_DIV2: CLK_M_A1_DIV2 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf2",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A1_OSC_PREDIV>,
+ <&CLK_M_A1_PLL0 2>, /* PLL0 PHI2 */
+ <&CLK_M_A1_PLL1 2>; /* PLL1 PHI2 */
+
+ clock-output-names = "CLK_M_FVDP_PROC_ALT",
+ "CLK_M_ICN_REG_13",
+ "CLK_M_TX_ICN_GPU",
+ "CLK_M_RX_ICN_GPU",
+ "", /* Unused */
+ "", /* Unused */
+ "", /* CLK_M_APB_PM_12 */
+ ""; /* Unused */
+ };
+
+ CLK_M_A1_DIV3: CLK_M_A1_DIV3 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf3",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A1_OSC_PREDIV>,
+ <&CLK_M_A1_PLL0 3>, /* PLL0 PHI3 */
+ <&CLK_M_A1_PLL1 3>; /* PLL1 PHI3 */
+
+ clock-output-names = "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ ""; /* CLK_M_GPU_ALT */
+ };
+ };
+
+ CLK_M_A9_EXT2F_DIV2: CLK_M_A9_EXT2F_DIV2S {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_M_A0_DIV1 2>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ clockgenA@fd345000 {
+ reg = <0xfd345000 0xb50>;
+
+ CLK_M_A2_PLL0: CLK_M_A2_PLL0 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A2_PLL0_PHI0",
+ "CLK_M_A2_PLL0_PHI1",
+ "CLK_M_A2_PLL0_PHI2",
+ "CLK_M_A2_PLL0_PHI3";
+ };
+
+ CLK_M_A2_PLL1: CLK_M_A2_PLL1 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A2_PLL1_PHI0",
+ "CLK_M_A2_PLL1_PHI1",
+ "CLK_M_A2_PLL1_PHI2",
+ "CLK_M_A2_PLL1_PHI3";
+ };
+
+ CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
+ #clock-cells = <0>;
+ compatible = "st,clkgena-prediv-c32",
+ "st,clkgena-prediv";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A2_OSC_PREDIV";
+ };
+
+ CLK_M_A2_DIV0: CLK_M_A2_DIV0 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf0",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A2_OSC_PREDIV>,
+ <&CLK_M_A2_PLL0 0>, /* PLL0 PHI0 */
+ <&CLK_M_A2_PLL1 0>; /* PLL1 PHI0 */
+
+ clock-output-names = "CLK_M_VTAC_MAIN_PHY",
+ "CLK_M_VTAC_AUX_PHY",
+ "CLK_M_STAC_PHY",
+ "CLK_M_STAC_SYS",
+ "", /* CLK_M_MPESTAC_PG */
+ "", /* CLK_M_MPESTAC_WC */
+ "", /* CLK_M_MPEVTACAUX_PG*/
+ ""; /* CLK_M_MPEVTACMAIN_PG*/
+ };
+
+ CLK_M_A2_DIV1: CLK_M_A2_DIV1 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf1",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A2_OSC_PREDIV>,
+ <&CLK_M_A2_PLL0 1>, /* PLL0 PHI1 */
+ <&CLK_M_A2_PLL1 1>; /* PLL1 PHI1 */
+
+ clock-output-names = "", /* CLK_M_MPEVTACRX0_WC */
+ "", /* CLK_M_MPEVTACRX1_WC */
+ "CLK_M_COMPO_MAIN",
+ "CLK_M_COMPO_AUX",
+ "CLK_M_BDISP_0",
+ "CLK_M_BDISP_1",
+ "CLK_M_ICN_BDISP",
+ "CLK_M_ICN_COMPO";
+ };
+
+ CLK_M_A2_DIV2: CLK_M_A2_DIV2 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf2",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A2_OSC_PREDIV>,
+ <&CLK_M_A2_PLL0 2>, /* PLL0 PHI2 */
+ <&CLK_M_A2_PLL1 2>; /* PLL1 PHI2 */
+
+ clock-output-names = "CLK_M_ICN_VDP_2",
+ "", /* Unused */
+ "CLK_M_ICN_REG_14",
+ "CLK_M_MDTP",
+ "CLK_M_JPEGDEC",
+ "", /* Unused */
+ "CLK_M_DCEPHY_IMPCTRL",
+ ""; /* Unused */
+ };
+
+ CLK_M_A2_DIV3: CLK_M_A2_DIV3 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf3",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A2_OSC_PREDIV>,
+ <&CLK_M_A2_PLL0 3>, /* PLL0 PHI3 */
+ <&CLK_M_A2_PLL1 3>; /* PLL1 PHI3 */
+
+ clock-output-names = "", /* Unused */
+ ""; /* CLK_M_APB_PM_11 */
+ /* Remaining outputs unused */
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 78746d2..f5e888e 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -89,7 +89,7 @@
status = "disabled";
reg = <0xfed32000 0x2c>;
interrupts = <0 197 0>;
- clocks = <&CLK_S_ICN_REG_0>;
+ clocks = <&CLK_S_A0_LS CLK_ICN_REG>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>;
};
@@ -109,7 +109,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfed40000 0x110>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CLK_S_ICN_REG_0>;
+ clocks = <&CLK_S_A0_LS CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -122,7 +122,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfed41000 0x110>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CLK_S_ICN_REG_0>;
+ clocks = <&CLK_S_A0_LS CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -176,7 +176,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii0>;
clock-names = "stmmaceth";
- clocks = <&CLK_S_GMAC0_PHY>;
+ clocks = <&CLK_S_A1_LS CLK_GMAC0_PHY>;
};
ethernet1: dwmac@fef08000 {
@@ -198,7 +198,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii1>;
clock-names = "stmmaceth";
- clocks = <&CLK_S_ETH1_PHY>;
+ clocks = <&CLK_S_A0_LS CLK_ETH1_PHY>;
};
rc: rc@fe518000 {
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12
2014-05-05 15:53 ` [PATCH 1/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12 Gabriel FERNANDEZ
@ 2014-05-06 7:18 ` Lee Jones
2014-05-06 8:20 ` Gabriel Fernandez
0 siblings, 1 reply; 17+ messages in thread
From: Lee Jones @ 2014-05-06 7:18 UTC (permalink / raw)
To: Gabriel FERNANDEZ
Cc: Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, linux-arm-kernel, kernel, devicetree, linux-kernel,
Gabriel Fernandez, Pankaj Dev
> Patch adds DT entries for clockgen A0/1/10/11/12
>
> Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
> arch/arm/boot/dts/stih416-clks.h | 15 ++
This should live in include/dt-bindings/clk
> arch/arm/boot/dts/stih416-clock.dtsi | 477 ++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/stih416.dtsi | 10 +-
> 3 files changed, 497 insertions(+), 5 deletions(-)
> create mode 100644 arch/arm/boot/dts/stih416-clks.h
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12
2014-05-06 7:18 ` Lee Jones
@ 2014-05-06 8:20 ` Gabriel Fernandez
[not found] ` <CAG374jD+msPPbPtFS+ji=8jS9+D-YHu31k7zzzC7Ty7jw9n7jQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 17+ messages in thread
From: Gabriel Fernandez @ 2014-05-06 8:20 UTC (permalink / raw)
To: Lee Jones
Cc: Mark Rutland, devicetree, Russell King, kernel, Pawel Moll,
Ian Campbell, Srinivas Kandagatla, Patrice Chotard, linux-kernel,
Rob Herring, Kumar Gala, Pankaj Dev, Gabriel FERNANDEZ,
linux-arm-kernel, Maxime Coquelin
Hi Lee,
On 6 May 2014 09:18, Lee Jones <lee.jones@linaro.org> wrote:
>> Patch adds DT entries for clockgen A0/1/10/11/12
>>
>> Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> ---
>> arch/arm/boot/dts/stih416-clks.h | 15 ++
>
> This should live in include/dt-bindings/clk
>
include/dt-bindings/clk or include/dt-bindings/clock ?
>> arch/arm/boot/dts/stih416-clock.dtsi | 477 ++++++++++++++++++++++++++++++++++
>> arch/arm/boot/dts/stih416.dtsi | 10 +-
>> 3 files changed, 497 insertions(+), 5 deletions(-)
>> create mode 100644 arch/arm/boot/dts/stih416-clks.h
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
Best regards
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A9/DDR/GPU
[not found] ` <1399305223-18703-1-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-05-05 15:53 ` [PATCH 1/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12 Gabriel FERNANDEZ
@ 2014-05-05 15:53 ` Gabriel FERNANDEZ
2014-05-05 15:53 ` [PATCH 6/9] ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12 Gabriel FERNANDEZ
` (2 subsequent siblings)
4 siblings, 0 replies; 17+ messages in thread
From: Gabriel FERNANDEZ @ 2014-05-05 15:53 UTC (permalink / raw)
To: Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Lee Jones, Gabriel Fernandez,
Pankaj Dev
Patch adds DT entries for clockgen A9/DDR/GPU
Signed-off-by: Pankaj Dev <pankaj.dev-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/boot/dts/stih416-clock.dtsi | 79 ++++++++++++++++++++++++++++++++----
1 file changed, 70 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index 7ff107b..d68860f 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -26,15 +26,6 @@
};
/*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: arm_periph_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <600000000>;
- };
-
- /*
* ClockGenAs on SASG2
*/
clockgenA@fee62000 {
@@ -505,6 +496,45 @@
};
/*
+ * A9 PLL
+ */
+ clockgenA9 {
+ reg = <0xfdde08b0 0x70>;
+
+ CLOCKGEN_A9_PLL: CLOCKGEN_A9_PLL {
+ #clock-cells = <1>;
+ compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+ clock-output-names = "CLOCKGEN_A9_PLL_ODF";
+ };
+ };
+
+ /*
+ * ARM CPU related clocks
+ */
+ CLK_M_A9: CLK_M_A9 {
+ #clock-cells = <0>;
+ compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux";
+ reg = <0xfdde08ac 0x4>;
+ clocks = <&CLOCKGEN_A9_PLL 0>,
+ <&CLOCKGEN_A9_PLL 0>,
+ <&CLK_M_A0_DIV1 2>,
+ <&CLK_M_A9_EXT2F_DIV2>;
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: CLK_M_A9_PERIPHS {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_M_A9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /*
* Frequency synthesizers on the SASG2
*/
CLOCKGEN_B0: CLOCKGEN_B0 {
@@ -692,5 +722,36 @@
"CLK_M_PIX_HDMIRX_0",
"CLK_M_PIX_HDMIRX_1";
};
+
+ /*
+ * DDR PLL
+ */
+ clockgenDDR {
+ reg = <0xfdde07d8 0x110>;
+
+ CLOCKGEN_DDR_PLL: CLOCKGEN_DDR_PLL {
+ #clock-cells = <1>;
+ compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+ clock-output-names = "CLOCKGEN_DDR0",
+ "CLOCKGEN_DDR1";
+ };
+ };
+
+ /*
+ * GPU PLL
+ */
+ clockgenGPU {
+ reg = <0xfd68ff00 0x910>;
+
+ CLOCKGEN_GPU_PLL: CLOCKGEN_GPU_PLL {
+ #clock-cells = <1>;
+ compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32";
+
+ clocks = <&CLK_SYSIN>;
+ clock-output-names = "CLOCKGEN_GPU_PLL";
+ };
+ };
};
};
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 6/9] ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12
[not found] ` <1399305223-18703-1-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-05-05 15:53 ` [PATCH 1/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12 Gabriel FERNANDEZ
2014-05-05 15:53 ` [PATCH 5/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A9/DDR/GPU Gabriel FERNANDEZ
@ 2014-05-05 15:53 ` Gabriel FERNANDEZ
2014-05-06 7:20 ` Lee Jones
2014-05-05 15:53 ` [PATCH 8/9] ARM: STi: DT: STiH415: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed clocks Gabriel FERNANDEZ
2014-05-14 11:46 ` [PATCH 0/9] ARM: STi: Add Clock driver support STiH415 & STiH416 Maxime Coquelin
4 siblings, 1 reply; 17+ messages in thread
From: Gabriel FERNANDEZ @ 2014-05-05 15:53 UTC (permalink / raw)
To: Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Lee Jones, Gabriel Fernandez,
Pankaj Dev
Patch adds DT entries for clockgen A0/1/10/11/12
Signed-off-by: Pankaj Dev <pankaj.dev-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/boot/dts/stih415-clks.h | 15 ++
arch/arm/boot/dts/stih415-clock.dtsi | 475 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 10 +-
3 files changed, 495 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/stih415-clks.h
diff --git a/arch/arm/boot/dts/stih415-clks.h b/arch/arm/boot/dts/stih415-clks.h
new file mode 100644
index 0000000..0d2c739
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-clks.h
@@ -0,0 +1,15 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH415 SoC.
+ */
+#ifndef _CLK_STIH415
+#define _CLK_STIH415
+
+/* CLOCKGEN A0 */
+#define CLK_ICN_REG 0
+#define CLK_ETH1_PHY 4
+
+/* CLOCKGEN A1 */
+#define CLK_GMAC0_PHY 3
+
+#endif
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index d047dbc..f67762d7a 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -5,8 +5,15 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+
+#include "stih415-clks.h"
+
/ {
clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
/*
* Fixed 30MHz oscillator input to SoC
*/
@@ -48,5 +55,473 @@
clock-frequency = <25000000>;
clock-output-names = "CLKS_ETH1_PHY";
};
+
+ /*
+ * ClockGenAs on SASG1
+ */
+ clockgenA@fee62000 {
+ reg = <0xfee62000 0xb48>;
+
+ CLK_S_A0_PLL: CLK_S_A0_PLL {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-plls-c65";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_S_A0_PLL0_HS",
+ "CLK_S_A0_PLL0_LS",
+ "CLK_S_A0_PLL1";
+ };
+
+ CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
+ #clock-cells = <0>;
+ compatible = "st,clkgena-prediv-c65",
+ "st,clkgena-prediv";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_S_A0_OSC_PREDIV";
+ };
+
+ CLK_S_A0_HS: CLK_S_A0_HS {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c65-hs",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_S_A0_OSC_PREDIV>,
+ <&CLK_S_A0_PLL 0>, /* PLL0 HS */
+ <&CLK_S_A0_PLL 2>; /* PLL1 */
+
+ clock-output-names = "CLK_S_FDMA_0",
+ "CLK_S_FDMA_1",
+ ""; /* CLK_S_JIT_SENSE */
+ /* Fourth output unused */
+ };
+
+ CLK_S_A0_LS: CLK_S_A0_LS {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c65-ls",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_S_A0_OSC_PREDIV>,
+ <&CLK_S_A0_PLL 1>, /* PLL0 LS */
+ <&CLK_S_A0_PLL 2>; /* PLL1 */
+
+ clock-output-names = "CLK_S_ICN_REG_0",
+ "CLK_S_ICN_IF_0",
+ "CLK_S_ICN_REG_LP_0",
+ "CLK_S_EMISS",
+ "CLK_S_ETH1_PHY",
+ "CLK_S_MII_REF_OUT";
+ /* Remaining outputs unused */
+ };
+ };
+
+ clockgenA@fee81000 {
+ reg = <0xfee81000 0xb48>;
+
+ CLK_S_A1_PLL: CLK_S_A1_PLL {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-plls-c65";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_S_A1_PLL0_HS",
+ "CLK_S_A1_PLL0_LS",
+ "CLK_S_A1_PLL1";
+ };
+
+ CLK_S_A1_OSC_PREDIV: CLK_S_A1_OSC_PREDIV {
+ #clock-cells = <0>;
+ compatible = "st,clkgena-prediv-c65",
+ "st,clkgena-prediv";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_S_A1_OSC_PREDIV";
+ };
+
+ CLK_S_A1_HS: CLK_S_A1_HS {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c65-hs",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_S_A1_OSC_PREDIV>,
+ <&CLK_S_A1_PLL 0>, /* PLL0 HS */
+ <&CLK_S_A1_PLL 2>; /* PLL1 */
+
+ clock-output-names = "", /* Reserved */
+ "", /* Reserved */
+ "CLK_S_STAC_PHY",
+ "CLK_S_VTAC_TX_PHY";
+ };
+
+ CLK_S_A1_LS: CLK_S_A1_LS {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c65-ls",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_S_A1_OSC_PREDIV>,
+ <&CLK_S_A1_PLL 1>, /* PLL0 LS */
+ <&CLK_S_A1_PLL 2>; /* PLL1 */
+
+ clock-output-names = "CLK_S_ICN_IF_2",
+ "CLK_S_CARD_MMC",
+ "CLK_S_ICN_IF_1",
+ "CLK_S_GMAC0_PHY",
+ "CLK_S_NAND_CTRL",
+ "", /* Reserved */
+ "CLK_S_MII0_REF_OUT",
+ ""; /* CLK_S_STAC_SYS */
+ /* Remaining outputs unused */
+ };
+ };
+
+ /*
+ * ClockGenAs on MPE41
+ */
+ clockgenA@fde12000 {
+ reg = <0xfde12000 0xb50>;
+
+ CLK_M_A0_PLL0: CLK_M_A0_PLL0 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A0_PLL0_PHI0",
+ "CLK_M_A0_PLL0_PHI1",
+ "CLK_M_A0_PLL0_PHI2",
+ "CLK_M_A0_PLL0_PHI3";
+ };
+
+ CLK_M_A0_PLL1: CLK_M_A0_PLL1 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A0_PLL1_PHI0",
+ "CLK_M_A0_PLL1_PHI1",
+ "CLK_M_A0_PLL1_PHI2",
+ "CLK_M_A0_PLL1_PHI3";
+ };
+
+ CLK_M_A0_OSC_PREDIV: CLK_M_A0_OSC_PREDIV {
+ #clock-cells = <0>;
+ compatible = "st,clkgena-prediv-c32",
+ "st,clkgena-prediv";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A0_OSC_PREDIV";
+ };
+
+ CLK_M_A0_DIV0: CLK_M_A0_DIV0 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf0",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A0_OSC_PREDIV>,
+ <&CLK_M_A0_PLL0 0>, /* PLL0 PHI0 */
+ <&CLK_M_A0_PLL1 0>; /* PLL1 PHI0 */
+
+ clock-output-names = "CLK_M_APB_PM", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "CLK_M_PP_DMU_0",
+ "CLK_M_PP_DMU_1",
+ "CLK_M_ICM_DISP",
+ ""; /* Unused */
+ };
+
+ CLK_M_A0_DIV1: CLK_M_A0_DIV1 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf1",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A0_OSC_PREDIV>,
+ <&CLK_M_A0_PLL0 1>, /* PLL0 PHI1 */
+ <&CLK_M_A0_PLL1 1>; /* PLL1 PHI1 */
+
+ clock-output-names = "", /* Unused */
+ "", /* Unused */
+ "CLK_M_A9_EXT2F",
+ "CLK_M_ST40RT",
+ "CLK_M_ST231_DMU_0",
+ "CLK_M_ST231_DMU_1",
+ "CLK_M_ST231_AUD",
+ "CLK_M_ST231_GP_0";
+ };
+
+ CLK_M_A0_DIV2: CLK_M_A0_DIV2 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf2",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A0_OSC_PREDIV>,
+ <&CLK_M_A0_PLL0 2>, /* PLL0 PHI2 */
+ <&CLK_M_A0_PLL1 2>; /* PLL1 PHI2 */
+
+ clock-output-names = "CLK_M_ST231_GP_1",
+ "CLK_M_ICN_CPU",
+ "CLK_M_ICN_STAC",
+ "CLK_M_ICN_DMU_0",
+ "CLK_M_ICN_DMU_1",
+ "", /* Unused */
+ "", /* Unused */
+ ""; /* Unused */
+ };
+
+ CLK_M_A0_DIV3: CLK_M_A0_DIV3 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf3",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A0_OSC_PREDIV>,
+ <&CLK_M_A0_PLL0 3>, /* PLL0 PHI3 */
+ <&CLK_M_A0_PLL1 3>; /* PLL1 PHI3 */
+
+ clock-output-names = "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "CLK_M_ICN_ERAM",
+ "CLK_M_A9_TRACE";
+ };
+ };
+
+ clockgenA@fd6db000 {
+ reg = <0xfd6db000 0xb50>;
+
+ CLK_M_A1_PLL0: CLK_M_A1_PLL0 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A1_PLL0_PHI0",
+ "CLK_M_A1_PLL0_PHI1",
+ "CLK_M_A1_PLL0_PHI2",
+ "CLK_M_A1_PLL0_PHI3";
+ };
+
+ CLK_M_A1_PLL1: CLK_M_A1_PLL1 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A1_PLL1_PHI0",
+ "CLK_M_A1_PLL1_PHI1",
+ "CLK_M_A1_PLL1_PHI2",
+ "CLK_M_A1_PLL1_PHI3";
+ };
+
+ CLK_M_A1_OSC_PREDIV: CLK_M_A1_OSC_PREDIV {
+ #clock-cells = <0>;
+ compatible = "st,clkgena-prediv-c32",
+ "st,clkgena-prediv";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A1_OSC_PREDIV";
+ };
+
+ CLK_M_A1_DIV0: CLK_M_A1_DIV0 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf0",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A1_OSC_PREDIV>,
+ <&CLK_M_A1_PLL0 0>, /* PLL0 PHI0 */
+ <&CLK_M_A1_PLL1 0>; /* PLL1 PHI0 */
+
+ clock-output-names = "CLK_M_FDMA_12",
+ "CLK_M_FDMA_10",
+ "CLK_M_FDMA_11",
+ "CLK_M_HVA_LMI",
+ "CLK_M_PROC_SC",
+ "CLK_M_TP",
+ "CLK_M_ICN_GPU",
+ "CLK_M_ICN_VDP_0";
+ };
+
+ CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf1",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A1_OSC_PREDIV>,
+ <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
+ <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
+
+ clock-output-names = "CLK_M_ICN_VDP_1",
+ "CLK_M_ICN_VDP_2",
+ "CLK_M_ICN_VDP_3",
+ "CLK_M_PRV_T1_BUS",
+ "CLK_M_ICN_VDP_4",
+ "CLK_M_ICN_REG_10",
+ "", /* Unused */
+ ""; /* CLK_M_ICN_ST231 */
+ };
+
+ CLK_M_A1_DIV2: CLK_M_A1_DIV2 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf2",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A1_OSC_PREDIV>,
+ <&CLK_M_A1_PLL0 2>, /* PLL0 PHI2 */
+ <&CLK_M_A1_PLL1 2>; /* PLL1 PHI2 */
+
+ clock-output-names = "CLK_M_FVDP_PROC_ALT",
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ ""; /* Unused */
+ };
+
+ CLK_M_A1_DIV3: CLK_M_A1_DIV3 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf3",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A1_OSC_PREDIV>,
+ <&CLK_M_A1_PLL0 3>, /* PLL0 PHI3 */
+ <&CLK_M_A1_PLL1 3>; /* PLL1 PHI3 */
+
+ clock-output-names = "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ "", /* Unused */
+ ""; /* Unused */
+ };
+ };
+
+ CLK_M_A9_EXT2F_DIV2: CLK_M_A9_EXT2F_DIV2S {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_M_A0_DIV1 2>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ clockgenA@fd345000 {
+ reg = <0xfd345000 0xb50>;
+
+ CLK_M_A2_PLL0: CLK_M_A2_PLL0 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A2_PLL0_PHI0",
+ "CLK_M_A2_PLL0_PHI1",
+ "CLK_M_A2_PLL0_PHI2",
+ "CLK_M_A2_PLL0_PHI3";
+ };
+
+ CLK_M_A2_PLL1: CLK_M_A2_PLL1 {
+ #clock-cells = <1>;
+ compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A2_PLL1_PHI0",
+ "CLK_M_A2_PLL1_PHI1",
+ "CLK_M_A2_PLL1_PHI2",
+ "CLK_M_A2_PLL1_PHI3";
+ };
+
+ CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
+ #clock-cells = <0>;
+ compatible = "st,clkgena-prediv-c32",
+ "st,clkgena-prediv";
+
+ clocks = <&CLK_SYSIN>;
+
+ clock-output-names = "CLK_M_A2_OSC_PREDIV";
+ };
+
+ CLK_M_A2_DIV0: CLK_M_A2_DIV0 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf0",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A2_OSC_PREDIV>,
+ <&CLK_M_A2_PLL0 0>, /* PLL0 PHI0 */
+ <&CLK_M_A2_PLL1 0>; /* PLL1 PHI0 */
+
+ clock-output-names = "CLK_M_VTAC_MAIN_PHY",
+ "CLK_M_VTAC_AUX_PHY",
+ "CLK_M_STAC_PHY",
+ "CLK_M_STAC_SYS",
+ "", /* CLK_M_MPESTAC_PG */
+ "", /* CLK_M_MPESTAC_WC */
+ "", /* CLK_M_MPEVTACAUX_PG*/
+ ""; /* CLK_M_MPEVTACMAIN_PG*/
+ };
+
+ CLK_M_A2_DIV1: CLK_M_A2_DIV1 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf1",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A2_OSC_PREDIV>,
+ <&CLK_M_A2_PLL0 1>, /* PLL0 PHI1 */
+ <&CLK_M_A2_PLL1 1>; /* PLL1 PHI1 */
+
+ clock-output-names = "", /* CLK_M_MPEVTACRX0_WC */
+ "", /* CLK_M_MPEVTACRX1_WC */
+ "CLK_M_COMPO_MAIN",
+ "CLK_M_COMPO_AUX",
+ "CLK_M_BDISP_0",
+ "CLK_M_BDISP_1",
+ "CLK_M_ICN_BDISP_0",
+ "CLK_M_ICN_BDISP_1";
+ };
+
+ CLK_M_A2_DIV2: CLK_M_A2_DIV2 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf2",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A2_OSC_PREDIV>,
+ <&CLK_M_A2_PLL0 2>, /* PLL0 PHI2 */
+ <&CLK_M_A2_PLL1 2>; /* PLL1 PHI2 */
+
+ clock-output-names = "", /* CLK_M_ICN_HQVDP0 */
+ "", /* CLK_M_ICN_HQVDP1 */
+ "CLK_M_ICN_COMPO",
+ "", /* CLK_M_ICN_VDPAUX */
+ "CLK_M_ICN_TS",
+ "CLK_M_ICN_REG_LP_10",
+ "CLK_M_DCEPHY_IMPCTRL",
+ ""; /* Unused */
+ };
+
+ CLK_M_A2_DIV3: CLK_M_A2_DIV3 {
+ #clock-cells = <1>;
+ compatible = "st,clkgena-divmux-c32-odf3",
+ "st,clkgena-divmux";
+
+ clocks = <&CLK_M_A2_OSC_PREDIV>,
+ <&CLK_M_A2_PLL0 3>, /* PLL0 PHI3 */
+ <&CLK_M_A2_PLL1 3>; /* PLL1 PHI3 */
+
+ clock-output-names = ""; /* Unused */
+ /* Remaining outputs unused */
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d89064c..3b69550 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -82,7 +82,7 @@
interrupts = <0 197 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2>;
- clocks = <&CLKS_ICN_REG_0>;
+ clocks = <&CLK_S_A0_LS CLK_ICN_REG>;
};
/* SBC comms block ASCs in SASG1 */
@@ -100,7 +100,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfed40000 0x110>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CLKS_ICN_REG_0>;
+ clocks = <&CLK_S_A0_LS CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -113,7 +113,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfed41000 0x110>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CLKS_ICN_REG_0>;
+ clocks = <&CLK_S_A0_LS CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -170,7 +170,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii0>;
clock-names = "stmmaceth";
- clocks = <&CLKS_GMAC0_PHY>;
+ clocks = <&CLK_S_A1_LS CLK_GMAC0_PHY>;
};
ethernet1: dwmac@fef08000 {
@@ -193,7 +193,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii1>;
clock-names = "stmmaceth";
- clocks = <&CLKS_ETH1_PHY>;
+ clocks = <&CLK_S_A0_LS CLK_ETH1_PHY>;
};
rc: rc@fe518000 {
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 6/9] ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12
2014-05-05 15:53 ` [PATCH 6/9] ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12 Gabriel FERNANDEZ
@ 2014-05-06 7:20 ` Lee Jones
0 siblings, 0 replies; 17+ messages in thread
From: Lee Jones @ 2014-05-06 7:20 UTC (permalink / raw)
To: Gabriel FERNANDEZ
Cc: Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, linux-arm-kernel, kernel, devicetree, linux-kernel,
Gabriel Fernandez, Pankaj Dev
> Patch adds DT entries for clockgen A0/1/10/11/12
>
> Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
> arch/arm/boot/dts/stih415-clks.h | 15 ++
Move to include/dt-bindings/clk.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 8/9] ARM: STi: DT: STiH415: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed clocks
[not found] ` <1399305223-18703-1-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
` (2 preceding siblings ...)
2014-05-05 15:53 ` [PATCH 6/9] ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12 Gabriel FERNANDEZ
@ 2014-05-05 15:53 ` Gabriel FERNANDEZ
2014-05-14 11:46 ` [PATCH 0/9] ARM: STi: Add Clock driver support STiH415 & STiH416 Maxime Coquelin
4 siblings, 0 replies; 17+ messages in thread
From: Gabriel FERNANDEZ @ 2014-05-05 15:53 UTC (permalink / raw)
To: Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Lee Jones, Gabriel Fernandez
CLK_S_GMAC0_PHY & CLK_S_ETH1_PH clocks are no longer used.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/boot/dts/stih415-clock.dtsi | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index 5bdba06..24a7508 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -32,20 +32,6 @@
clock-frequency = <500000000>;
};
- CLKS_GMAC0_PHY: clockgenA1@7 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <25000000>;
- clock-output-names = "CLKS_GMAC0_PHY";
- };
-
- CLKS_ETH1_PHY: clockgenA0@7 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <25000000>;
- clock-output-names = "CLKS_ETH1_PHY";
- };
-
/*
* ClockGenAs on SASG1
*/
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 0/9] ARM: STi: Add Clock driver support STiH415 & STiH416
[not found] ` <1399305223-18703-1-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
` (3 preceding siblings ...)
2014-05-05 15:53 ` [PATCH 8/9] ARM: STi: DT: STiH415: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed clocks Gabriel FERNANDEZ
@ 2014-05-14 11:46 ` Maxime Coquelin
4 siblings, 0 replies; 17+ messages in thread
From: Maxime Coquelin @ 2014-05-14 11:46 UTC (permalink / raw)
To: Gabriel FERNANDEZ, Srinivas Kandagatla, Patrice Chotard,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Lee Jones, Gabriel Fernandez
Hi Gabriel,
for the series:
Acked-by: Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>
Thanks,
Maxime
On 05/05/2014 05:53 PM, Gabriel FERNANDEZ wrote:
> The goal of this series is to add DT definition for STiH415
> and STiH416 SoCs on B2000 and B2020 boards.
>
> Gabriel Fernandez (9):
> ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12
> ARM: STi: DT: STiH416: Remove unused CLK_S_ICN_REG_0 fixed clock
> ARM: STi: DT: STiH416: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY
> fixed clocks
> ARM: STi: DT: STiH416: 416 DT Entry for clockgen B/C/D/E/F
> ARM: STi: DT: STiH416: 416 DT Entry for clockgen A9/DDR/GPU
> ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12
> ARM: STi: DT: STiH415: Remove unused CLK_S_ICN_REG_0 fixed clock
> ARM: STi: DT: STiH415: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY
> fixed clocks
> ARM: STi: DT: STiH415: 415 DT Entry for clockgen A9
>
> arch/arm/boot/dts/stih415-clks.h | 15 +
> arch/arm/boot/dts/stih415-clock.dtsi | 517 ++++++++++++++++++++++++-
> arch/arm/boot/dts/stih415.dtsi | 10 +-
> arch/arm/boot/dts/stih416-clks.h | 15 +
> arch/arm/boot/dts/stih416-clock.dtsi | 732 ++++++++++++++++++++++++++++++++++-
> arch/arm/boot/dts/stih416.dtsi | 10 +-
> 6 files changed, 1256 insertions(+), 43 deletions(-)
> create mode 100644 arch/arm/boot/dts/stih415-clks.h
> create mode 100644 arch/arm/boot/dts/stih416-clks.h
>
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^ permalink raw reply [flat|nested] 17+ messages in thread