[PATCH v3 00/13] ARM/DT: edma: IP configuration from hardware and cleanups

[PATCH v3 00/13] ARM/DT: edma: IP configuration from hardware and cleanups

[Peter Ujfalusi]

Hi,

Changes since v2:
- Comments from Sekhar and Arnd has been addressed best as I could.
- Use the CCCFG information in all cases instead of pdata provided information
- To achieve this I needed to do a bit more cleanup in this series
- In the documentation patch, retrain the old properties for reference
- Cleanups in the old davinci board files and removing edma_soc_info members

Changes sicne v1:
- added missing patch to remove the memset from edma_of_parse_dt()

We are requesting redundant information via DT for the driver since the very same
data is available in the HW: by reading and decoding the content of CCCFG
register we can get:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE

So these does not need to be provided by the DT binding.

The driver will no longer look for these properties from DT and they can be
removed from the binding documentation and from the dtsi files as well.
The change will not introduce regression when new kernel is booted using older
DTB (since we just ignore the mentioned properties).

Regards,
Peter
---
Peter Ujfalusi (13):
  ARM: edma: No need to clean the pdata in edma_of_parse_dt()
  ARM: edma: Take the number of tc from edma_soc_info (pdata)
  ARM: edma: Do not change TC -> Queue mapping, leave it to default.
  ARM: davinci: Remove eDMA3 queue_tc_mapping data from edma_soc_info
  ARM/platform_data: edma: Remove queue_tc_mapping data from
    edma_soc_info
  ARM: edma: Remove num_cc member from struct edma
  ARM: edma: Save number of regions from pdata to struct edma
  ARM: edma: Get IP configuration from HW (number of channels, tc, etc)
  dt/bindings: ti,edma: Remove redundant properties from documentation
  ARM: dts: am33xx: Remove obsolete properties from edma node
  ARM: dts: am4372: Remove obsolete properties from edma node
  ARM: davinci: Remove redundant/unused parameters for edma
  ARM/platform_data: edma: Remove redundant/unused parameters from
    edma_soc_info

 Documentation/devicetree/bindings/dma/ti-edma.txt |  13 +-
 arch/arm/boot/dts/am33xx.dtsi                     |   3 -
 arch/arm/boot/dts/am4372.dtsi                     |   3 -
 arch/arm/common/edma.c                            | 149 +++++++++++-----------
 arch/arm/mach-davinci/devices-da8xx.c             |  31 -----
 arch/arm/mach-davinci/dm355.c                     |  14 --
 arch/arm/mach-davinci/dm365.c                     |  16 ---
 arch/arm/mach-davinci/dm644x.c                    |  14 --
 arch/arm/mach-davinci/dm646x.c                    |  16 ---
 include/linux/platform_data/edma.h                |   8 --
 10 files changed, 81 insertions(+), 186 deletions(-)

-- 
1.9.3

[PATCH v3 01/13] ARM: edma: No need to clean the pdata in edma_of_parse_dt()

[Peter Ujfalusi]

The pdata has been just allocated with devm_kzalloc() in
edma_setup_info_from_dt() and passed to this function.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/common/edma.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 8452cf246330..01707aae0a2b 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1472,8 +1472,6 @@ static int edma_of_parse_dt(struct device *dev,
 	struct edma_rsv_info *rsv_info;
 	s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
 
-	memset(pdata, 0, sizeof(struct edma_soc_info));
-
 	ret = of_property_read_u32(node, "dma-channels", &value);
 	if (ret < 0)
 		return ret;
-- 
1.9.3

[PATCH v3 02/13] ARM: edma: Take the number of tc from edma_soc_info (pdata)

[Peter Ujfalusi]

Instead of saving the for loop length, take the num_tc value from the pdata.
In case of DT boot set the n_tc to 3 as it is hardwired in edma_of_parse_dt()
This is a temporary state since upcoming patch(es) will change how we are
dealing with these parameters.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/common/edma.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 01707aae0a2b..d42c84a3432a 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1488,6 +1488,7 @@ static int edma_of_parse_dt(struct device *dev,
 	pdata->n_slot = value;
 
 	pdata->n_cc = 1;
+	pdata->n_tc = 3;
 
 	rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
 	if (!rsv_info)
@@ -1648,6 +1649,7 @@ static int edma_probe(struct platform_device *pdev)
 							EDMA_MAX_PARAMENTRY);
 		edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
 							EDMA_MAX_CC);
+		edma_cc[j]->num_tc = info[j]->n_tc;
 
 		edma_cc[j]->default_queue = info[j]->default_queue;
 
@@ -1741,9 +1743,6 @@ static int edma_probe(struct platform_device *pdev)
 			map_queue_tc(j, queue_tc_mapping[i][0],
 					queue_tc_mapping[i][1]);
 
-		/* Save the number of TCs */
-		edma_cc[j]->num_tc = i;
-
 		/* Event queue priority mapping */
 		for (i = 0; queue_priority_mapping[i][0] != -1; i++)
 			assign_priority_to_queue(j,
-- 
1.9.3

Re: [PATCH v3 02/13] ARM: edma: Take the number of tc from edma_soc_info (pdata)

[Sekhar Nori]

Peter,

On Friday 16 May 2014 05:47 PM, Peter Ujfalusi wrote:
> Instead of saving the for loop length, take the num_tc value from the pdata.
> In case of DT boot set the n_tc to 3 as it is hardwired in edma_of_parse_dt()
> This is a temporary state since upcoming patch(es) will change how we are
> dealing with these parameters.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---
>  arch/arm/common/edma.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
> index 01707aae0a2b..d42c84a3432a 100644
> --- a/arch/arm/common/edma.c
> +++ b/arch/arm/common/edma.c

> @@ -1741,9 +1743,6 @@ static int edma_probe(struct platform_device *pdev)
>  			map_queue_tc(j, queue_tc_mapping[i][0],
>  					queue_tc_mapping[i][1]);
>  
> -		/* Save the number of TCs */
> -		edma_cc[j]->num_tc = i;
> -

To which baseline do the patches apply? These lines are not present at
least in v3.15-rc5. I am applying the patch without this hunk.

Thanks,
Sekhar

Re: [PATCH v3 02/13] ARM: edma: Take the number of tc from edma_soc_info (pdata)

[Peter Ujfalusi]

On 05/19/2014 02:07 PM, Sekhar Nori wrote:
> To which baseline do the patches apply? These lines are not present at
> least in v3.15-rc5. I am applying the patch without this hunk.

It is generate on top of linux-next-20140515.
next picked up several patches since 3.15-rc and I also have my other patch in
my working branch under this series:
ARM: edma: Clean up and simplify the code around irq request

--
Péter

[PATCH v3 03/13] ARM: edma: Do not change TC -> Queue mapping, leave it to default.

[Peter Ujfalusi]

There is no need to change the default TC -> Queue mapping. By default the
mapping is: TC0 -> Q0, TC1 -> Q1, etc.
Changing this has no benefits at all and all the board files are just setting
the same mapping back to the HW.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/common/edma.c | 28 +---------------------------
 1 file changed, 1 insertion(+), 27 deletions(-)

diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index d42c84a3432a..0bc5ed6fc249 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -290,12 +290,6 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
 			~(0x7 << bit), queue_no << bit);
 }
 
-static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
-{
-	int bit = queue_no * 4;
-	edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
-}
-
 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
 		int priority)
 {
@@ -1470,7 +1464,7 @@ static int edma_of_parse_dt(struct device *dev,
 	struct property *prop;
 	size_t sz;
 	struct edma_rsv_info *rsv_info;
-	s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
+	s8 (*queue_priority_map)[2];
 
 	ret = of_property_read_u32(node, "dma-channels", &value);
 	if (ret < 0)
@@ -1495,19 +1489,6 @@ static int edma_of_parse_dt(struct device *dev,
 		return -ENOMEM;
 	pdata->rsv = rsv_info;
 
-	queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
-	if (!queue_tc_map)
-		return -ENOMEM;
-
-	for (i = 0; i < 3; i++) {
-		queue_tc_map[i][0] = i;
-		queue_tc_map[i][1] = i;
-	}
-	queue_tc_map[i][0] = -1;
-	queue_tc_map[i][1] = -1;
-
-	pdata->queue_tc_mapping = queue_tc_map;
-
 	queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
 	if (!queue_priority_map)
 		return -ENOMEM;
@@ -1568,7 +1549,6 @@ static int edma_probe(struct platform_device *pdev)
 	struct edma_soc_info	**info = pdev->dev.platform_data;
 	struct edma_soc_info    *ninfo[EDMA_MAX_CC] = {NULL};
 	s8		(*queue_priority_mapping)[2];
-	s8		(*queue_tc_mapping)[2];
 	int			i, j, off, ln, found = 0;
 	int			status = -1;
 	const s16		(*rsv_chans)[2];
@@ -1735,14 +1715,8 @@ static int edma_probe(struct platform_device *pdev)
 		for (i = 0; i < edma_cc[j]->num_channels; i++)
 			map_dmach_queue(j, i, info[j]->default_queue);
 
-		queue_tc_mapping = info[j]->queue_tc_mapping;
 		queue_priority_mapping = info[j]->queue_priority_mapping;
 
-		/* Event queue to TC mapping */
-		for (i = 0; queue_tc_mapping[i][0] != -1; i++)
-			map_queue_tc(j, queue_tc_mapping[i][0],
-					queue_tc_mapping[i][1]);
-
 		/* Event queue priority mapping */
 		for (i = 0; queue_priority_mapping[i][0] != -1; i++)
 			assign_priority_to_queue(j,
-- 
1.9.3

[PATCH v3 04/13] ARM: davinci: Remove eDMA3 queue_tc_mapping data from edma_soc_info

[Peter Ujfalusi]

It is ignored by the edma driver since we are just setting back the default
mapping of TC -> Queue.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/mach-davinci/devices-da8xx.c | 16 ----------------
 arch/arm/mach-davinci/dm355.c         |  9 ---------
 arch/arm/mach-davinci/dm365.c         | 11 -----------
 arch/arm/mach-davinci/dm644x.c        |  9 ---------
 arch/arm/mach-davinci/dm646x.c        | 11 -----------
 5 files changed, 56 deletions(-)

diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 56ea41d5f849..7f376e54b266 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -134,13 +134,6 @@ struct platform_device da8xx_serial_device[] = {
 	}
 };
 
-static s8 da8xx_queue_tc_mapping[][2] = {
-	/* {event queue no, TC no} */
-	{0, 0},
-	{1, 1},
-	{-1, -1}
-};
-
 static s8 da8xx_queue_priority_mapping[][2] = {
 	/* {event queue no, Priority} */
 	{0, 3},
@@ -148,12 +141,6 @@ static s8 da8xx_queue_priority_mapping[][2] = {
 	{-1, -1}
 };
 
-static s8 da850_queue_tc_mapping[][2] = {
-	/* {event queue no, TC no} */
-	{0, 0},
-	{-1, -1}
-};
-
 static s8 da850_queue_priority_mapping[][2] = {
 	/* {event queue no, Priority} */
 	{0, 3},
@@ -166,7 +153,6 @@ static struct edma_soc_info da830_edma_cc0_info = {
 	.n_slot			= 128,
 	.n_tc			= 2,
 	.n_cc			= 1,
-	.queue_tc_mapping	= da8xx_queue_tc_mapping,
 	.queue_priority_mapping	= da8xx_queue_priority_mapping,
 	.default_queue		= EVENTQ_1,
 };
@@ -182,7 +168,6 @@ static struct edma_soc_info da850_edma_cc_info[] = {
 		.n_slot			= 128,
 		.n_tc			= 2,
 		.n_cc			= 1,
-		.queue_tc_mapping	= da8xx_queue_tc_mapping,
 		.queue_priority_mapping	= da8xx_queue_priority_mapping,
 		.default_queue		= EVENTQ_1,
 	},
@@ -192,7 +177,6 @@ static struct edma_soc_info da850_edma_cc_info[] = {
 		.n_slot			= 128,
 		.n_tc			= 1,
 		.n_cc			= 1,
-		.queue_tc_mapping	= da850_queue_tc_mapping,
 		.queue_priority_mapping	= da850_queue_priority_mapping,
 		.default_queue		= EVENTQ_0,
 	},
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 07381d8cea62..e27f7ff54570 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -569,14 +569,6 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
 
 static s8
-queue_tc_mapping[][2] = {
-	/* {event queue no, TC no} */
-	{0, 0},
-	{1, 1},
-	{-1, -1},
-};
-
-static s8
 queue_priority_mapping[][2] = {
 	/* {event queue no, Priority} */
 	{0, 3},
@@ -590,7 +582,6 @@ static struct edma_soc_info edma_cc0_info = {
 	.n_slot			= 128,
 	.n_tc			= 2,
 	.n_cc			= 1,
-	.queue_tc_mapping	= queue_tc_mapping,
 	.queue_priority_mapping	= queue_priority_mapping,
 	.default_queue		= EVENTQ_1,
 };
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 08a61b938333..88835b0aaead 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -853,16 +853,6 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /* Four Transfer Controllers on DM365 */
 static s8
-dm365_queue_tc_mapping[][2] = {
-	/* {event queue no, TC no} */
-	{0, 0},
-	{1, 1},
-	{2, 2},
-	{3, 3},
-	{-1, -1},
-};
-
-static s8
 dm365_queue_priority_mapping[][2] = {
 	/* {event queue no, Priority} */
 	{0, 7},
@@ -878,7 +868,6 @@ static struct edma_soc_info edma_cc0_info = {
 	.n_slot			= 256,
 	.n_tc			= 4,
 	.n_cc			= 1,
-	.queue_tc_mapping	= dm365_queue_tc_mapping,
 	.queue_priority_mapping	= dm365_queue_priority_mapping,
 	.default_queue		= EVENTQ_3,
 };
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 5debffba4b24..8ea34be879b4 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -499,14 +499,6 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
 
 static s8
-queue_tc_mapping[][2] = {
-	/* {event queue no, TC no} */
-	{0, 0},
-	{1, 1},
-	{-1, -1},
-};
-
-static s8
 queue_priority_mapping[][2] = {
 	/* {event queue no, Priority} */
 	{0, 3},
@@ -520,7 +512,6 @@ static struct edma_soc_info edma_cc0_info = {
 	.n_slot			= 128,
 	.n_tc			= 2,
 	.n_cc			= 1,
-	.queue_tc_mapping	= queue_tc_mapping,
 	.queue_priority_mapping	= queue_priority_mapping,
 	.default_queue		= EVENTQ_1,
 };
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 332d00d24dc2..97e90dc5ed43 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -533,16 +533,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /* Four Transfer Controllers on DM646x */
 static s8
-dm646x_queue_tc_mapping[][2] = {
-	/* {event queue no, TC no} */
-	{0, 0},
-	{1, 1},
-	{2, 2},
-	{3, 3},
-	{-1, -1},
-};
-
-static s8
 dm646x_queue_priority_mapping[][2] = {
 	/* {event queue no, Priority} */
 	{0, 4},
@@ -558,7 +548,6 @@ static struct edma_soc_info edma_cc0_info = {
 	.n_slot			= 512,
 	.n_tc			= 4,
 	.n_cc			= 1,
-	.queue_tc_mapping	= dm646x_queue_tc_mapping,
 	.queue_priority_mapping	= dm646x_queue_priority_mapping,
 	.default_queue		= EVENTQ_1,
 };
-- 
1.9.3

[PATCH v3 05/13] ARM/platform_data: edma: Remove queue_tc_mapping data from edma_soc_info

[Peter Ujfalusi]

It is no longer in use by the driver or board files.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 include/linux/platform_data/edma.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index 12f134b1493c..633e196ebdf2 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -175,7 +175,6 @@ struct edma_soc_info {
 	/* Resource reservation for other cores */
 	struct edma_rsv_info	*rsv;
 
-	s8	(*queue_tc_mapping)[2];
 	s8	(*queue_priority_mapping)[2];
 	const s16	(*xbar_chans)[2];
 };
-- 
1.9.3

Re: [PATCH v3 05/13] ARM/platform_data: edma: Remove queue_tc_mapping data from edma_soc_info

[Sekhar Nori]

On Friday 16 May 2014 05:47 PM, Peter Ujfalusi wrote:
> It is no longer in use by the driver or board files.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

I dropped the /platform_data in subject like to keep it consistent with
what has been done for this file so far. Even looking at logs for other
files in this directory there is no such convention.

Same thing for 13/13.

Thanks,
Sekhar

[PATCH v3 06/13] ARM: edma: Remove num_cc member from struct edma

[Peter Ujfalusi]

The struct edma is allocated per CC bases so the member num_cc does not make
any sense. One CC is one CC, it does not have sub CCs.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/common/edma.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 0bc5ed6fc249..929a03e4749c 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -233,7 +233,6 @@ struct edma {
 	unsigned	num_region;
 	unsigned	num_slots;
 	unsigned	num_tc;
-	unsigned	num_cc;
 	enum dma_event_q 	default_queue;
 
 	/* list of channels with no even trigger; terminated by "-1" */
@@ -1481,7 +1480,6 @@ static int edma_of_parse_dt(struct device *dev,
 		return ret;
 	pdata->n_slot = value;
 
-	pdata->n_cc = 1;
 	pdata->n_tc = 3;
 
 	rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
@@ -1627,8 +1625,6 @@ static int edma_probe(struct platform_device *pdev)
 							EDMA_MAX_DMACH);
 		edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
 							EDMA_MAX_PARAMENTRY);
-		edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
-							EDMA_MAX_CC);
 		edma_cc[j]->num_tc = info[j]->n_tc;
 
 		edma_cc[j]->default_queue = info[j]->default_queue;
-- 
1.9.3

[PATCH v3 07/13] ARM: edma: Save number of regions from pdata to struct edma

[Peter Ujfalusi]

To be consistent in the code that we take parameters from edma_cc[j] struct
and not randomly from info[j] as well.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/common/edma.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 929a03e4749c..aa9473cb0c23 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1628,6 +1628,7 @@ static int edma_probe(struct platform_device *pdev)
 		edma_cc[j]->num_tc = info[j]->n_tc;
 
 		edma_cc[j]->default_queue = info[j]->default_queue;
+		edma_cc[j]->num_region = info[j]->n_region;
 
 		dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
 			edmacc_regs_base[j]);
@@ -1725,7 +1726,7 @@ static int edma_probe(struct platform_device *pdev)
 		if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
 			map_dmach_param(j);
 
-		for (i = 0; i < info[j]->n_region; i++) {
+		for (i = 0; i < edma_cc[j]->num_region; i++) {
 			edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
 			edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
 			edma_write_array(j, EDMA_QRAE, i, 0x0);
-- 
1.9.3

[PATCH v3 08/13] ARM: edma: Get IP configuration from HW (number of channels, tc, etc)

[Peter Ujfalusi]

>From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE

In case when booted with DT or the queue_priority_mapping is not provided
set up a default priority map.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/common/edma.c | 115 +++++++++++++++++++++++++++++++------------------
 1 file changed, 73 insertions(+), 42 deletions(-)

diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index aa9473cb0c23..485be42519b9 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -102,7 +102,13 @@
 #define PARM_OFFSET(param_no)	(EDMA_PARM + ((param_no) << 5))
 
 #define EDMA_DCHMAP	0x0100  /* 64 registers */
-#define CHMAP_EXIST	BIT(24)
+
+/* CCCFG register */
+#define GET_NUM_DMACH(x)	(x & 0x7) /* bits 0-2 */
+#define GET_NUM_PAENTRY(x)	((x & 0x7000) >> 12) /* bits 12-14 */
+#define GET_NUM_EVQUE(x)	((x & 0x70000) >> 16) /* bits 16-18 */
+#define GET_NUM_REGN(x)		((x & 0x300000) >> 20) /* bits 20-21 */
+#define CHMAP_EXIST		BIT(24)
 
 #define EDMA_MAX_DMACH           64
 #define EDMA_MAX_PARAMENTRY     512
@@ -1408,6 +1414,67 @@ void edma_clear_event(unsigned channel)
 }
 EXPORT_SYMBOL(edma_clear_event);
 
+static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
+			      struct edma *edma_cc)
+{
+	int i;
+	u32 value, cccfg;
+	s8 (*queue_priority_map)[2];
+
+	/* Decode the eDMA3 configuration from CCCFG register */
+	cccfg = edma_read(0, EDMA_CCCFG);
+
+	value = GET_NUM_REGN(cccfg);
+	edma_cc->num_region = BIT(value);
+
+	value = GET_NUM_DMACH(cccfg);
+	edma_cc->num_channels = BIT(value + 1);
+
+	value = GET_NUM_PAENTRY(cccfg);
+	edma_cc->num_slots = BIT(value + 4);
+
+	value = GET_NUM_EVQUE(cccfg);
+	edma_cc->num_tc = value + 1;
+
+	dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
+	dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
+	dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
+	dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
+	dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);
+
+	/* Nothing need to be done if queue priority is provided */
+	if (pdata->queue_priority_mapping)
+		return 0;
+
+	/*
+	 * Configure TC/queue priority as follows:
+	 * Q0 - priority 0
+	 * Q1 - priority 1
+	 * Q2 - priority 2
+	 * ...
+	 * The meaning of priority numbers: 0 highest priority, 7 lowest
+	 * priority. So Q0 is the highest priority queue and the last queue has
+	 * the lowest priority.
+	 */
+	queue_priority_map = devm_kzalloc(dev,
+					  (edma_cc->num_tc + 1) * sizeof(s8),
+					  GFP_KERNEL);
+	if (!queue_priority_map)
+		return -ENOMEM;
+
+	for (i = 0; i < edma_cc->num_tc; i++) {
+		queue_priority_map[i][0] = i;
+		queue_priority_map[i][1] = i;
+	}
+	queue_priority_map[i][0] = -1;
+	queue_priority_map[i][1] = -1;
+
+	pdata->queue_priority_mapping = queue_priority_map;
+	pdata->default_queue = 0;
+
+	return 0;
+}
+
 #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
 
 static int edma_xbar_event_map(struct device *dev, struct device_node *node,
@@ -1458,50 +1525,16 @@ static int edma_of_parse_dt(struct device *dev,
 			    struct device_node *node,
 			    struct edma_soc_info *pdata)
 {
-	int ret = 0, i;
-	u32 value;
+	int ret = 0;
 	struct property *prop;
 	size_t sz;
 	struct edma_rsv_info *rsv_info;
-	s8 (*queue_priority_map)[2];
-
-	ret = of_property_read_u32(node, "dma-channels", &value);
-	if (ret < 0)
-		return ret;
-	pdata->n_channel = value;
-
-	ret = of_property_read_u32(node, "ti,edma-regions", &value);
-	if (ret < 0)
-		return ret;
-	pdata->n_region = value;
-
-	ret = of_property_read_u32(node, "ti,edma-slots", &value);
-	if (ret < 0)
-		return ret;
-	pdata->n_slot = value;
-
-	pdata->n_tc = 3;
 
 	rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
 	if (!rsv_info)
 		return -ENOMEM;
 	pdata->rsv = rsv_info;
 
-	queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
-	if (!queue_priority_map)
-		return -ENOMEM;
-
-	for (i = 0; i < 3; i++) {
-		queue_priority_map[i][0] = i;
-		queue_priority_map[i][1] = i;
-	}
-	queue_priority_map[i][0] = -1;
-	queue_priority_map[i][1] = -1;
-
-	pdata->queue_priority_mapping = queue_priority_map;
-
-	pdata->default_queue = 0;
-
 	prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
 	if (prop)
 		ret = edma_xbar_event_map(dev, node, pdata, sz);
@@ -1621,14 +1654,12 @@ static int edma_probe(struct platform_device *pdev)
 		if (!edma_cc[j])
 			return -ENOMEM;
 
-		edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
-							EDMA_MAX_DMACH);
-		edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
-							EDMA_MAX_PARAMENTRY);
-		edma_cc[j]->num_tc = info[j]->n_tc;
+		/* Get eDMA3 configuration from IP */
+		ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
+		if (ret)
+			return ret;
 
 		edma_cc[j]->default_queue = info[j]->default_queue;
-		edma_cc[j]->num_region = info[j]->n_region;
 
 		dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
 			edmacc_regs_base[j]);
-- 
1.9.3

Re: [PATCH v3 08/13] ARM: edma: Get IP configuration from HW (number of channels, tc, etc)

[Joel Fernandes]

On 05/16/2014 07:17 AM, Peter Ujfalusi wrote:
> From CCCFG register of eDMA3 we can get all the needed information for the
> driver about the IP:
> Number of channels: NUM_DMACH
> Number of regions: NUM_REGN
> Number of slots (PaRAM sets): NUM_PAENTRY
> Number of TC/EQ: NUM_EVQUE
> 
> In case when booted with DT or the queue_priority_mapping is not provided
> set up a default priority map.

Thanks.

Acked-by: Joel Fernandes <joelf@ti.com>


> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---
>  arch/arm/common/edma.c | 115 +++++++++++++++++++++++++++++++------------------
>  1 file changed, 73 insertions(+), 42 deletions(-)
> 
> diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
> index aa9473cb0c23..485be42519b9 100644
> --- a/arch/arm/common/edma.c
> +++ b/arch/arm/common/edma.c
> @@ -102,7 +102,13 @@
>  #define PARM_OFFSET(param_no)	(EDMA_PARM + ((param_no) << 5))
>  
>  #define EDMA_DCHMAP	0x0100  /* 64 registers */
> -#define CHMAP_EXIST	BIT(24)
> +
> +/* CCCFG register */
> +#define GET_NUM_DMACH(x)	(x & 0x7) /* bits 0-2 */
> +#define GET_NUM_PAENTRY(x)	((x & 0x7000) >> 12) /* bits 12-14 */
> +#define GET_NUM_EVQUE(x)	((x & 0x70000) >> 16) /* bits 16-18 */
> +#define GET_NUM_REGN(x)		((x & 0x300000) >> 20) /* bits 20-21 */
> +#define CHMAP_EXIST		BIT(24)
>  
>  #define EDMA_MAX_DMACH           64
>  #define EDMA_MAX_PARAMENTRY     512
> @@ -1408,6 +1414,67 @@ void edma_clear_event(unsigned channel)
>  }
>  EXPORT_SYMBOL(edma_clear_event);
>  
> +static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
> +			      struct edma *edma_cc)
> +{
> +	int i;
> +	u32 value, cccfg;
> +	s8 (*queue_priority_map)[2];
> +
> +	/* Decode the eDMA3 configuration from CCCFG register */
> +	cccfg = edma_read(0, EDMA_CCCFG);
> +
> +	value = GET_NUM_REGN(cccfg);
> +	edma_cc->num_region = BIT(value);
> +
> +	value = GET_NUM_DMACH(cccfg);
> +	edma_cc->num_channels = BIT(value + 1);
> +
> +	value = GET_NUM_PAENTRY(cccfg);
> +	edma_cc->num_slots = BIT(value + 4);
> +
> +	value = GET_NUM_EVQUE(cccfg);
> +	edma_cc->num_tc = value + 1;
> +
> +	dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
> +	dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
> +	dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
> +	dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
> +	dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);
> +
> +	/* Nothing need to be done if queue priority is provided */
> +	if (pdata->queue_priority_mapping)
> +		return 0;
> +
> +	/*
> +	 * Configure TC/queue priority as follows:
> +	 * Q0 - priority 0
> +	 * Q1 - priority 1
> +	 * Q2 - priority 2
> +	 * ...
> +	 * The meaning of priority numbers: 0 highest priority, 7 lowest
> +	 * priority. So Q0 is the highest priority queue and the last queue has
> +	 * the lowest priority.
> +	 */
> +	queue_priority_map = devm_kzalloc(dev,
> +					  (edma_cc->num_tc + 1) * sizeof(s8),
> +					  GFP_KERNEL);
> +	if (!queue_priority_map)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < edma_cc->num_tc; i++) {
> +		queue_priority_map[i][0] = i;
> +		queue_priority_map[i][1] = i;
> +	}
> +	queue_priority_map[i][0] = -1;
> +	queue_priority_map[i][1] = -1;
> +
> +	pdata->queue_priority_mapping = queue_priority_map;
> +	pdata->default_queue = 0;
> +
> +	return 0;
> +}
> +
>  #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
>  
>  static int edma_xbar_event_map(struct device *dev, struct device_node *node,
> @@ -1458,50 +1525,16 @@ static int edma_of_parse_dt(struct device *dev,
>  			    struct device_node *node,
>  			    struct edma_soc_info *pdata)
>  {
> -	int ret = 0, i;
> -	u32 value;
> +	int ret = 0;
>  	struct property *prop;
>  	size_t sz;
>  	struct edma_rsv_info *rsv_info;
> -	s8 (*queue_priority_map)[2];
> -
> -	ret = of_property_read_u32(node, "dma-channels", &value);
> -	if (ret < 0)
> -		return ret;
> -	pdata->n_channel = value;
> -
> -	ret = of_property_read_u32(node, "ti,edma-regions", &value);
> -	if (ret < 0)
> -		return ret;
> -	pdata->n_region = value;
> -
> -	ret = of_property_read_u32(node, "ti,edma-slots", &value);
> -	if (ret < 0)
> -		return ret;
> -	pdata->n_slot = value;
> -
> -	pdata->n_tc = 3;
>  
>  	rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
>  	if (!rsv_info)
>  		return -ENOMEM;
>  	pdata->rsv = rsv_info;
>  
> -	queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
> -	if (!queue_priority_map)
> -		return -ENOMEM;
> -
> -	for (i = 0; i < 3; i++) {
> -		queue_priority_map[i][0] = i;
> -		queue_priority_map[i][1] = i;
> -	}
> -	queue_priority_map[i][0] = -1;
> -	queue_priority_map[i][1] = -1;
> -
> -	pdata->queue_priority_mapping = queue_priority_map;
> -
> -	pdata->default_queue = 0;
> -
>  	prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
>  	if (prop)
>  		ret = edma_xbar_event_map(dev, node, pdata, sz);
> @@ -1621,14 +1654,12 @@ static int edma_probe(struct platform_device *pdev)
>  		if (!edma_cc[j])
>  			return -ENOMEM;
>  
> -		edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
> -							EDMA_MAX_DMACH);
> -		edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
> -							EDMA_MAX_PARAMENTRY);
> -		edma_cc[j]->num_tc = info[j]->n_tc;
> +		/* Get eDMA3 configuration from IP */
> +		ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
> +		if (ret)
> +			return ret;
>  
>  		edma_cc[j]->default_queue = info[j]->default_queue;
> -		edma_cc[j]->num_region = info[j]->n_region;
>  
>  		dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
>  			edmacc_regs_base[j]);
> 

[PATCH v3 09/13] dt/bindings: ti,edma: Remove redundant properties from documentation

[Peter Ujfalusi]

>From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE

The ti,edma-regions; ti,edma-slots and dma-channels in DT are
redundant since the very same information can be obtained from the HW.
The mentioned properties are deprecated.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
---
 Documentation/devicetree/bindings/dma/ti-edma.txt | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
index 68ff2137bae7..5ba525a10035 100644
--- a/Documentation/devicetree/bindings/dma/ti-edma.txt
+++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
@@ -2,11 +2,8 @@ TI EDMA
 
 Required properties:
 - compatible : "ti,edma3"
-- ti,edma-regions: Number of regions
-- ti,edma-slots: Number of slots
 - #dma-cells: Should be set to <1>
               Clients should use a single channel number per DMA request.
-- dma-channels: Specify total DMA channels per CC
 - reg: Memory map for accessing module
 - interrupt-parent: Interrupt controller the interrupt is routed through
 - interrupts: Exactly 3 interrupts need to be specified in the order:
@@ -17,6 +14,13 @@ Optional properties:
 - ti,hwmods: Name of the hwmods associated to the EDMA
 - ti,edma-xbar-event-map: Crossbar event to channel map
 
+Deprecated properties:
+Listed here in case one wants to boot an old kernel with new DTB. These
+properties might need to be added to the new DTS files.
+- ti,edma-regions: Number of regions
+- ti,edma-slots: Number of slots
+- dma-channels: Specify total DMA channels per CC
+
 Example:
 
 edma: edma@49000000 {
@@ -26,9 +30,6 @@ edma: edma@49000000 {
 	compatible = "ti,edma3";
 	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
 	#dma-cells = <1>;
-	dma-channels = <64>;
-	ti,edma-regions = <4>;
-	ti,edma-slots = <256>;
 	ti,edma-xbar-event-map = /bits/ 16 <1 12
 					    2 13>;
 };
-- 
1.9.3

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Re: [PATCH v3 09/13] dt/bindings: ti,edma: Remove redundant properties from documentation

[Sekhar Nori]

+ DT maintainers

On Friday 16 May 2014 05:47 PM, Peter Ujfalusi wrote:
> From CCCFG register of eDMA3 we can get all the needed information for the
> driver about the IP:
> Number of channels: NUM_DMACH
> Number of regions: NUM_REGN
> Number of slots (PaRAM sets): NUM_PAENTRY
> Number of TC/EQ: NUM_EVQUE
> 
> The ti,edma-regions; ti,edma-slots and dma-channels in DT are
> redundant since the very same information can be obtained from the HW.
> The mentioned properties are deprecated.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

DT maintainers,

Can I get an ack on deprecation of these bindings? We are using hardware
to detect the same properties so it should not cause any backward
compatibility issue when moving to newer kernels while keeping the same DTB.

Link to last mail on this topic as part of v2 thread:

http://lkml.iu.edu/hypermail/linux/kernel/1405.1/05152.html

Thanks,
Sekhar

> ---
>  Documentation/devicetree/bindings/dma/ti-edma.txt | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
> index 68ff2137bae7..5ba525a10035 100644
> --- a/Documentation/devicetree/bindings/dma/ti-edma.txt
> +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
> @@ -2,11 +2,8 @@ TI EDMA
>  
>  Required properties:
>  - compatible : "ti,edma3"
> -- ti,edma-regions: Number of regions
> -- ti,edma-slots: Number of slots
>  - #dma-cells: Should be set to <1>
>                Clients should use a single channel number per DMA request.
> -- dma-channels: Specify total DMA channels per CC
>  - reg: Memory map for accessing module
>  - interrupt-parent: Interrupt controller the interrupt is routed through
>  - interrupts: Exactly 3 interrupts need to be specified in the order:
> @@ -17,6 +14,13 @@ Optional properties:
>  - ti,hwmods: Name of the hwmods associated to the EDMA
>  - ti,edma-xbar-event-map: Crossbar event to channel map
>  
> +Deprecated properties:
> +Listed here in case one wants to boot an old kernel with new DTB. These
> +properties might need to be added to the new DTS files.
> +- ti,edma-regions: Number of regions
> +- ti,edma-slots: Number of slots
> +- dma-channels: Specify total DMA channels per CC
> +
>  Example:
>  
>  edma: edma@49000000 {
> @@ -26,9 +30,6 @@ edma: edma@49000000 {
>  	compatible = "ti,edma3";
>  	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
>  	#dma-cells = <1>;
> -	dma-channels = <64>;
> -	ti,edma-regions = <4>;
> -	ti,edma-slots = <256>;
>  	ti,edma-xbar-event-map = /bits/ 16 <1 12
>  					    2 13>;
>  };
> 

Re: [PATCH v3 09/13] dt/bindings: ti,edma: Remove redundant properties from documentation

[Sekhar Nori]

On Monday 19 May 2014 01:45 PM, Sekhar Nori wrote:
> + DT maintainers
> 
> On Friday 16 May 2014 05:47 PM, Peter Ujfalusi wrote:
>> From CCCFG register of eDMA3 we can get all the needed information for the
>> driver about the IP:
>> Number of channels: NUM_DMACH
>> Number of regions: NUM_REGN
>> Number of slots (PaRAM sets): NUM_PAENTRY
>> Number of TC/EQ: NUM_EVQUE
>>
>> The ti,edma-regions; ti,edma-slots and dma-channels in DT are
>> redundant since the very same information can be obtained from the HW.
>> The mentioned properties are deprecated.
>>
>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> 
> DT maintainers,
> 
> Can I get an ack on deprecation of these bindings? We are using hardware
> to detect the same properties so it should not cause any backward
> compatibility issue when moving to newer kernels while keeping the same DTB.
> 
> Link to last mail on this topic as part of v2 thread:
> 
> http://lkml.iu.edu/hypermail/linux/kernel/1405.1/05152.html

Ping. Sorry for being a pest, but this ack is the only thing holding
this series up. I would hate this series to miss the v3.16 deadline.

Thanks,
Sekhar

[PATCH v3 10/13] ARM: dts: am33xx: Remove obsolete properties from edma node

[Peter Ujfalusi]

dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
the the same information is available in the IP's CCCFG register.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/am33xx.dtsi | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index f1eea4af40ed..37d4cad4dd38 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -147,9 +147,6 @@
 				<0x44e10f90 0x40>;
 			interrupts = <12 13 14>;
 			#dma-cells = <1>;
-			dma-channels = <64>;
-			ti,edma-regions = <4>;
-			ti,edma-slots = <256>;
 		};
 
 		gpio0: gpio@44e07000 {
-- 
1.9.3

Re: [PATCH v3 10/13] ARM: dts: am33xx: Remove obsolete properties from edma node

[Tony Lindgren]

* Peter Ujfalusi <peter.ujfalusi@ti.com> [140516 05:18]:
> dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
> the the same information is available in the IP's CCCFG register.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

Acked-by: Tony Lindgren <tony@atomide.com>

> ---
>  arch/arm/boot/dts/am33xx.dtsi | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> index f1eea4af40ed..37d4cad4dd38 100644
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> @@ -147,9 +147,6 @@
>  				<0x44e10f90 0x40>;
>  			interrupts = <12 13 14>;
>  			#dma-cells = <1>;
> -			dma-channels = <64>;
> -			ti,edma-regions = <4>;
> -			ti,edma-slots = <256>;
>  		};
>  
>  		gpio0: gpio@44e07000 {
> -- 
> 1.9.3
> 

[PATCH v3 11/13] ARM: dts: am4372: Remove obsolete properties from edma node

[Peter Ujfalusi]

dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
the the same information is available in the IP's CCCFG register.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 03a225505126..b9f83b705f4b 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -108,9 +108,6 @@
 					<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
-			dma-channels = <64>;
-			ti,edma-regions = <4>;
-			ti,edma-slots = <256>;
 		};
 
 		uart0: serial@44e09000 {
-- 
1.9.3

Re: [PATCH v3 11/13] ARM: dts: am4372: Remove obsolete properties from edma node

[Tony Lindgren]

* Peter Ujfalusi <peter.ujfalusi@ti.com> [140516 05:19]:
> dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
> the the same information is available in the IP's CCCFG register.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

Acked-by: Tony Lindgren <tony@atomide.com>

> ---
>  arch/arm/boot/dts/am4372.dtsi | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
> index 03a225505126..b9f83b705f4b 100644
> --- a/arch/arm/boot/dts/am4372.dtsi
> +++ b/arch/arm/boot/dts/am4372.dtsi
> @@ -108,9 +108,6 @@
>  					<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>  					<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>  			#dma-cells = <1>;
> -			dma-channels = <64>;
> -			ti,edma-regions = <4>;
> -			ti,edma-slots = <256>;
>  		};
>  
>  		uart0: serial@44e09000 {
> -- 
> 1.9.3
> 

[PATCH v3 12/13] ARM: davinci: Remove redundant/unused parameters for edma

[Peter Ujfalusi]

The following parameters are no longer needed by the edma driver since the
information can be obtained from the IP's CCCFG register:
n_channel, n_region, n_slot and n_tc.
Remove the initialization of n_cc as well since in this context it has no
meaning. We have separate edma_soc_info struct/eDMA3_CC instance so this
member does not make any sense (and the driver no longer uses it).

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/mach-davinci/devices-da8xx.c | 15 ---------------
 arch/arm/mach-davinci/dm355.c         |  5 -----
 arch/arm/mach-davinci/dm365.c         |  5 -----
 arch/arm/mach-davinci/dm644x.c        |  5 -----
 arch/arm/mach-davinci/dm646x.c        |  5 -----
 5 files changed, 35 deletions(-)

diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 7f376e54b266..b85b781b05fd 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -148,11 +148,6 @@ static s8 da850_queue_priority_mapping[][2] = {
 };
 
 static struct edma_soc_info da830_edma_cc0_info = {
-	.n_channel		= 32,
-	.n_region		= 4,
-	.n_slot			= 128,
-	.n_tc			= 2,
-	.n_cc			= 1,
 	.queue_priority_mapping	= da8xx_queue_priority_mapping,
 	.default_queue		= EVENTQ_1,
 };
@@ -163,20 +158,10 @@ static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
 
 static struct edma_soc_info da850_edma_cc_info[] = {
 	{
-		.n_channel		= 32,
-		.n_region		= 4,
-		.n_slot			= 128,
-		.n_tc			= 2,
-		.n_cc			= 1,
 		.queue_priority_mapping	= da8xx_queue_priority_mapping,
 		.default_queue		= EVENTQ_1,
 	},
 	{
-		.n_channel		= 32,
-		.n_region		= 4,
-		.n_slot			= 128,
-		.n_tc			= 1,
-		.n_cc			= 1,
 		.queue_priority_mapping	= da850_queue_priority_mapping,
 		.default_queue		= EVENTQ_0,
 	},
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index e27f7ff54570..2f3ed3a58d57 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -577,11 +577,6 @@ queue_priority_mapping[][2] = {
 };
 
 static struct edma_soc_info edma_cc0_info = {
-	.n_channel		= 64,
-	.n_region		= 4,
-	.n_slot			= 128,
-	.n_tc			= 2,
-	.n_cc			= 1,
 	.queue_priority_mapping	= queue_priority_mapping,
 	.default_queue		= EVENTQ_1,
 };
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 88835b0aaead..0ae8114f5cc9 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -863,11 +863,6 @@ dm365_queue_priority_mapping[][2] = {
 };
 
 static struct edma_soc_info edma_cc0_info = {
-	.n_channel		= 64,
-	.n_region		= 4,
-	.n_slot			= 256,
-	.n_tc			= 4,
-	.n_cc			= 1,
 	.queue_priority_mapping	= dm365_queue_priority_mapping,
 	.default_queue		= EVENTQ_3,
 };
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 8ea34be879b4..dc52657909c4 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -507,11 +507,6 @@ queue_priority_mapping[][2] = {
 };
 
 static struct edma_soc_info edma_cc0_info = {
-	.n_channel		= 64,
-	.n_region		= 4,
-	.n_slot			= 128,
-	.n_tc			= 2,
-	.n_cc			= 1,
 	.queue_priority_mapping	= queue_priority_mapping,
 	.default_queue		= EVENTQ_1,
 };
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 97e90dc5ed43..6c3bbea7d77d 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -543,11 +543,6 @@ dm646x_queue_priority_mapping[][2] = {
 };
 
 static struct edma_soc_info edma_cc0_info = {
-	.n_channel		= 64,
-	.n_region		= 6,	/* 0-1, 4-7 */
-	.n_slot			= 512,
-	.n_tc			= 4,
-	.n_cc			= 1,
 	.queue_priority_mapping	= dm646x_queue_priority_mapping,
 	.default_queue		= EVENTQ_1,
 };
-- 
1.9.3

[PATCH v3 13/13] ARM/platform_data: edma: Remove redundant/unused parameters from edma_soc_info

[Peter Ujfalusi]

The following parameters are no longer needed by the edma driver since the
information can be obtained from the IP's CCCFG register:
n_channel, n_region, n_slot and n_tc.
Remove the n_cc as well since in this context it has no meaning. We have
separate edma_soc_info struct/eDMA3_CC instance so this member does not
make any sense (and the driver no longer uses it).

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 include/linux/platform_data/edma.h | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index 633e196ebdf2..eb8d5627d080 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -158,13 +158,6 @@ struct edma_rsv_info {
 
 /* platform_data for EDMA driver */
 struct edma_soc_info {
-
-	/* how many dma resources of each type */
-	unsigned	n_channel;
-	unsigned	n_region;
-	unsigned	n_slot;
-	unsigned	n_tc;
-	unsigned	n_cc;
 	/*
 	 * Default queue is expected to be a low-priority queue.
 	 * This way, long transfers on the default queue started
-- 
1.9.3

Re: [PATCH v3 00/13] ARM/DT: edma: IP configuration from hardware and cleanups

[Sekhar Nori]

On Friday 16 May 2014 05:47 PM, Peter Ujfalusi wrote:
> Hi,
> 
> Changes since v2:
> - Comments from Sekhar and Arnd has been addressed best as I could.
> - Use the CCCFG information in all cases instead of pdata provided information
> - To achieve this I needed to do a bit more cleanup in this series
> - In the documentation patch, retrain the old properties for reference
> - Cleanups in the old davinci board files and removing edma_soc_info members
> 
> Changes sicne v1:
> - added missing patch to remove the memset from edma_of_parse_dt()
> 
> We are requesting redundant information via DT for the driver since the very same
> data is available in the HW: by reading and decoding the content of CCCFG
> register we can get:
> Number of channels: NUM_DMACH
> Number of regions: NUM_REGN
> Number of slots (PaRAM sets): NUM_PAENTRY
> Number of TC/EQ: NUM_EVQUE
> 
> So these does not need to be provided by the DT binding.
> 
> The driver will no longer look for these properties from DT and they can be
> removed from the binding documentation and from the dtsi files as well.
> The change will not introduce regression when new kernel is booted using older
> DTB (since we just ignore the mentioned properties).

Applied all patches and pushed to branch v3.16/edma of:

git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci.git

Since the patches did not apply cleanly, please verify. I tested on
DA850 EVM using MMC/SD as EDMA user.

I will wait to get acks from DT maintainers before sending to ARM-SoC.

Thanks,
Sekhar

Re: [PATCH v3 00/13] ARM/DT: edma: IP configuration from hardware and cleanups

[Peter Ujfalusi]

On 05/19/2014 04:06 PM, Sekhar Nori wrote:
> On Friday 16 May 2014 05:47 PM, Peter Ujfalusi wrote:
>> Hi,
>>
>> Changes since v2:
>> - Comments from Sekhar and Arnd has been addressed best as I could.
>> - Use the CCCFG information in all cases instead of pdata provided information
>> - To achieve this I needed to do a bit more cleanup in this series
>> - In the documentation patch, retrain the old properties for reference
>> - Cleanups in the old davinci board files and removing edma_soc_info members
>>
>> Changes sicne v1:
>> - added missing patch to remove the memset from edma_of_parse_dt()
>>
>> We are requesting redundant information via DT for the driver since the very same
>> data is available in the HW: by reading and decoding the content of CCCFG
>> register we can get:
>> Number of channels: NUM_DMACH
>> Number of regions: NUM_REGN
>> Number of slots (PaRAM sets): NUM_PAENTRY
>> Number of TC/EQ: NUM_EVQUE
>>
>> So these does not need to be provided by the DT binding.
>>
>> The driver will no longer look for these properties from DT and they can be
>> removed from the binding documentation and from the dtsi files as well.
>> The change will not introduce regression when new kernel is booted using older
>> DTB (since we just ignore the mentioned properties).
> 
> Applied all patches and pushed to branch v3.16/edma of:
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci.git
> 
> Since the patches did not apply cleanly, please verify. I tested on
> DA850 EVM using MMC/SD as EDMA user.

The patches in this series looks OK in your branch.
However I can not find the following commits in there, which I have in linux-next:
c689a7b79c28 Merge remote-tracking branch 'slave-dma/next'
cdae05a0f0f7 dmaengine: edma: Make reading the position of active channels work
cf7eb979116c ARM: common: edma: Fix xbar mapping
232b223d8281 dmaengine: edma: Set DMA_CYCLIC capability flag
7cf2af90cd51 arm: common: edma: Save the number of event queues/TCs

They might come via different route...

> 
> I will wait to get acks from DT maintainers before sending to ARM-SoC.
> 
> Thanks,
> Sekhar
> 


Thanks,
Péter

Re: [PATCH v3 00/13] ARM/DT: edma: IP configuration from hardware and cleanups

[Sekhar Nori]

On Monday 19 May 2014 10:23 PM, Peter Ujfalusi wrote:
> On 05/19/2014 04:06 PM, Sekhar Nori wrote:
>> On Friday 16 May 2014 05:47 PM, Peter Ujfalusi wrote:
>>> Hi,
>>>
>>> Changes since v2:
>>> - Comments from Sekhar and Arnd has been addressed best as I could.
>>> - Use the CCCFG information in all cases instead of pdata provided information
>>> - To achieve this I needed to do a bit more cleanup in this series
>>> - In the documentation patch, retrain the old properties for reference
>>> - Cleanups in the old davinci board files and removing edma_soc_info members
>>>
>>> Changes sicne v1:
>>> - added missing patch to remove the memset from edma_of_parse_dt()
>>>
>>> We are requesting redundant information via DT for the driver since the very same
>>> data is available in the HW: by reading and decoding the content of CCCFG
>>> register we can get:
>>> Number of channels: NUM_DMACH
>>> Number of regions: NUM_REGN
>>> Number of slots (PaRAM sets): NUM_PAENTRY
>>> Number of TC/EQ: NUM_EVQUE
>>>
>>> So these does not need to be provided by the DT binding.
>>>
>>> The driver will no longer look for these properties from DT and they can be
>>> removed from the binding documentation and from the dtsi files as well.
>>> The change will not introduce regression when new kernel is booted using older
>>> DTB (since we just ignore the mentioned properties).
>>
>> Applied all patches and pushed to branch v3.16/edma of:
>>
>> git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci.git
>>
>> Since the patches did not apply cleanly, please verify. I tested on
>> DA850 EVM using MMC/SD as EDMA user.
> 
> The patches in this series looks OK in your branch.
> However I can not find the following commits in there, which I have in linux-next:
> c689a7b79c28 Merge remote-tracking branch 'slave-dma/next'
> cdae05a0f0f7 dmaengine: edma: Make reading the position of active channels work
> cf7eb979116c ARM: common: edma: Fix xbar mapping
> 232b223d8281 dmaengine: edma: Set DMA_CYCLIC capability flag
> 7cf2af90cd51 arm: common: edma: Save the number of event queues/TCs
> 
> They might come via different route...

Vinod,

Do you have an immutable branch based on which I can send this patch
series to ARM-SoC? Some of the patches in the series depend on code that
went through your tree.

Or if you are comfortable taking this series through your tree, thats
okay by me too. We are still waiting for acks from DT maintainers on the
binding change patches.

Thanks,
Sekhar

Re: [PATCH v3 00/13] ARM/DT: edma: IP configuration from hardware and cleanups

[Vinod Koul]

On Tue, May 20, 2014 at 04:26:09PM +0530, Sekhar Nori wrote:
> On Monday 19 May 2014 10:23 PM, Peter Ujfalusi wrote:
> > On 05/19/2014 04:06 PM, Sekhar Nori wrote:
> >> On Friday 16 May 2014 05:47 PM, Peter Ujfalusi wrote:
> >>> Hi,
> >>>
> >>> Changes since v2:
> >>> - Comments from Sekhar and Arnd has been addressed best as I could.
> >>> - Use the CCCFG information in all cases instead of pdata provided information
> >>> - To achieve this I needed to do a bit more cleanup in this series
> >>> - In the documentation patch, retrain the old properties for reference
> >>> - Cleanups in the old davinci board files and removing edma_soc_info members
> >>>
> >>> Changes sicne v1:
> >>> - added missing patch to remove the memset from edma_of_parse_dt()
> >>>
> >>> We are requesting redundant information via DT for the driver since the very same
> >>> data is available in the HW: by reading and decoding the content of CCCFG
> >>> register we can get:
> >>> Number of channels: NUM_DMACH
> >>> Number of regions: NUM_REGN
> >>> Number of slots (PaRAM sets): NUM_PAENTRY
> >>> Number of TC/EQ: NUM_EVQUE
> >>>
> >>> So these does not need to be provided by the DT binding.
> >>>
> >>> The driver will no longer look for these properties from DT and they can be
> >>> removed from the binding documentation and from the dtsi files as well.
> >>> The change will not introduce regression when new kernel is booted using older
> >>> DTB (since we just ignore the mentioned properties).
> >>
> >> Applied all patches and pushed to branch v3.16/edma of:
> >>
> >> git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci.git
> >>
> >> Since the patches did not apply cleanly, please verify. I tested on
> >> DA850 EVM using MMC/SD as EDMA user.
> > 
> > The patches in this series looks OK in your branch.
> > However I can not find the following commits in there, which I have in linux-next:
> > c689a7b79c28 Merge remote-tracking branch 'slave-dma/next'
> > cdae05a0f0f7 dmaengine: edma: Make reading the position of active channels work
> > cf7eb979116c ARM: common: edma: Fix xbar mapping
> > 232b223d8281 dmaengine: edma: Set DMA_CYCLIC capability flag
> > 7cf2af90cd51 arm: common: edma: Save the number of event queues/TCs
> > 
> > They might come via different route...
> 
> Vinod,
> 
> Do you have an immutable branch based on which I can send this patch
> series to ARM-SoC? Some of the patches in the series depend on code that
> went through your tree.
yup, pls pull my topic/edma for these change. This branch will not be rebased.

> Or if you are comfortable taking this series through your tree, thats
> okay by me too. We are still waiting for acks from DT maintainers on the
> binding change patches.
Since these patchs are for ARM, I think they are best suited thru arm tree. If
you run into issues with that I cna merge this but with right ACKs...

-- 
~Vinod