[PATCH v10 0/3] Exynos 5410 support

[PATCH v10 0/3] Exynos 5410 support

[Tarek Dakhran]

The series of patches represent support of Exynos 5410 SoC

The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture

Patches add new platform description, support of clock controller and device
tree for Exynos 5410.

Has been build on Samsung Linux Kernel
  (branch: for-next, commit: 19307a0 Merge branch 'v3.16-next/dt-samsung-2' into for-next)
Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig)
		    2) Odroid-XU board (exynos_defconfig)

Many thanks for reviewing to Tomasz Figa.

Tarek.

Tarek Dakhran (3):
  ARM: EXYNOS: Add support for EXYNOS5410 SoC
  clk: exynos5410: register clocks using common clock framework
  ARM: dts: Add initial device tree support for EXYNOS5410

 .../devicetree/bindings/clock/exynos5410-clock.txt |   51 +++++
 arch/arm/boot/dts/Makefile                         |    1 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts          |   82 ++++++++
 arch/arm/boot/dts/exynos5410.dtsi                  |  206 +++++++++++++++++++
 arch/arm/mach-exynos/Kconfig                       |    8 +
 arch/arm/mach-exynos/common.h                      |   11 +-
 arch/arm/mach-exynos/firmware.c                    |    2 +-
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-exynos5410.c               |  209 ++++++++++++++++++++
 include/dt-bindings/clock/exynos5410.h             |   33 ++++
 10 files changed, 602 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
 create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
 create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
 create mode 100644 drivers/clk/samsung/clk-exynos5410.c
 create mode 100644 include/dt-bindings/clock/exynos5410.h

-- 
1.7.9.5

[PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC

[Tarek Dakhran]

EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.

Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
 arch/arm/mach-exynos/Kconfig    |    8 ++++++++
 arch/arm/mach-exynos/common.h   |   11 ++++++++++-
 arch/arm/mach-exynos/firmware.c |    2 +-
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 1602abc..79a3e85 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,14 @@ config SOC_EXYNOS5250
 	help
 	  Enable EXYNOS5250 SoC support
 
+config SOC_EXYNOS5410
+	bool "SAMSUNG EXYNOS5410"
+	default y
+	depends on ARCH_EXYNOS5
+	select PM_GENERIC_DOMAINS if PM_RUNTIME
+	help
+	  Enable EXYNOS5410 SoC support
+
 config SOC_EXYNOS5420
 	bool "SAMSUNG EXYNOS5420"
 	default y
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index e2d0954..d64c6de 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -21,6 +21,7 @@
 #define EXYNOS4_CPU_MASK	0xFFFE0000
 
 #define EXYNOS5250_SOC_ID	0x43520000
+#define EXYNOS5410_SOC_ID	0xE5410000
 #define EXYNOS5420_SOC_ID	0xE5420000
 #define EXYNOS5440_SOC_ID	0xE5440000
 #define EXYNOS5_SOC_MASK	0xFFFFF000
@@ -37,6 +38,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 
@@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_exynos5250()	0
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5410)
+# define soc_is_exynos5410()	is_samsung_exynos5410()
+#else
+# define soc_is_exynos5410()	0
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5420)
 # define soc_is_exynos5420()	is_samsung_exynos5420()
 #else
@@ -82,7 +90,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 
 #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
 			  soc_is_exynos4412())
-#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
+#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
+			  soc_is_exynos5420())
 
 void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
 
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 739bdc8..971baf0 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 
 	boot_reg = sysram_ns_base_addr + 0x1c;
 
-	if (!soc_is_exynos4212())
+	if (!soc_is_exynos4212() && !soc_is_exynos5410())
 		boot_reg += 4*cpu;
 
 	__raw_writel(boot_addr, boot_reg);
-- 
1.7.9.5

[PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework

[Tarek Dakhran]

The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.

Signed-off-by: Tarek Dakhran <t.dakhran-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/clock/exynos5410-clock.txt |   51 +++++
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-exynos5410.c               |  209 ++++++++++++++++++++
 include/dt-bindings/clock/exynos5410.h             |   33 ++++
 4 files changed, 294 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
 create mode 100644 drivers/clk/samsung/clk-exynos5410.c
 create mode 100644 include/dt-bindings/clock/exynos5410.h

diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 0000000..82337c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,51 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+ - compatible: should be "samsung,exynos5410-oscclk"
+
+Example 1: An example of a clock controller node is listed below.
+
+	clock: clock-controller@0x10010000 {
+		compatible = "samsung,exynos5410-clock";
+		reg = <0x10010000 0x30000>;
+		#clock-cells = <1>;
+	};
+
+Example 2: Required external clock.
+
+	fixed-rate-clocks {
+		oscclk {
+			compatible = "samsung,exynos5410-oscclk";
+			clock-frequency = <24000000>;
+		};
+	};
+
+Example 3: UART controller node that consumes the clock generated by the clock
+	   controller. Refer to the standard clock bindings for information
+	   about 'clocks' and 'clock-names' property.
+
+	serial@12C20000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 51 0>;
+		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+	};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 25646c6..69e8177 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_EXYNOS3250)	+= clk-exynos3250.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5260)	+= clk-exynos5260.o
+obj-$(CONFIG_SOC_EXYNOS5410)	+= clk-exynos5410.o
 obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 0000000..c9505ab
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran <t.dakhran-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include <dt-bindings/clock/exynos5410.h>
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk.h"
+
+#define APLL_LOCK               0x0
+#define APLL_CON0               0x100
+#define CPLL_LOCK               0x10020
+#define CPLL_CON0               0x10120
+#define MPLL_LOCK               0x4000
+#define MPLL_CON0               0x4100
+#define BPLL_LOCK               0x20010
+#define BPLL_CON0               0x20110
+#define KPLL_LOCK               0x28000
+#define KPLL_CON0               0x28100
+
+#define SRC_CPU			0x200
+#define DIV_CPU0		0x500
+#define SRC_CPERI1		0x4204
+#define DIV_TOP0		0x10510
+#define DIV_TOP1		0x10514
+#define DIV_FSYS1		0x1054c
+#define DIV_FSYS2		0x10550
+#define DIV_PERIC0		0x10558
+#define SRC_TOP0		0x10210
+#define SRC_TOP1		0x10214
+#define SRC_TOP2		0x10218
+#define SRC_FSYS		0x10244
+#define SRC_PERIC0		0x10250
+#define SRC_MASK_FSYS		0x10340
+#define SRC_MASK_PERIC0		0x10350
+#define GATE_BUS_FSYS0		0x10740
+#define GATE_IP_FSYS		0x10944
+#define GATE_IP_PERIC		0x10950
+#define GATE_IP_PERIS		0x10960
+#define SRC_CDREX		0x20200
+#define SRC_KFC			0x28200
+#define DIV_KFC0		0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+	apll, cpll, mpll,
+	bpll, kpll,
+	nr_plls                 /* number of PLLs */
+};
+
+/* list of all parent clocks */
+PNAME(apll_p)		= { "fin_pll", "fout_apll", };
+PNAME(bpll_p)		= { "fin_pll", "fout_bpll", };
+PNAME(cpll_p)		= { "fin_pll", "fout_cpll" };
+PNAME(mpll_p)		= { "fin_pll", "fout_mpll", };
+PNAME(kpll_p)		= { "fin_pll", "fout_kpll", };
+
+PNAME(mout_cpu_p)	= { "mout_apll", "sclk_mpll", };
+PNAME(mout_kfc_p)	= { "mout_kpll", "sclk_mpll", };
+
+PNAME(mpll_user_p)	= { "fin_pll", "sclk_mpll", };
+PNAME(bpll_user_p)	= { "fin_pll", "sclk_bpll", };
+PNAME(mpll_bpll_p)	= { "sclk_mpll_muxed", "sclk_bpll_muxed", };
+
+PNAME(group2_p)		= { "fin_pll", "fin_pll", "none", "none",
+			"none", "none", "sclk_mpll_bpll",
+			 "none", "none", "sclk_cpll" };
+
+static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
+	MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
+	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+
+	MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
+	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
+
+	MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
+	MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
+
+	MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
+	MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
+
+	MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
+
+	MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
+
+	MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
+	MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
+	MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
+
+	MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
+	MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
+	MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
+
+	MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
+	MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
+};
+
+static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
+	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+	DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
+
+	DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
+	DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
+	DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
+	DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
+
+	DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
+	DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
+	DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
+
+	DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
+	DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
+
+	DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+	DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+	DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
+	DIV_F(0, "div_mmc_pre0", "div_mmc0",
+			DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
+	DIV_F(0, "div_mmc_pre1", "div_mmc1",
+			DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
+	DIV_F(0, "div_mmc_pre2", "div_mmc2",
+			DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
+
+	DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
+	DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
+	DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
+	DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
+
+	DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+	DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
+};
+
+static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
+	GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+
+	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
+			SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
+			SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
+			SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
+	GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
+	GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
+
+	GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
+	GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
+	GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+
+	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+			SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+			SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+			SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
+	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+		APLL_CON0, NULL),
+	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+		CPLL_CON0, NULL),
+	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+		MPLL_CON0, NULL),
+	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+		BPLL_CON0, NULL),
+	[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+		KPLL_CON0, NULL),
+};
+
+/* register exynos5410 clocks */
+static void __init exynos5410_clk_init(struct device_node *np)
+{
+	struct samsung_clk_provider *ctx;
+	void __iomem *reg_base;
+
+	reg_base = of_iomap(np, 0);
+	if (!reg_base)
+		panic("%s: failed to map registers\n", __func__);
+
+	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+
+	samsung_clk_register_pll(ctx, exynos5410_plls,
+			ARRAY_SIZE(exynos5410_plls), reg_base);
+
+	samsung_clk_register_mux(ctx, exynos5410_mux_clks,
+			ARRAY_SIZE(exynos5410_mux_clks));
+	samsung_clk_register_div(ctx, exynos5410_div_clks,
+			ARRAY_SIZE(exynos5410_div_clks));
+	samsung_clk_register_gate(ctx, exynos5410_gate_clks,
+			ARRAY_SIZE(exynos5410_gate_clks));
+
+	pr_debug("Exynos5410: clock setup completed.\n");
+}
+CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
new file mode 100644
index 0000000..9b180f0
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -0,0 +1,33 @@
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+
+/* core clocks */
+#define CLK_FIN_PLL 1
+#define CLK_FOUT_APLL 2
+#define CLK_FOUT_CPLL 3
+#define CLK_FOUT_MPLL 4
+#define CLK_FOUT_BPLL 5
+#define CLK_FOUT_KPLL 6
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0 128
+#define CLK_SCLK_UART1 129
+#define CLK_SCLK_UART2 130
+#define CLK_SCLK_UART3 131
+#define CLK_SCLK_MMC0 132
+#define CLK_SCLK_MMC1 133
+#define CLK_SCLK_MMC2 134
+
+/* gate clocks */
+#define CLK_UART0 257
+#define CLK_UART1 258
+#define CLK_UART2 259
+#define CLK_UART3 260
+#define CLK_MCT 315
+#define CLK_MMC0 351
+#define CLK_MMC1 352
+#define CLK_MMC2 353
+
+#define CLK_NR_CLKS 512
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
-- 
1.7.9.5

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[PATCH v10 3/3] ARM: dts: Add initial device tree support for EXYNOS5410

[Tarek Dakhran]

Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.

Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
 arch/arm/boot/dts/Makefile                |    1 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts |   82 ++++++++++++
 arch/arm/boot/dts/exynos5410.dtsi         |  206 +++++++++++++++++++++++++++++
 3 files changed, 289 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
 create mode 100644 arch/arm/boot/dts/exynos5410.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cd399a2..709f862 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 	exynos5250-smdk5250.dtb \
 	exynos5250-snow.dtb \
 	exynos5260-xyref5260.dtb \
+	exynos5410-smdk5410.dtb \
 	exynos5420-arndale-octa.dtb \
 	exynos5420-peach-pit.dtb \
 	exynos5420-smdk5420.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 0000000..7275bbd
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,82 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+	model = "Samsung SMDK5410 board based on EXYNOS5410";
+	compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttySAC2,115200";
+	};
+
+	fin_pll: xxti {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "fin_pll";
+		#clock-cells = <0>;
+	};
+
+	firmware@02037000 {
+		compatible = "samsung,secure-firmware";
+		reg = <0x02037000 0x1000>;
+	};
+
+};
+
+&mmc_0 {
+	status = "okay";
+	num-slots = <1>;
+	supports-highspeed;
+	broken-cd;
+	card-detect-delay = <200>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <2 3>;
+	samsung,dw-mshc-ddr-timing = <1 2>;
+
+	slot@0 {
+		reg = <0>;
+		bus-width = <8>;
+	};
+};
+
+&mmc_2 {
+	status = "okay";
+	num-slots = <1>;
+	supports-highspeed;
+	card-detect-delay = <200>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <2 3>;
+	samsung,dw-mshc-ddr-timing = <1 2>;
+
+	slot@0 {
+		reg = <0>;
+		bus-width = <4>;
+		disable-wp;
+	};
+};
+
+&uart0 {
+		status = "okay";
+};
+
+&uart1 {
+		status = "okay";
+};
+
+&uart2 {
+		status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 0000000..3839c26
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,206 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos5410.h>
+
+/ {
+	compatible = "samsung,exynos5410", "samsung,exynos5";
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x0>;
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x1>;
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x2>;
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x3>;
+		};
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		combiner: interrupt-controller@10440000 {
+			compatible = "samsung,exynos4210-combiner";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			samsung,combiner-nr = <32>;
+			reg = <0x10440000 0x1000>;
+			interrupts =	<0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+					<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+					<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+					<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+					<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+					<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+					<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+					<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+		};
+
+		gic: interrupt-controller@10481000 {
+			compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg =	<0x10481000 0x1000>,
+				<0x10482000 0x1000>,
+				<0x10484000 0x2000>,
+				<0x10486000 0x2000>;
+			interrupts = <1 9 0xf04>;
+		};
+
+		chipid@10000000 {
+			compatible = "samsung,exynos4210-chipid";
+			reg = <0x10000000 0x100>;
+		};
+
+		mct: mct@101C0000 {
+			compatible = "samsung,exynos4210-mct";
+			reg = <0x101C0000 0xB00>;
+			interrupt-parent = <&interrupt_map>;
+			interrupts = <0>, <1>, <2>, <3>,
+				<4>, <5>, <6>, <7>,
+				<8>, <9>, <10>, <11>;
+			clocks = <&fin_pll>, <&clock CLK_MCT>;
+			clock-names = "fin_pll", "mct";
+
+			interrupt_map: interrupt-map {
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = <0 &combiner 23 3>,
+						<1 &combiner 23 4>,
+						<2 &combiner 25 2>,
+						<3 &combiner 25 3>,
+						<4 &gic 0 120 0>,
+						<5 &gic 0 121 0>,
+						<6 &gic 0 122 0>,
+						<7 &gic 0 123 0>,
+						<8 &gic 0 128 0>,
+						<9 &gic 0 129 0>,
+						<10 &gic 0 130 0>,
+						<11 &gic 0 131 0>;
+			};
+		};
+
+		sysram@02020000 {
+			compatible = "mmio-sram";
+			reg = <0x02020000 0x54000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x02020000 0x54000>;
+
+			smp-sysram@0 {
+				compatible = "samsung,exynos4210-sysram";
+				reg = <0x0 0x1000>;
+			};
+
+			smp-sysram@53000 {
+				compatible = "samsung,exynos4210-sysram-ns";
+				reg = <0x53000 0x1000>;
+			};
+		};
+
+		clock: clock-controller@10010000 {
+			compatible = "samsung,exynos5410-clock";
+			reg = <0x10010000 0x30000>;
+			#clock-cells = <1>;
+		};
+
+		mmc_0: mmc@12200000 {
+			compatible = "samsung,exynos5250-dw-mshc";
+			reg = <0x12200000 0x1000>;
+			interrupts = <0 75 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x80>;
+			status = "disabled";
+		};
+
+		mmc_1: mmc@12210000 {
+			compatible = "samsung,exynos5250-dw-mshc";
+			reg = <0x12210000 0x1000>;
+			interrupts = <0 76 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x80>;
+			status = "disabled";
+		};
+
+		mmc_2: mmc@12220000 {
+			compatible = "samsung,exynos5250-dw-mshc";
+			reg = <0x12220000 0x1000>;
+			interrupts = <0 77 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x80>;
+			status = "disabled";
+		};
+
+		uart0: serial@12C00000 {
+			compatible = "samsung,exynos4210-uart";
+			reg = <0x12C00000 0x100>;
+			interrupts = <0 51 0>;
+			clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+			clock-names = "uart", "clk_uart_baud0";
+			status = "disabled";
+		};
+
+		uart1: serial@12C10000 {
+			compatible = "samsung,exynos4210-uart";
+			reg = <0x12C10000 0x100>;
+			interrupts = <0 52 0>;
+			clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+			clock-names = "uart", "clk_uart_baud0";
+			status = "disabled";
+		};
+
+		uart2: serial@12C20000 {
+			compatible = "samsung,exynos4210-uart";
+			reg = <0x12C20000 0x100>;
+			interrupts = <0 53 0>;
+			clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+			clock-names = "uart", "clk_uart_baud0";
+			status = "disabled";
+		};
+	};
+};
-- 
1.7.9.5

Re: [PATCH v10 3/3] ARM: dts: Add initial device tree support for EXYNOS5410

[Matthias Brugger]

2014-05-23 12:35 GMT+02:00 Tarek Dakhran <t.dakhran@samsung.com>:
> Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
>
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
>  arch/arm/boot/dts/Makefile                |    1 +
>  arch/arm/boot/dts/exynos5410-smdk5410.dts |   82 ++++++++++++
>  arch/arm/boot/dts/exynos5410.dtsi         |  206 +++++++++++++++++++++++++++++
>  3 files changed, 289 insertions(+)
>  create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
>  create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index cd399a2..709f862 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
>         exynos5250-smdk5250.dtb \
>         exynos5250-snow.dtb \
>         exynos5260-xyref5260.dtb \
> +       exynos5410-smdk5410.dtb \
>         exynos5420-arndale-octa.dtb \
>         exynos5420-peach-pit.dtb \
>         exynos5420-smdk5420.dtb \
> diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
> new file mode 100644
> index 0000000..7275bbd
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
> @@ -0,0 +1,82 @@
> +/*
> + * SAMSUNG SMDK5410 board device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +#include "exynos5410.dtsi"
> +/ {
> +       model = "Samsung SMDK5410 board based on EXYNOS5410";
> +       compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
> +
> +       memory {
> +               reg = <0x40000000 0x80000000>;
> +       };
> +
> +       chosen {
> +               bootargs = "console=ttySAC2,115200";
> +       };
> +
> +       fin_pll: xxti {
> +               compatible = "fixed-clock";
> +               clock-frequency = <24000000>;
> +               clock-output-names = "fin_pll";
> +               #clock-cells = <0>;
> +       };
> +
> +       firmware@02037000 {
> +               compatible = "samsung,secure-firmware";
> +               reg = <0x02037000 0x1000>;
> +       };
> +
> +};
> +
> +&mmc_0 {
> +       status = "okay";
> +       num-slots = <1>;
> +       supports-highspeed;
> +       broken-cd;
> +       card-detect-delay = <200>;
> +       samsung,dw-mshc-ciu-div = <3>;
> +       samsung,dw-mshc-sdr-timing = <2 3>;
> +       samsung,dw-mshc-ddr-timing = <1 2>;
> +
> +       slot@0 {
> +               reg = <0>;
> +               bus-width = <8>;
> +       };
> +};
> +
> +&mmc_2 {
> +       status = "okay";
> +       num-slots = <1>;
> +       supports-highspeed;
> +       card-detect-delay = <200>;
> +       samsung,dw-mshc-ciu-div = <3>;
> +       samsung,dw-mshc-sdr-timing = <2 3>;
> +       samsung,dw-mshc-ddr-timing = <1 2>;
> +
> +       slot@0 {
> +               reg = <0>;
> +               bus-width = <4>;
> +               disable-wp;
> +       };
> +};
> +
> +&uart0 {
> +               status = "okay";
> +};
> +
> +&uart1 {
> +               status = "okay";
> +};
> +
> +&uart2 {
> +               status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
> new file mode 100644
> index 0000000..3839c26
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5410.dtsi
> @@ -0,0 +1,206 @@
> +/*
> + * SAMSUNG EXYNOS5410 SoC device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + *
> + * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
> + * EXYNOS5410 based board files can include this file and provide
> + * values for board specfic bindings.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "skeleton.dtsi"
> +#include <dt-bindings/clock/exynos5410.h>
> +
> +/ {
> +       compatible = "samsung,exynos5410", "samsung,exynos5";
> +       interrupt-parent = <&gic>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               CPU0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a15";
> +                       reg = <0x0>;
> +               };
> +
> +               CPU1: cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a15";
> +                       reg = <0x1>;
> +               };
> +
> +               CPU2: cpu@2 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a15";
> +                       reg = <0x2>;
> +               };
> +
> +               CPU3: cpu@3 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a15";
> +                       reg = <0x3>;
> +               };
> +       };
> +
> +       soc: soc {
> +               compatible = "simple-bus";
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges;
> +
> +               combiner: interrupt-controller@10440000 {
> +                       compatible = "samsung,exynos4210-combiner";
> +                       #interrupt-cells = <2>;
> +                       interrupt-controller;
> +                       samsung,combiner-nr = <32>;
> +                       reg = <0x10440000 0x1000>;
> +                       interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
> +                                       <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
> +                                       <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
> +                                       <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
> +                                       <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
> +                                       <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
> +                                       <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
> +                                       <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
> +               };
> +
> +               gic: interrupt-controller@10481000 {
> +                       compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";

shouldn't it be just "arm,cortex-a15-gic", as this is your SoC architecture?

Cheers,
Matthias

Re: [PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework

[Mike Turquette]

Quoting Tarek Dakhran (2014-05-23 03:35:42)
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.
> 
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>

Quick glance over it. Looks good to me.

Regards,
Mike

> ---
>  .../devicetree/bindings/clock/exynos5410-clock.txt |   51 +++++
>  drivers/clk/samsung/Makefile                       |    1 +
>  drivers/clk/samsung/clk-exynos5410.c               |  209 ++++++++++++++++++++
>  include/dt-bindings/clock/exynos5410.h             |   33 ++++
>  4 files changed, 294 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>  create mode 100644 drivers/clk/samsung/clk-exynos5410.c
>  create mode 100644 include/dt-bindings/clock/exynos5410.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> new file mode 100644
> index 0000000..82337c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> @@ -0,0 +1,51 @@
> +* Samsung Exynos5410 Clock Controller
> +
> +The Exynos5410 clock controller generates and supplies clock to various
> +controllers within the Exynos5410 SoC.
> +
> +Required Properties:
> +
> +- compatible: should be "samsung,exynos5410-clock"
> +
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +
> +- #clock-cells: should be 1.
> +
> +All available clocks are defined as preprocessor macros in
> +dt-bindings/clock/exynos5410.h header and can be used in device
> +tree sources.
> +
> +External clock:
> +There is clock that is generated outside the SoC. It is expected
> +that it is defined using standard clock bindings with following
> + - compatible: should be "samsung,exynos5410-oscclk"
> +
> +Example 1: An example of a clock controller node is listed below.
> +
> +       clock: clock-controller@0x10010000 {
> +               compatible = "samsung,exynos5410-clock";
> +               reg = <0x10010000 0x30000>;
> +               #clock-cells = <1>;
> +       };
> +
> +Example 2: Required external clock.
> +
> +       fixed-rate-clocks {
> +               oscclk {
> +                       compatible = "samsung,exynos5410-oscclk";
> +                       clock-frequency = <24000000>;
> +               };
> +       };
> +
> +Example 3: UART controller node that consumes the clock generated by the clock
> +          controller. Refer to the standard clock bindings for information
> +          about 'clocks' and 'clock-names' property.
> +
> +       serial@12C20000 {
> +               compatible = "samsung,exynos4210-uart";
> +               reg = <0x12C00000 0x100>;
> +               interrupts = <0 51 0>;
> +               clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
> +               clock-names = "uart", "clk_uart_baud0";
> +       };
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index 25646c6..69e8177 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_EXYNOS3250)    += clk-exynos3250.o
>  obj-$(CONFIG_ARCH_EXYNOS4)     += clk-exynos4.o
>  obj-$(CONFIG_SOC_EXYNOS5250)   += clk-exynos5250.o
>  obj-$(CONFIG_SOC_EXYNOS5260)   += clk-exynos5260.o
> +obj-$(CONFIG_SOC_EXYNOS5410)   += clk-exynos5410.o
>  obj-$(CONFIG_SOC_EXYNOS5420)   += clk-exynos5420.o
>  obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
>  obj-$(CONFIG_ARCH_EXYNOS)      += clk-exynos-audss.o
> diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
> new file mode 100644
> index 0000000..c9505ab
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos5410.c
> @@ -0,0 +1,209 @@
> +/*
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * Author: Tarek Dakhran <t.dakhran@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Common Clock Framework support for Exynos5410 SoC.
> +*/
> +
> +#include <dt-bindings/clock/exynos5410.h>
> +
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +#include "clk.h"
> +
> +#define APLL_LOCK               0x0
> +#define APLL_CON0               0x100
> +#define CPLL_LOCK               0x10020
> +#define CPLL_CON0               0x10120
> +#define MPLL_LOCK               0x4000
> +#define MPLL_CON0               0x4100
> +#define BPLL_LOCK               0x20010
> +#define BPLL_CON0               0x20110
> +#define KPLL_LOCK               0x28000
> +#define KPLL_CON0               0x28100
> +
> +#define SRC_CPU                        0x200
> +#define DIV_CPU0               0x500
> +#define SRC_CPERI1             0x4204
> +#define DIV_TOP0               0x10510
> +#define DIV_TOP1               0x10514
> +#define DIV_FSYS1              0x1054c
> +#define DIV_FSYS2              0x10550
> +#define DIV_PERIC0             0x10558
> +#define SRC_TOP0               0x10210
> +#define SRC_TOP1               0x10214
> +#define SRC_TOP2               0x10218
> +#define SRC_FSYS               0x10244
> +#define SRC_PERIC0             0x10250
> +#define SRC_MASK_FSYS          0x10340
> +#define SRC_MASK_PERIC0                0x10350
> +#define GATE_BUS_FSYS0         0x10740
> +#define GATE_IP_FSYS           0x10944
> +#define GATE_IP_PERIC          0x10950
> +#define GATE_IP_PERIS          0x10960
> +#define SRC_CDREX              0x20200
> +#define SRC_KFC                        0x28200
> +#define DIV_KFC0               0x28500
> +
> +/* list of PLLs */
> +enum exynos5410_plls {
> +       apll, cpll, mpll,
> +       bpll, kpll,
> +       nr_plls                 /* number of PLLs */
> +};
> +
> +/* list of all parent clocks */
> +PNAME(apll_p)          = { "fin_pll", "fout_apll", };
> +PNAME(bpll_p)          = { "fin_pll", "fout_bpll", };
> +PNAME(cpll_p)          = { "fin_pll", "fout_cpll" };
> +PNAME(mpll_p)          = { "fin_pll", "fout_mpll", };
> +PNAME(kpll_p)          = { "fin_pll", "fout_kpll", };
> +
> +PNAME(mout_cpu_p)      = { "mout_apll", "sclk_mpll", };
> +PNAME(mout_kfc_p)      = { "mout_kpll", "sclk_mpll", };
> +
> +PNAME(mpll_user_p)     = { "fin_pll", "sclk_mpll", };
> +PNAME(bpll_user_p)     = { "fin_pll", "sclk_bpll", };
> +PNAME(mpll_bpll_p)     = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
> +
> +PNAME(group2_p)                = { "fin_pll", "fin_pll", "none", "none",
> +                       "none", "none", "sclk_mpll_bpll",
> +                        "none", "none", "sclk_cpll" };
> +
> +static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
> +       MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
> +       MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
> +
> +       MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
> +       MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
> +
> +       MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
> +       MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
> +
> +       MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
> +       MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
> +
> +       MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
> +
> +       MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
> +
> +       MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
> +       MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
> +       MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
> +
> +       MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
> +       MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
> +       MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
> +
> +       MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
> +       MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
> +};
> +
> +static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
> +       DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
> +       DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
> +
> +       DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
> +       DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
> +       DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
> +       DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
> +
> +       DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
> +       DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
> +       DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
> +
> +       DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
> +       DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
> +
> +       DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
> +       DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
> +       DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
> +
> +       DIV_F(0, "div_mmc_pre0", "div_mmc0",
> +                       DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
> +       DIV_F(0, "div_mmc_pre1", "div_mmc1",
> +                       DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
> +       DIV_F(0, "div_mmc_pre2", "div_mmc2",
> +                       DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
> +
> +       DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
> +       DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
> +       DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
> +       DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
> +
> +       DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
> +       DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
> +};
> +
> +static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
> +       GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
> +
> +       GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
> +                       SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
> +       GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
> +                       SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
> +       GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
> +                       SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
> +
> +       GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
> +       GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
> +       GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
> +
> +       GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
> +       GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
> +       GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
> +
> +       GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> +                       SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
> +       GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> +                       SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
> +       GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> +                       SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
> +};
> +
> +static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
> +       [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
> +               APLL_CON0, NULL),
> +       [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
> +               CPLL_CON0, NULL),
> +       [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
> +               MPLL_CON0, NULL),
> +       [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
> +               BPLL_CON0, NULL),
> +       [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
> +               KPLL_CON0, NULL),
> +};
> +
> +/* register exynos5410 clocks */
> +static void __init exynos5410_clk_init(struct device_node *np)
> +{
> +       struct samsung_clk_provider *ctx;
> +       void __iomem *reg_base;
> +
> +       reg_base = of_iomap(np, 0);
> +       if (!reg_base)
> +               panic("%s: failed to map registers\n", __func__);
> +
> +       ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
> +
> +       samsung_clk_register_pll(ctx, exynos5410_plls,
> +                       ARRAY_SIZE(exynos5410_plls), reg_base);
> +
> +       samsung_clk_register_mux(ctx, exynos5410_mux_clks,
> +                       ARRAY_SIZE(exynos5410_mux_clks));
> +       samsung_clk_register_div(ctx, exynos5410_div_clks,
> +                       ARRAY_SIZE(exynos5410_div_clks));
> +       samsung_clk_register_gate(ctx, exynos5410_gate_clks,
> +                       ARRAY_SIZE(exynos5410_gate_clks));
> +
> +       pr_debug("Exynos5410: clock setup completed.\n");
> +}
> +CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
> diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
> new file mode 100644
> index 0000000..9b180f0
> --- /dev/null
> +++ b/include/dt-bindings/clock/exynos5410.h
> @@ -0,0 +1,33 @@
> +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
> +#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
> +
> +/* core clocks */
> +#define CLK_FIN_PLL 1
> +#define CLK_FOUT_APLL 2
> +#define CLK_FOUT_CPLL 3
> +#define CLK_FOUT_MPLL 4
> +#define CLK_FOUT_BPLL 5
> +#define CLK_FOUT_KPLL 6
> +
> +/* gate for special clocks (sclk) */
> +#define CLK_SCLK_UART0 128
> +#define CLK_SCLK_UART1 129
> +#define CLK_SCLK_UART2 130
> +#define CLK_SCLK_UART3 131
> +#define CLK_SCLK_MMC0 132
> +#define CLK_SCLK_MMC1 133
> +#define CLK_SCLK_MMC2 134
> +
> +/* gate clocks */
> +#define CLK_UART0 257
> +#define CLK_UART1 258
> +#define CLK_UART2 259
> +#define CLK_UART3 260
> +#define CLK_MCT 315
> +#define CLK_MMC0 351
> +#define CLK_MMC1 352
> +#define CLK_MMC2 353
> +
> +#define CLK_NR_CLKS 512
> +
> +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
> -- 
> 1.7.9.5
> 

Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC

[Tomasz Figa]

Hi Tarek,

With v2 of the series I mentioned in review of previous version [1],
this patch can be skipped.

[1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html

Best regards,
Tomasz

On 23.05.2014 12:35, Tarek Dakhran wrote:
> EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
> Add initial support for this SoC.
> 
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
>  arch/arm/mach-exynos/Kconfig    |    8 ++++++++
>  arch/arm/mach-exynos/common.h   |   11 ++++++++++-
>  arch/arm/mach-exynos/firmware.c |    2 +-
>  3 files changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 1602abc..79a3e85 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -84,6 +84,14 @@ config SOC_EXYNOS5250
>  	help
>  	  Enable EXYNOS5250 SoC support
>  
> +config SOC_EXYNOS5410
> +	bool "SAMSUNG EXYNOS5410"
> +	default y
> +	depends on ARCH_EXYNOS5
> +	select PM_GENERIC_DOMAINS if PM_RUNTIME
> +	help
> +	  Enable EXYNOS5410 SoC support
> +
>  config SOC_EXYNOS5420
>  	bool "SAMSUNG EXYNOS5420"
>  	default y
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index e2d0954..d64c6de 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -21,6 +21,7 @@
>  #define EXYNOS4_CPU_MASK	0xFFFE0000
>  
>  #define EXYNOS5250_SOC_ID	0x43520000
> +#define EXYNOS5410_SOC_ID	0xE5410000
>  #define EXYNOS5420_SOC_ID	0xE5420000
>  #define EXYNOS5440_SOC_ID	0xE5440000
>  #define EXYNOS5_SOC_MASK	0xFFFFF000
> @@ -37,6 +38,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
>  IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
>  IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
>  IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
> +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
>  IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
>  IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
>  
> @@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
>  # define soc_is_exynos5250()	0
>  #endif
>  
> +#if defined(CONFIG_SOC_EXYNOS5410)
> +# define soc_is_exynos5410()	is_samsung_exynos5410()
> +#else
> +# define soc_is_exynos5410()	0
> +#endif
> +
>  #if defined(CONFIG_SOC_EXYNOS5420)
>  # define soc_is_exynos5420()	is_samsung_exynos5420()
>  #else
> @@ -82,7 +90,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
>  
>  #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
>  			  soc_is_exynos4412())
> -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
> +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
> +			  soc_is_exynos5420())
>  
>  void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
>  
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index 739bdc8..971baf0 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>  
>  	boot_reg = sysram_ns_base_addr + 0x1c;
>  
> -	if (!soc_is_exynos4212())
> +	if (!soc_is_exynos4212() && !soc_is_exynos5410())
>  		boot_reg += 4*cpu;
>  
>  	__raw_writel(boot_addr, boot_reg);
> 

Re: [PATCH v10 3/3] ARM: dts: Add initial device tree support for EXYNOS5410

[Tomasz Figa]

Hi Tarek,

On 23.05.2014 12:35, Tarek Dakhran wrote:
> Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
> 
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
>  arch/arm/boot/dts/Makefile                |    1 +
>  arch/arm/boot/dts/exynos5410-smdk5410.dts |   82 ++++++++++++
>  arch/arm/boot/dts/exynos5410.dtsi         |  206 +++++++++++++++++++++++++++++
>  3 files changed, 289 insertions(+)
>  create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
>  create mode 100644 arch/arm/boot/dts/exynos5410.dtsi

Looks good. Hopefully we can have this patch applied soon, so it won't
get outdated again.

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

Re: [PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework

[Tomasz Figa]

Hi Tarek,

Thanks for keeping up with addressing my comments. See below.

On 23.05.2014 12:35, Tarek Dakhran wrote:
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.
> 
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
>  .../devicetree/bindings/clock/exynos5410-clock.txt |   51 +++++
>  drivers/clk/samsung/Makefile                       |    1 +
>  drivers/clk/samsung/clk-exynos5410.c               |  209 ++++++++++++++++++++
>  include/dt-bindings/clock/exynos5410.h             |   33 ++++
>  4 files changed, 294 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>  create mode 100644 drivers/clk/samsung/clk-exynos5410.c
>  create mode 100644 include/dt-bindings/clock/exynos5410.h
> 

The driver itself looks good, but binding documentation seems to be
outdated. The part about external clocks, more specifically.

> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> new file mode 100644
> index 0000000..82337c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> @@ -0,0 +1,51 @@
> +* Samsung Exynos5410 Clock Controller
> +
> +The Exynos5410 clock controller generates and supplies clock to various
> +controllers within the Exynos5410 SoC.
> +
> +Required Properties:
> +
> +- compatible: should be "samsung,exynos5410-clock"
> +
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +
> +- #clock-cells: should be 1.
> +
> +All available clocks are defined as preprocessor macros in
> +dt-bindings/clock/exynos5410.h header and can be used in device
> +tree sources.
> +
> +External clock:
> +There is clock that is generated outside the SoC. It is expected
> +that it is defined using standard clock bindings with following
> + - compatible: should be "samsung,exynos5410-oscclk"

^^^^^

> +
> +Example 1: An example of a clock controller node is listed below.
> +
> +	clock: clock-controller@0x10010000 {
> +		compatible = "samsung,exynos5410-clock";
> +		reg = <0x10010000 0x30000>;
> +		#clock-cells = <1>;
> +	};
> +
> +Example 2: Required external clock.
> +
> +	fixed-rate-clocks {
> +		oscclk {
> +			compatible = "samsung,exynos5410-oscclk";
> +			clock-frequency = <24000000>;
> +		};
> +	};

^^^^^

Best regards,
Tomasz

Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC

[Tarek Dakhran]

Hi Tomazs,

On Sat, May 24, 2014 at 1:11 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Tarek,
>
> With v2 of the series I mentioned in review of previous version [1],
> this patch can be skipped.
>
> [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html
>
> Best regards,
> Tomasz
>
> On 23.05.2014 12:35, Tarek Dakhran wrote:
[snip]
>> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
>> index 739bdc8..971baf0 100644
>> --- a/arch/arm/mach-exynos/firmware.c
>> +++ b/arch/arm/mach-exynos/firmware.c
>> @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>>
>>       boot_reg = sysram_ns_base_addr + 0x1c;
>>
>> -     if (!soc_is_exynos4212())
>> +     if (!soc_is_exynos4212() && !soc_is_exynos5410())
>>               boot_reg += 4*cpu;
>>
>>       __raw_writel(boot_addr, boot_reg);
>>

I need to define SoC type to set correct bootreg in firmware,
otherwise only one cpu can be booted.
So, this stuff is needed.

Best regards,
     Tarek

Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC

[Tomasz Figa]

On 24.05.2014 00:44, Tarek Dakhran wrote:
> Hi Tomazs,
> 
> On Sat, May 24, 2014 at 1:11 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> Hi Tarek,
>>
>> With v2 of the series I mentioned in review of previous version [1],
>> this patch can be skipped.
>>
>> [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html
>>
>> Best regards,
>> Tomasz
>>
>> On 23.05.2014 12:35, Tarek Dakhran wrote:
> [snip]
>>> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
>>> index 739bdc8..971baf0 100644
>>> --- a/arch/arm/mach-exynos/firmware.c
>>> +++ b/arch/arm/mach-exynos/firmware.c
>>> @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>>>
>>>       boot_reg = sysram_ns_base_addr + 0x1c;
>>>
>>> -     if (!soc_is_exynos4212())
>>> +     if (!soc_is_exynos4212() && !soc_is_exynos5410())
>>>               boot_reg += 4*cpu;
>>>
>>>       __raw_writel(boot_addr, boot_reg);
>>>
> 
> I need to define SoC type to set correct bootreg in firmware,
> otherwise only one cpu can be booted.
> So, this stuff is needed.

The patch I referred to in my previous reply changes this condition from
!soc_is_exynos4212() to soc_is_exynos4412(), which makes the 4*cpu
offset being added only in case of Exynos4412 (and so not being added
for Exynos5410). What else is needed?

Best regards,
Tomasz

Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC

[Tarek Dakhran]

Sorry, only now catch it!
I agree, this patch is not needed anymore, except Kconfig option.
config SOC_EXYNOS5410 is needed to build clock stuff.
What is your opinion, Tomasz?

On Sat, May 24, 2014 at 2:44 AM, Tarek Dakhran <t.dakhran@gmail.com> wrote:
> Hi Tomazs,
>
> On Sat, May 24, 2014 at 1:11 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> Hi Tarek,
>>
>> With v2 of the series I mentioned in review of previous version [1],
>> this patch can be skipped.
>>
>> [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html
>>
>> Best regards,
>> Tomasz
>>
>> On 23.05.2014 12:35, Tarek Dakhran wrote:
> [snip]
>>> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
>>> index 739bdc8..971baf0 100644
>>> --- a/arch/arm/mach-exynos/firmware.c
>>> +++ b/arch/arm/mach-exynos/firmware.c
>>> @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>>>
>>>       boot_reg = sysram_ns_base_addr + 0x1c;
>>>
>>> -     if (!soc_is_exynos4212())
>>> +     if (!soc_is_exynos4212() && !soc_is_exynos5410())
>>>               boot_reg += 4*cpu;
>>>
>>>       __raw_writel(boot_addr, boot_reg);
>>>
>
> I need to define SoC type to set correct bootreg in firmware,
> otherwise only one cpu can be booted.
> So, this stuff is needed.
>
> Best regards,
>      Tarek

Re: [PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework

[Tarek Dakhran]

This is just my inattention.
Will be corrected until Monday.

On Sat, May 24, 2014 at 1:19 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Tarek,
>
> Thanks for keeping up with addressing my comments. See below.
>
> On 23.05.2014 12:35, Tarek Dakhran wrote:
>> The EXYNOS5410 clocks are statically listed and registered
>> using the Samsung specific common clock helper functions.
>>
>> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
>> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
>> ---
>>  .../devicetree/bindings/clock/exynos5410-clock.txt |   51 +++++
>>  drivers/clk/samsung/Makefile                       |    1 +
>>  drivers/clk/samsung/clk-exynos5410.c               |  209 ++++++++++++++++++++
>>  include/dt-bindings/clock/exynos5410.h             |   33 ++++
>>  4 files changed, 294 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>>  create mode 100644 drivers/clk/samsung/clk-exynos5410.c
>>  create mode 100644 include/dt-bindings/clock/exynos5410.h
>>
>
> The driver itself looks good, but binding documentation seems to be
> outdated. The part about external clocks, more specifically.
>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> new file mode 100644
>> index 0000000..82337c4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> @@ -0,0 +1,51 @@
>> +* Samsung Exynos5410 Clock Controller
>> +
>> +The Exynos5410 clock controller generates and supplies clock to various
>> +controllers within the Exynos5410 SoC.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be "samsung,exynos5410-clock"
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +All available clocks are defined as preprocessor macros in
>> +dt-bindings/clock/exynos5410.h header and can be used in device
>> +tree sources.
>> +
>> +External clock:
>> +There is clock that is generated outside the SoC. It is expected
>> +that it is defined using standard clock bindings with following
>> + - compatible: should be "samsung,exynos5410-oscclk"
>
> ^^^^^

Best regards,
     Tarek

Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC

[Tomasz Figa]

On 24.05.2014 00:48, Tarek Dakhran wrote:
> Sorry, only now catch it!
> I agree, this patch is not needed anymore, except Kconfig option.
> config SOC_EXYNOS5410 is needed to build clock stuff.

Right, I missed this.

> What is your opinion, Tomasz?
> 

I'd suggest re-spinning this series once more, removing changes that are
not needed anymore, but keeping the Kconfig entry.

Best regards,
Tomasz

Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC

[Tarek Dakhran]

Hi Tomasz

I faced another problem, while changing this patch.
See below.

On 05/24/2014 01:11 AM, Tomasz Figa wrote:
> Hi Tarek,
>
> With v2 of the series I mentioned in review of previous version [1],
> this patch can be skipped.
>
> [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html
>
> Best regards,
> Tomasz
>
> On 23.05.2014 12:35, Tarek Dakhran wrote:
>> EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
>> Add initial support for this SoC.
>>
>> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
>> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
>> ---
>>   arch/arm/mach-exynos/Kconfig    |    8 ++++++++
>>   arch/arm/mach-exynos/common.h   |   11 ++++++++++-
>>   arch/arm/mach-exynos/firmware.c |    2 +-
>>   3 files changed, 19 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index 1602abc..79a3e85 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -84,6 +84,14 @@ config SOC_EXYNOS5250
>>   	help
>>   	  Enable EXYNOS5250 SoC support
>>   
>> +config SOC_EXYNOS5410
>> +	bool "SAMSUNG EXYNOS5410"
>> +	default y
>> +	depends on ARCH_EXYNOS5
>> +	select PM_GENERIC_DOMAINS if PM_RUNTIME
>> +	help
>> +	  Enable EXYNOS5410 SoC support
>> +
>>   config SOC_EXYNOS5420
>>   	bool "SAMSUNG EXYNOS5420"
>>   	default y
>> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
>> index e2d0954..d64c6de 100644
>> --- a/arch/arm/mach-exynos/common.h
>> +++ b/arch/arm/mach-exynos/common.h
>> @@ -21,6 +21,7 @@
>>   #define EXYNOS4_CPU_MASK	0xFFFE0000
>>   
>>   #define EXYNOS5250_SOC_ID	0x43520000
>> +#define EXYNOS5410_SOC_ID	0xE5410000
>>   #define EXYNOS5420_SOC_ID	0xE5420000
>>   #define EXYNOS5440_SOC_ID	0xE5440000
>>   #define EXYNOS5_SOC_MASK	0xFFFFF000
>> @@ -37,6 +38,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
>>   IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
>>   IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
>>   IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
>> +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
>>   IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
>>   IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
>>   
>> @@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
>>   # define soc_is_exynos5250()	0
>>   #endif
>>   
>> +#if defined(CONFIG_SOC_EXYNOS5410)
>> +# define soc_is_exynos5410()	is_samsung_exynos5410()
>> +#else
>> +# define soc_is_exynos5410()	0
>> +#endif
>> +
>>   #if defined(CONFIG_SOC_EXYNOS5420)
>>   # define soc_is_exynos5420()	is_samsung_exynos5420()
>>   #else
>> @@ -82,7 +90,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
>>   
>>   #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
>>   			  soc_is_exynos4412())
>> -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
>> +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
>> +			  soc_is_exynos5420())
>>   
This is the place where we need it.
Or this macro should be changed (maybe read compatible property from dt).

-- 
Best regards,
     Tarek Dakhran

Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC

[Tomasz Figa]

Hi Tarek,

On 24.05.2014 11:33, Tarek Dakhran wrote:
> Hi Tomasz
> 
> I faced another problem, while changing this patch.
> See below.
> 
> On 05/24/2014 01:11 AM, Tomasz Figa wrote:
>> Hi Tarek,
>>
>> With v2 of the series I mentioned in review of previous version [1],
>> this patch can be skipped.
>>
>> [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html
>>
>> Best regards,
>> Tomasz
>>
>> On 23.05.2014 12:35, Tarek Dakhran wrote:
>>> EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
>>> Add initial support for this SoC.
>>>
>>> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
>>> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
>>> ---
>>>   arch/arm/mach-exynos/Kconfig    |    8 ++++++++
>>>   arch/arm/mach-exynos/common.h   |   11 ++++++++++-
>>>   arch/arm/mach-exynos/firmware.c |    2 +-
>>>   3 files changed, 19 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>>> index 1602abc..79a3e85 100644
>>> --- a/arch/arm/mach-exynos/Kconfig
>>> +++ b/arch/arm/mach-exynos/Kconfig
>>> @@ -84,6 +84,14 @@ config SOC_EXYNOS5250
>>>       help
>>>         Enable EXYNOS5250 SoC support
>>>   +config SOC_EXYNOS5410
>>> +    bool "SAMSUNG EXYNOS5410"
>>> +    default y
>>> +    depends on ARCH_EXYNOS5
>>> +    select PM_GENERIC_DOMAINS if PM_RUNTIME
>>> +    help
>>> +      Enable EXYNOS5410 SoC support
>>> +
>>>   config SOC_EXYNOS5420
>>>       bool "SAMSUNG EXYNOS5420"
>>>       default y
>>> diff --git a/arch/arm/mach-exynos/common.h
>>> b/arch/arm/mach-exynos/common.h
>>> index e2d0954..d64c6de 100644
>>> --- a/arch/arm/mach-exynos/common.h
>>> +++ b/arch/arm/mach-exynos/common.h
>>> @@ -21,6 +21,7 @@
>>>   #define EXYNOS4_CPU_MASK    0xFFFE0000
>>>     #define EXYNOS5250_SOC_ID    0x43520000
>>> +#define EXYNOS5410_SOC_ID    0xE5410000
>>>   #define EXYNOS5420_SOC_ID    0xE5420000
>>>   #define EXYNOS5440_SOC_ID    0xE5440000
>>>   #define EXYNOS5_SOC_MASK    0xFFFFF000
>>> @@ -37,6 +38,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
>>> EXYNOS4_CPU_MASK)
>>>   IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
>>>   IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
>>>   IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
>>> +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
>>>   IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
>>>   IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
>>>   @@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID,
>>> EXYNOS5_SOC_MASK)
>>>   # define soc_is_exynos5250()    0
>>>   #endif
>>>   +#if defined(CONFIG_SOC_EXYNOS5410)
>>> +# define soc_is_exynos5410()    is_samsung_exynos5410()
>>> +#else
>>> +# define soc_is_exynos5410()    0
>>> +#endif
>>> +
>>>   #if defined(CONFIG_SOC_EXYNOS5420)
>>>   # define soc_is_exynos5420()    is_samsung_exynos5420()
>>>   #else
>>> @@ -82,7 +90,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID,
>>> EXYNOS5_SOC_MASK)
>>>     #define soc_is_exynos4() (soc_is_exynos4210() ||
>>> soc_is_exynos4212() || \
>>>                 soc_is_exynos4412())
>>> -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
>>> +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410()
>>> || \
>>> +              soc_is_exynos5420())
>>>   
> This is the place where we need it.
> Or this macro should be changed (maybe read compatible property from dt).
> 

The problem is in fact not here, but in code using this macro. Let's
see, what git grep[1] gives us:

> arch/arm/mach-exynos/exynos.c-static void __init exynos_map_io(void)
> arch/arm/mach-exynos/exynos.c-{
> arch/arm/mach-exynos/exynos.c-  if (soc_is_exynos4())
> arch/arm/mach-exynos/exynos.c-          iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
> arch/arm/mach-exynos/exynos.c-
> arch/arm/mach-exynos/exynos.c:  if (soc_is_exynos5())
> arch/arm/mach-exynos/exynos.c-          iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));

OK, so we have an array of static mappings, which can't be handled using
DT yet. That would probably explain why it fails to boot.

> arch/arm/mach-exynos/exynos.c-}

> arch/arm/mach-exynos/exynos.c-static void __init exynos_dt_machine_init(void)
> arch/arm/mach-exynos/exynos.c-{
[snip]
> arch/arm/mach-exynos/exynos.c:  if (soc_is_exynos5()) {
> arch/arm/mach-exynos/exynos.c-          for_each_compatible_node(i2c_np, NULL, i2c_compat) {
> arch/arm/mach-exynos/exynos.c-                  if (of_device_is_available(i2c_np)) {
> arch/arm/mach-exynos/exynos.c-                          id = of_alias_get_id(i2c_np, "i2c");
> arch/arm/mach-exynos/exynos.c-                          if (id < 4) {
> arch/arm/mach-exynos/exynos.c-                                  tmp = readl(EXYNOS5_SYS_I2C_CFG);
> arch/arm/mach-exynos/exynos.c-                                  writel(tmp & ~(0x1 << id),
> arch/arm/mach-exynos/exynos.c-                                                  EXYNOS5_SYS_I2C_CFG);
> arch/arm/mach-exynos/exynos.c-                          }
> arch/arm/mach-exynos/exynos.c-                  }
> arch/arm/mach-exynos/exynos.c-          }

This one handles I2C interrupt signal mux and I'm not quite sure if
soc_is_exynos5() is the right condition here, but at least it shouldn't
cause crashes.

OK, so this means that soc_is_exynos5410() must stay until the remaining
low level drivers that currently use static mappings are rewritten
properly. So the only bit to be dropped from this patch is the change to
firmware.c, which is not needed any longer.

[1] The command used (on linux-next/master):
git grep -20 soc_is_exynos5\( arch/arm/mach-exynos/

Best regards,
Tomasz

Re: [PATCH v10 3/3] ARM: dts: Add initial device tree support for EXYNOS5410

[Kukjin Kim]

On 05/24/14 06:15, Tomasz Figa wrote:
> Hi Tarek,
>
> On 23.05.2014 12:35, Tarek Dakhran wrote:
>> Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
>>
>> Signed-off-by: Tarek Dakhran<t.dakhran@samsung.com>
>> Signed-off-by: Vyacheslav Tyrtov<v.tyrtov@samsung.com>
>> ---
>>   arch/arm/boot/dts/Makefile                |    1 +
>>   arch/arm/boot/dts/exynos5410-smdk5410.dts |   82 ++++++++++++
>>   arch/arm/boot/dts/exynos5410.dtsi         |  206 +++++++++++++++++++++++++++++
>>   3 files changed, 289 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
>>   create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
>
> Looks good. Hopefully we can have this patch applied soon, so it won't
> get outdated again.
>
Yes.

Tarek, please respin as soon as possible.

> Reviewed-by: Tomasz Figa<t.figa@samsung.com>
>

- Kukjin