Re: [PATCH 4/4] dts, altera: Arria10 SDRAM EDAC DTS additions.

Thor Thayer
2015-05-15T21:01:39Z

Hi Arnd,

On 05/15/2015 05:55 AM, Arnd Bergmann wrote:
> On Wednesday 13 May 2015 16:49:47 tthayer@opensource.altera.com wrote:
>> + sdr: sdr@ffc25000 {
>> + compatible = "syscon";
>> + reg = <0xffcfb100 0x80>;
>> + };
>> +
>>
>
> A syscon node with just 128 bytes seems very odd. Can you check the
> hardware manual to see if this is part of some bigger unit?
>
> Arnd
>

This is an unfortunate legacy of our previous SDRAM controller (in the
CycloneV) which had ECC registers interspersed with registers other
drivers needed - thus the use of syscon.

In the Arria10 chip, the ECC registers are in their own partitioned
group but I kept the syscon to remain consistent with the Device Tree
bindings from the CycloneV family.

I've implemented your other suggestions. Thank you for reviewing!

Thor