From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH v2 2/4] pinctrl: Add NVIDIA Tegra XUSB pad controller support Date: Thu, 12 Jun 2014 14:39:05 -0600 Message-ID: <539A0FE9.1080802@wwwdotorg.org> References: <1402398708-10722-1-git-send-email-thierry.reding@gmail.com> <1402398708-10722-2-git-send-email-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1402398708-10722-2-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding , Linus Walleij Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Andrew Bresticker , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 06/10/2014 05:11 AM, Thierry Reding wrote: > From: Thierry Reding > > The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads > that lanes can be assigned to in order to support a variety of interface > options: USB 2.0, USB 3.0, PCIe and SATA. > > In addition to the pin controller used to assign lanes to pads two PHYs > are exposed to allow the bricks for PCIe and SATA to be powered up and > down by PCIe and SATA drivers. Aside from the issue Andrew pointed out, this series looks good to me. I'll apply once that one issue is fixed. Linus, Patch 2 (pinctrl driver) depends on patch 1 (binding header), and there are other patches that will also depend on the binding header in patch 1. I guess I should apply patch 1 in a topic branch and send you a pull request which you can merge before applying patch 2. Does that sound OK to you?