[PATCH v2 1/3] of: Add NVIDIA Tegra flow controller bindings

[PATCH v2 1/3] of: Add NVIDIA Tegra flow controller bindings

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Add device tree bindings for the flow controller found on NVIDIA Tegra
SoCs.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/arm/tegra/nvidia,tegra114-flowctrl.txt          | 12 ++++++++++++
 .../bindings/arm/tegra/nvidia,tegra124-flowctrl.txt          | 12 ++++++++++++
 .../bindings/arm/tegra/nvidia,tegra20-flowctrl.txt           | 12 ++++++++++++
 .../bindings/arm/tegra/nvidia,tegra30-flowctrl.txt           | 12 ++++++++++++
 4 files changed, 48 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-flowctrl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-flowctrl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-flowctrl.txt

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-flowctrl.txt
new file mode 100644
index 000000000000..72599fdb09a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-flowctrl.txt
@@ -0,0 +1,12 @@
+NVIDIA Tegra114 Flow Controller
+
+Required properties:
+- compatible: "nvidia,tegra114-flowctrl"
+- reg: Should contain one register range (address and length)
+
+Example:
+
+	flow-controller@60007000 {
+		compatible = "nvidia,tegra114-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-flowctrl.txt
new file mode 100644
index 000000000000..3af5fe2019f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-flowctrl.txt
@@ -0,0 +1,12 @@
+NVIDIA Tegra124 Flow Controller
+
+Required properties:
+- compatible: "nvidia,tegra124-flowctrl"
+- reg: Should contain one register range (address and length)
+
+Example:
+
+	flow-controller@0,60007000 {
+		compatible = "nvidia,tegra124-flowctrl";
+		reg = <0x0 0x60007000 0x0 0x1000>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
new file mode 100644
index 000000000000..b077ca8a22c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
@@ -0,0 +1,12 @@
+NVIDIA Tegra20 Flow Controller
+
+Required properties:
+- compatible: "nvidia,tegra20-flowctrl"
+- reg: Should contain one register range (address and length)
+
+Example:
+
+	flow-controller@60007000 {
+		compatible = "nvidia,tegra20-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-flowctrl.txt
new file mode 100644
index 000000000000..72c90dd59110
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-flowctrl.txt
@@ -0,0 +1,12 @@
+NVIDIA Tegra30 Flow Controller
+
+Required properties:
+- compatible: "nvidia,tegra30-flowctrl"
+- reg: Should contain one register range (address and length)
+
+Example:
+
+	flow-controller@60007000 {
+		compatible = "nvidia,tegra30-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
-- 
2.0.0

[PATCH v2 2/3] ARM: tegra: Add device tree nodes for flow controller

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

These nodes are required so that the flow controller driver can obtain
the I/O memory region from device tree rather than hard-coding it.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/tegra114.dtsi | 5 +++++
 arch/arm/boot/dts/tegra124.dtsi | 5 +++++
 arch/arm/boot/dts/tegra20.dtsi  | 5 +++++
 arch/arm/boot/dts/tegra30.dtsi  | 5 +++++
 4 files changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index c8db5db8f5f3..f7236203d7a0 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -161,6 +161,11 @@
 		#reset-cells = <1>;
 	};
 
+	flow-controller@60007000 {
+		compatible = "nvidia,tegra114-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
+
 	apbdma: dma@6000a000 {
 		compatible = "nvidia,tegra114-apbdma";
 		reg = <0x6000a000 0x1400>;
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index e82dfdcab792..5a1977ed2502 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -205,6 +205,11 @@
 		#reset-cells = <1>;
 	};
 
+	flow-controller@0,60007000 {
+		compatible = "nvidia,tegra124-flowctrl";
+		reg = <0x0 0x60007000 0x0 0x1000>;
+	};
+
 	gpio: gpio@0,6000d000 {
 		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 		reg = <0x0 0x6000d000 0x0 0x1000>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index d063754d1324..ba4c02129286 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -201,6 +201,11 @@
 		#reset-cells = <1>;
 	};
 
+	flow-controller@60007000 {
+		compatible = "nvidia,tegra20-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
+
 	apbdma: dma@6000a000 {
 		compatible = "nvidia,tegra20-apbdma";
 		reg = <0x6000a000 0x1200>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 6fb72230b1e4..ad4202e01d60 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -282,6 +282,11 @@
 		#reset-cells = <1>;
 	};
 
+	flow-controller@60007000 {
+		compatible = "nvidia,tegra30-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
+
 	apbdma: dma@6000a000 {
 		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 		reg = <0x6000a000 0x1400>;
-- 
2.0.0

[PATCH v2 3/3] ARM: tegra: Initialize flow controller from DT

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Use a matching device tree node to initialize the flow controller driver
instead of hard-coding the I/O address. This is necessary to get rid of
the iomap.h include, which in turn make it easier to share this code
with 64-bit Tegra SoCs.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
Changes in v2:
- implement fallback when the device tree node is missing
- while at it, reorder includes alphabetically

 arch/arm/mach-tegra/flowctrl.c | 48 ++++++++++++++++++++++++++++++++++--------
 arch/arm/mach-tegra/flowctrl.h |  2 ++
 arch/arm/mach-tegra/tegra.c    |  2 ++
 3 files changed, 43 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index 4b31091f0d40..89d13b2fa0b5 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -18,14 +18,15 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/cpumask.h>
 #include <linux/init.h>
-#include <linux/kernel.h>
 #include <linux/io.h>
-#include <linux/cpumask.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/tegra-soc.h>
 
 #include "flowctrl.h"
-#include "iomap.h"
 
 static u8 flowctrl_offset_halt_cpu[] = {
 	FLOW_CTRL_HALT_CPU0_EVENTS,
@@ -41,23 +42,22 @@ static u8 flowctrl_offset_cpu_csr[] = {
 	FLOW_CTRL_CPU1_CSR + 16,
 };
 
+static void __iomem *tegra_flowctrl_base;
+
 static void flowctrl_update(u8 offset, u32 value)
 {
-	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
-
-	writel(value, addr);
+	writel(value, tegra_flowctrl_base + offset);
 
 	/* ensure the update has reached the flow controller */
 	wmb();
-	readl_relaxed(addr);
+	readl_relaxed(tegra_flowctrl_base + offset);
 }
 
 u32 flowctrl_read_cpu_csr(unsigned int cpuid)
 {
 	u8 offset = flowctrl_offset_cpu_csr[cpuid];
-	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
 
-	return readl(addr);
+	return readl(tegra_flowctrl_base + offset);
 }
 
 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
@@ -138,3 +138,33 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
 	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event */
 	flowctrl_write_cpu_csr(cpuid, reg);
 }
+
+static const struct of_device_id matches[] __initconst = {
+	{ .compatible = "nvidia,tegra124-flowctrl" },
+	{ .compatible = "nvidia,tegra114-flowctrl" },
+	{ .compatible = "nvidia,tegra30-flowctrl" },
+	{ .compatible = "nvidia,tegra20-flowctrl" },
+	{ }
+};
+
+void __init tegra_flowctrl_init(void)
+{
+	/* hardcoded fallback if device tree node is missing */
+	unsigned long base = 0x60007000;
+	unsigned long size = SZ_4K;
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, matches);
+	if (np) {
+		struct resource res;
+
+		if (of_address_to_resource(np, 0, &res) == 0) {
+			size = resource_size(&res);
+			base = res.start;
+		}
+
+		of_node_put(np);
+	}
+
+	tegra_flowctrl_base = ioremap_nocache(base, size);
+}
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index c89aac60a143..73a9c5016c1a 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -59,6 +59,8 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
 
 void flowctrl_cpu_suspend_enter(unsigned int cpuid);
 void flowctrl_cpu_suspend_exit(unsigned int cpuid);
+
+void tegra_flowctrl_init(void);
 #endif
 
 #endif
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 76a6779c5f84..8e139e246526 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -46,6 +46,7 @@
 #include "board.h"
 #include "common.h"
 #include "cpuidle.h"
+#include "flowctrl.h"
 #include "iomap.h"
 #include "irq.h"
 #include "pmc.h"
@@ -78,6 +79,7 @@ static void __init tegra_init_early(void)
 	tegra_cpu_reset_handler_init();
 	tegra_powergate_init();
 	tegra_hotplug_init();
+	tegra_flowctrl_init();
 }
 
 static void __init tegra_dt_init_irq(void)
-- 
2.0.0

Re: [PATCH v2 1/3] of: Add NVIDIA Tegra flow controller bindings

[Stephen Warren]

On 06/27/2014 06:07 AM, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Add device tree bindings for the flow controller found on NVIDIA Tegra
> SoCs.
> 

> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt

> +NVIDIA Tegra20 Flow Controller
> +
> +Required properties:
> +- compatible: "nvidia,tegra20-flowctrl"
> +- reg: Should contain one register range (address and length)
> +
> +Example:
> +
> +	flow-controller@60007000 {
> +		compatible = "nvidia,tegra20-flowctrl";
> +		reg = <0x60007000 0x1000>;
> +	};

The bindings all have the same structure. Can we collapse them all into
this one file and just list all the valid compatible values and say pick
one?

Re: [PATCH v2 2/3] ARM: tegra: Add device tree nodes for flow controller

[Stephen Warren]

On 06/27/2014 06:07 AM, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> These nodes are required so that the flow controller driver can obtain
> the I/O memory region from device tree rather than hard-coding it.

This patch,
Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Re: [PATCH v2 3/3] ARM: tegra: Initialize flow controller from DT

[Stephen Warren]

On 06/27/2014 06:07 AM, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Use a matching device tree node to initialize the flow controller driver
> instead of hard-coding the I/O address. This is necessary to get rid of
> the iomap.h include, which in turn make it easier to share this code
> with 64-bit Tegra SoCs.

This patch,
Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Re: [PATCH v2 1/3] of: Add NVIDIA Tegra flow controller bindings

[Stephen Warren]

On 06/27/2014 03:20 PM, Stephen Warren wrote:
> On 06/27/2014 06:07 AM, Thierry Reding wrote:
>> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> Add device tree bindings for the flow controller found on NVIDIA Tegra
>> SoCs.
>>
>
>> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
>
>> +NVIDIA Tegra20 Flow Controller
>> +
>> +Required properties:
>> +- compatible: "nvidia,tegra20-flowctrl"
>> +- reg: Should contain one register range (address and length)
>> +
>> +Example:
>> +
>> +	flow-controller@60007000 {
>> +		compatible = "nvidia,tegra20-flowctrl";
>> +		reg = <0x60007000 0x1000>;
>> +	};
>
> The bindings all have the same structure. Can we collapse them all into
> this one file and just list all the valid compatible values and say pick
> one?

Thierry, did you post an updated version of this patch? If so, I seem to 
have lost it, so a repost would be good. Thanks.

Re: [PATCH v2 1/3] of: Add NVIDIA Tegra flow controller bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1313 bytes --]

On Mon, Aug 25, 2014 at 11:32:20AM -0600, Stephen Warren wrote:
> On 06/27/2014 03:20 PM, Stephen Warren wrote:
> >On 06/27/2014 06:07 AM, Thierry Reding wrote:
> >>From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> >>
> >>Add device tree bindings for the flow controller found on NVIDIA Tegra
> >>SoCs.
> >>
> >
> >>diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
> >
> >>+NVIDIA Tegra20 Flow Controller
> >>+
> >>+Required properties:
> >>+- compatible: "nvidia,tegra20-flowctrl"
> >>+- reg: Should contain one register range (address and length)
> >>+
> >>+Example:
> >>+
> >>+	flow-controller@60007000 {
> >>+		compatible = "nvidia,tegra20-flowctrl";
> >>+		reg = <0x60007000 0x1000>;
> >>+	};
> >
> >The bindings all have the same structure. Can we collapse them all into
> >this one file and just list all the valid compatible values and say pick
> >one?
> 
> Thierry, did you post an updated version of this patch? If so, I seem to
> have lost it, so a repost would be good. Thanks.

I don't think I did. If my memory serves me well then I did address your
comments but never sent out the patches. I'll check what the status is.

Thierry

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