[PATCH v5 0/2] Add R8A7790/Lager board PCI USB DT support

[PATCH v5 0/2] Add R8A7790/Lager board PCI USB DT support

[Sergei Shtylyov]

Hello.

   Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-v3.16-rc2-20140623' tag. Here we add PCI USB device tree support
for the R8A7790-based Lager board. As the 'pci-rcar-gen2' driver device tree
support has been merged for 3.16, this patchset can now be merged too...

[1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes
[2/2] ARM: shmobile: lager: enable internal PCI

WBR, Sergei

[PATCH v5 1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes

[Sergei Shtylyov]

From: Ben Dooks <ben.dooks@codethink.co.uk>

Add device nodes for the R8A7790 internal PCI bridge devices.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
[Sergei: added several properties to the PCI bridge nodes]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
Changes in version 5:
- added "device_type" and "ranges" properties to the PCI bridge nodes;
- removed "0x" prefix from zero values in the "reg" properties.

Changes in version 4:
- refreshed the patch.

Changes in version 3:
- added interrupt-related properties to the PCI bridge nodes;
- refreshed the patch.

Changes in version 2:
- reworded summary (fixing typo) and changelog;
- removed extra spaces before {;
- refreshed the patch.

 arch/arm/boot/dts/r8a7790.dtsi |   60 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7790.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7790.dtsi
+++ renesas/arch/arm/boot/dts/r8a7790.dtsi
@@ -930,6 +930,66 @@
 		status = "disabled";
 	};
 
+	pci0: pci@ee090000 {
+		compatible = "renesas,pci-r8a7790";
+		device_type = "pci";
+		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+		reg = <0 0xee090000 0 0xc00>,
+		      <0 0xee080000 0 0x1100>;
+		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+
+		bus-range = <0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+		interrupt-map-mask = <0xff00 0 0 0x7>;
+		interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
+			      	 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
+			      	 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pci1: pci@ee0b0000 {
+		compatible = "renesas,pci-r8a7790";
+		device_type = "pci";
+		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+		reg = <0 0xee0b0000 0 0xc00>,
+		      <0 0xee0a0000 0 0x1100>;
+		interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+
+		bus-range = <1 1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
+		interrupt-map-mask = <0xff00 0 0 0x7>;
+		interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
+			      	 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
+			      	 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pci2: pci@ee0d0000 {
+		compatible = "renesas,pci-r8a7790";
+		device_type = "pci";
+		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+		reg = <0 0xee0d0000 0 0xc00>,
+		      <0 0xee0c0000 0 0x1100>;
+		interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+
+		bus-range = <2 2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+		interrupt-map-mask = <0xff00 0 0 0x7>;
+		interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
+			      	 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
+			      	 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	pciec: pcie@fe000000 {
 		compatible = "renesas,pcie-r8a7790";
 		reg = <0 0xfe000000 0 0x80000>;

[PATCH v5 2/2] ARM: shmobile: lager: enable internal PCI

[Sergei Shtylyov]

From: Ben Dooks <ben.dooks@codethink.co.uk>

Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to
them.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
[Sergei: enabled PCI0]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
Changes in version 4:
- refreshed the patch.

Changes in version 3:
- refreshed the patch.

Changes in version 2:
- enabled PCI0 device;
- reworded summary and changelog;
- refreshed the patch.

 arch/arm/boot/dts/r8a7790-lager.dts |   33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7790-lager.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7790-lager.dts
+++ renesas/arch/arm/boot/dts/r8a7790-lager.dts
@@ -219,6 +219,21 @@
 		renesas,groups = "i2c3";
 		renesas,function = "i2c3";
 	};
+
+	usb0_pins: usb0 {
+		renesas,groups = "usb0";
+		renesas,function = "usb0";
+	};
+
+	usb1_pins: usb1 {
+		renesas,groups = "usb1";
+		renesas,function = "usb1";
+	};
+
+	usb2_pins: usb2 {
+		renesas,groups = "usb2";
+		renesas,function = "usb2";
+	};
 };
 
 &ether {
@@ -368,3 +383,21 @@
 		regulator-always-on;
 	};
 };
+
+&pci0 {
+	status = "okay";
+	pinctrl-0 = <&usb0_pins>;
+	pinctrl-names = "default";
+};
+
+&pci1 {
+	status = "okay";
+	pinctrl-0 = <&usb1_pins>;
+	pinctrl-names = "default";
+};
+
+&pci2 {
+	status = "okay";
+	pinctrl-0 = <&usb2_pins>;
+	pinctrl-names = "default";
+};

Re: [PATCH v5 1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes

[Arnd Bergmann]

On Tuesday 24 June 2014 21:59:54 Sergei Shtylyov wrote:
> From: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> Add device nodes for the R8A7790 internal PCI bridge devices.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
> [Sergei: added several properties to the PCI bridge nodes]
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Yes, looks better, thanks for the update.

Acked-by: Arnd Bergmann <arnd@arndb.de>

Re: [PATCH v5 1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes

[Yoshihiro Shimoda]

Hi Sergei,

(2014/06/25 2:59), Sergei Shtylyov wrote:
> From: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> Add device nodes for the R8A7790 internal PCI bridge devices.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
> [Sergei: added several properties to the PCI bridge nodes]
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Thank you for the patch!
I tested this patch on my lager board and a usb memory, and it works.

Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda

> ---
> Changes in version 5:
> - added "device_type" and "ranges" properties to the PCI bridge nodes;
> - removed "0x" prefix from zero values in the "reg" properties.
> 
> Changes in version 4:
> - refreshed the patch.
> 
> Changes in version 3:
> - added interrupt-related properties to the PCI bridge nodes;
> - refreshed the patch.
> 
> Changes in version 2:
> - reworded summary (fixing typo) and changelog;
> - removed extra spaces before {;
> - refreshed the patch.
> 
>  arch/arm/boot/dts/r8a7790.dtsi |   60 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 60 insertions(+)
> 
> Index: renesas/arch/arm/boot/dts/r8a7790.dtsi
> ===================================================================
> --- renesas.orig/arch/arm/boot/dts/r8a7790.dtsi
> +++ renesas/arch/arm/boot/dts/r8a7790.dtsi
> @@ -930,6 +930,66 @@
>  		status = "disabled";
>  	};
>  
> +	pci0: pci@ee090000 {
> +		compatible = "renesas,pci-r8a7790";
> +		device_type = "pci";
> +		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
> +		reg = <0 0xee090000 0 0xc00>,
> +		      <0 0xee080000 0 0x1100>;
> +		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
> +		status = "disabled";
> +
> +		bus-range = <0 0>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		#interrupt-cells = <1>;
> +		ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
> +		interrupt-map-mask = <0xff00 0 0 0x7>;
> +		interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
> +			      	 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
> +			      	 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	pci1: pci@ee0b0000 {
> +		compatible = "renesas,pci-r8a7790";
> +		device_type = "pci";
> +		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
> +		reg = <0 0xee0b0000 0 0xc00>,
> +		      <0 0xee0a0000 0 0x1100>;
> +		interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
> +		status = "disabled";
> +
> +		bus-range = <1 1>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		#interrupt-cells = <1>;
> +		ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
> +		interrupt-map-mask = <0xff00 0 0 0x7>;
> +		interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
> +			      	 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
> +			      	 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	pci2: pci@ee0d0000 {
> +		compatible = "renesas,pci-r8a7790";
> +		device_type = "pci";
> +		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
> +		reg = <0 0xee0d0000 0 0xc00>,
> +		      <0 0xee0c0000 0 0x1100>;
> +		interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
> +		status = "disabled";
> +
> +		bus-range = <2 2>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		#interrupt-cells = <1>;
> +		ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
> +		interrupt-map-mask = <0xff00 0 0 0x7>;
> +		interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
> +			      	 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
> +			      	 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
>  	pciec: pcie@fe000000 {
>  		compatible = "renesas,pcie-r8a7790";
>  		reg = <0 0xfe000000 0 0x80000>;
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v5 2/2] ARM: shmobile: lager: enable internal PCI

[Yoshihiro Shimoda]

Hi Sergei,

(2014/06/25 3:02), Sergei Shtylyov wrote:
> From: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to
> them.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
> [Sergei: enabled PCI0]
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

I also tested this patch, and it works.

Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro shimoda

> ---
> Changes in version 4:
> - refreshed the patch.
> 
> Changes in version 3:
> - refreshed the patch.
> 
> Changes in version 2:
> - enabled PCI0 device;
> - reworded summary and changelog;
> - refreshed the patch.
> 
>  arch/arm/boot/dts/r8a7790-lager.dts |   33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> Index: renesas/arch/arm/boot/dts/r8a7790-lager.dts
> ===================================================================
> --- renesas.orig/arch/arm/boot/dts/r8a7790-lager.dts
> +++ renesas/arch/arm/boot/dts/r8a7790-lager.dts
> @@ -219,6 +219,21 @@
>  		renesas,groups = "i2c3";
>  		renesas,function = "i2c3";
>  	};
> +
> +	usb0_pins: usb0 {
> +		renesas,groups = "usb0";
> +		renesas,function = "usb0";
> +	};
> +
> +	usb1_pins: usb1 {
> +		renesas,groups = "usb1";
> +		renesas,function = "usb1";
> +	};
> +
> +	usb2_pins: usb2 {
> +		renesas,groups = "usb2";
> +		renesas,function = "usb2";
> +	};
>  };
>  
>  &ether {
> @@ -368,3 +383,21 @@
>  		regulator-always-on;
>  	};
>  };
> +
> +&pci0 {
> +	status = "okay";
> +	pinctrl-0 = <&usb0_pins>;
> +	pinctrl-names = "default";
> +};
> +
> +&pci1 {
> +	status = "okay";
> +	pinctrl-0 = <&usb1_pins>;
> +	pinctrl-names = "default";
> +};
> +
> +&pci2 {
> +	status = "okay";
> +	pinctrl-0 = <&usb2_pins>;
> +	pinctrl-names = "default";
> +};
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v5 1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes

[Magnus Damm]

Hi Shimoda-san,

On Thu, Jun 26, 2014 at 11:47 AM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Hi Sergei,
>
> (2014/06/25 2:59), Sergei Shtylyov wrote:
>> From: Ben Dooks <ben.dooks@codethink.co.uk>
>>
>> Add device nodes for the R8A7790 internal PCI bridge devices.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>> Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
>> [Sergei: added several properties to the PCI bridge nodes]
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Thank you for the patch!
> I tested this patch on my lager board and a usb memory, and it works.
>
> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for testing. Just one quick question from my side: Which USB
port did you test?

I somehow assumed that at least the majority of the USB ports on R-Car
Gen2 require a USB PHY device driver to work?

Cheers,

/ magnus

Re: [PATCH v5 1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes

[Yoshihiro Shimoda]

Hi Magnus-san,

(2014/06/26 12:01), Magnus Damm wrote:
> Hi Shimoda-san,
> 
> On Thu, Jun 26, 2014 at 11:47 AM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
>> Hi Sergei,
>>
>> (2014/06/25 2:59), Sergei Shtylyov wrote:
>>> From: Ben Dooks <ben.dooks@codethink.co.uk>
>>>
>>> Add device nodes for the R8A7790 internal PCI bridge devices.
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>> Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
>>> [Sergei: added several properties to the PCI bridge nodes]
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> Thank you for the patch!
>> I tested this patch on my lager board and a usb memory, and it works.
>>
>> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for testing. Just one quick question from my side: Which USB
> port did you test?

I tested usb ch1 only...

> I somehow assumed that at least the majority of the USB ports on R-Car
> Gen2 require a USB PHY device driver to work?

Thank you for the point.
About usb ch1, a USB PHY device driver doesn't need, I think.
But, about ch0 and ch2, I think that they should require a USB PHY device driver.

Best regards,
Yoshihiro Shimoda

> Cheers,
> 
> / magnus
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v5 1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes

[Magnus Damm]

Hi Shimoda-san,

On Thu, Jun 26, 2014 at 12:37 PM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Hi Magnus-san,
>
> (2014/06/26 12:01), Magnus Damm wrote:
>> Hi Shimoda-san,
>>
>> On Thu, Jun 26, 2014 at 11:47 AM, Yoshihiro Shimoda
>> <yoshihiro.shimoda.uh@renesas.com> wrote:
>>> Hi Sergei,
>>>
>>> (2014/06/25 2:59), Sergei Shtylyov wrote:
>>>> From: Ben Dooks <ben.dooks@codethink.co.uk>
>>>>
>>>> Add device nodes for the R8A7790 internal PCI bridge devices.
>>>>
>>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>>> Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
>>>> [Sergei: added several properties to the PCI bridge nodes]
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>
>>> Thank you for the patch!
>>> I tested this patch on my lager board and a usb memory, and it works.
>>>
>>> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>>
>> Thanks for testing. Just one quick question from my side: Which USB
>> port did you test?
>
> I tested usb ch1 only...
>
>> I somehow assumed that at least the majority of the USB ports on R-Car
>> Gen2 require a USB PHY device driver to work?
>
> Thank you for the point.
> About usb ch1, a USB PHY device driver doesn't need, I think.
> But, about ch0 and ch2, I think that they should require a USB PHY device driver.

Thanks for your clarification. It all makes sense now!

Cheers,

/ magnus

Re: [PATCH v5 1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes

[Sergei Shtylyov]

Hello.

On 06/26/2014 07:01 AM, Magnus Damm wrote:

>>> From: Ben Dooks <ben.dooks@codethink.co.uk>

>>> Add device nodes for the R8A7790 internal PCI bridge devices.

>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>> Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
>>> [Sergei: added several properties to the PCI bridge nodes]
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

>> Thank you for the patch!
>> I tested this patch on my lager board and a usb memory, and it works.

>> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

> Thanks for testing. Just one quick question from my side: Which USB
> port did you test?

> I somehow assumed that at least the majority of the USB ports on R-Car
> Gen2 require a USB PHY device driver to work?

    In fact, channel #2 also works without the PHY driver as the default 
UGCTRL2 setting route USB2 pins to OHCI/EHCI.

> Cheers,
> / magnus

WBR, Sergei

Re: [PATCH v5 1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes

[Sergei Shtylyov]

Hello.

On 06/26/2014 07:37 AM, Yoshihiro Shimoda wrote:

>>>> From: Ben Dooks <ben.dooks@codethink.co.uk>

>>>> Add device nodes for the R8A7790 internal PCI bridge devices.

>>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>>> Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
>>>> [Sergei: added several properties to the PCI bridge nodes]
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

>>> Thank you for the patch!

>>> I tested this patch on my lager board and a usb memory, and it works.

>>> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

>> Thanks for testing. Just one quick question from my side: Which USB
>> port did you test?

> I tested usb ch1 only...

    Note that channel #2 also should work.

>> I somehow assumed that at least the majority of the USB ports on R-Car
>> Gen2 require a USB PHY device driver to work?
>
> Thank you for the point.
> About usb ch1, a USB PHY device driver doesn't need, I think.
> But, about ch0 and ch2, I think that they should require a USB PHY device driver.

    Only channel #0 requires the PHY driver as the default routing for USB0 is 
to USBHS; channel #2 is routed to OHCI/EHCI by default.

> Best regards,
> Yoshihiro Shimoda

WBR, Sergei

Re: [PATCH v5 0/2] Add R8A7790/Lager board PCI USB DT support

[Simon Horman]

On Tue, Jun 24, 2014 at 09:57:04PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
>    Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-v3.16-rc2-20140623' tag. Here we add PCI USB device tree support
> for the R8A7790-based Lager board. As the 'pci-rcar-gen2' driver device tree
> support has been merged for 3.16, this patchset can now be merged too...
> 
> [1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes
> [2/2] ARM: shmobile: lager: enable internal PCI

Thanks, I will queue these up with
Shimoda-san's Tested-by.

Re: [PATCH v5 0/2] Add R8A7790/Lager board PCI USB DT support

[Simon Horman]

On Sat, Jun 28, 2014 at 08:56:22AM +0900, Simon Horman wrote:
> On Tue, Jun 24, 2014 at 09:57:04PM +0400, Sergei Shtylyov wrote:
> > Hello.
> > 
> >    Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
> > 'renesas-devel-v3.16-rc2-20140623' tag. Here we add PCI USB device tree support
> > for the R8A7790-based Lager board. As the 'pci-rcar-gen2' driver device tree
> > support has been merged for 3.16, this patchset can now be merged too...
> > 
> > [1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes
> > [2/2] ARM: shmobile: lager: enable internal PCI
> 
> Thanks, I will queue these up with
> Shimoda-san's Tested-by.

And Arnd's Ack

Re: [PATCH v5 1/2] ARM: shmobile: r8a7790: add internal PCI bridge nodes

[Yoshihiro Shimoda]

Hello,

(2014/06/26 21:34), Sergei Shtylyov wrote:
> Hello.
> 
> On 06/26/2014 07:37 AM, Yoshihiro Shimoda wrote:
> 
>>>>> From: Ben Dooks <ben.dooks@codethink.co.uk>
> 
>>>>> Add device nodes for the R8A7790 internal PCI bridge devices.
> 
>>>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>>>> Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
>>>>> [Sergei: added several properties to the PCI bridge nodes]
>>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> 
>>>> Thank you for the patch!
> 
>>>> I tested this patch on my lager board and a usb memory, and it works.
> 
>>>> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
>>> Thanks for testing. Just one quick question from my side: Which USB
>>> port did you test?
> 
>> I tested usb ch1 only...
> 
>     Note that channel #2 also should work.

Thank you for the point.
I tried to test usb ch2, and then it worked on my environment.

>>> I somehow assumed that at least the majority of the USB ports on R-Car
>>> Gen2 require a USB PHY device driver to work?
>>
>> Thank you for the point.
>> About usb ch1, a USB PHY device driver doesn't need, I think.
>> But, about ch0 and ch2, I think that they should require a USB PHY device driver.
> 
>     Only channel #0 requires the PHY driver as the default routing for USB0 is 
> to USBHS; channel #2 is routed to OHCI/EHCI by default.

I understood it.

Best regards,
Yoshihiro Shimoda

>> Best regards,
>> Yoshihiro Shimoda
> 
> WBR, Sergei
>